Burst-Mode Controller With Integrated Monitoring DS1863 controls
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19-4883; 8/09
Burst-Mode Controller With Integrated Monitoring
DS1863 controls monitors burst-mode transmitter video receiver biasing functions passive optical network (PON) transceiver. loop with tracking-error compensation that provides reference laser driver's bias current temperature-indexed lookup table (LUT) that controls modulation current. continually monitors high output current, high bias current, high transmit power with internal fast comparators ensure that laser shutdown safety requirements without adding external components. Five channels monitor VCC, internal temperature, three external monitor inputs (MON1, MON2, MON3) that used meet transmitter receive monitoring requirements.
Features
Meets BPON, GPON, GEPON Timing Requirements Burst-Mode Transceivers Bias Current Control Provided Loop with Tracking Error Compensation Modulation Current Controlled Temperature-Indexed Lookup Table Supports 0dB, -3dB, -6dB Power Leveling Settings with Additional Calibration Internal Direct-to-Digital Temperature Sensor Five Analog Monitor Channels: Temperature, VCC, MON1, MON2, MON3 Comprehensive Fault Management System with Maskable Laser Shutdown Capability Two-Level Password Access Protect Calibration Data Bytes Password (PW1) Protected Nonvolatile Memory Bytes Password (PW2) Protected Nonvolatile Memory I2C-Compatible Interface Calibration Monitoring Operating Voltage: 2.85V 3.9V Operating Temperature: -40°C +95°C 16-Pin, Lead-Free TSSOP Package
DS1863
Applications
BPON, GPON, GEPON Burst-Mode Transmitters Laser Control Monitoring Broadband Local Access
Configuration
VIEW
TX-D N.C. TX-F FETG BIAS
Ordering Information
PART DS1863E+ DS1863E+T&R TEMP RANGE -40°C +95°C -40°C +95°C PIN-PACKAGE TSSOP TSSOP
+Denotes lead(Pb)-free/RoHS-compliant package. Tape reel.
DS1863
MON3 MON2 MON1
TSSOP (173 mils)
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim Direct 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Burst-Mode Controller With Integrated Monitoring DS1863
ABSOLUTE MAXIMUM RATINGS
Voltage VCC, Relative Ground.-0.5V Voltage BEN, TX-D, TX-F, MON1-MON3, Relative Ground .-0.5V 0.5V (subject exceeding +6V) Operating Temperature Range .-40°C +95°C Programming Temperature Range .0°C +70°C Storage Temperature Range .-55°C +125°C Soldering Temperature .See J-STD-020 specification
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
-40°C +95°C, unless otherwise noted.)
PARAMETER Supply Voltage High-Level Input Voltage (SDA, SCL, BEN) Low-Level Input Voltage (SDA, SCL, BEN) High-Level Input Voltage (TX-D) Low-Level Input Voltage (TX-D) SYMBOL VIH:1 VIL:1 VIH:2 VIL:2 (Note CONDITIONS +2.85 -0.3 -0.3 UNITS
ELECTRICAL CHARACTERISTICS
(VCC= +2.85V +3.9V, -40°C +95°C, unless otherwise noted.)
PARAMETER Supply Current Output Leakage (SDA, TX-F) Low-Level Output Voltage (SDA, TX-F, FETG) High-Level Output Voltage (FETG) FETG Before Recall Input Leakage Current (SCL, BEN, TX-D) Digital Power-On Reset Analog Power-On Reset ILI:1 SYMBOL (Note (Note 2.75 (Notes CONDITIONS UNITS
ANALOG INPUT CHARACTERISTICS (BMD)
(VCC +2.85V +3.9V, -40°C +95°C, unless otherwise noted.)
PARAMETER Full-Scale Voltage Range Resolution VAPC Error VAPC Integral Nonlinearity VAPC Differential Nonlinearity VAPC Temp Drift Input Resistance SYMBOL VAPC (Note (Note +25°C (Note -1.75 -2.5 50.0 CONDITIONS +1.75 +2.5 UNITS bits
Burst-Mode Controller With Integrated Monitoring
ANALOG OUTPUT CHARACTERISTICS
(VCC= +2.85V +3.9V, -40°C +95°C, unless otherwise noted.)
PARAMETER BIAS Current IBIAS Shutdown Current Voltage IBIAS Full-Scale Voltage Output Impedance VMOD Error VMOD Integral Nonlinearity VMOD Differential Nonlinearity VMOD Temperature Drift VMOD (Note (Note +25°C (Note -1.25 SYMBOL IBIAS IBIAS:OFF (Note CONDITIONS 1.25 3.14 +1.25 UNITS
DS1863
CONTROL LOOP QUICK-TRIP TIMING CHARACTERISTICS
(VCC= +2.85V +3.9V, -40°C +95°C, unless otherwise noted.)
PARAMETER First Sample Following Remaining Updates During High Time Time BIAS Turn-Off Delay BIAS Turn-On Delay FETG Turn-On Delay FETG Turn-Off Delay Binary Search Time Round-Robin Time SYMBOL tFIRST tREP tBEN:HIGH tBEN:LOW tOFF tFETG:ON tFETG:OFF tSEARCH (Note (Note (Note BIAS Samples CONDITIONS UNITS
ANALOG VOLTAGE MONITORING
(VCC +2.85V +3.9V, -40°C +95°C, unless otherwise noted.)
PARAMETER Resolution Input/Supply Accuracy (MON1, MON2, MON3, VCC) Update Rate Temperature, MON1, MON2, MON3, Input/Supply Offset (MON1, MON2, MON3, VCC) Factory Setting MON1, MON2, MON3 Full scales user programmable tFRAME:1 (Note factory setting SYMBOL CONDITIONS 0.25 6.5536 UNITS Bits
Burst-Mode Controller With Integrated Monitoring DS1863
ELECTRICAL CHARACTERISTICS
(VCC +2.85V +3.9V, -40°C +95°C, unless otherwise noted, Figure
PARAMETER Clock Frequency Clock Pulse-Width Clock Pulse-Width High Free Time Between STOP START Condition START Hold Time START Setup Time Data-In Hold Time Data-In Setup Time Rise Time Both Signals Fall Time Both Signals STOP Setup Time Capacitive Load Each Line EEPROM Write Time SYMBOL fSCL tLOW tHIGH tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO (Note (Note (Note (Note (Note CONDITIONS 0.1CB 0.1CB UNITS
NONVOLATILE MEMORY CHARACTERISTICS
(VCC +2.85V +3.9V, unless otherwise noted.)
PARAMETER EEPROM Write Cycles SYMBOL +70°C CONDITIONS 50,000 UNITS
Note Note Note Note Note Note Note Note Note Note Note Note Note Note
voltages referenced ground. Currents into positive negative. Digital Inputs rail. FETG disconnected Safety Shutdown (FETG) Output section details. Eight ranges allow full-scale range change from 625mV 2.5V. This specification applies expected full-scale value selected range. Comp Ranging byte available full-scale ranges. Eight ranges allow full-scale range change from 312.5mV 1.25V. output impedance DS1863 proportional scale setting. instance, using scale, output impedance would 1.5k. This specification applies expected full-scale value selected range. Ranging byte available full-scale ranges. APC/Quick-Trip Sample Timing section details. Assuming appropriate initial step programmed that would cause power exceed point within steps, bias current will within within time specified binary search time. Guaranteed design. interface timing shown fast-mode (400kHz) operation. This device also backward-compatible with standard-mode timing. CB-total capacitance line picofarads. EEPROM write begins after STOP condition occurs.
Burst-Mode Controller With Integrated Monitoring DS1863
Typical Operating Characteristics
(VCC 3.3V, +25°C, unless otherwise noted.)
SUPPLY CURRENT SUPPLY VOLTAGE
DS1863 toc01
SUPPLY CURRENT TEMPERATURE
3.45 3.40 SUPPLY CURRENT (mA) 3.35 (LSB) 3.30 3.25 3.20 3.15 3.10 3.05 3.00 3.9V 2.85V
DS1863 toc02
-0.2 -0.4 -0.6 -0.8 -1.0
DS1863 toc03
4.00 3.85 3.70 SUPPLY CURRENT (mA) 3.55 3.40 3.25 3.10 2.95 2.80 2.65 2.50 2.85 3.35 3.85 4.35 4.85 5.35 -40°C +25°C +95°C
3.50
TEMPERATURE (°C)
INPUT CODE (DEC)
DS1863 toc04
CALCULATED DESIRED CHANGE VMOD RANGING
DS1863 toc05
DESIRED CALCULATED CHANGE VBMD COMP RANGING
CHANGE VBMD DESIRED VALUE CALCULATED VALUE
DS1863 toc06 DS1863 toc09
(LSB) -0.2 -0.4 -0.6 -0.8 -1.0 INPUT CODE (DEC)
CHANGE VMOD DESIRED VALUE CALCULATED VALUE
RANGING VALUE (DEC)
COMP RANGING (DEC)
MON1-3
DS1863 toc07
MON1-3
MON1-3 (LSB) -0.2 -0.4 -0.6 -0.8 -1.0 VBMD (LSB) USING FACTORY-PROGRAMMED FULL-SCALE VALUE 2.5V
DS1863 toc08
VBMD INDEX
-0.2 -0.4 -0.6 -0.8 -1.0
MON1-3 (LSB) -0.2 -0.4 -0.6 -0.8 -1.0 USING FACTORY-PROGRAMMED FULL-SCALE VALUE 2.5V
MON1-3 INPUT VOLTAGE
MON1-3 INPUT VOLTAGE
INDEX (DEC)
Burst-Mode Controller With Integrated Monitoring DS1863
Description
NAME TX-D N.C. TX-F FETG MON1 MON2 MON3 BIAS DESCRIPTION Burst Enable Input. Triggers sampling Quick-trip monitors. Transmit Disable Input. Disables BIAS outputs. Connection Transmit Fault Output. Open-drain. Output Gate. Signals external Channel MOSFET enable/disable laser's current. Serial Data Serial Clock Input Ground External Analog Inputs. voltage these pins digitized internal analog-to-digital converter read through interface. Alarm warning values assigned interrupt processor based result. Ground Bias Current Output. This current generates bias current reference MAX3643. Modulation Output Voltage. This 8-bit voltage output full-scale ranges from 1.25V 0.3125V. This connected MAX3643's VMSET input control modulation current. Monitor Diode Input (Feedback Voltage, Transmit Power Monitor) Power Supply Input
Burst-Mode Controller With Integrated Monitoring
Block Diagram
DS1863
DS1863 MEMORY ORGANIZATION LOWER MEMORY EEPROM/SRAM INTERFACE CONFIG/RESULTS SYSTEM STATUS BITS ALARM/WARNING COMPARISON RESULTS/THRESHOLDS TABLE EEPROM TABLE EEPROM TABLE EEPROM TABLE EEPROM TABLE EEPROM
SRAM RESET
CONFIGURATION MODULATION TRACKING USER MEMORY USER MEMORY ERROR ALARM CALIBRATION TRAPS
POWER ANALOG VPOA NONMASKABLE INTERRUPT TX-F
MON1 ANALOG MON2 MON3 DIGITAL LIMIT COMPARATOR RESULTS INTERRUPT MASK INTERRUPT LATCH
13-BIT
RIGHT SHIFT
LATCH ENABLE
TEMP SENSOR
INTERRUPT MASK
INTERRUPT LATCH
FETG
SAMPLE CONTROL
BIAS QUICKTRIP
HBIAS QUICK TRIP LIMIT HTXP QUICK TRIP LIMIT LTXP QUICK TRIP LIMIT SETPOINT FROM TRACKING ERROR TABLE 8-BIT W/SCALING
DIGITAL INTEGRATOR
13-BIT
BIAS
DS1863
TX-D MODULATION LOOKUP TABLE (TABLE 04h)
8-BIT W/SCALING
Burst-Mode Controller With Integrated Monitoring DS1863
Typical Operating Circuit
3.3V
INBEN+ BENDIS
OUT+ OUTBIAS-
MAX3643
COMPACT BURST MODE LASER DRIVER BIAS+ MDIN MDOUT BIASMON MON1 MODSET BIASSET BIAS BENOUT MON2 VMSET IMAX VREF VBEST
COMMUNICATION
TX-F TX-D
FAULT OUTPUT DISABLE INPUT
DS1863
TRANSMIT POWER RECEIVE POWER
BURST MODE MON3 MONITOR/CONTROL CIRCUIT FETG
Detailed Description
DS1863 integrates control monitoring functionality required implement system using Maxim's MAX3643 compact burst mode laser driver. compact laser driver solution offers considerable cost benefit integrating control monitoring features power CMOS process, while leaving only high speed portions laser driver
loop's feedback monitor diode (BMD) current, which converted voltage using external resistor. feedback voltage compared 8bit scaleable voltage reference, which determines point system. Scaling reference voltage along with modulation output utilized implement GPON power leveling. DS1863 Lookup Table allow point change function temperature compensate Tracking Error (TE). (Table 05h), entries that determine setting windows between -40°C +100°C. Ranging possible programming single byte Table 02h.
Control
BIAS current controlled Average Power Control (APC) loop. loop uses digital techniques overcome difficulties associated with controlling burst mode systems.
Burst-Mode Controller With Integrated Monitoring
Modulation Control
voltage controlled using internal temperature indexed Lookup Table. output 8-bit scaleable voltage output that interfaces with MAX3643's VMSET input. external resistor ground from MAX3643's MODSET sets maximum current voltage VMSET input produce given output range. This resistor value should chosen produce maximum modulation current laser type requires over temperature. modulation programmed increments over -40°C +102°C range provide temperature compensation laser's modulation. modulation DAC's scaling used (with scaling) implement GPON power leveling with single that works three power levels. Ranging possible programming single byte Table 02h. fied, output will enabled with value determined temperature conversion modulation LUT. When output enabled high, IBIAS output will turned value equal ISTEP (see above). start-up algorithm checks this bias current causes feedback voltage above set-point, does continues increasing BIAS STEP until set-point exceeded. When point exceeded, device will begin binary search quickly reach bias current corresponding proper power level. After binary search completed integrator enabled, single steps taken tightly control average power. quick-trip alarm flags masked until binary search completed. However, BIAS alarm monitored during this time prevent bias output from exceeding IBIAS. During bias current initialization, bias current allowed exceed IBIAS. this occurs during STEP sequence then binary search routine enabled. IBIAS exceeded during binary search, then next smaller step activated. ISTEP binary increments that would cause IBIAS exceed IBIAS taken. Many alarm sources likely trip
DS1863
BIAS Output During Initial Power-Up
power-up modulation bias outputs will remain until above VPOA, temperature conversion been completed, alarm enabled, then conversion above customer defined alarm level cleared alarm. Once these conditions satis-
POWER-UP TIMING
VPOA
VOLTAGE tSEARCH ISTEP ISTEP ISTEP ISTEP BINARY SEARCH INTEGRATOR
BIAS CURRENT
BIAS SAMPLE
Figure DS1863 Power-Up.
Burst-Mode Controller With Integrated Monitoring
during start-up. Masking alarms until completion binary search prevents false alarms. ISTEP programmed customer using Startup Step register. This value should programmed maximum safe current increase that allowable during start-up. this value programmed low, DS1863 will still operate, could take significantly longer algorithm converge hence control average power. fault detected, TX-D toggled re-enable outputs, DS1863 will power following similar sequence initial power only difference that DS1863 already determined present temperature, tINIT time required DS1863 recall points from EEPROM. internal BIAS reference. HTXP/LTXP comparison will check HTXP last bias-update comparison above set-point, LTXP last bias update comparison below set-point. DS1863 programmable comparator sample time based internally generated clock facilitate wide variety external filtering options suitable burst mode transmitter data rates between 155Mbits/s 1250Mbits/s. rising edge burst enable (BEN) triggers sample occur, Sample Rate register determines delay. internal clock asynchronous BEN, causing 100ns uncertainty when first sample will occur following BEN. After first sample occurs, subsequent samples will occur regular interval. following sample rate options available.
MINIMUM TIME REPEATED SAMPLE FROM FIRST PERIOD FOLLOWING SAMPLE (tFIRST) FIRST SAMPLE (tREP) ±50ns 350ns 550ns 750ns 950ns 1350ns 1550ns 1750ns 2150ns 2950ns 3150ns 800ns 1200ns 1600ns 2000ns 2800ns 3200ns 3600ns 4400ns 6000ns 6400ns
DS1863
BIAS Output Function Transmit Disable (TX-D)
TX-D asserted (logic during operation, outputs will immediately turn When TX-D deasserted (logic DS1863 will turn output with value associated with present temperature, initialize IBIAS using same search algorithm done start-up. Soft TX-D (Lower Memory, Register 6Eh) when asserted would allow software control identical TX-D pin.
TX-D TIMING (NORMAL OPERATION) TX-D IBIAS IMOD tOFF tOFF
SR3-SR0
0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b*
*All codes greater than 1001b (1010b-111b) maximum sample time code 1001b.
Figure TX-D Timing (Output Disabled During Normal Operating Conditions).
APC/Quick-Trip Shared Comparator Timing
DS1863's input comparator shared between control loop three quick-trip alarms (HTXP, LTXP HBIAS). comparator polls alarms round-robin multiplexed sequence. every eight comparator readings will used Loop bias current control. other updates will used check HTXP/LTXP (Monitor Diode voltage) HBIAS (MON1) signals against
Comparisons HTXP, LTXP, HBIAS quick-trip alarms will occur during burst enable time. quick-trip alarm that detected will default remain active until subsequent comparator sample shows condition longer exists. second bias current monitor compares DS1863's bias current DAC's code digital value stored IBIAS register. This comparison made every bias current update ensure that high bias current will quickly detected.
Burst-Mode Controller With Integrated Monitoring DS1863
LOOP/QUICK TRIP SAMPLE TIMING tFIRST
BIAS CODE QUICK-TRIP SAMPLE TIMES
LAST BURST'S BIAS SAMPLE
BIAS SAMPLE tREP
BIAS SAMPLE
BIAS SAMPLE
BIAS SAMPLE
BIAS SAMPLE
BIAS SAMPLE H/LTXP SAMPLE HBIAS SAMPLE
BIAS SAMPLE
Figure APC/Quick-Trip Alarm Sample Timing.
Monitors Fault Detection
Monitors Monitoring functions DS1863 include four quicktrip comparators five channels This monitoring combined with interrupt masks determines when/if DS1863 shuts down outputs triggers TX-F FETG outputs. monitoring levels interrupt masks user programmable with exception POA, which trips fixed range non-maskable safety reasons. Four Quick-Trip Monitors Alarms Four quick-trip monitors provided detect potential laser safety issues. These monitor High Bias Current (HBIAS) Transmit Power (LTXP) High Transmit Power (HTXP) Output Current (MAX IBIAS) high transmit power quick-trip registers (HTXP LTXP) thresholds used compare against voltage determine transmit power within specification. HBIAS quick-trip compares MON1 input (generally from MAX3643 bias monitor output) against threshold setting determine present bias current above specification. Bias quick-trip digital comparison that determines Bias Output code indicates bias current above specification. bias current will allowed exceed value this register. When DS1863 detects bias limit will BIAS status hold bias current IBIAS level. quick-trips routed TX-F FETG outputs interrupt masks allow combinations these alarms used trigger these outputs. time FETG triggered DS1863 will also disable outputs.
quick-trip alarm levels masks programmable through interface. Five Monitors Alarms monitors five channels that measure temperature (internal temp sensor), VCC, MON1, MON2, MON3 using analog multiplexer measure them round robin with single ADC. Each channel customer programmable full scale range offset value that will factory programmed default value (see below). Additionally, MON1, MON2, MON3 have ability right shift results bits before results compared alarm thresholds read over bus. This allows customers with specified ranges calibrate full scale factor 1/2n their specified range measure small signals. DS1863 then right shift results bits maintain weight their specification.
Default Monitor Full Scale Ranges
SIGNAL (UNITS) Temperature (oC) MON1, MON2, MON3 SIGNAL 127.996 6.5528 2.4997 7FFF FFF8 FFF8 SIGNAL -128 8000 0000 0000
results (after right shifting, used) compared high alarm thresholds check results exceeded this threshold), alarm thresholds check results below this threshold) warning threshold after each conversion comparisons total), corresponding alarms which used trigger TX-F FETG outputs. These thresholds user programmable interface, masking registers that
Burst-Mode Controller With Integrated Monitoring DS1863
used prevent alarms from triggering TX-F FETG outputs. below more detail TX-F FETG outputs. Timing There five analog channels that digitized round robin fashion order shown Figure total time required convert five channels (see electrical specifications details). Right Shifting Conversion Result weighting digital reading must conform Predetermined Full-Scale (PFS) value defined specification, then right shifting used adjust analog measurement range while maintaining weighting results. DS1863's range wide enough cover requirements; when maximum input value short value, right shifting used obtain greater accuracy. instance, maximum voltage might specified value, only converter's range effective over this range. alternative calibrate ADC's full scale range readable value right-shift value With this implementation, resolution measurement increased factor because result digitally divided right shifting, weight measurement still meets standard. right shift operation converter results carried based contents Right Shift Control Registers (Table Registers 8Fh) EEPROM. Three analog channels: MON1 MON3 each have bits allocated number right shifts. right shift operations allowed will executed part every conversion before results compared high alarm levels, loaded into their corresponding measurement registers 69h. This true during setup internal calibration well during subsequent data conversions.
Transmit Fault (TX-F) Output
TX-F output masking registers five alarms four alarms select which comparisons cause assert. addition, FETG alarm selectable TX-F mask cause TX-F assert. alarms, with exception FETG, will only cause TX-F remain active while alarm condition persists. However, TX-F latch enable TX-F output remain active until cleared TX-F reset bit, TX-D, soft TX-D, power cycling part. FETG output configured trigger TX-F, then indicating that DS1863 shutdown, will require TX-D, soft TX-D, cycling power reset. Quick-trip alarms (with exception BIAS MAX) ignored first 8-10 bias current updates during power Only enabled alarms will activate TX-F. following table shows TX-F function TX-D alarm sources.
TX-F Function TX-D Alarm Sources
VPOA TX-D NON-MASKED TX-F ALARM TX-F
Safety Shutdown (FETG) Output FETG output masking registers (separate from TX-F) five alarms four alarms select which comparisons cause assert. Unlike TX-F,
NORMAL SAMPLE TIMING ROUND-ROBIN CYCLE MON3 TEMP MON1 MON2 MON3 TEMP
Figure Round-Robin Timing. alarm either TX-F FETG output, Round Robin timing will cycle between only TEMP VCC.
Burst-Mode Controller With Integrated Monitoring DS1863
TX-F LATCHED OPERATION DETECTION TX-F FAULT
TX-D TX-F RESET TX-F
TX-F NON-LATCHED OPERATION DETECTION TX-F FAULT
TX-F
Figure DS1863 TX-F Timing.
FETG output always latched case triggered unmasked alarm condition. output polarity programmable allow external MOSFET open during alarms shut laser diode current. FETG output triggers indicating DS1863 shutdown, then requires TX-D, soft TX-D, cycling power reset. Under conditions when analog outputs re-initialized after being disabled, alarms with exception alarm will cleared. alarm must remain active prevent output from attempting operate when inadequate exists operate laser driver. Once adequate present clear alarm, outputs will enabled following same sequence power mentioned before FETG output used disable laser current series MOSFET. This requires that FETG output capable sinking sourcing current. Because DS1863 will know should sink source current before exceeds VPOA, which triggers recall, this output will high impedance when below VPOA. (see "Low Voltage Operation" section details diagram). application circuit must pull-up pull-down resistor this that pulls FETG alarm/shutdown state (high PMOS, NMOS). Once above VPOA, DS1863 will pull FETG output state determined FETG (Table 02h, Register 89h). FETG will NMOS used PMOS used.
FETG BIAS Outputs Function TX-D Alarm Sources
VPOA TX-D NON-MASKED FETG ALARM FETG FETG FETG FETG BIAS OUTPUTS Enabled Disabled Disabled
Determining Alarm Causes Using Interface
determine cause TX-F FETG alarm, system processor read DS1863's Alarm Trap Bytes (ATB) through interface Table 01h). have each alarm. time alarm occurs, regardless mask bit's state, DS1863 sets corresponding ATB. Active bits will remain until written zeros interface. power will zeros until alarms dictate otherwise.
Identification
DS1863 will have hard coded die. registers (Table bytes 86h-87h) assigned this feature. Byte will read identify part DS1863, byte will read (for revision).
Low-Voltage Operation
DS1863 contains Power-On Reset (POR) levels. lower level Digital POD)
Burst-Mode Controller With Integrated Monitoring DS1863
FETG/OUTPUT DISABLE TIMING (FAULT CONDITION DETECTED)
DETECTION FETG FAULT
TX-D
IBIAS
tOFF
IMOD
tOFF
FETG
tFETG:ON
tFETG:OFF
Figure FETG/Modulation Bias Timing (Fault Condition Detected).
higher level Analog start before supply voltage rises above VPOA, outputs disabled (FETG BIAS outputs high impedance, low), SRAM outputs (including Shadowed EEPROM), analog circuitry disabled. When reaches VPOA, recalled, analog circuitry enabled. While remains above VPOA, device normal operating state, responds based nonvolatile configuration. during operation falls below VPOA, still above VPOD, then SRAM will retain settings from first recall, device analog will shut down outputs disabled. FETG will driven alarm state defined FETG (Table 02h, Register 89h). supply voltage recovers back above VPOA, then device will immediately resume normal functioning. supply voltage falls below VPOD, then device SRAM will placed default state another recall will required reload nonvolatile settings. EEPROM recall will occur next time next exceeds VPOA. Figure shows sequence events voltage varies. time above VPOD, interface used determine below VPOA level. This accomplished checking RDYB Status
(6Eh) byte. RDYB when below VPOA; when rises above VPOA RDYB timed (within 500µs) which point part fully functional. Device Addresses sourced from EEPROM (Byte 8Ch, Table memory) default Device Address until exceeds VPOA allowing device address recalled from EEPROM. Power-On Analog (POA) holds DS1863 reset until suitable level (VCC VPOA) part accurately measure with compare analog signals with quicktrip monitors. Because cannot measured when less than VPOA, also asserts alarm, which must cleared conversion that greater than customer programmable limit. This prevents TX-F FETG outputs from glitching during slow power TX-F FETG output will latch until there conversion above limit. alarm non-maskable. TX-F, FETG outputs shuts time below VPOA. Voltage Operation section more information.
Burst-Mode Controller With Integrated Monitoring DS1863
RECALL VPOA RECALL
VPOD
FETG
HIGH IMPEDANCE
NORMAL OPERATION
DRIVEN FETG
HIGH IMPEDANCE
NORMAL OPERATION
DRIVEN FETG
NORMAL OPERATION
DRIVEN FETG
HIGH IMPEDANCE
SEE*
PRECHARGED
RECALLED VALUE
PRECHARGED
RECALLED VALUE
PRECHARGED
Figure DS1863 Digital Analog Power-On Reset.
DS1863 Memory
Memory Organization
DS1863 features memory banks that include following. Lower Memory addressed from contains alarm warning thresholds, flags, masks, several control registers, password entry area (PWE), Table Select byte. Table Select Byte determines which Table (01h-05h) will mapped into upper memory locations. Table primarily contains user EEPROM (with level access) well some Alarm Warning status bytes. Table multifunction space that contains Configuration registers, scaling offset values, Passwords, interrupt registers well other miscellaneous control bytes. Table strictly user EEPROM that protected level password. Table contains temperature indexed Look Table (LUT) control modulation voltage. modulation programmed increments over -40°C +102°C range. Access this register protected level password. Table contains another which allows point change function temperature compensate Tracking Error (TE). This LUT, entries that determine setting windows between -40°C 100°C. Access this register protected level password.
Complete detail each byte's function, well Read/Write permissions each Byte each table provided Register Descriptions sections.
Shadowed EEPROM
Many nonvolatile (NV) memory locations (listed within Detailed Register Description section) actually Shadowed-EEPROM which controlled SEEB Table 02h, Byte 80h. DS1863 incorporates Shadowed EEPROM memory locations memory addresses that rewritten many times. default Shadowed EEPROM Bit, SEEB, these locations ordinary EEPROM. setting SEEB these locations function like SRAM cells, which allow infinite number write cycles without concern wearing EEPROM. This also eliminates requirement EEPROM write time, tWR. Because changes made with SEEB enabled affect EEPROM, these changes retained through power cycles. power-up value last value written with SEEB disabled. This function used limit number EEPROM writes during calibration change monitor thresholds periodically during normal operation helping reduce number times EEPROM written. Memory description indicates which locations shadowed-EEPROM.
Burst-Mode Controller With Integrated Monitoring DS1863
SLAVE ADDRESS LOWER MEMORY
DIGITAL DIAGNOSTIC FUNCTIONS
PASSWORD ENTRY (PWE) BYTES) TABLE SELECT BYTE
TABLE LEVEL ACCESS EEPROM (120 BYTES)
TABLE CONFIGURATION CONTROL
TABLE LEVEL ACCESS EEPROM (128 BYTES)
TABLE MODULATION VOLTAGE CONTROL TEMPERATURE INDEXED
TABLE TRACKING ERROR TEMPERATURE INDEXED CONTROL SET-POINT
EMPTY MISC. CONTROL BITS
Figure DS1863 Memory Map.
Definitions
Master Device: master device controls slave devices bus. master device generates clock pulses, START STOP conditions. Slave Devices: Slave devices send receive data master's request. Idle Busy: Time between STOP START conditions when both inactive their logic-high states. When idle often initiates low-power mode slave devices. START Condition: START condition generated master initiate data transfer with slave.
Transitioning from high while remains high generates START condition. timing diagram applicable timing. STOP Condition: STOP condition generated master data transfer with slave. Transitioning from high while remains high generates STOP condition. timing diagram applicable timing. Repeated START Condition: master repeated START condition data transfer indicate that will immediately initiate data transfer following current one. Repeated STARTS commonly used during read operations identify
Burst-Mode Controller With Integrated Monitoring
specific memory address begin data transfer. repeated START condition issued identically normal START condition. timing diagram applicable timing. Write: Transitions must occur during state SCL. data must remain valid unchanged during entire high pulse plus setup hold-time requirements (Figure Data shifted into device during rising edge SCL. Read: write operation, master must release line proper amount setup time before next rising edge during read. device shifts each data falling edge previous pulse data valid rising edge current pulse. Remember that master generates clock pulses including when reading bits from slave. Acknowledgement (ACK NACK): Acknowledgement (ACK) Acknowledge (NACK) always transmitted during byte transfer. device receiving data (the master during read slave during write operation) performs transmitting zero during bit. device performs NACK transmitting during bit. Timing NACK identical other writes. acknowledgment that device properly receiving data. NACK used terminate read sequence indication that device receiving data. Byte Write: byte write consists bits information transferred from master slave (most significant first) plus 1-bit acknowledgement from slave master. bits transmitted master done according write definition acknowledgement read using read definition. Byte Read: byte read 8-bit information transfer from slave master plus 1-bit NACK from master slave. bits information that transferred (most significant first) from slave master read master using read definition, master transmits using write definition receive additional data bytes. master must NACK last byte read terminate communication slave will return control master. Slave Address Byte: Each slave responds slave addressing byte (Figure sent immediately following START condition. slave address byte contains slave address most significant bits least significant bit. DS1863's slave address configured value between using Device Address Byte (Table 02h, Register 8Ch). user also ASEL (Table 02h, Register 89h) this address active. default address (see Figure 10). writing correct slave address with master indicates will write data slave. master will read data from slave. incorrect slave address written, DS1863 will assume master communicating with another device ignore communications until next START condition sent. Memory Address: During write operation, master must transmit memory address identify memory location where slave store data. memory address always second byte transmitted during write operation following slave address byte.
DS1863
tBUF tLOW
tHD:STA
tHD:STA STOP START tHD:DAT NOTE: TIMING REFERENCED VIL(MAX) VIH(MIN). tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure Timing Diagram.
Burst-Mode Controller With Integrated Monitoring
SLAVE ADDRESS*
READ/WRITE
DEFAULT SLAVE ADDRESS SHOWN, HOWEVER CHANGED USING DEVICE ADDRESS BYTE (TABLE 02h, BYTE 8Ch)., ASEL BIT.
Figure DS1863 Slave Address Byte (Default)
Acknowledge Polling: time EEPROM location written, DS1863 requires EEPROM write time (tW) after STOP condition write contents byte data EEPROM. During EEPROM write time, device will acknowledge slave address because busy. possible take advantage that phenomenon repeatedly addressing DS1863, which allows next page written soon DS1863 ready receive data. alternative acknowledge polling wait maximum period elapse before attempting write again device. EEPROM Write Cycles: When EEPROM writes occur memory, DS1863 will write three EEPROM memory locations, even only single byte modified. Because three bytes written, bytes that were modified during write transaction still subject write cycle. This result three bytes being worn over time writing single byte repeatedly. DS1863's EEPROM write cycles specified Memory Characteristics table. specification shown worst-case temperature. zero-crossing detection enabled, EEPROM write cycles cannot begin until after zero-crossing detection complete. Reading Single Byte from Slave: read single byte from slave, master generates START condition, writes slave address byte with reads data byte with NACK indicate transfer, generates STOP condition. When single byte read, will always Potentiometer value. Reading Multiple Bytes from Slave: read operation used read multiple bytes with single transfer. When reading bytes from slave, master simply ACKs data byte desires read another byte before terminating transaction. After master reads last byte, NACKs indicate transfer generates STOP condition. first byte read will Potentiometer Wiper Setting. next byte will Potentiometer Wiper Setting. third byte Configuration Register byte. issued master following Configuration Register byte, then DS1863 will send Potentiometer Wiper Setting again. This round robin reading will occur long each byte read followed from master.
DS1863
Communication
Writing Single Byte Slave: master must generate START condition, write slave address byte (R/W write byte data, generate STOP condition. master must read slave's acknowledgement during byte write operations. Writing Multiple Bytes Slave: write multiple bytes slave, master generates start condition, writes slave address byte (R/W writes memory address, writes data bytes, generates stop condition. DS1863 writes bytes page row) with single write transaction. This internally controlled address counter that allows data written consecutive addresses without transmitting memory address before each data byte sent. address counter limits write 8-byte page (one memory map). Attempts write additional pages memory without sending stop condition between pages results address counter wrapping around beginning present row. Example: 3-byte write starts address writes three data bytes (11h, 22h, 33h) three "consecutive" addresses. result that addresses would contain 22h, respectively, third data byte, 33h, would written address 00h. prevent address wrapping from occurring, master must send stop condition page, then wait bus-free EEPROM-write time elapse. Then master generate start condition, write slave address byte (R/W first memory address next memory before continuing write data.
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory Register
This register shows each byte/word terms memory. first byte located memory address (hexadecimal) left most column. Each subsequent byte one/ memory locations beyond previous byte/word's address. total eight bytes present each row. more information about each these bytes corresponding register description.
LOWER MEMORY (HEX)
NAME THRESHOLD0 THRESHOLD1 THRESHOLD2 THRESHOLD3 THRESHOLD4
WORD BYTE BYTE
WORD BYTE BYTE
WORD BYTE BYTE
WORD BYTE BYTE
TEMP ALARM ALARM MON1 ALARM MON2 ALARM MON3 ALARM
TEMP ALARM ALARM MON1 ALARM MON2 ALARM MON3 ALARM VALUE
TEMP WARN WARN MON1 WARN MON2 WARN MON3 WARN
TEMP WARN WARN MON1 WARN MON2 WARN MON3 WARN
SHADOWED
VALUES0 VALUES1 ALARM/WARN
TEMP VALUE MON3 VALUE ALARM2
MON1 VALUE RESERVED WARN2
MON2 VALUE STATUS UPDATE
RESERVED ALARM0
ALARM3 RESERVED
ALARM1 RESERVED
WARN3
RESERVED
TABLE SELECT
RESERVED
Access Code Read Access Write Access
each bit/byte separately
DS1863 Hardware
mode
<10>
<11>
Burst-Mode Controller With Integrated Monitoring DS1863
Table 01h. Register
TABLE (PW1) (HEX)
<11>
NAME
WORD BYTE
ALARM3
WORD BYTE
ALARM1
WORD BYTE
WARN3
WORD BYTE BYTE
BYTE
ALARM2
BYTE
ALARM0
BYTE
ALARM TRAP
WARN2
RESERVED
Access Code Read Access Write Access
each bit/byte separately
DS1863 Hardware
mode
<10>
<11>
Burst-Mode Controller With Integrated Monitoring
Table 02h. Register
TABLE (PW2) (HEX) C0-F7
DS1863
NAME CONFIG0 CONFIG1 SCALE0 SCALE1
WORD BYTE
WORD BYTE
WORD BYTE
WORD BYTE
<10>
BYTE
BYTE
BYTE
BYTE
<10>
MODE
TINDEX
BIAS DAC2
BIAS DAC2
DEVICE
DEVICE RSHIFT0
UPDATE RATE
CONFIG
START-UP STEP
RANGING
DEVICE ADDRESS
COMP RANGING
RSHIFT1
RESERVED MON3 SCALE RESERVED MON3 OFFSET FETG EMPTY IBIAS0 FETG EMPTY IBIAS1
SCALE RESERVED OFFSET RESERVED TX-F EMPTY MAN_CNTL TX-F EMPTY RESERVED
MON1 SCALE RESERVED MON1 OFFSET RESERVED HTXP EMPTY RESERVED LTXP EMPTY RESERVED
MON2 SCALE RESERVED MON2 OFFSET INTERNAL TEMP OFFSET* HBIAS EMPTY RESERVED IBIAS EMPTY RESERVED
OFFSET0 OFFSET1
VALUE INTERRUPT EMPTY IBIAS
*The Final Result must XOR'ed with BB40h before writing this register.
Access Code Read Access Write Access
each bit/byte separately
DS1863 Hardware
mode
<10>
<11>
Burst-Mode Controller With Integrated Monitoring DS1863
Table 03h. Register
TABLE (PW2) (HEX) NAME
WORD BYTE BYTE
WORD BYTE BYTE
WORD BYTE BYTE
WORD BYTE BYTE
Access Code Read Access Write Access
each bit/byte separately
DS1863 Hardware
mode
<10>
<11>
Burst-Mode Controller With Integrated Monitoring
Table 04h. Register
TABLE (LUT MOD) (HEX) NAME
DS1863
WORD BYTE BYTE
WORD BYTE BYTE
WORD BYTE BYTE
WORD BYTE BYTE
LUT4 LUT4 LUT4 LUT4 LUT4 LUT4 LUT4 LUT4 LUT4
Table 05h. Register
TABLE (LUT APC) (HEX) NAME
WORD BYTE BYTE
WORD BYTE BYTE
WORD BYTE RESERVED BYTE RESERVED
WORD BYTE RESERVED BYTE RESERVED
LUT5 LUT5 LUT5 LUT5 LUT5
Access Code Read Access Write Access
each bit/byte separately
DS1863 Hardware
mode
<10>
<11>
SPRINGER
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory Registers Description
Lower Memory Register 01h: Temp Alarm FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
7FFFh Nonvolatile (SEE)
bit0
bit7
Temperature measurements above this complement threshold will corresponding alarm bit. Measurements equal below this threshold will clear alarm bit. Lower Memory Register 03h: Temp Alarm FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
8000h Nonvolatile (SEE)
bit0
bit7
Temperature measurements above this complement threshold will corresponding alarm bit. Measurements equal below this threshold will clear alarm bit. Lower Memory Register 05h: Temp Warn FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
7FFFh Nonvolatile (SEE)
bit0
bit7
Temperature measurements above this complement threshold will corresponding warning bit. Measurements equal below this threshold will clear warning bit.
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory Register 07h: Temp Warn FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
8000h Nonvolatile (SEE)
bit0
bit7
Temperature measurements below this complement threshold will corresponding warning bit. Measurements above this threshold will clear warning bit. Lower Memory Register 09h: Alarm FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
FFFFh Nonvolatile (SEE)
bit0
bit7
Voltage measurements input above this unsigned threshold will corresponding alarm bit. Measurements below this threshold will clear alarm bit. Lower Memory Register 0Bh: Alarm FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
0000h Nonvolatile (SEE)
bit0
bit7
Voltage measurements below above this unsigned threshold will corresponding alarm bit. Measurements above this threshold will clear alarm bit.
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory Register 0Dh: Alarm FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
FFFFh Nonvolatile (SEE)
bit0
bit7
Voltage measurements input above this unsigned threshold will corresponding warning bit. Measurements below this threshold will clear warning bit. Lower Memory Register 0Fh: Warn FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
0000h Nonvolatile (SEE)
bit0
bit7
Voltage measurements below above this unsigned threshold will corresponding warning bit. Measurements above this threshold will clear warning bit. Lower Memory Register 11h: MON1 Alarm FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
FFFFh Nonvolatile (SEE)
bit0
bit7
Voltage measurements MON1 input above this unsigned threshold will corresponding alarm bit. Measurements below this threshold will clear alarm bit.
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory Register 13h: MON1 Alarm FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
0000h Nonvolatile (SEE)
bit0
bit7
Voltage measurements MON1 input below this unsigned threshold will corresponding alarm bit. Measurements above this threshold will clear alarm bit. Lower Memory Register 15h: MON1 Warn FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
FFFFh Nonvolatile (SEE)
bit0
bit7
Voltage measurements MON1 input above this unsigned threshold will corresponding warning bit. Measurements below this threshold will clear warning bit. Lower Memory Register 17h: MON1 Warn FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
0000h Nonvolatile (SEE) bit0
bit7
Voltage measurements MON1 input below this unsigned threshold will corresponding warning bit. Measurements above this threshold will clear warning bit.
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory Register 19h: MON2 Alarm FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
FFFFh Nonvolatile (SEE)
bit0
bit7
Voltage measurements MON2 input above this unsigned threshold will corresponding alarm bit. Measurements below this threshold will clear alarm bit. Lower Memory Register 1Bh: MON2 Alarm FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
0000h Nonvolatile (SEE)
bit0
bit7
Voltage measurements MON2 input below this unsigned threshold will corresponding alarm bit. Measurements above this threshold will clear alarm bit. Lower Memory Register 1Dh: MON2 Alarm FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
FFFFh Nonvolatile (SEE)
bit0
bit7
Voltage measurements MON2 input above this unsigned threshold will corresponding warning bit. Measurements below this threshold will clear warning bit.
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory Register 1Fh: MON2 Warn FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
0000h Nonvolatile (SEE)
bit0
bit7
Voltage measurements MON2 input below this unsigned threshold will corresponding warning bit. Measurements above this threshold will clear warning bit. Lower Memory Register 21h: MON3 Alarm FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
FFFFh Nonvolatile (SEE)
bit0
bit7
Voltage measurements MON3 input above this unsigned threshold will corresponding alarm bit. Measurements below this threshold will clear alarm bit. Lower Memory Register 23h: MON3 Alarm FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
0000h Nonvolatile (SEE)
bit0
bit7
Voltage measurements MON3 input below this unsigned threshold will corresponding alarm bit. Measurements above this threshold will clear alarm bit.
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory Register 25h: MON3 Warn FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
FFFFh Nonvolatile (SEE)
bit0
bit7
Voltage measurements MON3 input above this unsigned threshold will corresponding warning bit. Measurements below this threshold will clear warning bit. Lower Memory Register 27h: MON3 Warn FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
0000h Nonvolatile (SEE)
bit0
bit7
Voltage measurements MON3 input below this unsigned threshold will corresponding warning bit. Measurements above this threshold will clear warning bit. Lower Memory Register 2Fh: Shadowed EEPROM FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 28h-2Fh bit7 Shadowed EEPROM memory (see details Memory section). level access controlled data user. Nonvolatile (SEE) bit0
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory Register 5Fh: FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: 30h-5Fh bit7 Nonvolatile EEPROM memory. level access controlled data user. Lower Memory Register 61h: Temp Value POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE:
Nonvolatile (EE) bit0
0000h Volatile
bit0
bit7 Signed complement Direct-to-Temperature measurement. Lower Memory, Register 62h-63h: Value Lower Memory, Register 64h-65h: MON1 Value Lower Memory, Register 66h-67h: MON2 Value Lower Memory, Register 68h-69h: MON3 Value POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE:
0000h Volatile
bit0
bit7 Unsigned voltage measurement.
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory, Register Reserved POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE These registers reserved. value when read 00h. Lower Memory, Register 6Eh: Status POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE Write Access FETG STATUS bit7 FETG STATUS: Reflects active state FETG. Bias modulation outputs enabled. FETG output asserted disable bias modulation outputs. SOFT FETG: (Default) Force bias modulation outputs their states asserts FETG output. Reserved (Default TX-F RESET: Does affect TX-F output (Default). Resets latch TX-F output. This self clearing after reset. SOFT TX-D: This allows software control that identical TX-D pin. Please section TX-D further information. It's value wired OR'ed with logic value TX-D pin. Internal TX-D signal equal external TX-D pin. Internal TX-D signal high. x000 0x0x Below Volatile SOFT FETG RESERVED TX-F RESET SOFT TX-D TX-F STATUS RESERVED RDYB bit0
bit7
bit6 bit5
bit4
bit3
TX-F STATUS: Reflects active state TX-F. bit2 bit1 bit0 TX-F active. TX-F active. RESERVED (Default RDYB: Ready Bar. above POA. below communicate over bus.
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory, Register 6Fh: Update POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE TEMP bit7 DS1863 Hardware Volatile MON1 MON2 MON3 RESERVED RESERVED RESERVED bit0
Status completed conversions. Power-On, these bits cleared will each conversion completed. These bits cleared that completion conversion verified. TEMP RDY: Temperature conversion ready (Default). Temperature conversion ready. RDY: bit6 conversion ready (Default). conversion ready. bit5 MON1 RDY: MON1 conversion ready (Default). MON1 conversion ready. MON2 RDY: MON2 conversion ready (Default). MON2 conversion ready. MON3 RDY: MON3 conversion ready (Default). MON3 conversion ready. bit2:0 RESERVED
bit7
bit4
bit3
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory, Register 70h: Alarm3 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE TEMP bit7 Alarm Status Bits TEMP High Alarm Status Temperature measurement. (Default) Last measurement equal below threshold setting. Last measurement above threshold setting. bit6 TEMP Alarm Status Temperature measurement. (Default) Last measurement equal above threshold setting. Last measurement below threshold setting. High Alarm Status measurement. bit5 (Default) Last measurement equal below threshold setting. Last measurement above threshold setting. Alarm Status measurement. This when supply below trip point value. will clear itself when measurement completed value above threshold. Last measurement equal above threshold setting. (Default) Last measurement below threshold setting. MON1 High Alarm Status MON1 measurement. (Default) Last measurement equal below threshold setting. Last measurement above threshold setting. bit2 MON1 Alarm Status MON1 measurement. (Default) Last measurement equal above threshold setting. Last measurement below threshold setting. MON2 High Alarm Status MON2 measurement. (Default) Last measurement equal below threshold setting. Last measurement above threshold setting. bit0 MON2 Alarm Status MON2 measurement. (Default) Last measurement equal above threshold setting. Last measurement below threshold setting. Volatile TEMP MON1 MON1 MON2 MON2 bit0
bit7
bit4
bit3
bit1
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory, Register 71h: Alarm2 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE MON3 bit7 Alarm Status Bits MON3 High Alarm Status MON3 measurement. (Default) Last measurement equal below threshold setting. Last measurement above threshold setting. bit6 bit5:0 MON3 Alarm Status MON3 measurement. (Default) Last measurement equal above threshold setting. Last measurement below threshold setting. RESERVED Volatile MON3 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED bit0
bit7
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory, Register 72h: Alarm1 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE RESERVED bit7 Alarm Status Bits bit7:4 bit3 bit2 bit1 RESERVED BIAS High Alarm Status Bias; Fast Comparison. (Default) Last measurement equal below threshold setting. Last measurement above threshold setting. RESERVED TX-P High Alarm Status TX-P; Fast Comparison. (Default) Last measurement equal below threshold setting. Last measurement above threshold setting. TX-P Alarm Status TX-P; Fast Comparison. Last measurement equal above threshold setting. Last measurement below threshold setting. Volatile RESERVED RESERVED RESERVED BIAS RESERVED TX-P TX-P bit0
bit0
Lower Memory, Register 73h: Alarm0 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE RESERVED bit7 Alarm Status Bits bit7:4 bit3 RESERVED BIAS MAX: Maximum digital setting IBIAS. (Default) value IBIAS equal below IBIAS setting. Requested value IBIAS greater than IBIAS setting. bit2:0 RESERVED Volatile RESERVED RESERVED RESERVED BIAS RESERVED RESERVED RESERVED bit0
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory, Register 74h: Warn3 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE TEMP bit7 Warning Status Bits bit7 TEMP High Warning Status Temperature measurement. (Default) Last measurement equal below threshold setting. Last measurement above threshold setting. bit6 TEMP Warning Status Temperature measurement. (Default) Last measurement equal above threshold setting. Last measurement below threshold setting. bit5 High Warning Status measurement. (Default) Last measurement equal below threshold setting. Last measurement above threshold setting. bit4 Warning Status measurement. This when supply below trip point value. will clear itself when measurement completed value above threshold. Last measurement equal above threshold setting. (Default) Last measurement below threshold setting. bit3 MON1 High Warning Status MON1 measurement. (Default) Last measurement equal below threshold setting. Last measurement above threshold setting. MON1 Warning Status MON1 measurement. (Default) Last measurement equal above threshold setting. Last measurement below threshold setting. bit1 MON2 High Warning Status MON2 measurement. (Default) Last measurement equal below threshold setting. Last measurement above threshold setting. bit0 MON2 Warning Status MON2 measurement. (Default) Last measurement equal above threshold setting. Last measurement below threshold setting. Volatile TEMP MON1 MON1 MON2 MON2 bit0
bit2
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory, Register 75h: Warn2 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE MON3 bit7 Warning Status Bits bit7 MON3 High Warning Status Mon3 measurement. (Default) Last measurement equal below threshold setting. Last measurement above threshold setting. bit6 MON3 Warning Status Mon3 measurement. (Default) Last measurement equal above threshold setting. Last measurement below threshold setting. RESERVED Volatile MON3 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED bit0
bit5
Lower Memory, Register 7Ah: Reserved POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE These registers reserved. value when read 00h. Lower Memory, Register 7Eh: Password Entry (PWE) FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE FFFF FFFFh Volatile
bit0
bit7
Password Entry. There passwords DS1863. Each password bytes long. lower level password (PW1) will have access normal user plus those made available with PW1. higher level password (PW2) will have access plus those made available with PW2. values passwords reside inside memory. Power bits reads this location
Burst-Mode Controller With Integrated Monitoring DS1863
Lower Memory Register 7Fh: Table Select (TBL SEL) POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE
Volatile bit0
bit7
upper memory tables (Table 01h-Table 05h) DS1863 accessible writing correct table value this register.
Burst-Mode Controller With Integrated Monitoring DS1863
Table 01h, Registers
Table 01h, Register F7h: EEPROM POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80h-F7h bit7 EEPROM level access. Nonvolatile(EE) bit0
Table 01h, Register F8h: Alarm3 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE TEMP bit7 Layout identical Alarm3 Lower Memory Register with exceptions. alarm power-on. These bits latched. They cleared power-down write with access. Volatile TEMP MON1 MON1 MON2 MON2 bit0
Table 01h, Register F9h: Alarm2 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE MON3 bit7 Layout identical Alarm2 Lower Memory Register with exception. These bits latched. They cleared power-down write with access. Volatile MON3 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED bit0
Burst-Mode Controller With Integrated Monitoring DS1863
Table 01h, Register FAh: Alarm1 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE BIAS bit7 Layout identical Alarm1 Lower Memory Register with exception. These bits latched. They cleared power-down write with access. Volatile TX-P TX-P RESERVED RESERVED RESERVED RESERVED RESERVED bit0
Table 01h, Register FBh: Alarm0 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE RESERVED bit7 Layout identical Alarm0 Lower Memory Register with exception. These bits latched. They cleared power-down write with access Volatile RESERVED RESERVED RESERVED BIAS RESERVED RESERVED RESERVED bit0
Table 01h, Register FCh: Warn3 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE TEMP bit7 Layout identical Warn3 Lower Memory Register with exceptions. Warning power-on. These bits latched. They cleared power-down write with access. Volatile TEMP MON1 MON1 MON2 MON2 bit0
Burst-Mode Controller With Integrated Monitoring DS1863
Table 01h, Register FDh: Warn2 POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE MON3 bit7 Layout identical Warn2 Lower Memory Register with exception. These bits latched. They cleared power-down write with access. Volatile MON3 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED bit0
Table 01h, Register FFh: Reserved POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE These registers reserved. Volatile
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Registers
Table 02h, Register 80h: Mode POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE SEEB bit7 Volatile RESERVED RESERVED RESERVED MOD-EN APC-EN BIAS-EN bit0 SEEB: Enables EEPROM writes bytes Table (Default). Disables EEPROM writes bytes during configuration, that configuration part delayed cycle time. Once values known, write this write locations again data written EEPROM. RESERVED AEN: temperature calculated index value Index') write-able user updates calculated indexes disabled. This allows user interactively test their modules controlling indexing look-up tables. recalled values from LUTs will appear registers after next completion temperature conversion (just like would happen auto mode). Both DACs will update same time (just like auto mode). Enables auto control (Default). MOD-EN: "MOD DAC" write-able user recalls disabled. This allows user interactively test their modules writing value modulation. output updated with value write cycle. Stop condition write cycle. Enables auto control modulation (Default). APC-EN: "APC DAC" write-able user recalls disabled. This allows user interactively test their modules writing value reference. output updated with value write cycle. Stop condition write cycle. Enables auto control reference (Default). BIAS-EN: "BIAS DAC" controlled user open loop. "BIAS DAC" value written "MAN IBIAS" Register. values that written "MAN IBIAS" greater than "MAX IBIAS" register setting updated will "BIAS MAX" alarm bit. "BIAS DAC" register will continue reflect value Bias DAC. This allows user interactively test their modules writing value bias. output updated with value write cycle "MAN IBIAS" register. Stop condition write cycle. Enables auto control feedback (Default).
bit7
bit6:4
bit3
bit2
bit1
bit0
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register 81h: Tindex POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE bit7 (AEN Volatile bit0
Tindex
Temperature 40°C
Holds calculated index based Temperature Measurement. This index used address during Look-Up Tables 05h. Table 04h, exact address value Tindex used. Table address used calculated follows
Tindex
Table 02h, Register 82h: POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE bit7 (MOD-EN Volatile bit0
digital value used recalled from Table adjusted memory address found Tindex. address used calculated follows
Tindex
TEMP
This register updated Temperature conversion. Table 02h, Register 83h: POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE
(APC-EN Volatile bit0
bit7
digital value used reference recalled from Table memory address found Index'. This register updated Temperature conversion.
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register 85h: BIAS FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE bit7 digital value used IBIAS. Table 02h, Register 86h: Device FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE bit7 Hard wired show device Table 02h, Register 87h: Device FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE bit7 Hard wired connections show Device Version. Device Version DEVICE VERSION bit0 bit0 (BIAS-EN Volatile bit0
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register 88h: Update Rate FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE Nonvolatile (SEE)
Defines update rate comparison control.
bit7
SR(3:0) bit0
bit7:4 bit3:0
SR(3:0) 4-bit update rate comparison control.
SR3-SR0
MINIMUM TIME REPEATED SAMPLE FROM FIRST PERIOD FOLLOWING SAMPLE (tFIRST) FIRST SAMPLE (tREP) ±50ns 350ns 550ns 750ns 950ns 1350ns 1550ns 1750ns 2150ns 2950ns 3150ns 800ns 1200ns 1600ns 2000ns 2800ns 3200ns 3600ns 4400ns 6000ns 6400ns
0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b*
*All codes greater than 1001b (1010b-111b) maximum sample time code 1001b.
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register 89h: Config FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE Nonvolatile (SEE)
FETG bit7
TX-F
RESERVED
ASEL
RESERVED
RESERVED
RESERVED
RESERVED bit0
Configure memory location polarity digital outputs. FETG DIR: Chooses direction polarity FETG output normal operation. bit7 Under normal operation, FETG will pulled low. (Default) Under normal operation, FETG will pulled high. TX-F alarm bits will immediately reflect status last comparison. (Default) bit6 alarm bits latched until cleared TX-D transition Power-down. alarm enabled either FETG TX-F then latching disabled until after first measurement made above set-point allow proper operation during slow power-on cycles. RESERVED ASEL: Address SELect. Device Address (Default). Device-Address equal value found byte `device_address' (Table 02h, 8Ch). RESERVED
bit5
bit4
bit3:0
Table 02h, Register 8Ah: Startup Step FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: bit7 This value will define maximum allowed step upper bits IBIAS output during start-up. Nonvolatile (SEE) bit0
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register 8Bh: Ranging FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: RESERVED bit7 lower nibble this byte controls Full-Scale range Modulation bit7:3 bit2:0 RESERVED (Default RANGING: 3-bit value select output voltage VMOD. Default 0006 creates 1.25V. Nonvolatile (SEE) RESERVED RESERVED RESERVED RESERVED MOD2 MOD1 MOD0 bit0
MOD2 MOD0 000b 001b 010b 011b 100b 101b 110b 111b
1.25V 80.05 66.75 50.13 40.16 33.5 28.75 25.18
VOLTAGE 1.250 1.001 0.833 0.627 0.502 0.419 0.359 0.315
Table 02h, Register 8Ch: Device Address FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: bit7 Don't care. This value becomes Device address main memory when ASEL (Table 02h, 89h) set. Nonvolatile (SEE) bit0
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register 8Dh: Comp Ranging FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: RESERVED bit7 Nonvolatile (SEE) RESERVED RESERVED RESERVED RESERVED APC2 APC1 APC0 bit0
This byte controls Full-Scale range Quick-Trip monitoring reference well closed loop monitoring APC. bit7:3 bit2:0 RESERVED (Default RANGING: 3-bit value select comparison voltage with APC. Default 000b creates voltage 2.5V.
APC2 APC0 000b 001b 010b 011b 100b 101b 110b 111b
2.5V 80.07 66.79 50.18 40.22 33.57 28.82 25.26
VOLTAGE 2.500 2.002 1.670 1.255 1.006 0.839 0.721 0.632
Table 02h, Register 8Eh: Right Shift1 FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: RESERVED bit7 Nonvolatile (SEE) MON1_2 MON1_1 MON1_0 RESERVED MON2_2 MON2_1 MON2_0 bit0
Allows right-shifting final answer MON1 MON2 voltage measurements. This allows scaling measurements smallest Full-scale voltage then right-shifting final result reading weighted correct LSB.
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register 8Fh: Right Shift0 FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: RESERVED bit7 Nonvolatile (SEE) MON3_2 MON3_1 MON3_0 RESERVED RESERVED RESERVED RESERVED bit0
Allows right-shifting final answer MON3 voltage measurements. This allows scaling measurements smallest full-scale voltage then right-shifting final result reading weighted correct LSB. Table 02h, Register 91h: Reserved FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: These registers reserved. Table 02h, Register 93h: Scale FACTORY CALIBRATED READ ACCESS WRITE ACCESS MEMORY TYPE
0000h Nonvolatile (SEE)
Nonvolatile (SEE)
bit0
bit7 Controls Scaling Gain measurements. factory-calibrated value will produce voltage 6.5536V.
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register 95h: MON1 Scale Table 02h, Register 97h: MON2 Scale Table 02h, Register 99h: MON3 Scale FACTORY CALIBRATED READ ACCESS WRITE ACCESS MEMORY TYPE
Nonvolatile (SEE)
bit0
bit7
Controls Scaling Gain MON1, MON2, MON3 measurements. default hexadecimal value will correspond 2.5V. factory-calibrated value will produce voltage 2.5V. Table 02h, Register A1h: Reserved FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers reserved. Table 02h, Register A3h: Offset FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE
0000h Nonvolatile (SEE)
0000h Nonvolatile (SEE)
bit0
bit7 Allows offset control measurement desired.
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register A5h: MON1 Offset Table 02h, Register A7h: MON2 Offset Table 02h, Register A9h: MON3 Offset FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE
0000h Nonvolatile (SEE)
bit0
bit7 Allows offset control MON1, MON2, MON3 measurement desired. Table 02h, Register ADh: Reserved FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE These registers reserved. Table 02h, Register AFh: Temp Offset FACTORY CALIBRATED READ ACCESS WRITE ACCESS MEMORY TYPE
0000 0000h Nonvolatile (SEE)
Nonvolatile (SEE)
bit0
bit7 Allows offset control Temp measurement desired. Final Result must XOR'ed with BB40h before writing this register. Factory calibration contains desired value reading temperature degrees celcius.
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register B3h: FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE
FFFF FFFFh Nonvolatile (SEE)
bit0
bit7
value compared against value written this location enable access. power-on, value ones. Thus writing these bytes ones grants access power-up without writing password entry. reads this register 00h. Table 02h, Register B7h: FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE
FFFF FFFFh Nonvolatile (SEE)
bit0
bit7
value compared against value written this location enable access. power-on, value ones. Thus writing these bytes ones grants access power-up without writing password entry. reads this register 00h.
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register B8h: FETG Enable1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE Nonvolatile (SEE)
TEMP bit7
MON1
MON2
MON3
RESERVED
RESERVED
RESERVED bit0
Configures maskable interrupt FETG pin. TEMP Enables/Disables active interrupts FETG temperature measurements outside threshold limits. Disable (Default) Enable Enables/Disables active interrupts FETG measurements outside threshold limits. Disable (Default) Enable MON1 Enables/Disables active interrupts FETG MON1 measurements outside threshold limits. Disable (Default) Enable MON2 Enables/Disables active interrupts FETG MON2 measurements outside threshold limits. Disable (Default) Enable MON3 Enables/Disables active interrupts FETG MON3 measurements outside threshold limits. Disable (Default) Enable RESERVED (Default
bit7
bit6
bit5
bit4
bit3
bit2:0
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register B9h: FETG Enable0 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE Nonvolatile (SEE)
TXP-HI bit7
TXP-LO
BIAS-HI
BIAS
RESERVED
RESERVED
RESERVED
RESERVED bit0
Configures maskable interrupt FETG pin. TX-P-HI Enables/Disables active interrupts FETG Tx-P fast comparisons above threshold limit. Disable (Default) Enable. TX-P-LO Enables/Disables active interrupts FETG Tx-P fast comparisons below threshold limit. Disable (Default) Enable BIAS-HI Enables/Disables active interrupts FETG BIAS fast comparisons above threshold limit. Disable (Default) Enable BIAS Enables/Disables active interrupts FETG BIAS fast comparisons below threshold limit. bit4 Disable (Default) Enable RESERVED (Default
bit7
bit6
bit5
bit3:0
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register BAh: TX-F Enable1 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE Nonvolatile (SEE)
TEMP bit7
MON1
MON2
MON3
RESERVED
RESERVED
RESERVED bit0
Configures maskable interrupt TX-F pin. TEMP Enables/Disables active interrupts TX-F temperature measurements outside threshold limits. Disable (Default) Enable Enables/Disables active interrupts TX-F measurements outside threshold limits. Disable (Default) Enable MON1 Enables/Disables active interrupts TX-F MON1measurements outside threshold limits. Disable (Default) Enable MON2 Enables/Disables active interrupts TX-F MON2 measurements outside threshold limits. Disable (Default) Enable. MON3 Enables/Disables active interrupts TX-F MON3 measurements outside threshold limits. Disable (Default) Enable RESERVED (Default
bit7
bit6
bit5
bit4
bit3
bit2:0
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register BBh: TX-F Enable0 FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE Nonvolatile (SEE)
TXP-HI bit7
TXP-LO
BIAS-HI
BIAS
RESERVED
RESERVED
RESERVED
FETG bit0
Configures maskable interrupt Tx-F pin. TXP-HI Enables/Disables active interrupts Tx-F Tx-P fast comparisons above threshold limit. Disable (Default) Enable. TXP-LO Enables/Disables active interrupts Tx-F Tx-P fast comparisons below threshold limit. Disable (Default) Enable BIAS-HI Enables/Disables active interrupts Tx-F BIAS fast comparisons above threshold limit. Disable (Default) Enable BIAS Enables/Disables active interrupts Tx-F BIAS fast comparisons above threshold limit. bit4 Disable (Default) Enable RESERVED (Default FETG Normal FETG operation (Default) Enables FETG input Tx-F output.
bit7
bit6
bit5
bit3:1 bit0
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register BCh: HTXP FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
Nonvolatile (SEE) bit0
bit7
Fast comparison adjust High TXP. This value added APC_DAC value recalled from Table 04h. greater than 0xFF then 0xFF used. Comparisons greater than APC_DAC plus this value, found pin, will create TX-P alarm. Table 02h, Register BDh: LTXP FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
Nonvolatile (SEE) bit0
bit7
Fast comparison adjust TXP. This value subtracted from APC_DAC value recalled from Table 04h. difference less than 0x00 then 0x00 used. Comparisons less than APC_DAC minus this value, found pin, will create TX-PLO alarm. Table 02h, Register BEh: HBIAS FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
Nonvolatile (SEE) bit0
bit7 Fast comparison setting High BIAS.
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register BFh: IBIAS FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE:
Nonvolatile (SEE) bit0
bit7
This value will define maximum value allowed upper bits IBIAS output during operations. During initial step binary search, this value will cause alarm will still clamp IBIAS output. After startup sequence normal operations), loop tries create IBIAS value greater than this setting, IBIAS clamped, creates BIAS alarm. Settings through intended normal mode operation. Setting reserved manual IBIAS mode. Table 02h, Register F7h: Empty Table 02h, Register F8h-F9h: IBIAS FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: RESERVED
(BIAS-EN Volatile RESERVED
bit0
bit7 When "BIAS-EN" (Table 02h, 80h) written writes these bytes will control lower portion IBIAS [7:0]. Table 02h, Register FAh: MAN_CNTL FACTORY DEFAULT: READ ACCESS WRITE ACCESS MEMORY TYPE: RESERVED bit7 (BIAS-EN Volatile RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
MAN_CLK bit0
When "BIAS-EN" (Table 02h, 80h) written zero, zero this byte will control updates IBIAS value Bias output. Values IBIAS should written with separate write command. Setting zero will clock IBIAS value output DAC. Write IBIAS value with write command. with separate write command. Clear with separate write command.
Burst-Mode Controller With Integrated Monitoring DS1863
Table 02h, Register FFh: Reserved FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: These registers reserved.
Table 03h, Register Descriptions
Table 03h, Register FFh: EEPROM FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: 80h-FFh bit7 general-purpose EEPROM. Nonvolatile (EE) bit0
Table 04h, Register Descriptions
Table 04h, Register C7h: Modulation FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: 80h-C7h bit7 unsigned value modulation output. Modulation registers assigned hold temperature profile Modulation DAC. values this table combined with bits Ranging register (Table 02h, Register 8Bh) determine point Modulation Voltage. temperature measurement used index INDEX, Table 02h, Register 81h) increments from -40°C +102°C, starting Table 04h. Register defines -40°C -38°C output, register defines -38°C -36°C output, Values recalled from this EEPROM memory table written into location which holds value until next temperature conversion. part placed into manual mode (Mod_En bit, Table 02h, Register 80h), where directly controlled calibration. temperature compensation functionality required, then program entire Table 04h, desired modulation setting. Nonvolatile (EE) bit0
Burst-Mode Controller With Integrated Monitoring DS1863
Table 05h, Register Descriptions
Table 05h, Register C7h: Tracking Error FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: 80h-A3h
Nonvolatile (EE) bit0
bit7
Tracking Error registers assigned hold temperature profile reference DAC. values this table combined with bits Comp Ranging register (Table 02h, Register 8Dh) determine point loop. board temperature measurement used index INDEX, Table 02h, Register 81h) increments from -40°C +100°C, starting register Table 05h. Register defines -40°C -36°C reference value, register defines -36°C -32°C reference value, Values recalled from this EEPROM memory table written into location, which holds value until next temperature conversion. part placed into manual mode (Apc_En bit, Table 02h, Register 80h), where directly controlled calibration. tracking error temperature compensation required application, program entire set-point. Table 05h, Register A7h: Reserved FACTORY DEFAULT READ ACCESS WRITE ACCESS MEMORY TYPE: These registers reserved.
Package Information
latest package outline information land patterns, www.maxim-ic.com/packages. PACKAGE TYPE TSSOP PACKAGE CODE U16+1 DOCUMENT 21-0066
Burst-Mode Controller With Integrated Monitoring DS1863
Revision History
REVISION NUMBER REVISION DATE 10/06 Initial release. Changed "triplexer" "transceiver" General Description. Added "Turn-Off Delay" "Turn-On Delay" PARAMETER specs Control Loop Quick-Trip Timing Characteristics table. Corrected reference "312-5mV" Note "312.5mV." 12/06 Changed IINIT Figure Corrected reference "BIAS MAX" IBIAS" BIAS Output During Initial Power-Up section. Corrected reference "MAX IBIAS" "BIAS MAX" BIAS-EN (Table 02h) description. Corrected reference "Factory Default" "Power-On Value" register descriptions Tindex, DAC, DAC. 8/09 Replaced instances 5.5V with 3.9V. Added Analog Voltage Monitoring table. DESCRIPTION PAGES CHANGED
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2009 Maxim Integrated Products Maxim registered trademark Maxim Integrated Products, Inc.
registered trademark Dallas Semiconductor Corporation.
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