Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies Sin
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19-4821; 7/09
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Single-/Dual-Phase, Quick-PWM Controller ±8mV VOUT Accuracy Over Line, Load, Temperature 7-Bit 1.50V Control Dynamic Phase Selection Optimizes Active/Sleep Efficiency Transient Phase Overlap Reduces Output Capacitance Integrated Boost Switches Active Voltage Positioning with Adjustable Gain Programmable 200kHz 800kHz Switching Frequency Accurate Current Balance Current Limit Adjustable Slew-Rate Control Power-Good, Clock Enable, Thermal-Fault Outputs Phase Current Imbalance Fault Output Drives Large Synchronous Rectifier MOSFETs Battery Input-Voltage Range Undervoltage Thermal-Fault Protection IMVP-6.5 Power Sequencing Timing Compliant Soft-Startup Soft-Shutdown
MAX17582
MAX17582 2-/1-phase-interleaved QuickPWMstep-down power-supply controller notebook CPUs. True out-of-phase operation reduces input-ripple-current requirements output-voltage ripple, while easing component selection layout difficulties. Quick-PWM control provides instantaneous response fast load-current steps. Active voltage positioning reduces power dissipation bulk output capacitance requirements allows ideal positioning compensation tantalum, polymer, ceramic bulk output capacitors. slew-rate controller allows controlled transitions among codes, controlled soft-start shutdown, controlled exit from suspend. thermistor-based temperature sensor provides programmable thermal-fault output (VRHOT). current-monitor output (IMON) provides analog current output proportional power consumed CPU. MAX17582 includes output undervoltage thermal protection. When these protection features detect fault, controller shuts down. voltage-regulator power-OK (PWRGD) output indicates output regulation. Additionally, MAX17582 features true differential current sense phase-good (PHASEGD) output that indicates phase imbalance fault condition. MAX17582 implements Intel IMVP-6.5 code set. MAX17582 available 6mm, 48-pin TQFN package.
Configuration
PGND1 PGND2 VRHOT
Applications
IMVP-6.5 Core Supply Multiphase Core Supply Voltage-Positioned, Step-Down Converters Notebook/Desktop Computers Blade Servers
VIEW
BST1
N.C. SLOW N.C. PHASEGD PWRGD CLKEN V3P3
Ordering Information
PART MAX17582GTM+ TEMP RANGE -40°C +105°C PIN-PACKAGE TQFN-EP*
CSP1 CSN1 PGDIN THRM IMON ILIM TIME FBAC GNDS N.C.
MAX17582
BST2 DPRSLPVR SHDN CSP2 CSN2
+Denotes lead(Pb)-free/RoHS-compliant package. Exposed pad.
THIN (6mm 6mm)
Quick-PWM trademark Maxim Integrated Products, Inc.
*EXPOSED PAD. CONNECTED GND.
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim Direct 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
ABSOLUTE MAXIMUM RATINGS
VCC, VDD, V3P3 .-0.3V D0-D6 GND.-0.3V PGDIN, DPRSLPVR, GND.-0.3V SLOW .-0.3V CSP1, CSP2, CSN1, CSN2 GND.-0.3V THRM, ILIM, PHASEGD GND.-0.3V PWRGD, VRHOT .-0.3V CLKEN .(-0.3V V3P3) 0.3V FBAC GND.(-0.3V VCC) 0.3V TIME, IMON, .(-0.3V VCC) 0.3V PGND, GNDS .-0.3V +0.3V SHDN (Note 1).-0.3V +16V .-0.3V +30V DL1, .-0.3V (VDD 0.3V) BST1, BST2 .-0.3V +36V BST1, BST2 .-0.3V +30V BST1.-6V +0.3V BST2.-6V +0.3V .(-0.3V VBST1) 0.3V .(-0.3V VBST2) 0.3V Continuous Power Dissipation 6mm, 48-Pin TQFN +70°C .2105mW (derate above +70°C) .26.3mW/°C Operating Temperature Range .-40°C +105°C Junction Temperature .+150°C Storage Temperature Range .-65°C +165°C Lead Temperature (soldering, 10s) .+300°C
Note SHDN might forced purpose debugging prototype boards using no-fault test mode, which disables fault protection overlapping operation.
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit Figure 10V, VSHDN VPGDIN VPSI VILIM V3P3 3.3V, DPRSLPVR GNDS GND, VCSP1 VCSN1 VCSP2 VCSN1 1.0000V, FBAC, RFBAC 3.57k from FBAC CSN1, D6-D0 [0101000]; VSLOW +85°C, unless otherwise noted. Typical values +25°C.)
PARAMETER CONTROLLER Input-Voltage Range VCC, V3P3 Measured with respect GNDS; includes loadregulation error (Note codes from 0.8125V 1.5000V codes from 0.3750V 0.8000V codes from 0.3625V -0.5 1.094 4.5V 5.5V, 4.5V +25°C GNDS IGNDS VTIME VOUT/ VGNDS +25°C RTIME 71.5k -0.1 -200 0.97 -0.5 1.985 2.000 1.00 1.100 +0.1 +200 1.03 +0.5 2.015 +0.5 1.106 SYMBOL CONDITIONS UNITS
Output-Voltage Accuracy
VOUT
Boot Voltage Line Regulation Error Input Bias Current GNDS Input Range GNDS Gain GNDS Input Bias Current TIME Regulation Voltage
VBOOT
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit Figure 10V, VSHDN VPGDIN VPSI VILIM V3P3 3.3V, DPRSLPVR GNDS GND, VCSP1 VCSN1 VCSP2 VCSN1 1.0000V, FBAC, RFBAC 3.57k from FBAC CSN1, D6-D0 [0101000]; VSLOW +85°C, unless otherwise noted. Typical values +25°C.)
PARAMETER SYMBOL RTIME 71.5k CONDITIONS (12.5mV/s nominal) RTIME 35.7k (25mV/s nominal) 178k (5mV/s nominal) Soft-start soft-shutdown: RTIME 35.7k (3.125mV/s nominal) 178k (0.625mV/s nominal) TIME Slew-Rate Accuracy Slow: SLOW nominal slew rate, RTIME 71.5k (6.25mV/s nominal) Slow: SLOW nominal slew rate, RTIME 35.7k (12.5mV/s nominal) 178k (2.5mV/s nominal) RTON 96.75k (600kHz phase), 167ns nominal On-Time Measured (Note RTON 200k (300kHz phase), 333ns nominal RTON 303.25k 500ns nominal Minimum Off-Time Shutdown Input Current BIAS CURRENTS Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Quiescent Supply Current (V3P3) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) Shutdown Supply Current (V3P3) I3P3 ICC,SDN IDD,SDN I3P3,SDN Measured VCC, VDPRSLPVR forced above regulation point Measured VDD, VDPRSLPVR forced above regulation point, +25°C Measured V3P3, forced within CLKEN power-good window Measured VCC, SHDN GND, +25°C Measured VDD, SHDN GND, +25°C Measured V3P3, SHDN GND, +25°C 0.02 0.01 0.01 0.01 OFF(MIN) IRTON,SDN Measured (Note SHDN GND, 26V, +25°C (200kHz phase), UNITS
MAX17582
0.01
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
ELECTRICAL CHARACTERISTICS (continued)
(Circuit Figure 10V, VSHDN VPGDIN VPSI VILIM V3P3 3.3V, DPRSLPVR GNDS GND, VCSP1 VCSN1 VCSP2 VCSN1 1.0000V, FBAC, RFBAC 3.57k from FBAC CSN1, D6-D0 [0101000]; VSLOW +85°C, unless otherwise noted. Typical values +25°C.)
PARAMETER FAULT PROTECTION Output UndervoltageProtection Threshold Output UndervoltagePropagation Delay CLKEN Startup Delay Boot Time Period PWRGD Startup Delay VUVP tUVP tBOOT Measured with respect voltage target code; Table forced 25mV below trip threshold Measured from time when reaches boot target voltage (Note Measured startup from time when CLKEN goes Measured with respect voltage target code; Table 20mV hysteresis (typ) Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage) -450 -400 -350 SYMBOL CONDITIONS UNITS
-350
-300
-250
CLKEN PWRGD Threshold
+150
+200
+250
CLKEN PWRGD Delay PHASEGD Delay CLKEN, PWRGD, PHASEGD Transition Blanking Time (VID Transitions) PHASEGD Transition Blanking Time (Phase Enable Transitions) CLKEN Output Voltage CLKEN Output High Voltage PWRGD, PHASEGD Output Voltage PWRGD, PHASEGD Leakage Current CSN1 Pulldown Resistance Shutdown Undervoltage Lockout (UVLO) Threshold VUVLO(VCC)
forced 25mV outside PWRGD trip thresholds V(CCI,FB) forced 25mV outside trip thresholds Measured from time when reaches target voltage (Note
tBLANK
Number pulses which PHASEGD blanked after phase enabled state, ISINK High state, SOURCE state, SINK High-impedance state, PWRGD, PHASEGD forced +25°C SHDN measured after soft-shutdown completed (DL_ low) Rising edge, 65mV typical hysteresis, controller disabled below this level 4.05 V3P3
Pulses
4.27 4.48
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit Figure 10V, VSHDN VPGDIN VPSI VILIM V3P3 3.3V, DPRSLPVR GNDS GND, VCSP1 VCSN1 VCSP2 VCSN1 1.0000V, FBAC, RFBAC 3.57k from FBAC CSN1, D6-D0 [0101000]; VSLOW +85°C, unless otherwise noted. Typical values +25°C.)
PARAMETER THERMAL PROTECTION VRHOT Trip Threshold VRHOT Delay VRHOT Output On-Resistance VRHOT Leakage Current THRM Input Leakage Thermal-Shutdown Threshold ITHRM SHDN VRHOT Measured THRM percentage VCC, falling edge, typical hysteresis 75mV THRM forced 25mV below VRHOT trip threshold, falling edge -0.1 22.5 +0.1 SYMBOL CONDITIONS UNITS
MAX17582
ON(VRHOT) state High-impedance state, VRHOT forced +25°C VTHRM +25°C Typical hysteresis 15°C VTIME VILIM 100mV VLIMIT VCSP_ VCSN_ VTIME VILIM 500mV ILIM
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE Current-Limit Threshold Voltage (Positive) Current-Limit Threshold Voltage (Negative) Accuracy Current-Limit Threshold Voltage (Zero Crossing) CSP_, CSN_ CommonMode Input Range Phase Disable Threshold CSP_, CSN_ Input Current ILIM Input Current Measured CSP2 ICSP_, ICSN_ +25°C ILIM +25°C (1/N) (VCSP_ VCSN_) IFBAC indicates summation over phases from Gm(FBAC) +25oC +85oC
VLIMIT(NEG)
VCSP_ VCSN_, nominally -125% VLIMIT
VZERO
VGND VLX_, DPRSLPVR -0.2 -0.1 -0.5 -0.75
+0.2 +0.1 +0.5 +0.75
phase
Droop Amplifier Offset
Droop Amplifier Transconductance Current-Balance Amplifier Offset Current-Balance Amplifier Transconductance
IFBAC/ (VCSP_ VCSN_)]; indicates summation over phases from VFBAC VCSN- 0.45V (VCSP1 VCSN1) (VCSP2 VCSN2) ICCI
-1.0
+1.0
Gm(CCI)
ICCI/[(VCSP1 VCSN1) (VCSP2 VCSN2)]
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
ELECTRICAL CHARACTERISTICS (continued)
(Circuit Figure 10V, VSHDN VPGDIN VPSI VILIM V3P3 3.3V, DPRSLPVR GNDS GND, VCSP1 VCSN1 VCSP2 VCSN1 1.0000V, FBAC, RFBAC 3.57k from FBAC CSN1, D6-D0 [0101000]; VSLOW +85°C, unless otherwise noted. Typical values +25°C.)
PARAMETER CURRENT MONITOR Current-Monitor Output Current Full Load Condition Current-Monitor Transconductance IMON Clamp Voltage IMON Pulldown Resistance Shutdown GATE DRIVERS Gate Driver On-Resistance Gate Driver On-Resistance Gate Driver Source Current Gate Driver Sink Current Gate Driver Source Current Gate Driver Sink Current Internal BST_ Switch On-Resistance LOGIC Logic Input High Voltage Logic Input Voltage SHDN No-Fault Level Low-Voltage Logic Input High Voltage Low-Voltage Logic Input Voltage Logic Input Current VIHLV VILLV SHDN, PGDIN SHDN, PGDIN enable no-fault mode PSI, D0-D6; DPRSLPVR, SLOW PSI, D0-D6; DPRSLPVR, SLOW +25°C, SHDN, DPRSLPVR, PGDIN, PSI, SLOW, D0-D6 0.67 0.33 ON(DH_) ON(DL_) BST_ forced High state (pullup) state (pulldown) High state (pullup) state (pulldown) 0.25 IMON VCSP1 VCSN1 VCSP2 VCSN2 20mV, VCSN_ 0.45V 2.0V IMON/ (VCSP_ VCSN_)]; indicates summation over phases from CSN_ 0.45V SINK 10mA SHDN measured after soft-shutdown completed (DL_ low) 93.12 98.88 SYMBOL CONDITIONS UNITS
Gm(IMON)
VIMON,MAX
1.05
1.10
1.15
IDH_(SOURCE) forced 2.5V, BST_ forced IDH_(SINK) forced 2.5V, BST_ forced
IDL_(SOURCE) forced 2.5V IDL_(SINK) ON(BST_) forced 2.5V
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
ELECTRICAL CHARACTERISTICS
(Circuit Figure 10V, VSHDN VPGDIN VPSI VILIM V3P3 3.3V, DPRSLPVR GNDS GND, VCSP1 VCSN1 VCSP2 VCSN2 1.0000V, FBAC, RFBAC 3.57k from FBAC CSN1, D6-D0 [0101000]; VSLOW -40°C +105°C, unless otherwise noted.) (Note
PARAMETER CONTROLLER Input-Voltage Range VCC, V3P3 codes from 0.8125V 1.5000V -0.75 1.09 -200 GNDS VTIME VOUT/ VGNDS RTIME 71.5k RTIME 71.5k (12.5mV/s nominal) RTIME 35.7k (25mV/s nominal) 178k (5mV/s nominal) Soft-start soft-shutdown: RTIME 35.7k (3.125mV/s nominal) 178k (0.625mV/s nominal) TIME Slew-Rate Accuracy Slow: SLOW nominal slew rate, RTIME 71.5k (6.25mV/s nominal) Slow: SLOW nominal slew rate, RTIME 35.7k (12.5mV/s nominal) 178k (2.5mV/s nominal) RTON 96.75k 167ns nominal On-Time (600kHz phase), 0.97 1.985 +0.75 1.11 +200 1.03 2.015 SYMBOL CONDITIONS UNITS
MAX17582
Output-Voltage Accuracy
VOUT
Measured with respect GNDS; codes from includes load0.3750V 0.8000V regulation error (Note codes from 0.3625V
Boot Voltage GNDS Input Range GNDS Gain TIME Regulation Voltage
VBOOT
Measured RTON 200k (300kHz phase), 333ns nominal (Note RTON 303.25k (200kHz phase), 500ns nominal Measured (Note Measured VCC, VDPRSLPVR forced above regulation point Measured V3P3, forced within CLKEN power-good window
Minimum Off-Time BIAS CURRENTS Quiescent Supply Current (VCC) Quiescent Supply Current (V3P3)
OFF(MIN)
I3P3
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
ELECTRICAL CHARACTERISTICS (continued)
(Circuit Figure 10V, VSHDN VPGDIN VPSI VILIM V3P3 3.3V, DPRSLPVR GNDS GND, VCSP1 VCSN1 VCSP2 VCSN2 1.0000V, FBAC, RFBAC 3.57k from FBAC CSN1, D6-D0 [0101000]; VSLOW -40°C +105°C, unless otherwise noted.) (Note
PARAMETER FAULT PROTECTION Output UndervoltageProtection Threshold CLKEN Startup Delay Boot Time Period PWRGD Startup Delay VUVP tBOOT Measured with respect voltage target code; Table Measured from time when reaches boot target voltage (Note Measured startup from time when CLKEN goes Measured with respect voltage target code; Table 20mV hysteresis (typ) state, ISINK High state, SOURCE state, SINK VUVLO(VCC) Rising edge, 65mV typical hysteresis, controller disabled below this level V3P3 Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage) -450 -350 +150 -350 -250 +250 SYMBOL CONDITIONS UNITS
CLKEN PWRGD Threshold CLKEN Output Voltage CLKEN Output High Voltage PWRGD, PHASEGD Output Voltage Undervoltage-Lockout Threshold (UVLO) THERMAL PROTECTION VRHOT Trip Threshold VRHOT Output On-Resistance
Measured THRM percentage VCC, falling edge, typical hysteresis 75mV ON(VRHOT) state
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE Current-Limit Threshold Voltage (Positive) CSP_, CSN_ Common-Mode Input Range Droop Amplifier Transconductance Current-Balance Amplifier Offset Gm(FBAC) IFBAC/ (VCSP_ VCSN_)], indicates summation over phases from VFBAC VCSN- 0.45V (VCSP1 VCSN1) (VCSP2 VCSN2) ICCI VTIME VILIM 100mV VLIMIT VCSP_ VCSN_ VTIME VILIM 500mV ILIM
-1.25
+1.25
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit Figure 10V, VSHDN VPGDIN VPSI VILIM V3P3 3.3V, DPRSLPVR GNDS GND, VCSP1 VCSN1 VCSP2 VCSN2 1.0000V, FBAC, RFBAC 3.57k from FBAC CSN1, D6-D0 [0101000]; VSLOW -40°C +105°C, unless otherwise noted.) (Note
PARAMETER CURRENT MONITOR Current-Monitor Transconductance IMON Clamp Voltage GATE DRIVERS Gate Driver On-Resistance Gate Driver On-Resistance LOGIC Logic Input High Voltage Logic Input Voltage Low-Voltage Logic Input High Voltage Low-Voltage Logic Input Voltage VIHLV VILLV SHDN, PGDIN SHDN, PGDIN PSI, D0-D6: DPRSLPVR, SLOW PSI, D0-D6: DPRSLPVR, SLOW 0.67 0.33 ON(DH_) ON(DL_) BST_ forced High state (pullup) state (pulldown) High state (pullup) state (pulldown) Gm(IMON) VIMON,MAX IMON/ (VCSP_ VCSN_)], indicates summation over phases from VCSN_ 0.45V SINK 10mA 1.05 1.15 SYMBOL CONDITIONS UNITS
MAX17582
Note When pulse skipping, output rises approximately 1.5% when transitioning from continuous conduction load. Note On-time minimum off-time specifications measured from pins, with forced GND, BST_ forced 500pF capacitor from simulate external MOSFET gate capacitance. Actual incircuit times might different MOSFET switching speeds. Note Specifications -40°C +105°C guaranteed design production tested.
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
Typical Operating Characteristics
(Circuit Figure 12V, SHDN VCC, D0-D6 1.075V, +25°C, unless otherwise specified.)
OUTPUT VOLTAGE LOAD CURRENT (VOUT(HFM) 1.075V)
MAX17582 toc01
EFFICIENCY LOAD CURRENT (VOUT(HFM) 1.075V)
EFFICIENCY
MAX17582 toc02
OUTPUT VOLTAGE LOAD CURRENT (VOUT(LFM) 0.875V)
0.89 OUTPUT VOLTAGE 0.88 0.87 0.86 0.85 0.84 SKIP MODE
MAX17582 toc03
1.15
0.90
OUTPUT VOLTAGE
1.10
1.05
MODE
1.00
0.95 LOAD CURRENT
10.0 100.0 LOAD CURRENT
0.83 LOAD CURRENT
EFFICIENCY LOAD CURRENT (VOUT(LFM) 0.875V)
MAX17582 toc04
OUTPUT VOLTAGE LOAD CURRENT (VOUT(C4) 0.4V)
MAX17582 toc05
EFFICIENCY LOAD CURRENT (VOUT(C4) 0.4V)
EFFICIENCY
MAX17582 toc06
EFFICIENCY
0.41
OUTPUT VOLTAGE
0.40
SKIP MODE MODE 10.0 100.0 LOAD CURRENT 0.39 LOAD CURRENT
0.01 0.10
DPRSLPVR 1.00 10.00 LOAD CURRENT
SWITCHING FREQUENCY LOAD CURRENT
MAX17582 toc07
NO-LOAD SUPPLY CURRENT INPUT VOLTAGE (VOUT(HFM) 1.075V)
MAX17582 toc08
NO-LOAD SUPPLY CURRENT INPUT VOLTAGE SKIP MODE (VOUT(HFM) 1.075V)
MAX17582 toc09
SWITCHING FREQUENCY (kHz) DPRSLPVR DPRSLPVR VOUT(LFM) 0.875V VOUT(HFM) 1.075V
NO-LOAD SUPPLY CURRENT (mA)
10.0 NO-LOAD SUPPLY CURRENT (mA)
DPRSLPVR
DPRSLPVR
LOAD CURRENT
INPUT VOLTAGE
INPUT VOLTAGE SKIP MODE
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
0.8125V OUTPUT-VOLTAGE DISTRIBUTION
MAX17582 toc10
Gm(FB) TRANSCONDUCTANCE DISTRIBUTION
MAX17582 toc11
CURRENT BALANCE LOAD CURRENT
VCSP_ VCSN_ (mV) LOAD CURRENT
MAX17582 toc12
SAMPLE PERCENTAGE
+85°C +25°C
SAMPLE SIZE
SAMPLE PERCENTAGE
+85°C +25°C
SAMPLE SIZE
VOUT 1.075V
VCSPN1 VCSPN2 (mV)
0.8075
0.8085
0.8095
0.8105
0.8115
0.8125
0.8135
0.8145
0.8155
0.8165
0.8175
TRANSCONDUCTANCE (µS)
OUTPUT VOLTAGE
SOFT-START WAVEFORM CLKEN)
MAX17582 toc13
SOFT-START WAVEFORM PWRGD)
MAX17582 toc14
SHUTDOWN WAVEFORM
MAX17582 toc15
1.075V
200µs/div SHDN, 10V/div CLKEN, 10V/div VOUT, 500mV/div ILX1, 10A/div ILX2, 10A/div IOUT
1.075V
1.075V
100µs/div SHDN, 10V/div CLKEN, 10V/div PWRGD, 10V/div DL_, 10V/div VOUT, 500mV/div ILX1, 10A/div ILX2, 10A/div
1ms/div SHDN, 10V/div PWRGD, 10V/div PHASEGD, 10V/div CLKEN, 10V/div VOUT, 1V/div ILX1, 10A/div ILX2, 10A/div IOUT
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
Typical Operating Characteristics (continued)
(Circuit Figure 12V, SHDN VCC, D0-D6 1.075V, +25°C, unless otherwise specified.)
LOAD-TRANSIENT RESPONSE (HFM MODE)
MAX17582 toc16
LOAD-TRANSIENT RESPONSE (LFM MODE)
MAX17582 toc17
CODE CHANGE (SLOW GND)
MAX17582 toc18
1.075V
1.075V
0.875V 20s/div IOUT VOUT, 50mV/div ILX1, 10A/div ILX2, 10A/div IOUT VOUT, 50mV/div 20µs/div INDUCTOR CURRENT, 10A/div
0.975V
20µs/div VID3, 5V/div VOUT, 50mV/div ILX1, 10A/div ILX2, 10A/div
CODE CHANGE (SLOW VDD)
MAX17582 toc19
DYNAMIC CODE CHANGE 12.5mV)
MAX17582 toc20
OUTPUT UNDERVOLTAGE FAULT
MAX17582 toc21
1.075V
1.075V
0.975V
1.075V 1.0625V
20µs/div VID3, 5V/div VOUT, 50mV/div ILX1, 10A/div ILX2, 10A/div 5V/div VOUT, 20mV/div IOUT
20µs/div ILX1, 10A/div ILX2, 10A/div VOUT, 500mV/div PWRGD, 10V/div
100s/div DL_, 10V/div ILX1, 15A/div
VIMON LOAD CURRENT
VIMON DPRSLPVR DPRSLPVR VOUT 1.075V
MAX17582 toc22
BIAS SUPPLY REMOVAL (UVLO RESPONSE)
MAX17582 toc23
0.875V
40s/div BIAS SUPPLY, 5V/div VOUT, 500mV/div PWRGD, 5V/div DL_, 5V/div ILX1, 10A/div IOUT
VCSPN1 VCSPN2 (mV)
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Description
NAME FUNCTION System Power-Good Logic Input. PGDIN indicates power status other system rails used power-supply sequencing. After power-up boot voltage, output voltage remains VBOOT, CLKEN remains high, PWRGD remains long PGDIN stays low. When PGDIN pulled high, output transitions selected voltage, CLKEN pulled low. system pulls PGDIN during normal operation, MAX17582 immediately drives CLKEN high, pulls PWRGD low, slews output boot voltage (using two-phase pulse-skipping mode). controller remains boot voltage until PGDIN goes high again, SHDN toggled, input power supply cycled. Input Internal Comparator. Connect output resistor- thermistor-divider (between GND) THRM. Select components such that voltage THRM falls below 1.5V (30% VCC) desired high temperature. Current-Monitor Output. MAX17582 IMON output sources current that directly proportional current-sense voltage defined IMON Gm(IMON) (VCSP_ VCSN_) where Gm(IMON) (typ). IMON current unidirectional (sources current IMON only) positive current-sense values. negative current-sense voltages, IMON current zero. Connect external resistor between IMON GNDS create desired IMON gain based following equation: RIMON 0.9V/(IMAX SENSE(MIN) Gm(IMON_MIN)) where IMAX defined Current Monitor section Intel IMVP-6.5 specification based discrete increments (20A, 30A, 40A, etc.), RSENSE(MIN) minimum effective value currentsense element (sense resistor inductor DCR) that used provide current-sense voltage, Gm(IMON_MIN) minimum transconductance amplifier gain defined Electrical Characteristics table. IMON voltage internally clamped maximum 1.1V (typ). transconductance amplifier voltage clamp internally compensated, IMON cannot directly drive large capacitance values. filter IMON signal, filter shown Figure IMON pulled ground when MAX17582 shutdown. Valley Current-Limit Adjustment Input. valley current-limit threshold voltage CSP_ CSN_ equals precisely 1/10 differential TIME ILIM voltage over 0.1V 0.5V range (10mV 50mV current-sense range). negative current-limit threshold nominally -125% corresponding valley current-limit threshold. Connect ILIM directly default current-limit threshold setting 22.5mV (typ) nominal. Slew-Rate Adjustment. TIME regulates 2.0V load current determines slew rate internal error-amplifier target. resistance between TIME (RTIME) determines nominal slew-rate: SLEW RATE (12.5mV/s) (71.5k /RTIME) guaranteed RTIME range between 35.7k 178k This "nominal" slew rate applies transitions transition from boot mode VID. inputs clocked, slew rate other transitions rate which they clocked, maximum slew rate equal nominal slew rate defined above. startup shutdown slew rates always nominal slew rate order minimize surge currents. SLOW low, then slew rate reduced nominal. Analog Ground Controller Analog Bias Supply Voltage. Connect 4.5V 5.5V source. Bypass with minimum. Current-Balance Compensation. Connect 470pF capacitor between positive side feedback remote sense. internally forced shutdown.
MAX17582
PGDIN
THRM
IMON
ILIM
TIME
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
Description (continued)
NAME FUNCTION Remote Feedback-Sense Input. Normally shorted FBAC connected VCC_SENSE socket through load-line gain resistor (see FBAC description). internally connects error amplifier integrator. Voltage-Positioning Transconductance Amplifier Output. Connect resistor between FBAC positive side feedback remote sense steady-state droop based voltagepositioning gain requirement: RDROOP/(RSENSE Gm(FBAC)) where RDROOP desired voltage-positioning slope Gm(FBAC) 600S (typ). RSENSE value current-sense resistors that used provide (CSP_, CSN_) current-sense voltages. lossless sensing used, SENSE this case, consider making resistor network that includes thermistor minimize temperature dependence voltage-positioning slope. FBAC high impedance shutdown. Remote Ground-Sense Input. Normally connected VSS_SENSE socket. GNDS internally connects transconductance amplifier that fine tunes output voltage-compensating voltage drops from regulator ground load ground. Internally Connected Negative Current-Sense Input Phase Connect CSN2 negative terminal inductor current-sensing resistor directly negative terminal inductor lossless sensing method used (see Figure Positive Current-Sense Input Phase Connect CSP2 positive terminal inductor currentsensing resistor directly positive terminal filtering capacitor used when lossless sensing method used (see Figure Short CSP2 dedicated 1-phase operation. Shutdown Control Input. This input cannot withstand battery voltage. Connect normal operation. Connect ground into shutdown state. During startup, output voltage ramped boot voltage slowly slew rate that slew rate TIME resistor. During transition from normal operation shutdown, output voltage ramped down same slow slew rate. Forcing SHDN 11V~13V disables undervoltage protection, clears fault latch, disables transient phase overlap, disables BST_ charging switches. connect SHDN 13V. Pulse-Skipping Control Input. This 1.0V logic input signal indicates power usage sets operating mode MAX17582. When DPRSLPVR forced high, controller immediately enters automatic pulse-skipping mode. controller returns forced-PWM mode when DPRSLPVR forced output regulation. PWRGD upper threshold blanked during downward output-voltage transition that occurs when controller pulse-skipping mode, stays blanked until transitionrelated PWRGD blanking period complete output reaches regulation. MAX17582 2-phase pulse-skipping mode during startup while boot mode, forced-PWM mode during transition from boot mode mode plus 20s, during softshutdown, irrespective DRPSLPVR logic level. DPRSLPVR together determine operating mode number active phases shown following truth table: DPRSLPVR MODE PHASES Very current (1-phase pulse skipping) current (approximately (1-phase pulse skipping) Intermediate power potential (1-phase PWM) power potential 1-phase configured CSP2)
FBAC
GNDS
N.C.
CSN2
CSP2
SHDN
DPRSLPVR
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Description (continued)
NAME FUNCTION Power-State Indicator Input. DPRSLPVR together determine operating mode number active phases shown truth table included under description. Switching Frequency Setting Input. external resistor between input power source sets switching period phase according following equation: 16.3pF (RTON 6.5k becomes high impedance shutdown reduce input quiescent current. current less than 10A, MAX17582 disables controller, sets open fault latch, pulls low. 3.3V CLKEN Input Supply. V3P3 input supplies CLKEN CMOS push-pull logic output. Connect system's standard 3.3V supply voltage before SHDN pulled high proper IMVP-6.5 operation. Clock Enable Push-Pull Logic Output. This inverted logic output indicates when output voltage sensed regulation. During soft-start, shutdown, when regulation, MAX17582 pulls CLKEN V3P3. During transitions, controller forces CLKEN low. Except during power-up sequence, CLKEN inverse PWRGD. Startup Timing Diagram (Figure When pulse-skipping mode (DPRSLPVR high), upper CLKEN threshold disabled. Open-Drain Power-Good Output. After output-voltage transitions, except during power-up powerdown; regulation then PWRGD high impedance. During startup, PWRGD held continues while part boot mode until (typ) after CLKEN goes low. PWRGD forced shutdown. PWRGD forced high impedance whenever slew-rate controller active (output-voltage transitions). When pulse-skipping mode (DPRSLPVR high), upper PWRGD threshold comparator blanked during downward transitions. pullup resistor PWRGD causes additional finite shutdown current. Phase-Good Current-Balance Open-Drain Output. Used signal system that phases either fault condition matched with other. Detection done identifying need large on-time difference between phases order achieve move towards current balance. PHASEGD shutdown. PHASEGD forced high impedance whenever slew-rate controller active (output-voltage transitions). PHASEGD forced high impedance while 1-phase operation (DPRSLPVR high low). Boost Flying-Capacitor Connection Phase BST2 provides upper supply rail highside gate driver. internal switch between BST2 charges flying capacitor while lowside MOSFET (DL2 pulled high pulled ground). Inductor Connection Phase internal lower supply rail high-side gate driver. Also used input controller's zero-crossing comparator phase High-Side Gate-Driver Output Phase swings from BST2. controller pulls shutdown. Power Ground Low-Side Gate-Driver Output Phase swings from VDD. forced skip mode after detecting inductor current zero crossing. forced during 1-phase operation (PSI CSP2 VCC). Open-Drain Output Internal Comparator. VRHOT pulled when voltage THRM goes below 1.5V (30% VCC). VRHOT high impedance shutdown. Driver Supply Voltage Input. supply voltage used internally power low-side gate drivers refresh BST_ flying capacitors during off-times. Connect 4.5V 5.5V system supply voltage. Bypass system power ground with each greater ceramic capacitor.
MAX17582
V3P3
CLKEN
PWRGD
PHASEGD
BST2 PGND2 VRHOT
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
Description (continued)
NAME PGND1 FUNCTION Low-Side Gate-Driver Output Phase swings from VDD. forced after softshutdown skip mode after detecting inductor current zero crossing. Power Ground High-Side Gate-Driver Output Phase swings from BST1. controller pulls shutdown. Inductor Connection Phase internal lower supply rail high-side gate driver. Also used input controller's zero-crossing comparator phase Boost Flying-Capacitor Connection Phase BST1 provides upper supply rail highside gate driver. internal switch between BST1 charges flying capacitor while lowside MOSFET (DL1 pulled high pulled ground). IMVP-6.5 Slew-Rate Select Input. This 1.0V logic input signal selects between nominal "slow" (half nominal rate) slew rates. When SLOW forced high, selected nominal slew rate TIME resistance defined above. When SLOW forced low, slew rate reduced half nominal slew rate. Low-Voltage Code Input. D0-D6 inputs have internal pullups. These 1.0V logic inputs designed interface directly with CPU. output voltage code indicated logic-level voltages D0-D6 (see Table Positive Current-Sense Input Phase Connect CSP1 positive terminal inductor currentsensing resistor directly positive terminal filtering capacitor used when lossless sensing method used (see Figure Negative Current-Sense Input Phase Connect CSN1 negative terminal inductor current-sensing resistor directly negative terminal inductor lossless sensing method used (see Figure Under UVLO conditions after soft-shutdown completed, CSN1 internally pulled through discharge output. Exposed Pad. Internally connected GND. Connect ground plane through thermally enhanced via.
BST1
SLOW
39-45
D0-D6
CSP1
CSN1
Detailed Description
Table lists component selection standard applications. Table lists component suppliers MAX17582.
Free-Running, Constant-On-Time Controller with Input Feed-Forward
Quick-PWM control architecture pseudo-fixedfrequency, constant-on-time, current-mode regulator with voltage feed-forward (Figure This architecture relies output filter capacitor's current-sense resistor, output ripple voltage provides ramp signal. control algorithm
simple: high-side switch on-time determined solely one-shot whose period inversely proportional input voltage directly proportional output voltage, difference between main secondary inductor currents (see On-Time One-Shot section). Another one-shot sets minimum off-time. on-time one-shot triggers when error comparator goes low, inductor current selected phase below valley current-limit threshold, minimum off-time one-shot times out. controller maintains 180° out-ofphase operation alternately triggering main secondary phases after error comparator drops below output-voltage point.
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Table Component Selection Standard Applications
DESIGN PARAMETERS CIRCUIT Input-Voltage Range Maximum Load Current (TDC Current) Transient Load Current Load Line COMPONENTS Resistance (RTON) Inductance High-Side MOSFET (NH) Low-Side MOSFET (NL) Output Capacitors (COUT) Input Capacitors (CIN) TIME-ILIM Resistance (R1) ILIM-GND Resistance (R2) Resistance (RFB) IMON Resistance LX_-CSP_ Resistance (R5) CSP_-CSN_ Series Resistance (R6) Parallel Resistance Sense (NTC1) Sense Capacitance (CSENSE) 200k 300kHz) 200k 300kHz) NEC/TOKIN MPC1055LR36 0.36H, 32A, 0.8m Siliconix Si4386DY 7.8m /9.5m (typ/max) Siliconix Si4642DY 3.9m /4.7m (typ/max) 330F, 2.5V Panasonic EEFSX0D0D331XR 10F, ceramic (0805) 10F, ceramic (1210) 4.02k 9.09k 1.21k 1.50k 3380 NTCG163JH103F 0.22F, ceramic (0805) NEC/TOKIN MPC1055LR36 0.36H, 32A, 0.8m Siliconix Si4386DY 7.8m /9.5m (typ/max) Siliconix Si4642DY 3.9m /4.7m (typ/max) 330F, 2.5V Panasonic EEFSX0D0D331XR 10F, ceramic (0805) 10F, ceramic (1210) 6.34k 18.2k 1.21k 1.50k 3380 NTCG163JH103F 0.22F, ceramic (0805) IMVP-6.5 AUBURNDALE CORE FIGURE (37A) (10A/s) -1.9mV/A IMVP-6.5 AUBURNDALE CORE FIGURE (19A) (10A/s) -3mV/A
MAX17582
Table Component Suppliers
SUPPLIER Corp. Technologies Fairchild Semiconductor International Rectifier KEMET Corp NEC/TOKIN America, Inc. Panasonic Corp. WEBSITE www.avxcorp.com www.bitechnologies.com www.fairchildsemi.com www.irf.com www.kemet.com www.nec-tokin.com www.panasonic.com SUPPLIER Pulse Engineering SANYO Electric Ltd. Siliconix (Vishay) Sumida Corp. Taiyo Yuden Corp. TOKO America, Inc. WEBSITE www.pulseeng.com www.sanyodevice.com www.vishay.com www.sumida.com www.t-yuden.com www.component.tdk.com www.tokoam.com
Renesas Technology Corp. www.renesas.com
Central Semiconductor Corp. www.centralsemi.com
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
(VRON) AGND INPUTS VALLEY CURRENT LIMIT ILIM VLIMIT 0.2V R1/(R1 SLEW RATE TIME BIAS CURRENT dV/dt 12.5mV/s 71.5k/(R1 59.0k AGND 12.1k ILIM TIME SHDN DPRSLPVR SLOW PGDIN BST1 0.22F 1000pF 0.22F 0.22F OPEN AGND RTON 200k 1.0F AGND BIAS INPUT 1.0F SWITCHING FREQUENCY (fSW 1/TSW): 16.3pF (RTON 6.5k) INPUT
MAX17582
PGND1 CSP1 CSN1
1.21k 1.50k 0.22F
COUT
NTC1 3380
THERMAL COMPENSATION 0.22F NTC2 3380 COUT
CORE OUTPUT
3.3V 1.1V 1.9k
V3P3
CSN2 CSP2
PHASEGD PWRGD VRHOT CLKEN THRM BST2 PGND2
OPEN AGND
1.50k 1.21k
0.22F
NTC3 100k 4250
AGND 0.1F VSS_SENSE (EP) 9.09k
LOAD-LINE ADJUSTMENT: RDROOP/(RSENSE 600s) IMON 4.02k 1000pF AGND 1000pF AGND REMOTE-SENSE FILTERS VCC_SENSE REMOTE-SENSE INPUTS VSS_SENSE CATCH RESISTORS REQUIRED WHEN POPULATED
FBAC GNDS
Figure Standard 2-Phase IMVP-6.5 (Calpella) Application Circuit
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
THRM VRHOT SECONDARY PHASE DRIVERS BLANK CSP2 CSN2 CSP1 CSN1 ILIM TIME MINIMUM OFF-TIME TRIG ONE-SHOT PHASE ON-TIME ONE-SHOT (2.0V) D0-D6 PGDIN SHDN R-TO-I CONVERTER SLEW MAIN PHASE DRIVERS BST1 TRIG Gm(CCI) CSN1 TRIG CURRENTBALANCE FAULT STARTUP DELAY PHASEGD BST2
MAX17582
ONE-SHOT PHASE ON-TIME
200k CSN2 CSP2 CSP1
Gm(CCI)
FAULT
TARGET
SKIP
TARGET 300mV TARGET 200mV STARTUP DELAY STARTUP DELAY BLANK MAX17582 CSP_ IMON V3P3 CLKEN PWRGD
GNDS
SLEW
MODE/PHASE/ SLEW-RATE CONTROL FBAC Gm(FB) CSP_
DPRSLPVR
SKIP
(SLOW)
PGDIN
CSN_
CSN_
Gm(IMON)
Figure Functional Diagram
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
Dual 180° Out-of-Phase Operation
phases MAX17582 operate 180° out-ofphase minimize input output filtering requirements, reduce electromagnetic interference (EMI), improve efficiency. This effectively lowers component count- reducing cost, board space, component power requirements-making MAX17582 ideal highpower, cost-sensitive applications. Typically, switching regulators provide power using only phase instead dividing power among several phases. these applications, input capacitors must support high instantaneous current requirements. high ripple current lower efficiency power loss associated with input capacitor's effective series resistance (ESR). Therefore, system typically requires several lowESR input capacitors parallel minimize input-voltage ripple, reduce ESR-related power losses, meet necessary ripple current rating. With MAX17582, controller shares current between phases that operate 180° out-of-phase, high-side MOSFETs never turn simultaneously during normal operation. instantaneous input current either phase effectively halved, resulting reduced input-voltage ripple, power loss, ripple current (see Input Capacitor Selection section). Therefore, same performance achieved with fewer less-expensive input capacitors.
Switching Frequency (TON)
Connect resistor (RTON) between switching period 1/fSW, phase: 16.3pF (RTON 6.5k) 96.75k 303.25k corresponds switching periods 167ns (600kHz) 500ns (200kHz), respectively. High-frequency (600kHz) operation optimizes application smallest component size, trading efficiency higher switching losses. This might acceptable ultra-portable devices where load currents lower controller powered from lower voltage supply. Low-frequency (200kHz) operation offers best overall efficiency expense component size board space.
Open-Circuit Protection input includes open-circuit protection avoid long, uncontrolled on-times that could result overvoltage condition output. MAX17582 detects open-circuit fault current drops below reason-the resistor unpopulated, high resistance value used, input voltage low, etc. Under these conditions, MAX17582 stops switching (DH_ pulled low) immediately sets fault latch. Toggle SHDN cycle power supply below 0.5V clear fault latch reactivate controller. On-Time One-Shot core each phase contains fast, low-jitter, adjustable one-shot that sets high-side MOSFETs on-time. one-shot main phase varies ontime response input feedback voltages. main high-side switch on-time inversely proportional input voltage measured input, proportional feedback voltage (VFB):
tON(MAIN) 0.075V
Bias Supply (VCC VDD) Quick-PWM controller requires external bias supply addition battery. Typically, this bias supply notebook's efficient system supply. Keeping bias supply external improves efficiency eliminates cost associated with linear regulator that would otherwise needed supply circuit gate drivers. stand-alone capability needed, bias supply generated with external linear regulator. bias supply must provide (PWM controller) (gate-drive power), maximum current drawn IBIAS (QG(LOW) QG(HIGH)) where provided Electrical Characteristics table, switching frequency, QG(LOW) G(HIGH) MOSFET data sheet's total gatecharge specification limits
connected together input power source fixed +4.5V +5.5V supply. bias supply powered prior battery supply, enable signal (SHDN going from high) must delayed until battery voltage present ensure startup.
where switching period (TSW 1/fSW) resistor pin, 0.075V approximation accommodate expected drop across lowside MOSFET switch. one-shot secondary phase varies ontime response input voltage difference between main secondary inductor currents. identical transconductance amplifiers integrate difference between master slave current-sense signals. summed output internally connected CCI, allowing adjustment integration time constant with compensation network connected between
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
resulting compensation current voltage determined following equations: ICCI Gm(VCSP1 VCSN1) Gm(VCSP2 VCSN2) VCCI ICCIZCCI where ZCCI impedance output. secondary on-time one-shot uses this integrated signal (VCCI) secondary high-side MOSFETs ontime. When main secondary current-sense signals (VCM VCSP1 VCSN1 VCSP2 VCSN2) become unbalanced, transconductance amplifiers adjust secondary on-time, which increases decreases secondary inductor current until current-sense signals properly balanced:
0.075V tON(SEC) 0.075V ICCIZCCI
causes high earlier than normal, extending on-time period equal DH_-rising dead time. loads above critical conduction point, where dead-time effect longer factor, actual switching frequency (per phase) VDROP1 VDROP2
MAX17582
VOUT VDROP1)
where VDROP1 parasitic voltage drops inductor discharge path, including synchronous rectifier, inductor, resistances; VDROP2 parasitic voltage drops inductor charge path, including high-side switch, inductor, resistances; on-time determined above.
Current Sense
output current each phase sensed. Low-offset amplifiers used current balance, voltage-positioning gain, current limit. Sensing current output each phase offers advantages, including less noise sensitivity, more accurate current sharing between phases, flexibility using either current-sense resistor resistance output inductor. Using resistance (RDCR) output inductor allows higher efficiency. this configuration, initial tolerance temperature coefficient inductor's must accounted output-voltage droop-error budget power monitor. This currentsense method uses filtering network extract current information from output inductor (see Figure resistive divider used should provide current-sense resistance (RCS) enough meet current-limit requirements, time constant network should match inductor's time constant (L/RCS): and:
(Main On-time) Secondary Current Balance Correction)
This algorithm results nearly constant switching frequency balanced inductor currents despite lack fixed-frequency clock generator. benefits constant switching frequency twofold: first, frequency selected avoid noise-sensitive regions such 455kHz band; second, inductor ripple-current operating point remains relatively constant, resulting easy design methodology predictable output-voltage ripple. on-time oneshots have good accuracy operating points specified Electrical Characteristics table. Ontimes operating points removed from conditions specified Electrical Characteristics table vary over wider range. On-times translate only roughly switching frequencies. on-times guaranteed Electrical Characteristics table influenced switching delays external high-side MOSFET. Resistive losses, including inductor, both MOSFETs, output capacitor ESR, copper losses output ground tend raise switching frequency higher output currents. Also, dead-time effect increases effective on-time, reducing switching frequency. occurs only during forced-PWM operation dynamic output-voltage transitions when inductor current reverses light- negative-load currents. With reversed inductor current, inductor's
where required current-sense resistance RDCR inductor's series resistance.
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
worst-case inductance RDCR values provided inductor manufacturer, adding some margin inductance drop over temperature load. minimize current-sense error currentsense inputs' bias current (ICSP_ ICSN_), choose R1||R2 less than previous equation determine sense capacitance (CEQ). Choose capacitors with tolerance resistors with tolerance specifications. Temperature compensation recommended this current-sense method. Voltage Positioning Loop Compensation section detailed information. When using current-sense resistor accurate outputvoltage positioning, circuit requires differential filter eliminate voltage step caused equivalent series inductance (LESL) current-sense
MAX17582
resistor (see Figure induced-voltage step does affect average current-sense voltage, results significant peak current-sense voltage error that results unwanted offsets regulation voltage results early current-limit detection. Similar inductor sensing method above, filter's time constant should match time constant formed current-sense resistor's parasitic inductance: LESL CEQR1 RSENSE where LESL equivalent series inductance current-sense resistor, RSENSE current-sense resistance value, time-constant matching components.
INPUT (VIN)
SENSE RESISTOR LESL RSENSE COUT LSENSE RSENSE
MAX17582
CEQR1
PGND CSP_ CSN_
OUTPUT SERIES RESISTOR SENSING INPUT (VIN)
INDUCTOR RDCR COUT RDCR
MAX17582
RDCR
PGND CSP_ CSN_
LOSSLESS INDUCTOR SENSING
THERMAL COMPENSATION: SHOULD CONSIST RESISTOR SERIES WITH STANDARD THIN-FILM RESISTOR.
Figure Current-Sense Methods
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Current Balance MAX17582 integrates difference between current-sense voltages adjusts on-time secondary phase maintain current balance. current balance relies accuracy currentsense resistors instead inaccurate, thermally sensitive on-resistance low-side MOSFETs. With active current balancing, current mismatch determined current-sense resistor values offset voltage transconductance amplifiers:
VOS(IBAL) IOS(IBAL) ILMAIN ILSEC RSENSE where RSENSE effective sense resistance seen current-sense pins VOS(IBAL) current-balance offset specification Electrical Characteristics table. worst-case current mismatch occurs immediately after load transient inductor value mismatches resulting different di/dt phases. time takes current-balance loop correct transient imbalance depends mismatch between inductor values switching frequency. positive valley current-limit threshold voltage CSP_ CSN_ equals precisely 1/10 differential TIME ILIM voltage over 0.1V 0.5V range (10mV 50mV current-sense range). Connect ILIM directly default current-limit threshold setting 22.5mV (typ). negative current-limit threshold (forced-PWM mode only) nominally -125% corresponding valley current-limit threshold. When inductor current drops below negative current limit, controller immediately activates on-time pulse-DL_ turns turns on-allowing inductor current remain above negative-current threshold. Carefully observe layout guidelines ensure that noise errors corrupt current-sense signals seen current-sense inputs (CSP_, CSN_).
MAX17582
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier (Steady-State Droop) MAX17582 includes transconductance amplifier adding gain voltage-positioning sense path. amplifier's input generated summing current-sense inputs, which differentially sense voltage across either current-sense resistors inductor's DCR. amplifier's output connects directly regulator's voltage-positioned feedback input (FB), resistance between output-voltage sense point determines voltage-positioning gain: VOUT VTARGET RFB|FB
where target voltage (VTARGET) defined Nominal Output-Voltage Selection section, amplifier's output current (IFB) determined current-sense voltages: Gm(FB) VCSX
Current Limit current-limit circuit employs unique "valley" current-sensing algorithm that uses current-sense resistors between current-sense inputs (CSP_ CSN_) current-sensing elements. current-sense signal selected phase above current-limit threshold, controller does initiate cycle until inductor current selected phase drops below valley current-limit threshold. When either phase trips current limit, both phases effectively current limited since interleaved controller does initiate cycle with either phase. Since only valley current actively limited, actual peak current greater than current-limit threshold amount equal inductor ripple current. Therefore, exact current-limit characteristic maximum load capability function currentsense resistance, inductor value, battery voltage. When combined with undervoltage-protection circuit, this current-limit method effective almost every circumstance.
where VCSP_ VCSN_ differential currentsense voltage, m(FB) typically 600S defined Electrical Characteristics table.
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Differential Remote Sense MAX17582 includes differential, remote-sense inputs eliminate effects voltage drops along traces through processor's power pins. feedback-sense node connects voltage-positioning resistor (RFB). ground-sense (GNDS) input connects amplifier that adds offset directly target voltage, effectively adjusting output voltage counteract voltage drop ground path. Connect voltage-positioning resistor (RFB) ground-sense (GNDS) input directly processor's remote-sense outputs, shown Figure Integrator Amplifier integrator amplifier forces average voltage equal target voltage. This transconductance amplifier integrates feedback voltage provides fine adjustment regulation voltage (Figure allowing accurate output-voltage regulation regardless output ripple voltage. integrator amplifier shift output voltage ±100mV (typ). differential input-voltage range least ±60mV total, including offset ripple. MAX17582 disables integrator connecting amplifier inputs together beginning transitions done pulse-skipping mode (DPRSLPVR high). integrator remains disabled until after transition completed (the internal target settles) output regulation (edge detected error comparator).
MAX17582
turns both high-side MOSFETs during next ontime cycle. This maximizes total inductor current slew rate. phases remain overlapped until output voltage exceeds regulation voltage after minimum off-time expires. After phase-overlap mode ends, controller automatically begins with opposite phase. example, secondary phase provided last on-time pulse before overlap operation began, controller starts switching with main phase when overlap operation ends. Table operating mode truth table.
Nominal Output-Voltage Selection
nominal no-load output voltage TARGET defined selected voltage reference (VID DAC) plus remote ground-sense adjustment (VGNDS) defined following equation: VTARGET VDAC VGNDS where VDAC selected voltage. startup, MAX17582 slews target voltage from ground preset boot voltage.
Transient-Overlap Operation
When transient occurs, response time controller depends quickly slew inductor current. Multiphase controllers that remain 180° out-ofphase when transient occurs actually respond slower than equivalent single-phase controller. provide fast-transient response, MAX17582 supports phase-overlap mode, which allows dual regulators operate in-phase when heavy load transients detected, effectively reducing response time. After either high-side MOSFET turns off, output voltage does exceed regulation voltage when minimum off-time expires, controller simultaneously
Inputs (D0-D6) digital-to-analog converter (DAC) programs output voltage using D0-D6 inputs. D0-D6 lowvoltage (1.0V) logic inputs, designed interface directly with CPU. leave D0-D6 unconnected. Changing D0-D6 initiates transition outputvoltage level. Change D0-D6 together, avoiding greater than 20ns skew between bits. Otherwise, incorrect readings might cause partial transition wrong voltage level followed intended transition correct voltage level, lengthening overall transition time. available codes resulting output voltages compatible with IMVP-6.5 (Table specifications.
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Table Operating Mode Truth Table
INPUTS SHDN SLOW DPRSLPVR PHASE OPERATION* Disabled Multiphase pulse-skipping RTIME slew rate Multiphase forced-PWM nominal RTIME slew rate 1-phase forcedPWM nominal RTIME slew rate OPERATING MODE Low-Power Shutdown Mode. forced low, controller disabled. supply current drops (max). Startup/Boot. When SHDN pulled high, MAX17582 begins startup sequence. controller enables regulator ramps output voltage boot voltage. Figure
MAX17582
Rising
High
High
High
Full Power. no-load output voltage determined selected code (D0-D6, Table Intermediate Power. no-load output voltage determined selected code (D0-D6, Table When pulled low, MAX17582 immediately disables phase pulled low. Deeper Sleep Mode. no-load output voltage determined selected code (D0-D6, Table When DPRSLPVR pulled high, MAX17582 immediately enters 1-phase pulse-skipping operation, allowing automatic PWM/ switchover under light loads. PWRGD CLKEN upper thresholds blanked during downward transitions. pulled low. Deeper Sleep Slow Exit Mode. no-load output voltage determined selected code (D0-D6, Table When SLOW pulled low, MAX17582 reduces slew rate normal. PWRGD CLKEN upper thresholds blanked. pulled low. Shutdown. When SHDN pulled low, MAX17582 immediately pulls PWRGD PHASEGD low, CLKEN becomes high, enabled phases activated, output voltage ramped down ground. Once output reaches controller enters low-power shutdown state. Figure Fault Mode. fault latch been MAX17582 thermal-shutdown protection. controller remains fault mode until power cycled SHDN toggled.
High
High
High
High
High
1-phase pulseskipping nominal RTIME slew rate
High
High
1-phase pulseskipping
Falling
Multiphase forced-PWM RTIME slew rate
High
Disabled
*Multiphase operation-all enabled phases active.
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
Table IMVP-6.5 Output-Voltage Codes
OUTPUT VOLTAGE 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1125 OUTPUT VOLTAGE 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3125
Note: MAX17582 enters shutdown sequence code set, forcing PWRGD PHASEGD forcing CLKEN high. Exit from code follows startup sequence. code present when SHDN pulled high, MAX17582 remains off.
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Table IMVP-6.5 Output-Voltage Codes (continued)
OUTPUT VOLTAGE 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 OUTPUT VOLTAGE 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125
MAX17582
Note: MAX17582 enters shutdown sequence code set, forcing PWRGD PHASEGD forcing CLKEN high. Exit from code follows startup sequence. code present when SHDN pulled high, MAX17582 remains off.
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Suspend Mode When processor enters low-power deeper sleep mode, sets code lower output voltage drives DPRSLPVR high. MAX17582 responds slewing internal target voltage code, switching single-phase operation, letting output voltage gradually drift down deeper sleep voltage. During transition, MAX17582 blanks both upper lower PWRGD CLKEN thresholds until after internal target reaches deeper sleep voltage. Once timer expires, MAX17582 reenables lower PWRGD CLKEN threshold, keeps upper threshold blanked until output voltage reaches regulation level. PHASEGD remains blanked high impedance while DPRSLPVR high.
MAX17582
TRAN
VNEW VOLD (dVTARGET
where dVTARGET/dt 12.5mV/s 71.5k/RTIME slew rate, VOLD original output voltage, VNEW target voltage. TIME Slew Rate Accuracy Electrical Characteristics slew-rate limits. soft-start shutdown, controller automatically reduces slew rate 1/8. output voltage tracks slewed target voltage, making transitions relatively smooth. average inductor current phase required make outputvoltage transition COUT (dVTARGET TOTAL
Output-Voltage-Transition Timing
MAX17582 performs mode transitions controlled manner, automatically minimizing input surge currents. This feature allows circuit designer achieve nearly ideal transitions, guaranteeing just-in-time arrival output-voltage level with lowest possible peak currents given output capacitance. beginning output-voltage transition, MAX17582 blanks both PWRGD thresholds, preventing PWRGD open-drain output from changing states during transition. controller enables lower PWRGD threshold approximately after slewrate controller reaches target output voltage, upper PWRGD threshold remains blanked until output voltage reaches regulation level controller enters pulse-skipping operation. slew rate (set resistor RTIME) must fast enough ensure that transition completed within maximum allotted time. MAX17582 automatically controls current minimum level required complete transition calculated time. slew-rate controller uses internal capacitor current source programmed RTIME transition output voltage. total transition time depends RTIME, voltage difference, accuracy slew-rate controller (CSLEW accuracy). slew rate dependent total output capacitance, long surge current less than current limit. dynamic transitions, transition time (tTRAN) given
where dVTARGET/dt required slew rate, COUT total output capacitance, TOTAL number active phases.
Deeper Sleep Transitions When DPRSLPVR goes high, MAX17582 immediately disables phase (DH2 forced low), blanks PHASEGD high impedance, enters pulse-skipping operation (see Figures VIDs lower voltage setting, output drops rate determined load output capacitance. internal target still ramps before, PWRGD remains blanked high impedance until after output voltage reaches internal target.
Fast Deeper Sleep Exit: When exiting deeper sleep (DPRSLPVR pulled low) while output voltage still exceeds deeper sleep voltage, MAX17582 quickly slews (50mV/s regardless RTIME setting) internal target voltage code provided processor long output voltage above target. controller remains skip mode until output voltage equals internal target. Once internal target reaches output voltage, phase enabled. controller blanks PWRGD, PHASEGD, CLKEN until after transition completed. Figure
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
ACTUAL VOUT CORE VOLTAGE INTERNAL TARGET
(D0-D6)
DEEPER SLEEP
DPRSLPVR CARE (DPRSLPVR DOMINATES STATE) 1-PHASE SKIP (DH1 ACTIVE, FORCED LOW) PULSES: VOUT VTARGET FORCED-PWM
INTERNAL CONTROL
PWRGD CLKEN PHASEGD
BLANK HIGH IMPEDANCE BLANK
BLANK HIGH THRESHOLD ONLY BLANK HIGH THRESHOLD ONLY
BLANK HIGH IMPEDANCE BLANK
BLANK HIGH IMPEDANCE (1-PHASE OPERATION) tBLANK tBLANK
Figure Early Exit) Transition
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
Standard Deeper Sleep Exit: When exiting deeper sleep (DPRSLPVR pulled low) while output voltage regulating deeper sleep voltage, MAX17582 immediately activates enabled phases ramps output voltage code provided processor slew rate TIME controller blanks PWRGD, PHASEGD, CLKEN until after transition completed. Figure
ACTIVE CORE VOLTAGE INTERNAL TARGET ACTUAL VOUT DPRSLP
(D0-D6) DPRSLPVR
DEEPER SLEEP
INTERNAL CONTROL
CARE (DPRSLPVR DOMINATES STATE)
1-PHASE SKIP (DH1 ACTIVE, FORCED LOW) PULSES: VOUT VTARGET
1-PHASE FORCED-PWM
PWRGD
BLANK HIGH IMPEDANCE
BLANK HIGH THRESHOLD ONLY
BLANK HIGH IMPEDANCE
CLKEN
BLANK
BLANK HIGH THRESHOLD ONLY
BLANK
PHASEGD tBLANK
BLANK HIGH IMPEDANCE (1-PHASE OPERATION) tBLANK
Figure Standard Transition
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Transitions When pulled low, MAX17582 immediately disables phase (DH2 forced low), blanks PHASEGD high impedance, enters single-phase operation (see Figure When pulled high, MAX17582 enables phase PHASEGD blanked
high impedance switching cycles DH2, allowing sufficient time/cycles phases achieve current balance. typical IMVP-6.5 application, reduced (12.5mV) when pulled low, increased when pulled high.
MAX17582
FREQ
LOAD
(D0-D6)
CORE VOLTAGE INTERNAL CONTROL 2-PHASE 1-PHASE 2-PHASE
PWRGD CLKEN PHASEGD
BLANK HIGH IMPEDANCE BLANK BLANK HIGH IMPEDANCE tBLANK
BLANK HIGH IMPEDANCE BLANK
tBLANK SWITCHING CYCLES
Figure Transition
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
Forced-PWM Operation (Normal Mode)
During soft-shutdown normal operation-when actively running (DPRSLPVR low)-the MAX17582 operates with low-noise, forced-PWM control scheme. Forced-PWM operation disables zero-crossing comparators active phases, forcing low-side gate-drive waveforms constantly complement high-side gate-drive waveforms. This keeps switching frequency constant allows inductor current reverse under light loads, providing fast, accurate negative output-voltage transitions quickly discharging output capacitors. Forced-PWM operation comes cost: no-load bias supply current remains between 10mA 50mA phase, depending external MOSFETs switching frequency. maintain high efficiency under light-load conditions, processor switch controller low-power pulse-skipping control scheme after entering suspend mode. determines many phases active when operating forced-PWM mode (DPRSLPVR low). When pulled low, main phase remains active secondary phase disabled (DH2 forced low). inductor-current operation. PFM/PWM crossover occurs when load current each phase equal peak-to-peak ripple current, which function inductor value (Figure battery input range 20V, this threshold relatively constant, with only minor dependence input voltage typically duty cycles. total load current PFM/PWM crossover threshold LOAD(SKIP) approximately: ILOAD(SKIP) TOTAL where TOTAL number active phases. switching waveforms might appear noisy asynchronous when light loading activates pulse-skipping operation, this normal operating condition that results high light-load efficiency. Trade-offs between noise light-load efficiency made varying inductor value. Generally, inductor values produce broader efficiency load curve, while higher values result higher full-load efficiency (assuming that coil resistance remains fixed) less output-voltage ripple. Penalties using higher inductor values include larger physical size degraded load-transient response, especially input-voltage levels.
Light-Load Pulse-Skipping Operation (Deeper Sleep)
When DPRSLPVR pulled high, MAX17582 operates with single-phase pulse-skipping mode. pulseskipping mode enables driver's zero-crossing comparator, controller pulls when detects zero inductor current. This keeps inductor from discharging output capacitors forces controller skip pulses under light-load conditions avoid overcharging output.
Automatic Pulse-Skipping Switchover skip mode (DPRSLPVR high), inherent automatic switchover takes place light loads (Figure This switchover affected comparator that truncates low-side switch on-time inductor current's zero crossing. zero-crossing comparator senses inductor current across low-side MOSFETs. Once drops below zero-crossing comparator threshold (see Electrical Characteristics table), comparator forces low. This mechanism causes threshold between pulse-skipping nonskipping operation coincide with boundary between continuous discontinuous
INDUCTOR CURRENT
MAX17582 automatically uses forced-PWM operation during soft-shutdown, regardless DPRSLPVR configuration.
VBATT VOUT
IPEAK
ILOAD IPEAK/2
ON-TIME TIME
Figure Pulse-Skipping/Discontinuous Crossover Point
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Power-Up Sequence (POR, UVLO)
MAX17582 enabled when SHDN driven high (Figure internal reference powers first. Once reference exceeds UVLO threshold, internal analog blocks turned masked one-shot delay. controller then enabled. Power-on reset (POR) occurs when rises above approximately resetting fault latch preparing controller operation. UVLO circuitry inhibits switching until rises above 4.25V. controller powers reference once system enables controller, above 4.25V, SHDN driven high. With reference regulation, controller ramps output voltage boot voltage slew rate RTIME: TRAN(START) 8VBOOT dVTARGET current limit, full output current available immediately. CLKEN pulled approximately after MAX17582 reaches boot voltage PGDIN high. same time, MAX17582 slews output voltage inputs programmed slew rate. PWRGD PHASEGD become high impedance approximately after CLKEN pulled low. MAX17582 automatically uses forced-PWM operation during soft-start soft-shutdown, regardless DPRSLPVR configuration. automatic startup, battery voltage should present before VCC. controller attempts bring output into regulation without battery voltage present, fault latch trips. controller remains shut down until fault latch cleared toggling SHDN cycling power supply below 0.5V. voltage drops below 4.25V, controller assumes that there enough supply voltage make valid decisions. protect output from overvoltage faults, controller shuts down immediately forces high-impedance output.
MAX17582
where dVTARGET/dt 12.5mV/s 71.5k/RTIME slew rate. soft-start circuitry does variable
SHDN INVALID CODE VBOOT INVALID CODE SOFT-SHUTDOWN SLEW RATE RTIME
(D0-D6) SOFT-START SLEW RATE RTIME
VCORE
INTERNAL CONTROL
SKIP
FORCED-PWM
FORCED-PWM
PHASEGD CLKEN PWRGD tBLANK tBLANK tBLANK tBLANK
Figure Power-Up Shutdown Sequence Timing Diagram
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
Shutdown
When SHDN goes low, MAX17582 enters low-power shutdown mode. PWRGD pulled immediately, output voltage ramps down slew rate RTIME: TRAN(SHDN) 8VOUT dVTARGET increments (10A, 20A, 30A, 40A, etc.), RSENSE(MIN) minimum effective value current-sense element (sense resistor inductor DCR) that used provide current-sense voltage, Gm(IMON_MIN) minimum transconductance amplifier gain defined Electrical Characteristics table. IMON voltage internally clamped maximum 1.1V (typ), preventing IMON output from exceeding IMON voltage rating even under overload short-circuit conditions. When controller disabled, IMON pulled ground. filter IMON signal, filter shown Figure
where dVTARGET/dt 12.5mV/s 71.5k/RTIME slew rate. Slowly discharging output capacitors slewing output over long period time keeps average negative inductor current (damped response), thereby eliminating negative output-voltage excursion that occurs when controller discharges output quickly permanently turning low-side MOSFET (underdamped response). This eliminates need Schottky diode normally connected between output ground clamp negative output-voltage excursion. After controller reaches zero target, MAX17582 shuts down completely-the drivers disabled (DL1 driven low) supply current drops below When fault condition-output UVLO thermal shutdown-activates shutdown sequence, protection circuitry sets fault latch prevent controller from restarting. clear fault latch reactivate controller, toggle SHDN cycle power below 0.5V.
Phase Fault (PHASEGD)
MAX17582 includes phase-fault output that signals system that phases either fault condition matched with other. Detection done identifying need large on-time difference between phases order achieve move towards current balance. PHASEGD high impedance when controller operates 1-phase mode (DPRSLPVR high DPRSLPVR low). exit 2-phase mode, PHASEGD forced high impedance switching cycles DH2. PHASEGD shutdown. PHASEGD forced high impedance whenever slew-rate controller active (output-voltage transitions).
Current Monitor (IMON)
MAX17582 includes unidirectional transconductance amplifier that sources current proportional positive current-sense voltage. IMON output current defined IIMON Gm(IMON) (VCSP_ VCSN_) where Gm(IMON) 2.4mS (typ) IMON current unidirectional (sources current IMON only) positive current-sense values. negative currentsense voltages, IMON current zero. current monitor allows processor accurately monitor load quickly calculate power dissipation determine system about overheat before significantly slower temperature sensor signals over-temperature alert. Connect external resistor between IMON GNDS create desired IMON gain based following equation: RIMON 0.9V/(IMAX RSENSE(MIN) Gm(IMON_MIN)) where IMAX defined Current Monitor section Intel IMVP-6.5 specification based discrete
Temperature Comparator (VRHOT)
MAX17582 also features independent comparator with accurate threshold (VHOT) that tracks analog supply voltage (VHOT 0.3VCC). This makes thermal trip threshold independent supply voltage tolerance. resistor- thermistor-divider between generate voltage-regulator over-temperature monitor. Place thermistor close MOSFETs inductors possible.
Output Undervoltage Protection (UVP) output function similar foldback current limiting, employs timer rather than variable current limit. MAX17582 output voltage 400mV below target voltage, controller activates shutdown sequence sets fault latch. Once controller ramps down zero, forces high pulls low. Toggle SHDN cycle power supply below 0.5V clear fault latch reactivate controller. disabled through no-fault test mode (see No-Fault Test Mode section).
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Thermal-Fault Protection MAX17582 features thermal-fault-protection circuit. When junction temperature rises above +160°C, thermal sensor sets fault latch activates soft-shutdown sequence. Once controller ramps down zero, forces high pulls low. Toggle SHDN cycle power supply below 0.5V clear fault latch reactivate controller after junction temperature cools 15°C. Thermal shutdown disabled through no-fault test mode (see No-Fault Test Mode section). No-Fault Test Mode latched fault-protection features complicate process debugging prototype breadboards since there most) milliseconds which determine what went wrong. Therefore, no-fault test mode provided disable fault protection-undervoltage protection thermal shutdown. Additionally, test mode clears fault latch been set. no-fault test mode entered forcing SHDN.
internal pulldown transistor that drives robust, with 0.25 (typ) on-resistance. This helps prevent from being pulled capacitive coupling from drain gate low-side MOSFETs when inductor node (LX_) quickly switches from ground VIN. Applications with high input voltages long inductive driver traces might require that rising edges pull lowside MOSFETs' gate, causing shoot-through currents. capacitive coupling between created MOSFET's gate-to-drain capacitance (CRSS), gate-to-source capacitance (CISS CRSS), additional board parasitics should exceed following minimum threshold: VGS(TH) CISS Typically, adding 4700pF capacitor between power ground (CNL Figure close low-side MOSFETs, greatly reduces coupling. exceed 22nF total gate capacitance prevent excessive turn-off delays.
MAX17582
MOSFET Gate Drivers
drivers optimized driving moderate-sized high-side larger low-side power MOSFETs. This consistent with duty factor seen notebook applications, where large differential exists. high-side gate drivers (DH_) source sink 2.2A, low-side gate drivers (DL_) source 2.7A sink This ensures robust gate drive high-current applications. floating high-side MOSFET drivers powered internal boost switch charge pumps BST_, while synchronous-rectifier drivers powered directly bias supply (VDD). Adaptive dead-time circuits monitor drivers prevent either from turning until other fully off. adaptive driver dead time allows operation without shoot-through with wide range MOSFETs, minimizing delays maintaining efficiency. There must low-resistance, low-inductance path from drivers MOSFET gates adaptive dead-time circuits work properly; otherwise, sense circuitry MAX17582 interprets MOSFET gates while charge actually remains. very short, wide traces mils mils wide MOSFET from driver).
BST_
(RBST_)* INPUT (VIN)
CBST_
CBYP
(CNL)* PGND
(RBST_)* OPTIONAL-THE RESISTOR LOWERS DECREASING SWITCHING NODE RISE TIME. (CNL)* OPTIONAL-THE CAPACITOR REDUCES CAPACITIVE COUPLING THAT CAUSE SHOOT-THROUGH CURRENTS.
Figure Gate Drive Circuit
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Alternatively, shoot-through currents caused combination fast high-side MOSFETs slow lowside MOSFETs. turn-off delay time low-side MOSFETs long, high-side MOSFETs turn before low-side MOSFETs have actually turned off. Adding resistor less than series with BST_ slows down high-side MOSFET turn-on time, eliminating shoot-through currents without degrading turn-off time BST_ Figure Slowing down high-side MOSFET also reduces node rise time, thereby reducing high-frequency coupling responsible switching noise.
MAX17582
Multiphase Quick-PWM Design Procedure
Firmly establish input-voltage range maximum load current before choosing switching frequency inductor operating point (ripple-current ratio). primary design trade-off lies choosing good switching frequency inductor operating point, following four factors dictate rest design: Input-voltage range: maximum value (VIN(MAX)) must accommodate worst-case high adapter voltage. minimum value (VIN(MIN)) must account lowest input voltage after drops connectors, fuses, battery selector switches. there choice all, lower input voltages result better efficiency. Maximum load current: There values consider. peak load current (ILOAD(MAX)) determines instantaneous component stresses filtering requirements, thus drives output capacitor selection, inductor saturation rating, design current-limit circuit. continuous load current (ILOAD) determines thermal stresses thus drives selection input capacitors, MOSFETs, other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD ILOAD(MAX) 80%. multiphase systems, each phase supports fraction load, depending current balancing. When properly balanced, load current evenly distributed among each phase: ILOAD(PHASE) LOAD TOTAL where TOTAL total number active phases.
Switching frequency: This choice determines basic trade-off between size efficiency. optimal frequency largely function maximum input voltage, MOSFET switching losses that proportional frequency VIN2. optimum frequency also moving target rapid improvements MOSFET technology that making higher frequencies more practical. Inductor operating point: This choice provides trade-offs between size efficiency transient response output noise. inductor values provide better transient response smaller physical size, also result lower efficiency higher output noise increased ripple current. minimum practical inductor value that causes circuit operate edge critical conduction (where inductor current just touches zero with every cycle maximum load). Inductor values lower than this grant further size-reduction benefit. optimum operating point usually found between ripple current.
Inductor Selection
switching frequency operating point ripple current LIR) determine inductor value follows: VOUT VOUT TOTAL fSWILOAD(MAX)LIR where TOTAL total number phases. Find low-loss inductor having lowest possible resistance that fits allotted dimensions. Ferrite cores often best choice, although powdered iron inexpensive work well 200kHz. core must large enough saturate peak inductor current (IPEAK): ILOAD(MAX) IPEAK TOTAL
Transient Response
inductor ripple current impacts transient-response performance, especially VOUT differentials. inductor values allow inductor current slew faster, replenishing charge removed from output filter capacitors sudden load step. amount output also function maximum duty factor, which calculated from on-time minimum off-time. dual-phase controller, worst-case output voltage determined
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
ILOAD(MAX) tOFF(MIN) VSAG 2VOUT 2COUT VOUT 2tOFF(MIN) ILOAD(MAX) VOUT tOFF(MIN) 2COUT
VOUT
ripple voltage step-down controller equals total inductor ripple current multiplied output capacitor's ESR. When operating multiphase systems out-ofphase, peak inductor currents each phase staggered, resulting lower output ripple voltage reducing total inductor ripple current. multiphase operation, maximum meet ripple requirements VINfSWL RESR VRIPPLE TOTAL VOUT VOUT where TOTAL total number active phases, switching frequency phase. actual capacitance value required relates physical size needed achieve ESR, well chemistry capacitor technology. Thus, capacitor usually selected voltage rating rather than capacitance value (this true polymer types). When using low-capacity ceramic filter capacitors, capacitor size usually determined capacity needed prevent SOAR from causing problems during load transients. Generally, once enough capacitance added meet overshoot requirement, undershoot rising load edge longer problem (see VSAG VSOAR equations Transient Response section).
MAX17582
where OFF(MIN) minimum off-time (see Electrical Characteristics table). amount overshoot stored inductor energy calculated VSOAR
ILOAD(MAX)
2TOTAL COUT VOUT
where TOTAL total number active phases.
Setting Current Limit
minimum current-limit threshold must high enough support maximum load current when current limit minimum tolerance value. valley inductor current occurs ILOAD(MAX) minus half ripple current, therefore: ILOAD(MAX) ILIMIT(LOW) TOTAL where TOTAL total number active phases, ILIMIT(LOW) equals minimum current-limit threshold voltage divided current-sense resistor (RSENSE).
Output Capacitor Stability Considerations
Quick-PWM controllers, stability determined value zero relative switching frequency. boundary instability given following equation: fESR where: fESR and: REFF RESR RDROOP RPCB where COUT total output capacitance, RESR total equivalent series resistance, RDROOP voltage-positioning gain, RPCB parasitic board resistance between output capacitors sense resistors. 2REFF COUT
Output Capacitor Selection
output filter capacitor must have low-enough meet output ripple load-transient requirements, have high enough satisfy stability requirements. VCORE converters other applications where output subject large-load transients, output capacitor's size typically depends much needed prevent output from dipping under load transient. Ignoring finite capacitance:
(RESR RPCB
VSTEP ILOAD(MAX)
non-CPU applications, output capacitor's size often depends much needed maintain acceptable level output ripple voltage. output
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
standard 300kHz application, zero frequency must well below 95kHz, preferably below 50kHz. Tantalum, Sanyo POSCAP, Panasonic capacitors widespread time publication have typical zero frequencies below 50kHz. standard application circuit, needed support 30mVP-P ripple 30mV/(40A 0.3) 2.5m. Four 330F/2.5V Panasonic (type capacitors parallel provide 1.5m (max) ESR. With droop 0.5m resistance, typical combined results zero 30kHz. Ceramic capacitors have high-ESR zero frequency, applications with significant voltage positioning take advantage their size ESR. high-value ceramic capacitors directly across output without verifying that circuit contains enough voltage positioning series resistance ensure stability. When only using ceramic output capacitors, output overshoot (VSOAR) typically determines minimum output capacitance requirement. Their relatively capacitance value cause output overshoot when stepping from full-load no-load conditions, unless small inductor value used (high switching frequency) minimize energy transferred from inductor capacitor during load-step recovery. Unstable operation manifests itself related distinctly different ways: double pulsing feedbackloop instability. Double pulsing occurs noise output because that there enough voltage ramp output-voltage signal. This "fools" error comparator into triggering cycle immediately after minimum off-time period expired. Double pulsing more annoying than harmful, resulting nothing worse than increased output ripple. However, indicate possible presence loop instability insufficient ESR. Loop instability result oscillations output after line load steps. Such perturbations usually damped, cause output voltage rise above fall below tolerance limits. easiest method checking stability apply very fast zero-to-max load transient carefully observe output-voltage-ripple envelope overshoot ringing. help simultaneously monitor inductor current with current probe. allow more than cycle ringing after initial step-response under/overshoot.
MAX17582
Input Capacitor Selection
input capacitor must meet ripple current requirement (IRMS) imposed switching currents. multiphase Quick-PWM controllers operate out-ofphase while Quick-PWM slave controllers provide selectable out-of-phase in-phase on-time triggering. Out-of-phase operation reduces input current dividing input current between several staggered stages. duty cycles less than 100%/OUTPH phase, IRMS requirements determined following equation:
IRMS LOAD TOTAL VOUT TOTAL VOUT TOTAL
where TOTAL total number out-of-phase switching regulators. worst-case current requirement occurs when operating with 2TOTALVOUT. this point, above equation simplifies IRMS ILOAD/TOTAL. most applications, nontantalum chemistries (ceramic, aluminum, OS-CON) preferred their resistance inrush surge currents typical systems with mechanical switch connector series with input. Quick-PWM controller operated second stage two-stage power-conversion system, tantalum input capacitors acceptable. either configuration, choose input capacitor that exhibits less than +10°C temperature rise input current optimal circuit longevity.
Power-MOSFET Selection
Most following MOSFET guidelines focus challenge obtaining high load-current capability when using high-voltage 20V) adapters. Lowcurrent applications usually require less attention. high-side MOSFET (NH) must able dissipate resistive losses plus switching losses both IN(MIN) IN(MAX) Calculate both these sums. Ideally, losses VIN(MIN) should approximately equal losses IN(MAX) with lower losses between. losses VIN(MIN) significantly higher than losses VIN(MAX), consider increasing size (reducing RDS(ON) with higher CGATE). Conversely, losses VIN(MAX) significantly higher than losses VIN(MIN), consider reducing size (increasing RDS(ON) lower CGATE). does vary over wide range, minimum power dissipation occurs where resistive losses equal switching losses.
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
Choose low-side MOSFET that lowest possible on-resistance (RDS(ON)), comes moderate-sized package (i.e., 8-pin SOs, DPAK, D2PAK), reasonably priced. Make sure that gate driver supply sufficient current support gate charge current injected into parasitic gateto-drain capacitor caused high-side MOSFET turning otherwise, cross-conduction problems might occur (see MOSFET Gate Drivers section). MOSFET chosen adequate RDS(ON) low-battery voltages becomes extraordinarily when biased from IN(MAX) consider choosing another MOSFET with lower parasitic capacitance. low-side MOSFET (NL), worst-case power dissipation always occurs maximum input voltage:
ILOAD sistive) RDS(ON) VIN(MAX) TOTAL
MAX17582
MOSFET Power Dissipation
Worst-case conduction losses occur duty factor extremes. high-side MOSFET (NH), worstcase power dissipation resistance occurs minimum input voltage: sistive) LOAD RDS(ON) TOTAL where TOTAL total number phases. Generally, small high-side MOSFET desired reduce switching losses high input voltages. However, RDS(ON) required stay within package power dissipation often limits small MOSFET Again, optimum occurs when switching losses equal conduction (RDS(ON)) losses. Highside switching losses usually become issue until input greater than approximately 15V. Calculating power dissipation high-side MOSFET (NH) switching losses difficult since must allow difficult quantifying factors that influence turn-on turn-off times. These factors include internal gate resistance, gate charge, threshold voltage, source inductance, layout characteristics. following switching-loss calculation provides only very rough estimate substitute breadboard evaluation, preferably including verification using thermocouple mounted VIN(MAX)ILOAD QG(SW) Switching) TOTAL GATE where COSS MOSFET's output capacitance, G(SW) charge needed turn MOSFET, IGATE peak gate-drive source/sink current (2.2A typ). Switching losses high-side MOSFET become insidious heat problem when maximum adapter voltages applied squared term VIN2 switching-loss equation. high-side
worst case MOSFET power dissipation occurs under heavy overloads that greater than ILOAD(MAX), quite high enough exceed current limit cause fault latch trip. protect against this possibility, over design circuit tolerate: ILOAD TOTAL IVALLEY(MAX) INDUCTOR ILOAD(MAX)LIR TOTALIVALLEY(MAX) where VALLEY(MAX) maximum valley current allowed current-limit circuit, including threshold tolerance on-resistance variation. MOSFETs must have good-size heatsink handle overload power dissipation. Choose Schottky diode (DL) with forward voltage enough prevent low-side MOSFET body diode from turning during dead time. Select diode that handle load current phase during dead times. This diode optional removed efficiency critical.
Boost Capacitors
boost capacitors (CBST_) must selected large enough handle gate-charging requirements high-side MOSFETs. Typically, 0.1F ceramic capacitors work well low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1F. these applications, select boost capacitors avoid discharging capacitor more than 200mV while charging highside MOSFETs' gates: CBST QGATE 200mV
where number high-side MOSFETs used regulator, QGATE gate charge specified MOSFET's data sheet. example, assume IRF7811W n-channel MOSFETs used high
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
side. According manufacturer's data sheet, single IRF7811W maximum gate charge 24nC (VGS 5V). Using above equation, required boost capacitance would CBST_ 24nC 0.24F 200mV transconductance m(FB) typically 600S defined Electrical Characteristics table. controller sums together input signals currentsense inputs (CSP_, CSN_). When inductors' used current-sense element (RSENSE RDCR), each current-sense input should include thermistor minimize temperature dependence voltage-positioning slope.
Selecting closest standard value, this example requires 0.22F ceramic capacitor.
Current-Balance Compensation (CCI)
current-balance compensation capacitor (CCCI) integrates difference between main secondary current-sense voltages. internal compensation resistor 200k) improves transient response increasing phase margin. This allows dynamics current-balance loop optimized. Excessively large capacitor values increase integration time constant, resulting larger current differences between phases during transients. Excessively small capacitor values allow current loop respond cycle-by-cycle, result small current variations between phases. most applications, 470pF capacitor from switching regulator's output works well. Connecting compensation network output (VOUT) allows controller feed-forward outputvoltage signal, especially during transients.
Minimum Input-Voltage Requirements Dropout Performance
output-voltage-adjustable range continuousconduction operation restricted nonadjustable minimum off-time one-shot number phases. best dropout performance, slower (200kHz) on-time settings. When working with input voltages, duty-factor limit must calculated using worstcase values off-times. Manufacturing tolerances internal propagation delays introduce error on-times. This error greater higher frequencies. Also, keep mind that transient-response performance buck regulators operated close dropout poor, bulk output capacitance must often added (see equation Multiphase Quick-PWM Design Procedure section). absolute point dropout when inductor current ramps down during minimum off-time (IDOWN) much ramps during on-time (IUP). ratio IUP/IDOWN indicator ability slew inductor current higher response increased load, must always greater than approaches absolute minimum dropout point, inductor current cannot increase much during each switching cycle greatly increases unless additional output capacitance used. reasonable minimum value 1.5, adjusting this down allows trade-offs between VSAG, output capacitance, minimum operating voltage. given value minimum operating voltage calculated VDROP1 VIN(MIN) TOTAL DROOP TOTALh tOFF(MIN)fSW VDROP2 VDROP1 VDROOP where TOTAL total number out-of-phase switching regulators, voltage-positioning droop, VDROP1 VDROP2 parasitic voltage drops discharge charge paths (see OnTime One-Shot section), OFF(MIN) from Electrical Characteristics table. absolute minimum input voltage calculated with
Voltage Positioning Loop Compensation
Voltage positioning dynamically lowers output voltage response load current, reducing output capacitance processor's power-dissipation requirements. controller uses transconductance amplifier transient output-voltage droop (Figure function load. This adjustability allows flexibility selected current-sense resistor value inductor DCR, allows smaller current-sense resistance used, reducing overall power dissipated.
Steady-State Voltage Positioning Connect resistor (RFB) between VOUT steady-state droop (load line) based required voltage-positioning slope (RDROOP):
RDROOP RSENSEGm(FB)
where effective current-sense resistance (RSENSE) depends current-sense method (see Current Sense section), voltage-positioning amplifier's
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies
calculated VIN(MIN) greater than required minimum input voltage, then reduce operating frequency output capacitance obtain acceptable VSAG. operation near dropout anticipated, calculate sure adequate transient response. Dropout design example: 1.4V 300kHz tOFF(MIN) 400ns VDROOP 3mV/A 90mV VDROP1 VDROP2 150mV (30A Load) TOTAL 1.4V 90mV 150mV VIN(MIN) (0.4s 300kHz) 150mV 150mV 90mV 4.96V Calculating again with gives absolute limit dropout: 1.4V 90mV 150mV VIN(MIN) (0.4s 300kHz) 150mV 150mV 90mV 4.07V Therefore, must greater than 4.1V, even with very large output capacitance, practical input voltage with reasonable output capacitance would 5.0V. copper PCBs (2oz 1oz) enhance full-load efficiency more. Correctly routing traces difficult task that must approached terms fractions centimeters, where single excess trace resistance causes measurable efficiency penalty. Keep high-current, gate-driver traces (DL_, DH_, LX_, BST_) short wide minimize trace resistance inductance. This essential high-power MOSFETs that require low-impedance gate drivers avoid shoot-through currents. CSP_ CSN_ connections current limiting voltage positioning must made using Kelvinsense connections guarantee current-sense accuracy. When trade-offs trace lengths must made, preferable allow inductor charging path made longer than discharge path. example, better allow some extra distance between input capacitors high-side MOSFET than allow distance between inductor lowside MOSFET between inductor output filter capacitor. Route high-speed switching nodes away from sensitive analog areas (CCI, CSP_, CSN_, etc.).
MAX17582
Layout Procedure
Place power components first, with ground terminals adjacent (low-side MOSFET source, COUT, anode). possible, make these connections layer with wide, copperfilled areas. Mount controller adjacent low-side MOSFET. gate traces must short wide mils mils wide MOSFET from controller IC). Group gate-drive components (BST_ diodes capacitors, bypass capacitor) together near controller Make DC-DC controller ground connections shown Figure This diagram viewed having four separate ground planes: input/output ground, where high-power components power ground plane, where bypass capacitor master's analog ground plane, where sensitive analog components master's bypass capacitor slave's analog ground plane, where slave's bypass capacitor master's plane must meet plane only single point directly beneath
Applications Information
Layout Guidelines
Careful layout critical achieve switching losses clean, stable operation. switching power stage requires particular attention. possible, mount power components side board with their ground terminals flush against another. Refer MAX17582 evaluation specification layout example follow these guidelines good layout: Keep high-current paths short, especially ground terminals. This essential stable, jitterfree operation. Connect analog grounds separate solid copper plane, which connects Quick-PWM controller. This includes VCC, GNDS bypass capacitors. Keep power traces load connections short. This essential high efficiency. thick
Dual-Phase, Quick-PWM Controller IMVP-6.5 Core Power Supplies MAX17582
Similarly, slave's plane must meet plane only single point directly beneath respective master slave ground planes should connect high-power output ground with short metal trace from source low-side MOSFET (the middle star ground). This point must also very close output capacitor ground terminal. Connect output power planes (VCORE system ground planes) directly output filter capacitor positive negative terminals with multiple vias. Place entire DC-DC converter circuit close practical.
Chip Information
PROCESS: BiCMOS
PACKAGE TYPE TQFN-EP
Package Information
latest package outline information land patterns, www.maxim-ic.com/packages. PACKAGE CODE T4866+2 DOCUMENT 21-0141
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2009 Maxim Integrated Products Maxim registered trademark Maxim Integrated Products, Inc.
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