®1719 UltraFastcomparator optimized voltage operation. input voltage r
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LT1719 4.5ns Single/Dual Supply 3V/5V Comparator with Rail-to-Rail Output DESCRIPTION
®1719 UltraFastcomparator optimized voltage operation. input voltage range extends from 100mV below 1.2V below VCC. Internal hysteresis makes LT1719 easy even with slow moving input signals. rail-to-rail outputs directly interface CMOS. Alternatively symmetric output drive harnessed analog applications easy translation other single supply logic levels. shutdown control allows reduced power consumption extended battery life portable applications. LT1719 available SO-8 6-lead SOT-23 package. SO-8 package separate supplies which allow flexible operation, accomodating separate analog input ranges output logic levels. dual/quad comparator with similar performance, LT1720/LT1721.
LTC, LTM, Linear Technology Linear logo registered trademarks Linear Technology Corporation. UltraFast trademark Linear Technology Corporation. other trademarks property their respective owners.
UltraFast: 4.5ns 20mV Overdrive Overdrive Power: 4.2mA Separate Input Output Power Supplies (SO-8 Only) Output Optimized Supplies TTL/CMOS Compatible Rail-to-Rail Output Power Shutdown Mode: 0.1A Profile (1mm) SOT-23 (ThinSOTTM) Package
APPLICATIONS
High Speed Differential Line Receiver Crystal Oscillator Circuits Level Translators Threshold Detectors/Discriminators Zero-Crossing Detectors High Speed Sampling Circuits Delay Lines
TYPICAL APPLICATION
2.7V Crystal Oscillator with TTL/CMOS Output
2.7V
FALLING EDGE (tPDHL)
Propagation Delay Overdrive
25°C VSTEP 100mV CLOAD 10pF
1MHz 10MHz CRYSTAL (AT-CUT)
RISING EDGE (tPDLH)
GROUND CASE OUTPUT
LT1719
1719 TA01
DELAY (ns)
OVERDRIVE (mV)
1719 TA02
0.1F
1.8k
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LT1719 ABSOLUTE MAXIMUM RATINGS
(Note
Supply Voltage (LT1719S8) (LT1719S8) (LT1719S8) (LT1719S8) -12V 0.3V (LT1719S6) Input Current (+IN, SHDN) ±10mA
Output Current (Continuous) 20mA Operating Temperature Range C-Grade 70°C I-Grade -40°C 85°C Junction Temperature 150°C Storage Temperature Range. -65°C 150°C Lead Temperature (Soldering, sec) 300°C
CONFIGURATION
VIEW
SHDN
VIEW SHDN
PACKAGE 8-LEAD PLASTIC TJMAX 150°C, 110°C/W
PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX 150°C, 230°C/W
ORDER INFORMATION
LEAD FREE FINISH LT1719CS8#PBF LT1719IS8#PBF LT1719CS6#PBF LT1719IS6#PBF TAPE REEL LT1719CS8#TRPBF LT1719IS8#TRPBF LT1719CS6#TRPBF LT1719IS6#TRPBF PART MARKING 1719 1719I LTHW LTJF PACKAGE DESCRIPTION 8-Lead Plastic 8-Lead Plastic 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 TEMPERATURE RANGE 70°C -40°C 85°C 70°C -40°C 85°C
Consult Marketing parts specified with wider operating temperature ranges. Consult Marketing information non-standard lead based finish parts. more information lead free part marking, http://www.linear.com/leadfree/ more information tape reel specifications,
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LT1719 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Input Supply Voltage VCMR VTRIP+ VTRIP- VHYST VOS/T CMRR PSRR tPD20 Output Supply Voltage Supply Voltage Input Voltage Range Input Trip Points Input Offset Voltage Input Hysteresis Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Common Mode Rejection Ratio Power Supply Rejection Ratio Voltage Gain Output High Voltage Output Voltage Propagation Delay (Note (Note (Note (Note (Note ISOURCE 4mA, VTRIP+ 10mV ISINK 10mA, VTRIP- 10mV VOVERDRIVE 20mV (Note 0V(LT1719S8) 0V(LT1719S6) VOVERDRIVE 20mV, tPD5 tSKEW tJITTER fMAX tOFF Propagation Delay Propagation Delay Skew Output Rise Time Output Fall Time Output Timing Jitter Maximum Toggle Frequency Turn-Off Delay Wake-Up Delay Positive Input Stage Supply Current Negative Input Stage Supply Current (LT1719S8 Only)
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. VSHDN 0.5V, VOVERDRIVE 20mV, COUT 10pF LT1719S8 -5V, LT1719S6 unless otherwise specified.
CONDITIONS (LT1719S8 Only) (LT1719S8 Only) (LT1719CS6 Only) (Note (Note (Note (Note (LT1719S8) (LT1719S6)
-1.5 -5.5
10.5
UNITS V/°C
-2.5
(LT1719S8) (LT1719S6) (LT1719S8) (LT1719S6) (LT1719S8) (LT1719S6)
psRMS psRMS
VOVERDRIVE (Notes 0V(LT1719S8) 0V(LT1719S6) (Note 1.2VP-P (6dBm), 20MHz VOVERDRIVE 50mV, VOVERDRIVE 50mV, Time ZOUT Time VOL, ILOAD tPD+ tPD-
62.5
-4.8 -3.8 -2.6 -2.2
(LT1719S8 Only) (LT1719S8 Only)
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LT1719 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER ISHDN5 ISHDN3 ICCS IEES
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. VSHDN 0.5V, VOVERDRIVE 20mV, COUT 10pF LT1719S8 -5V, LT1719S6 unless otherwise specified.
CONDITIONS Shutdown Current Shutdown Current
UNITS
Positive Output Stage Supply Current Supply Current (LT1719S6)
(LT1719S8 Only)
-300 -200
-110 -0.2
Disabled Supply Currents (LT1719S8) (LT1719S8) VSHDN 0.5V (LT1719S8) (LT1719S6)
SHDN 0.5V
ICCSO ISSO IEEO
(LT1719S8) (LT1719S8) Shutdown Open (LT1719S8) (LT1719S6) Shutdown Open
Note Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. Exposure Absolute Maximum Rating condition extended periods affect device reliability lifetime. Note input within these common mode limits, other input outside common mode limits output will valid. Note LT1719 comparator includes internal hysteresis. trip points input voltage needed change output state each direction. offset voltage defined average VTRIP+ VTRIP-, while hysteresis voltage difference these two. Note LT1719S8 common mode rejection ratio measured with defined change offset voltage measured from -5.1V 3.8V, divided 8.9V. Note LT1719S6 common mode rejection ratio measured with defined change offset voltage measured from -0.1V 3.8V, divided 3.9V. Note LT1719S8 power supply rejection ratio measured with defined worst change offset voltage from
5.5V divided 5.5V, change offset voltage from 2.7V (with divided 3.3V. Note LT1719S6 power supply rejection ratio measured with defined change offset voltage measured from 2.7V divided 3.3V. Note Because internal hysteresis, there small-signal region which measure gain. Proper operation internal circuity ensured measuring with only 10mV overdrive. Note Propagation delay measurements made with 100mV steps. Overdrive measured relative VTRIP±. Note cannot measured automatic handling equipment with values overdrive. LT1719 100% tested with 100mV step 20mV overdrive. Correlation tests have shown that limits guaranteed with this test, additional tests performed guarantee that internal bias conditions correct. Note Propagation Delay Skew defined tSKEW |tPDLH tPDHL|
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LT1719 TYPICAL PERFORMANCE CHARACTERISTICS
Input Offset Trip Voltages Supply Voltage
TRIP POINT VOLTAGE (mV)
Input Offset Trip Voltages Temperature
COMMON MODE INPUT VOLTAGE
Input Common Mode Limits Temperature
-0.2 -5.0 -5.2 -5.4 (LT1719S8) TEMPERATURE (°C) (LT1719S6)
TRIP POINT VOLTAGE (mV)
VTRIP+ 25°C SUPPLY VOLTAGE,
1719
VTRIP
VTRIP-
VTRIP-
TEMPERATURE (°C)
1719
1719
Input Current Differential Input Voltage
25°C
SUPPLY CURRENT (mA)
Quiescent Supply Current Temperature
(LT1719S8) (LT1719S8) (LT1719S8)
Quiescent Supply Current Supply Voltage
25°C (LT1719S6)
(LT1719S6)
SUPPLY CURRENTS (mA)
SUPPLY VOLTAGE, (LT1719S8) (LT1719S8) (LT1719S8)
INPUT BIAS
DIFFERENTIAL INPUT VOLTAGE
TEMPERATURE (°C)
1339
1719
1719
Propagation Delay Load Capacitance
Propagation Delay Temperature
RISING EDGE (tPDLH)
PROPAGATION DELAY (ns)
Propagation Delay Supply Voltage
25°C VSTEP 100mV OVERDRIVE 20mV CLOAD 10pF VEE/V-=
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
25°C VSTEP 100mV OVERDRIVE 20mV
tPDLH VSTEP 100mV
CLOAD 10pF
tTPLH tTPHL
FALLING EDGE (tPDHL)
OVERDRIVE OVERDRIVE 20mV
tTPLH tTPHL (VCC, 5.5VMAX) (LT1719S8 ONLY) SUPPLY VOLTAGE,
1719
OUTPUT LOAD CAPACITANCE (pF)
1719
TEMPERATURE (°C)
1719
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LT1719 TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage Load Current
OUTPUT VOLTAGE RELATIVE
Output High Voltage Load Current
125°C 10mV
SUPPLY CURRENT (mA)
Supply Current Frequency
CLOAD 20pF LOAD CLOAD 10pF 25°C
-10mV 125°C 125°C 2.7V 25°C -55°C
OUTPUT VOLTAGE
-0.2
-55°C -0.4 25°C
-0.6
-0.8 25°C 2.7V -1.0 OUTPUT SOURCE CURRENT (mA)
1719
OUTPUT SINK CURRENT (mA)
1719
FREQUENCY (MHz)
1719
Shutdown Currents Shutdown Voltage
Shutdown Currents Shutdown Voltage
LT1719S6
SHDN CURRENT
SUPPLY CURRENTS (mA)
LT1719S8 25°C
SHDN CURRENT
SUPPLY CURRENT (mA)
25°C SHDN VOLTAGE
1719 G13b
-100
SHDN VOLTAGE
1719 G13a
-100
Shutdown Currents Temperature
Wake-Up Delay Temperature
SHUTDOWN CURRENT
SHUTDOWN 0.5V
SHUTDOWN CURRENTS
WAKE-UP DELAY (ns)
SHUTDOWN OPEN TEMPERATURE (°C)
1719
TEMPERATURE (°C)
1719
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LT1719 FUNCTIONS
LT1719S8
(Pin Positive Supply Voltage Input Stage. (Pin Noninverting Input Comparator. (Pin Inverting Input Comparator. (Pin Negative Supply Voltage Input Stage Chip Substrate. (Pin Ground. SHDN (Pin Shutdown. Pull ground enable comparator. (Pin Output Comparator. (Pin Positive Supply Voltage Output Stage.
LT1719S6
(Pin Inverting Input Comparator. (Pin Negative Supply, Usually Grounded. (Pin3): Noninverting Input Comparator. (Pin Positive Supply Voltage. (Pin Output Comparator. SHDN (Pin Shutdown. Pull ground enable comparator.
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LT1719 TEST CIRCUITS
Response Time Test Circuit
VCM) -100mV 0.1F PULSE 2N3866 1N5711
0.01F
6(6) 0.01F SCOPE PROBE (CIN 10pF)
LT1719S8
-VCM -1000 (OVERDRIVE VTRIP+) NOTE: RISING EDGE TEST SHOWN. FALLING EDGE, REVERSE LT1719 INPUTS
1719 TC02
±VTRIP Test Circuit
BANDWIDTH-LIMITED TRIANGLE WAVE 1kHz, ±7.5V 0.1F
LTC203 1000 VTRIP+ 10nF LT1112 1000 VHYST
LT1719
200k
1000 LTC203 LT1638 100k 100k 2.4k LT1112 0.15F NOTES: LT1638, LT1112, LTC203s POWERED FROM ±15V. 200k PULL-DOWN PROTECTS LTC203 LOGIC INPUTS WHEN POWERED
1719 TC01
1000 VTRIP-
10nF
100k 100k
LT1638
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LT1719 APPLICATIONS INFORMATION
Power Supply Configurations (SO-8 Package) LT1719S8 separate supply pins input output stages that allow flexible operation, accommodating separate voltage ranges analog input output logic. course, single 3V/5V supply used tying together well VEE. minimum voltage requirement simply stated both output input stages need least 2.7V must equal less than ground. following rules must adhered configuration: 2.7V (VCC VEE) 10.5V 2.7V GND) (+VS VEE) 10.5V Ground Although ground need tied system ground, most applications will that way. Figure shows three common configurations. final uncommon, will work useful level translator; input stage from 5.2V ground while output stage from ground. this case common mode input voltage range does include ground, helpful anyway. Conversely, also tied below ground, long above rules violated. Input Voltage Considerations LT1719 specified common mode range -100mV 3.8V when used with single supply. more general consideration that common mode range 100mV below 1.2V below /V+. criterion this common mode limit that output still responds correctly small differential input signal. input within common mode limit, other input signal outside common mode limits, absolute maximum limits, output will retain correct polarity.
LT1719S8 2.7V
LT1719S8
Single Supply
±5VIN, 3VOUT
-5.2V
1719
LT1719S8
LT1719S8
10VIN, 5VOUT
Front Entirely Negative
Figure Variety SO-8 Power Supply Configurations
When either input signal falls below negative common mode limit, internal diode formed with substrate turn resulting significant current flow through die. external Schottky clamp diode between input negative rail speed recovery from negative overdrive preventing substrate diode from turning When both input signals below negative common mode limit, phase reversal protection circuitry prevents false output inversion least 400mV common mode. However, offset hysteresis this mode will increase dramatically, much 15mV each. input bias currents will also increase. When both input signals above positive common mode limit, input stage will debiased output polarity will random. However, internal hysteresis will hold output valid logic level. When least inputs returns within common mode limits, recovery from this state take long
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LT1719 APPLICATIONS INFORMATION
propagation delay does increase significantly when driven with large differential voltages, with levels overdrive, apparent increase seen with large source resistances delay caused typical input capacitance. Input Protection input stage protected against damage from large differential signals, beyond differential voltage equal supply voltage, limited only absolute maximum currents noted. External input protection circuitry only needed currents would otherwise exceed these absolute maximums. internal catch diodes conduct current these rated maximums without latchup, even when supply voltage absolute maximum rating. LT1719 input stage general purpose internal protection human body model. line receiver, additional external protection required. with most integrated circuits, level immunity much greater when residing printed circuit board where power supply decoupling capacitance will limit voltage rise caused pulse. Input Bias Current Input bias current measured with both inputs held with differential input stage, LT1719 bias current flows device. will zero higher inputs double lower inputs. With more than diode drops differential input voltage, LT1719's input protection circuitry activates, current lower input will increase additional there will small bias current into higher input pins, less. Typical Performance curve Input Current Differential Input Voltage. High Speed Design Considerations Application high speed comparators often plagued oscillations. LT1719 internal hysteresis, which will prevent oscillations long parasitic output
Figure Typical Topside Metal Multilayer Layouts
input feedback kept below 4mV. However, with 2V/ns slew rate LT1719 outputs, step created input source with only 0.02pF output input coupling. LT1719's pinout been arranged minimize problems placing sensitive inputs away from outputs, shielded power rails. input output traces circuit board should also separated, requisite level isolation readily achieved topside ground plane runs between output inputs. multilayer boards where ground plane internal, topside ground supply trace should between inputs output. Figure shows typical topside layout LT1719S8 such multilayer board. Shown topside metal etch including traces, escape vias, land pads SO-8 LT1719 adjacent 10nF bypass capacitors 1206 case. same principles should used with 23-6.
1719
ground trace from runs under device bypass capacitor, shielding inputs from outputs. Note common LT1719 bypass capacitors, which minimizes interference from high frequency energy running around ground plane power distribution traces. supply bypass should include adjacent 10nF ceramic capacitor 2.2F tantalum capacitor farther than away; more capacitance driving more than loads. prevent oscillations, helpful balance impedance inverting noninverting inputs; source impedances should kept low, preferably less.
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LT1719 APPLICATIONS INFORMATION
outputs LT1719 capable very high slew rates. prevent overshoot, ringing other problems with transmission line effects, keep output traces shorter than 10cm, sure terminate lines maintain signal integrity. LT1719 drive terminations more, lower characteristic impedance traces used with series termination termination topologies. Shutdown Control LT1719 features shutdown control reduced quiescent current when comparator needed. During shutdown, inputs outputs become high impedances. LT1719 enabled when shutdown input pulled with threshold roughly diode drops below Therefore, driven standard gate, pull-up resistor should used. Because shutdown active high, this resistor adds little power drain during shutdown. logic high disables comparator. LT1719S8 logic interface based output power rails, GND. applications that shutdown feature, helpful shutdown control ground through resistor rather than directly. This allows SHDN pulled high during debug in-circuit test (bed nails) that output node wiggled without damaging impedance output driver LT1719. shutdown state guaranteed useful multiplexer. Digital signals have extremely fast edge rates that enough momentarily activate LT1719 output stage internal capacitive coupling. damage LT1719 will result, this could prove deleterious intended recipient signal. LT1719 includes pull-up shutdown control (see Simplified Schematic) well other internal structures make shutdown state current drain <<1A. Shutdown guaranteed with open circuit shutdown control pin. When shutdown control driven +VS/V+ 0.5V, linear region impedance pull-up will cause current flow (typ) into +VS/V+ shutdown pin. Currents other power supply terminals will <1A.
VTRIP- VTRIP TRIP
1719
Power Supply Sequencing LT1719S8 designed tolerate power supply sequencing system turn-on power down. previously shown power supply configurations, various supplies activate order without excessive current drain LT1719. always, Absolute Maximum Ratings must exceeded, either power supply terminals input terminals. Power supply sequencing problems occur when input signals powered from supplies that independent LT1719's supplies. comparator inputs, signals should powered from same supplies LT1719. shutdown input, signal should powered from same LT1719. Hysteresis LT1719 includes internal hysteresis, which makes easier than many other similar speed comparators. input-output transfer characteristic illustrated Figure showing definitions VHYST based upon measurable trip points. hysteresis band makes LT1719 well behaved, even with slowly moving inputs.
VOUT
VHYST VTRIP+ VTRIP-)
VHYST/2
VIN+ VIN-
VTRIP+
Figure Hysteresis Characteristics
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LT1719 APPLICATIONS INFORMATION
exact amount hysteresis will vary from part part indicated specifications table. hysteresis level will also vary slightly with changes supply voltage common mode voltage. advantage LT1719 significant reduction these effects, which important whenever LT1719 used detect threshold crossing direction only. such case, relevant trip point will that matters, stable offset voltage with unpredictable level hysteresis, seen competing comparators, useless. LT1719 many times better than prior comparators these regards. fact, CMRR PSRR tests performed checking changes either trip point limits indicated specifications table. Because offset voltage average trip points, CMRR PSRR offset voltage therefore guaranteed least good those limits. This more stringent test also puts limit common mode power supply dependence hysteresis voltage. Additional hysteresis added externally. railto-rail outputs LT1719 make this more predictable than with output comparators LT1719's small variability (output high voltage). additional hysteresis, positive feedback adding additional external resistor shown Figure Resistor adds portion output threshold resistor string. LT1719 pulls outputs ground within 200mV rails with light loads, within 400mV with heavy loads. load most circuits, good model voltage right side 300mV 300mV, total voltage swing (+VS 300mV) (300mV) 600mV.
VREF
LT1719S8
INPUT
1719
Figure Additional External Hysteresis
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LT1719 APPLICATIONS INFORMATION
With this mind, calculation resistor values needed two-step process. First, calculate value based additional hysteresis desired, output voltage swing impedance primary bias string: (R1R2)(+VS 0.6V)/(additional hysteresis) Additional hysteresis desired overall hysteresis less internal hysteresis. second step recalculate same average threshold before. average threshold before (VREF)(R1)/(R1 R2). calculated based average output voltage (+VS/2) simplified circuit model Figure assure that comparator's noninverting input average, same before: (VREF VTH)/(VTH/R1 [VTH (+VS)/2]/R3) additional hysteresis 10mV less, uncommon same within resistor tolerances. This method will work additional hysteresis hundred millivolts. Beyond that, impedance enough effect bias string, adjustment also required. Note that currents through R1/R2 bias string should many times input currents LT1719. accuracy, current must least times input current, more higher accuracy. This illustration used LT1719S8; with LT1719S6 same procedure used with substituted +VS.
VREF VAVERAGE
LT1719S8
1719
Figure Model Additional Hysteresis Calculations
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LT1719 APPLICATIONS INFORMATION
Interfacing LT1719 LT1719 comparators used high speed applications where emitter-coupled logic (ECL) deployed. interface output LT1719 logic inputs, standard TTL/CMOS level translators such 10H124, 10H424 100124 used. These components come cost nanoseconds additional delay well supply currents 50mA more, only available quads. faster, simpler lower power translator constructed with resistors shown Figure
LT1719 LEVEL TRANSLATION. TEXT 10KH/E
Figure shows standard Positive (PECL) resistive level translator. This translator cannot used LT1719, with CMOS logic, because depends resistor limit output swing (VOH) all-NPN gate with so-called totem-pole output. LT1719 fabricated complementary bipolar process output stage driver that pulls output nearly supply rail, even when sourcing 10mA.
LSTTL
STANDARD PECL TRANSLATOR
LT1719
10KH/E 100K/E
5.2V 4.5V
LT1719 OUTPUT PECL TRANSLATOR VECL
LT1719
10KH/E 100K/E VECL 5.2V OMIT 4.5V 1500 1000
LT1719 OUTPUT PECL TRANSLATOR
LT1719
FAMILY 10KH/E 100K/E VECL
-5.2V -4.5V VECL
1200 1500
1719
LT1719 OUTPUT STANDARD TRANSLATOR
Figure
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LT1719 APPLICATIONS INFORMATION
Figure shows three resistor level translator interfacing LT1719 running same supply rail. pull-down output LT1719 needed, pull-down limits seen PECL gate. This needed because inputs have both minimum maximum specification proper operation. Resistor values given both interface types; both cases assumed that LT1719 operates from same supply rail. Figure shows case translating PECL from LT1719 powered supply rail. Again, resistor values given both interface types. This time four resistors needed, although with 10KH/E, needed. that case, circuit resembles standard translator Figure function resistor, much different. loads LT1719 output when high that current flowing through doesn't forward bias LT1719's internal clamp diode. Although this diode handle 20mA without damage, normal operation performance output stage impaired above 100A forward current. prevents this with minimum additional power dissipation. Finally, Figure shows case driving standard, negative-rail, with LT1719. Resistor values given both interface types both LT1719 supply rail. Again, fourth resistor, needed prevent state current from flowing LT1719, turning internal ESD/substrate diodes. Resistor again prevents this with minimum additional power dissipation. course, SO-8 package, LT1719 same negative supply, tied well grounded. Then output stage same power rails circuits Figure used. dividers shown, output impedance about 110. This makes these fast, less than nanosecond, with most layouts. Avoid temptation speedup capacitors. only they foul operation gate because overshoots, they damage inputs, particularly during power-up separate supply configurations. Similar circuits used with emerging LVECL LVPECL standards. level translator designs shown assume gate load. Multiple gates have significant loading, transmission line routing termination issues also make this case difficult. ECL, particularly PECL, valuable technology high speed system design, must used with care. With less than volt swing, noise margins need evaluated carefully. Note that there some degradation noise margin resistor selections shown. With 10KH/E, there temperature compensation logic levels, whereas LT1719 circuits shown give levels that stable with temperature. This will lower noise margin over temperature. some configurations possible compensation with diode transistor junctions series with resistors these networks. more information design, refer ECLiPS data book (DL140), 10KH system design handbook (HB205) PECL design (AN1406), from Motorola, Semiconductor.
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LT1719 APPLICATIONS INFORMATION
Circuit Description block diagram LT1719 shown Figure circuit topology consists differential input stage, gain stage with hysteresis complementary common-emitter output stage. internal signal paths utilize voltage swings high speed power. input stage topology maximizes input dynamic range available without requiring power, complexity area complete input stages such found rail-to-rail input comparators. With single 2.7V supply, LT1719 still respectable 1.6V input common mode range. differential input voltage range rail-to-rail, without large input currents found competing devices. input stage also features phase reversal protection prevent false outputs when inputs driven below -100mV common mode voltage limit. internal hysteresis implemented positive, nonlinear feedback around second gain stage. Until this point, signal path been entirely differential. signal path then split into drive signals upper lower output transistors. output transistors connected common emitter rail-to-rail output operation. Schottky clamps limit output voltages about 300mV from rail, quite 50mV 15mV Linear Technology's rail-to-rail amplifiers other products. output comparator digital, this output stage drive CMOS directly. also drive ECL, described earlier, analog loads demonstrated applications follow. bias conditions signal swings output stage designed turn their respective output transistors faster than This helps minimize surge current from ground that occurs transitions, minimize frequency-dependent increase power consumption. frequency dependence supply current shown Typical Performance Characteristics. Speed Limits LT1719 comparator intended high speed applications, where important understand limitations. These limitations roughly divided into
NONLINEAR STAGE
1719
SHUTDOWN BIAS CONTOL
Figure LT1719 Block Diagram
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LT1719 APPLICATIONS INFORMATION
three categories: input speed limits, output speed limits, internal speed limits. There significant input speed limits except shunt capacitance input nodes. typical input nodes driven, LT1719 will respond. output speed constrained mechanisms, first which slew currents available from output transistors. maintain power quiescent operation, LT1719 output transistors sized deliver 25mA 45mA typical slew currents. This sufficient drive small capacitive loads logic gate inputs extremely high speeds. slew rate will slow dramatically with heavy capacitive loads. Because propagation delay (tPD) definition ends time output voltage halfway between supplies, fixed slew current makes LT1719 faster than with large capacitive loads sufficient input overdrive. Another manifestation this output speed limit skew, difference between tPD+ tPD-. slew currents LT1719 vary with process variations transistors, rising edges falling edges respectively. typical 0.5ns skew have either polarity, rising edge falling edge faster. Again, skew will increase dramatically with heavy capacitive loads. separate output speed limit clamp turnaround. LT1719 output optimized fast initial response, with some loss turnaround speed, limiting toggle frequency. output transistors idled power state once reached, detecting Schottky clamp action. only when output slewed from voltage voltage, clamp circuitry settled, that idle state reached LT1719 fully ready toggle again. This typically each direction, resulting maximum toggle frequency 62.5MHz. With higher frequencies, dropout runt pulses result. Increases capacitive load will increase time needed slewing limited slew currents maximum toggle frequency will decrease further. high toggle frequency applications, consider LT1394, whose linear output stage toggle 100MHz typical. internal speed limits manifest themselves dispersion. comparators have some degree dispersion, defined change propagation delay versus input overdrive. propagation delay LT1719 will vary with overdrive, from typical 4.5ns 20mV overdrive overdrive (typical). LT1719's primary source dispersion hysteresis stage. change polarity arrives gain stage, positive feedback hysteresis stage subtracts from overdrive available. Only when enough time elapsed signal propagate forward through gain stage, backwards through hysteresis path forward through gain stage again, will output stage receive same level overdrive that would have received absence hysteresis. LT1719S8 several hundred picoseconds faster when relative single supply operation. This internal speed limit; gain stage operates between +VS, faster with higher reverse voltage bias reduced silicon junction capacitances. many applications, shown following examples, there plenty input overdrive. Even applications providing levels overdrive, LT1719 fast enough that absolute dispersion 2.5ns 4.5) often small enough ignore. gain hysteresis stage LT1719 simple, short high speed help prevent parasitic oscillations while adding minimum dispersion. This internal "self-latch" usefully exploited many applications because occurs early signal chain, power, fully differential stage. therefore highly immune disturbances from other parts circuit, such output, supply lines. Once high speed signal trips hysteresis, output will respond, after fixed propagation delay, without regard these external influences that cause trouble nonhysteretic comparators.
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LT1719 APPLICATIONS INFORMATION
±VTRIP Test Circuit input trip points test circuit uses 1kHz triangle wave repeatedly trip comparator being tested. LT1719 output used trigger switched capacitor sampling triangle wave, with sampler each direction. Because triangle wave attenuated 1000:1 LT1719's differential input, sampled voltages therefore 1000 times input trip voltages. hysteresis offset computed from trip points shown. Crystal Oscillator simple crystal oscillator using LT1719 shown first page this data sheet. 2k-620 resistor pair bias point comparator's noninverting input. 2k-1.8k-0.1F path sets inverting input node appropriate average level based output. crystal's path provides resonant positive feedback stable oscillation occurs. Although LT1719 will give correct logic output when input outside common mode range, additional delays occur when operated, opening possibility spurious operating modes. Therefore, bias voltages inputs near center LT1719's common mode range resistor attenuates feedback noninverting input. circuit will operate with AT-cut crystal from 1MHz 10MHz over 2.7V supply range. power applied, circuit remains until LT1719 bias circuits activate, typical 2.2V (25°C), which point desired frequency output generated. output duty cycle this circuit roughly 50%, affected resistor tolerances lesser extent, comparator offsets timings. duty cycle required, circuit Figure forces duty cycle. Crystals narrow-band elements, feedback noninverting input filtered analog version square wave output. Changing noninverting reference level therefore vary duty cycle. operates previous example while compares band-limited version output biases C1's negative input. C1's only degree freedom respond variation pulse width; hence output forced duty cycle. Again, circuit operates from 2.7V There slight duty cycle dependence comparator loading, minimal capacitive resistive loading should used critical applications.
2.7V 1MHz 10MHz CRYSTAL (AT-CUT)
LT1719
GROUND CASE OUTPUT 100k 0.1F 1.8k 0.1F
LT1636
0.1F
200k 200k
1720
Figure Crystal Oscillator with Forced Duty Cycle
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(V+)
BIAS SOURCES
OUTPUT
SIMPLIFIED SCHEMATIC
SHDN
(V-)
(V+)
LT1719
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(V-)
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LT1719 PACKAGE DESCRIPTION
Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference 05-08-1610)
.045 ±.005 .050
.189 .197 (4.801 5.004) NOTE
.245
.160 ±.005 .228 .244 (5.791 6.197)
.150 .157 (3.810 3.988) NOTE
.030 ±.005 RECOMMENDED SOLDER LAYOUT
.010 .020 (0.254 0.508) .008 .010 (0.203 0.254)
.053 .069 (1.346 1.752)
.004 .010 (0.101 0.254)
.016 .050 (0.406 1.270) NOTE: DIMENSIONS
INCHES (MILLIMETERS) DRAWING SCALE THESE DIMENSIONS INCLUDE MOLD FLASH PROTRUSIONS. MOLD FLASH PROTRUSIONS SHALL EXCEED .006" (0.15mm)
.014 .019 (0.355 0.483)
.050 (1.270)
0303
1719fa
LT1719 PACKAGE DESCRIPTION
Package 6-Lead Plastic TSOT-23
(Reference 05-08-1636)
0.62
0.95
2.90 (NOTE
1.22
3.85 2.62
2.80
1.50 1.75 (NOTE
RECOMMENDED SOLDER LAYOUT CALCULATOR
0.95
0.30 0.45 PLCS (NOTE
0.80 0.90 0.20 1.00 DATUM 0.01 0.10
0.30 0.50
NOTE: DIMENSIONS MILLIMETERS DRAWING SCALE DIMENSIONS INCLUSIVE PLATING DIMENSIONS EXCLUSIVE MOLD FLASH METAL BURR MOLD FLASH SHALL EXCEED 0.254mm JEDEC PACKAGE REFERENCE MO-193
0.09 0.20 (NOTE
1.90
TSOT-23 0302
1719fa
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LT1719 TYPICAL APPLICATION
High Performance Sine Wave Square Wave Converter Propagation delay comparators typically specified 100mV step with some fraction that overdrive. many signal processing applications, such communications, goal convert sine wave, such carrier, square wave timing clock. desired behavior output timing dependent input timing only. phase shift should occur function input amplitude, which would result conversion. circuit Figure simple LT1719S8-based sine wave square wave converter. supplies input allow very large swing inputs, while logic supply keeps output swing small minimize cross talk. Figure shows time delay input amplitude with 10MHz sine wave. LT1719 delay changes just 0.65ns over 26dB amplitude range; 2.33° 10MHz. delay particularly flat yielding excellent rejection from 0dBm 15dBm. transformer used drive input differentially, this exceptionally flat zone spans -5dBm 10dBm, common range signal levels. Similar delay performance achieved with input frequencies high 50MHz. There however, some additional encroachment into central flat zone both small amplitude large amplitude variations. With small input signals, hysteresis dispersion make LT1719 like comparator with 12mV hysteresis span. other words, 12mVP-P sine wave 10MHz will barely toggle LT1719, with phase 25ns additional delay. Above 5VP-P 10MHz, LT1719 delay starts decrease internal capacitive feed-forward input stage. Unlike some comparators, LT1719 will falsely anticipate change input polarity, feed-forward enough make transition propagate through LT1719 faster once input polarity does change.
SINE WAVE INPUT SQUARE WAVE OUTPUT
TIME DELAY (ns)
LT1719S8
25°C 10MHz
Figure LT1719-Based Sine Wave Square Wave Converter
RELATED PARTS
PART NUMBER LT1016 LT1116 LT1394 LT1671 LT1713/LT1714 LT1720/LT1721 DESCRIPTION UltraFast Precision Comparator 12ns Single Supply Ground-Sensing Comparator 7ns, UltraFast, Single Supply Comparator 60ns, Power, Single Supply Comparator Single/Dual 7ns, Rail-to-Rail Comparator Dual/Quad 4.5ns, Single Supply 3V/5V Comparator COMMENTS Industry Standard 10ns Comparator Single Supply Version LT1016 Single Supply Comparator 450A Single Supply Comparator Rail-to-Rail Inputs Outputs Dual/Quad Comparator Similar LT1719
1719fa 0809 PRINTED
Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, 95035-7417
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2000
1719 F09a
632mVP-P 2VP-P 6.32VP-P
1719 F09b
INPUT AMPLITUDE (dBm)
Figure Time Delay Sine Wave Input Amplitude
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