Dual symmetric high performance Blackfin cores 328K bytes on-chip memo
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Blackfin Embedded Symmetric Multiprocessor ADSP-BF561
Dual symmetric high performance Blackfin cores 328K bytes on-chip memory (see Memory Architecture Page Each Blackfin core includes 16-bit MACs, 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register instruction model ease programming compiler-friendly support Advanced debug, trace, performance monitoring Wide range operating voltages, (see Operating Conditions Page 256-ball CSP_BGA sizes) 297-ball PBGA package options internal memory-to-memory DMAs internal memory controller general-purpose 32-bit timers/counters with capability SPI-compatible port UART with support IrDA Dual watchdog timers Dual 32-bit core timers programmable flags (GPIO) On-chip phase-locked loop capable frequency multiplication parallel input/output peripheral interface units supporting ITU-R video glueless interface analog front ADCs dual channel, full duplex synchronous serial ports supporting eight stereo channels
PERIPHERALS
Dual 12-channel controllers (supporting peripheral DMAs) memory-to-memory DMAs
VOLTAGE REGULATOR CONTROL/ WATCHDOG TIMER JTAG TEST EMULATION
CONTROL/ WATCHDOG TIMER
INSTRUCTION MEMORY DATA MEMORY
INSTRUCTION MEMORY DATA MEMORY SRAM 128K BYTES
UART IrDA
SPORT0
CORE SYSTEM/BUS INTERFACE
IMDMA CONTROLLER
SPORT1
CONTROLLER1 CONTROLLER2 EXTERNAL PORT FLASH/SDRAM CONTROL PPI0 PPI1
GPIO
TIMERS
BOOT
Figure Functional Block Diagram
Blackfin Blackfin logo registered trademarks Analog Devices, Inc.
Rev.
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ADSP-BF561
TABLE CONTENTS
Features Peripherals Table Contents Revision History General Description Portable Power Architecture Blackfin Processor Core Memory Architecture Controllers Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port Programmable Flags (PFx) Parallel Peripheral Interface Dynamic Power Management Voltage Regulation Clock Signals Booting Modes Instruction Description Development Tools Designing Emulator-Compatible Processor Board Related Documents Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Package Information Sensitivity Timing Specifications Output Drive Currents Power Dissipation Test Conditions Environmental Conditions 256-Ball CSP_BGA Ball Assignment 256-Ball CSP_BGA Ball Assignment 297-Ball PBGA ball assignment Outline Dimensions Surface Mount Design Automotive Products Ordering Guide
REVISION HISTORY
2/09-Changes from Rev. Rev. Correct outstanding document errata. Revised master slave specifications Added Automotive Products
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ADSP-BF561
GENERAL DESCRIPTION
ADSP-BF561 processor high performance member Blackfin® family products targeting variety multimedia, industrial, telecommunications applications. heart this device independent Analog Devices Blackfin processors. These Blackfin processors combine dual-MAC state-of-the-art signal processing engine, advantage clean, orthogonal RISC-like microprocessor instruction set, single instruction, multiple data (SIMD) multimedia capabilities single instruction architecture. ADSP-BF561 processor 328K bytes on-chip memory. Each Blackfin core includes: bytes instruction SRAM/cache bytes instruction SRAM bytes data SRAM/cache bytes data SRAM bytes scratchpad SRAM Additional on-chip memory peripherals include: 128K bytes latency on-chip SRAM Four-channel internal memory controller External memory controller with glueless support SDRAM, mobile SDRAM, SRAM, flash. powerful 40-bit shifter extensive capabilities performing shifting, rotating, normalization, extraction, depositing data. data computational units found multiported register file sixteen 16-bit entries eight 32-bit entries. powerful program sequencer controls flow instruction execution, including instruction alignment decoding. sequencer supports conditional jumps subroutine calls, well zero overhead looping. loop buffer stores instructions locally, eliminating instruction memory accesses tight looped code. data address generators (DAGs) provide addresses simultaneous dual operand fetches from memory. DAGs share register file containing four sets 32-bit Index, Modify, Length, Base registers. Eight additional 32-bit registers provide pointers general indexing variables stack locations. Blackfin processors support modified Harvard architecture combination with hierarchical memory structure. Level (L1) memories those that typically operate full processor speed with little latency. Level (L2) memories other memories, on-chip off-chip, that take multiple processor cycles access. level, instruction memory holds instructions only. data memories hold data, dedicated scratchpad data memory stores stack local variable information. level, there single unified memory space, holding both instructions data. addition, half instruction memory half data memory configured either Static RAMs (SRAMs) caches. Memory Management Unit (MMU) provides memory protection individual tasks that operating core protect system registers from unintended access. architecture provides three modes operation: user mode, supervisor mode, emulation mode. User mode restricted access certain system resources, thus providing protected software environment, while supervisor mode unrestricted access system core resources. Blackfin instruction been optimized that 16-bit op-codes represent most frequently used instructions, resulting excellent compiled code density. Complex instructions encoded into 32-bit op-codes, representing fully featured multifunction instructions. Blackfin processors support limited multi-issue capability, where 32-bit instruction issued parallel with 16-bit instructions, allowing programmer many core resources single instruction cycle. Blackfin assembly language uses algebraic syntax ease coding readability. architecture been optimized conjunction with VisualDSP C/C++ compiler, resulting fast efficient software implementations.
PORTABLE POWER ARCHITECTURE
Blackfin processors provide world-class power management performance. Blackfin processors designed power voltage design methodology feature dynamic power management, ability vary both voltage frequency operation significantly lower overall power consumption. Varying voltage frequency result substantial reduction power consumption, compared with just varying frequency operation. This translates into longer battery life portable appliances.
BLACKFIN PROCESSOR CORE
shown Figure each Blackfin core contains multiplier/accumulators (MACs), 40-bit ALUs, four video ALUs, single shifter. computational units process 8-bit, 16-bit, 32-bit data from register file. Each performs 16-bit 16-bit multiply every cycle, with accumulation 40-bit result, providing eight bits extended precision. ALUs perform standard arithmetic logical operations. With ALUs capable operating 16-bit 32-bit data, flexibility computation units covers signal processing requirements varied application needs. Each 32-bit input registers regarded 16-bit halves, each accomplish very flexible single 16-bit arithmetic operations. viewing registers pairs 16-bit operands, dual 16-bit single 32-bit operations accomplished single cycle. further taking advantage second ALU, quad 16-bit operations accomplished simply, accelerating cycle throughput.
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ADSP-BF561
ADDRESS ARITHMETIC UNIT
MEMORY
DAG1 DAG0
PREG
ASTAT
SEQUENCER R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L BARREL SHIFTER DECODE ALIGN
LOOP BUFFER
CONTROL UNIT
DATA ARITHMETIC UNIT
Figure Blackfin Processor Core
MEMORY ARCHITECTURE
ADSP-BF561 views memory single unified byte address space, using 32-bit addresses. resources including internal memory, external memory, control registers occupy separate sections this common address space. memory portions this address space arranged hierarchical structure provide good cost/performance balance some very fast, latency memory cache SRAM very close processor, larger, lower cost performance memory systems farther away from processor. ADSP-BF561 memory shown Figure memory system each core highest performance memory available each Blackfin core. memory provides additional capacity with lower performance. Lastly, off-chip memory system, accessed through External Interface Unit (EBIU), provides expansion with SDRAM, flash memory, SRAM, optionally accessing more than 768M bytes physical memory. memory controllers provide high bandwidth data movement capability. They perform block transfers code data between internal L1/L2 memories external memory spaces.
Internal (On-Chip) Memory
ADSP-BF561 four blocks on-chip memory providing high bandwidth access core. first instruction memory each Blackfin core consisting bytes four-way set-associative cache memory bytes SRAM. cache memory also configured SRAM. This memory accessed full processor speed. When configured SRAM, each banks memory broken into sub-banks which independently accessed processor DMA. second on-chip memory block data memory each Blackfin core which consists four banks bytes each. data memory banks configured two-way set-associative cache SRAM. other banks configured SRAM. banks accessed full processor speed. When configured SRAM, each four banks memory broken into sub-banks which independently accessed processor DMA. third memory block associated with each core byte scratchpad SRAM which runs same speed memories, only accessible data SRAM cannot configured cache memory accessible DMA).
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CORE MEMORY 0xFFFF FFFF 0xFFE0 0000 0xFFC0 0000 0xFFB0 1000 0xFFB0 0000 0xFFA1 4000 0xFFA1 0000 0xFFA0 4000 0xFFA0 0000 0xFF90 8000 0xFF90 4000 0xFF90 0000 0xFF80 8000 0xFF80 4000 0xFF80 0000 RESERVED SCRATCHPAD SRAM (4K) RESERVED INSTRUCTION SRAM/CACHE (16K) RESERVED INSTRUCTION SRAM (16K) RESERVED DATA BANK SRAM/CACHE (16K) DATA BANK SRAM (16K) RESERVED DATA BANK SRAM/CACHE (16K) DATA BANK SRAM (16K) RESERVED SCRATCHPAD SRAM (4K) RESERVED INSTRUCTION SRAM/CACHE (16K) RESERVED RESERVED INSTRUCTION SRAM (16K) RESERVED DATA BANK SRAM/CACHE (16K) DATA BANK SRAM (16K) RESERVED DATA BANK SRAM/CACHE (16K) DATA BANK SRAM (16K) 0xFEB2 0000 0xFEB0 0000 0xEF00 4000 0xEF00 0000 0x3000 0000 0x2C00 0000 0x2800 0000 0x2400 0000 0x2000 0000 last SDRAM page RESERVED SRAM (128K) RESERVED BOOT RESERVED ASYNC MEMORY BANK ASYNC MEMORY BANK ASYNC MEMORY BANK ASYNC MEMORY BANK RESERVED SDRAM BANK SDRAM BANK SDRAM BANK 0x0000 0000 SDRAM BANK EXTERNAL MEMORY 0xFF80 0000 0xFF70 1000 0xFF70 0000 0xFF61 4000 0xFF61 0000 0xFF60 4000 0xFF60 0000 0xFF50 8000 0xFF50 4000 0xFF50 0000 0xFF40 8000 0xFF40 4000 0xFF40 0000 INTERNAL MEMORY RESERVED CORE REGISTERS CORE REGISTERS SYSTEM REGISTERS CORE MEMORY
Figure Memory
fourth on-chip memory system SRAM memory array which provides 128K bytes high speed SRAM operating half frequency core, slightly longer latency than memory banks. memory unified instruction data memory hold mixture code data required system design. Blackfin cores share dedicated latency 64-bit wide data path port into SRAM memory. Each Blackfin core processor core Memory Mapped Registers (MMRs) share same system registers 128K bytes SRAM memory.
(SDRAM) well four banks asynchronous memory devices, including flash, EPROM, ROM, SRAM, memory mapped devices. PC133-compliant SDRAM controller programmed interface four banks SDRAM, with each bank containing between bytes 128M bytes providing access 512M bytes SDRAM. Each bank independently programmable contiguous with adjacent banks regardless sizes different banks their placement. This allows flexible configuration upgradability system memory while allowing core view SDRAM single, contiguous, physical address space. asynchronous memory controller also programmed control four banks devices with very flexible timing parameters wide variety devices. Each bank occupies
External (Off-Chip) Memory
ADSP-BF561 external memory accessed External Interface Unit (EBIU). This interface provides glueless connection four banks synchronous DRAM
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byte segment regardless size devices used that these banks will only contiguous fully populated with bytes memory. ADSP-BF561 event controller consists stages: Core Event Controller (CEC) System Interrupt Controller (SIC). Core Event Controller works with System Interrupt Controller prioritize control system events. Conceptually, interrupts from peripherals enter into SIC, then routed directly into general-purpose interrupts CEC.
Memory Space
Blackfin processors define separate space. resources mapped through flat 32-bit address space. Onchip devices have their control registers mapped into memory mapped registers (MMRs) addresses near byte address space. These separated into smaller blocks, which contains control MMRs core functions, other which contains registers needed setup control on-chip peripherals outside core. core MMRs accessible only core only supervisor mode appear reserved space on-chip peripherals. system MMRs accessible core supervisor mode mapped either visible reserved other devices, depending system protection model desired.
Core Event Controller (CEC)
supports nine general-purpose interrupts (IVG15-7), addition dedicated interrupt exception events. these general-purpose interrupts, lowest priority interrupts (IVG15-14) recommended reserved software interrupt handlers, leaving seven prioritized interrupt inputs support peripherals ADSP-BF561. Table describes inputs CEC, identifies their names Event Vector Table (EVT), lists their priorities. Table Core Event Controller (CEC)
Priority Highest) Event Class Emulation/Test Control Reset Nonmaskable Interrupt Exceptions Global Enable Hardware Error Core Timer General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt Entry IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
Booting
ADSP-BF561 contains small boot kernel, which configures appropriate peripheral booting. ADSP-BF561 configured boot from boot memory space, processor starts executing from on-chip boot ROM.
Event Handling
event controller ADSP-BF561 handles asynchronous synchronous events processor. ADSP-BF561 provides event handling that supports both nesting prioritization. Nesting allows multiple event service routines active simultaneously. Prioritization ensures that servicing higher priority event takes precedence over servicing lower priority event. controller provides support five different types events: Emulation emulation event causes processor enter emulation mode, allowing command control processor JTAG interface. Reset This event resets processor. Nonmaskable Interrupt (NMI) event generated software watchdog timer input signal processor. event frequently used power-down indicator initiate orderly shutdown system. Exceptions Events that occur synchronously program flow, i.e., exception will taken before instruction allowed complete. Conditions such data alignment violations undefined instructions cause exceptions. Interrupts Events that occur asynchronously program flow. They caused timers, peripherals, input pins, explicit software instruction. Each event associated register hold return address associated "return from event" instruction. When event triggered, state processor saved supervisor stack.
System Interrupt Controller (SIC)
System Interrupt Controller provides mapping routing events from many peripheral interrupt sources prioritized general-purpose interrupt inputs CEC. Although ADSP-BF561 provides default mapping, user alter mappings priorities interrupt events writing appropriate values into Interrupt Assignment Registers (SIC_IAR7-0). Table describes inputs into default mappings into CEC.
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Table System Interrupt Controller (SIC)
Peripheral Interrupt Event Wakeup DMA1 Error (Generic) DMA2 Error (Generic) IMDMA Error PPI0 Error PPI1 Error SPORT0 Error SPORT1 Error Error UART Error Reserved DMA1 Channel Interrupt (PPI0) DMA1 Channel Interrupt (PPI1) DMA1 Channel Interrupt DMA1 Channel Interrupt DMA1 Channel Interrupt DMA1 Channel Interrupt DMA1 Channel Interrupt DMA1 Channel Interrupt DMA1 Channel Interrupt DMA1 Channel Interrupt DMA1 Channel Interrupt DMA1 Channel Interrupt DMA2 Channel Interrupt (SPORT0 DMA2 Channel Interrupt (SPORT0 DMA2 Channel Interrupt (SPORT1 DMA2 Channel Interrupt (SPORT1 DMA2 Channel Interrupt (SPI) DMA2 Channel Interrupt (UART DMA2 Channel Interrupt (UART DMA2 Channel Interrupt DMA2 Channel Interrupt DMA2 Channel Interrupt DMA2 Channel Interrupt DMA2 Channel Interrupt Timer0 Interrupt Timer1 Interrupt Timer2 Interrupt Timer3 Interrupt Timer4 Interrupt Timer5 Interrupt Timer6 Interrupt Timer7 Interrupt Timer8 Interrupt Timer9 Interrupt Default Mapping IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10
Table System Interrupt Controller (SIC) (Continued)
Peripheral Interrupt Event Timer10 Interrupt Timer11 Interrupt Programmable Flags 15-0 Interrupt Programmable Flags 15-0 Interrupt Programmable Flags 31-16 Interrupt Programmable Flags 31-16 Interrupt Programmable Flags 47-32 Interrupt Programmable Flags 47-32 Interrupt DMA1 Channel 12/13 Interrupt (Memory DMA/Stream DMA1 Channel 14/15 Interrupt (Memory DMA/Stream DMA2 Channel 12/13 Interrupt (Memory DMA/Stream DMA2 Channel 14/15 Interrupt (Memory DMA/Stream IMDMA Stream Interrupt IMDMA Stream Interrupt Watchdog Timer Interrupt Reserved Reserved Supplemental Interrupt Supplemental Interrupt Default Mapping IVG10 IVG10 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG8 IVG8 IVG9 IVG9 IVG12 IVG12 IVG13 IVG7 IVG7 IVG7 IVG7
Event Control
ADSP-BF561 provides user with very flexible mechanism control processing events. CEC, three registers used coordinate control events. Each registers bits wide, while each represents particular event class. Interrupt Latch Register (ILAT) ILAT register indicates when events have been latched. appropriate when processor latched event cleared when event been accepted into system. This register updated automatically controller, also written clear (cancel) latched events. This register read while supervisor mode only written while supervisor mode when corresponding IMASK cleared. Interrupt Mask Register (IMASK) IMASK register controls masking unmasking individual events. When IMASK register, that event unmasked will processed when asserted. cleared IMASK register masks event, thereby preventing processor from servicing event even though event latched ILAT register. This register read from written while supervisor mode.
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ADSP-BF561
Note that general-purpose interrupts globally enabled disabled with instructions, respectively. Interrupt Pending Register (IPEND) IPEND register keeps track nested events. IPEND register indicates event currently active nested some level. This register updated automatically controller read while supervisor mode. allows further control event processing providing 32-bit interrupt control status registers. Each register contains corresponding each peripheral interrupt events shown Table Interrupt Mask Registers (SIC_IMASKx) These registers control masking unmasking each peripheral interrupt event. When these registers, that peripheral event unmasked will processed system when asserted. cleared these registers masks peripheral event, thereby preventing processor from servicing event. Interrupt Status Registers (SIC_ISRx) multiple peripherals mapped single event, these registers allow software determine which peripheral event source triggered interrupt. indicates peripheral asserting interrupt; cleared indicates peripheral asserting event. Interrupt Wakeup Enable Registers (SIC_IWRx) enabling corresponding these registers, each peripheral configured wake processor, should processor powered-down mode when event generated. Because multiple interrupt sources single generalpurpose interrupt, multiple pulse assertions occur simultaneously, before during interrupt processing interrupt event already detected this interrupt input. IPEND register contents monitored interrupt acknowledgement. appropriate ILAT register when interrupt rising edge detected (detection requires core clock cycles). cleared when respective IPEND register set. IPEND indicates that event entered into processor pipeline. this point will recognize queue next rising edge event corresponding event input. minimum latency from rising edge transition generalpurpose interrupt IPEND output asserted three core clock cycles; however, latency much higher, depending activity within mode processor. controller. DMA-capable peripherals include SPORTs, port, UART, PPIs. Each individual DMA-capable peripheral least dedicated channel. ADSP-BF561 controllers support both 1-dimensional (1-D) 2-dimensional (2-D) transfers. transfer initialization implemented from registers from sets parameters called descriptor blocks. capability supports arbitrary column sizes elements elements, arbitrary column step sizes elements. Furthermore, column step size less than step size, allowing implementation interleaved data streams. This feature especially useful video applications where data deinterleaved fly. Examples types supported ADSP-BF561 controllers include: single linear buffer that stops upon completion. circular autorefreshing buffer that interrupts each full fractionally full buffer. using linked list descriptors. using array descriptors, specifying only base address within common page. addition dedicated peripheral channels, each Controller four memory channels provided transfers between various memories ADSP-BF561 system. These enable transfers blocks data between memories-including external SDRAM, ROM, SRAM, flash memory-with minimal processor intervention. Memory transfers controlled very flexible descriptorbased methodology standard register-based autobuffer mechanism. Further, ADSP-BF561 four channel Internal Memory (IMDMA) Controller. IMDMA Controller allows data transfers between internal memories.
WATCHDOG TIMER
Each ADSP-BF561 core includes 32-bit timer, which used implement software watchdog function. software watchdog improve system availability forcing processor known state, generation hardware reset, nonmaskable interrupt (NMI), general-purpose interrupt, timer expires before being reset software. programmer initializes count value timer, enables appropriate interrupt, then enables timer. Thereafter, software must reload counter before counts zero from programmed value. This protects system from remaining unknown state where software, which would normally reset timer, stopped running external noise condition software error. After reset, software determine watchdog source hardware reset interrogating status timer control register, which only upon watchdog generated reset.
CONTROLLERS
ADSP-BF561 independent controllers that support automated data transfers with minimal overhead cores. transfers occur between ADSP-BF561 internal memories DMA-capable peripherals. Additionally, transfers accomplished between DMA-capable peripherals external devices connected external memory interfaces, including SDRAM controller asynchronous memory
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ADSP-BF561
timer clocked system clock (SCLK) maximum frequency fSCLK. Interrupts Each transmit receive port generates interrupt upon completing transfer data word after transferring entire data buffer buffers through DMA. Multichannel capability Each SPORT supports channels 1,024-channel window compatible with H.100, H.110, MVIP-90, HMVIP standards. additional SPORT input hysteresis enabled setting PLL_CTL register. When this set, SPORT input pins have increased hysteresis.
TIMERS
There programmable timer units ADSP-BF561. Each general-purpose timer units independently programmed Pulse Width Modulator (PWM), internally externally clocked timer, pulse width counter. general-purpose timer units used conjunction with UART measure width pulses data stream provide autobaud detect function serial channel. general-purpose timers generate interrupts processor core providing periodic events synchronization, either processor clock count external signals. addition general-purpose programmable timers, another timer also provided each core. These extra timers clocked internal processor clock (CCLK) typically used system tick clock generation operating system periodic interrupts.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
ADSP-BF561 processor SPI-compatible port that enables processor communicate with multiple SPI-compatible devices. interface uses three pins transferring data: data pins (master output-slave input, MOSI, master input-slave output, MISO) clock (serial clock, SCK). chip select input (SPISS) lets other devices select processor, seven chip select output pins (SPISEL7-1) processor select other devices. select pins reconfigured programmable flag pins. Using these pins, port provides full-duplex, synchronous serial interface which supports both master/slave modes multimaster environments. baud rate clock phase/polarities port programmable, integrated controller, configurable support transmit receive data streams. controller only service unidirectional accesses given time. port clock rate calculated SCLK Clock Rate SPI_BAUD Where 16-bit SPI_BAUD register contains value 65,535. During transfers, port simultaneously transmits receives serially shifting data serial data lines. serial clock line synchronizes shifting sampling data serial data lines.
SERIAL PORTS (SPORTs)
ADSP-BF561 incorporates dual-channel synchronous serial ports (SPORT0 SPORT1) serial multiprocessor communications. SPORTs support following features: capable operation. Bidirectional operation Each SPORT sets independent transmit receive pins, enabling eight channels stereo audio. Buffered (8-deep) transmit receive ports Each port data register transferring data words from other components shift registers shifting data data registers. Clocking Each transmit receive port either external serial clock generate own, frequencies ranging from (fSCLK/131,070) (fSCLK/2) Word length Each SPORT supports serial data words from bits bits length, transferred most significant first least significant first. Framing Each transmit receive port with without frame sync signals each data word. Frame sync signals generated internally externally, active high low, with either pulse widths early late frame sync. Companding hardware Each SPORT perform A-law -law companding according recommendation G.711. Companding selected transmit and/or receive channel SPORT without additional latencies. operations with single-cycle overhead Each SPORT automatically receive transmit multiple buffers memory data. link chain sequences transfers between SPORT memory.
UART PORT
ADSP-BF561 processor provides full-duplex universal asynchronous receiver/transmitter (UART) port, which fully compatible with PC-standard UARTs. UART port provides simplified UART interface other peripherals hosts, supporting full-duplex, DMA-supported, asynchronous transfers serial data. UART port includes support data bits data bits, stop stop bits, none, even, parity. UART port supports modes operation: (programmed I/O) processor sends receives data writing reading I/O-mapped UART registers. data double-buffered both transmit receive. (direct memory access) controller transfers both transmit receive data. This reduces number frequency interrupts required transfer data from memory. UART dedicated
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channels, transmit receive. These channels have lower default priority than most channels because their relatively service rates. baud rate, serial data format, error code generation status, interrupts UART port programmable. UART programmable features include: Supporting rates ranging from (fSCLK/1,048,576) bits second (fSCLK/16) bits second. Supporting data formats from seven bits bits frame. Both transmit receive operations configured generate maskable interrupts processor. UART port's clock rate calculated SCLK UART Clock Rate UART_Divisor Where 16-bit UART_Divisor comes from UART_DLH register (most significant bits) UART_DLL register (least significant bits). conjunction with general-purpose timer functions, autobaud detection supported. capabilities UART further extended with support Infrared Data Association (IrDA®) serial infrared physical layer link specification (SIR) protocol. Flag interrupt sensitivity registers These registers specify whether individual pins level- edge-sensitive specify, edge-sensitive, whether just rising edge both rising falling edges signal significant. register selects type sensitivity, register selects which edges significant edge sensitivity.
PARALLEL PERIPHERAL INTERFACE
ADSP-BF561 processor provides parallel peripheral interfaces (PPI0, PPI1) that connect directly parallel converters, video encoders decoders, other general-purpose peripherals. consists dedicated input clock pin, frame synchronization pins, data pins. input clock supports parallel data rates fSCLK/2 MHz, synchronization signals configured either inputs outputs. supports variety general-purpose ITU-R modes operation. general-purpose mode, provides half-duplex, bi-directional data transfer with bits data. frame synchronization signals also provided. ITU-R mode, provides half-duplex, bi-directional transfer 10-bit video data. Additionally, on-chip decode embedded start-of-line (SOL) start-of-field (SOF) preamble packets supported.
General-Purpose Mode Descriptions
general-purpose modes intended suit wide variety data capture transmission applications. Three distinct submodes supported: Input mode frame syncs data inputs into PPI. Frame capture mode frame syncs outputs from PPI, data inputs. Output mode frame syncs data outputs from PPI.
PROGRAMMABLE FLAGS (PFx)
ADSP-BF561 bidirectional, general-purpose I/O, programmable flag (PF47-0) pins. Some programmable flag pins used peripherals (see Descriptions Page 17). When used peripheral pin, each programmable flag individually controlled manipulation flag control, status, interrupt registers follows: Flag direction control register Specifies direction each individual input output. Flag control status registers Rather than forcing software read-modify-write process control setting individual flags, ADSP-BF561 employs "write set" "write clear" mechanism that allows combination individual flags cleared single instruction, without affecting level other flags. control registers provided, register written-to order flag values, while another register written-to order clear flag values. Reading flag status register allows software interrogate sense flags. Flag interrupt mask registers These registers allow each individual function interrupt processor. Similar flag control registers that used clear individual flag values, flag interrupt mask register sets bits enable interrupt function, other flag interrupt mask register clears bits disable interrupt function. pins defined inputs configured generate hardware interrupts, while output pins configured generate software interrupts.
Input Mode
Input mode intended applications, well video communication with hardware signaling. simplest form, PPI_FS1 external frame sync input that controls when read data. PPI_DELAY allows delay PPI_CLK cycles) between reception this frame sync initiation data reads. number input data samples user programmable defined contents PPI_COUNT register. supports 8-bit, 10-bit through 16-bit data, programmable PPI_CONTROL register.
Frame Capture Mode
Frame capture mode allows video source(s) slave (e.g., frame capture). ADSP-BF561 processors control when read from video source(s). PPI_FS1 HSYNC output PPI_FS2 VSYNC output.
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Output Mode
Output mode used transmitting video other data with three output frame syncs. Typically, single frame sync appropriate data converter applications, whereas three frame syncs could used sending video with hardware signaling. ITU-R Mode Descriptions ITU-R modes intended suit wide variety video capture, processing, transmission applications. Three distinct submodes supported: Active video only mode Vertical blanking only mode Entire field mode Table Power Settings
Mode/State Bypassed Full-On Enabled Active Enabled/ Disabled Sleep Enabled Deep Sleep Disabled Hibernate Disabled Core Clock (CCLK) Enabled Enabled System Clock (SCLK) Enabled Enabled Core Power
Disabled Enabled Disabled Disabled Disabled Disabled
Active Operating Mode-Moderate Power Savings
active mode, enabled bypassed. Because bypassed, processor's core clock (CCLK) system clock (SCLK) input clock (CLKIN) frequency. this mode, CLKIN CCLK multiplier ratio changed, although changes realized until full-on mode entered. access available appropriately configured memories. active mode, possible disable through control register (PLL_CTL). disabled, must re-enabled before transitioning full-on sleep modes.
Active Video Only Mode
Active video only mode used when only active video portion field interest blanking intervals. does read data between active video (EAV) start active video (SAV) preamble symbols, data present during vertical blanking intervals. this mode, control byte sequences stored memory; they filtered PPI. After synchronizing start Field ignores incoming samples until sees code. user specifies number active video lines frame PPI_COUNT register).
Sleep Operating Mode-High Dynamic Power Savings
sleep mode reduces power dissipation disabling clock processor core (CCLK). system clock (SCLK), however, continue operate this mode. Typically external event will wake processor. When sleep mode, assertion wakeup will cause processor sense value BYPASS control register (PLL_CTL). When sleep mode, system access only available external memory, on-chip memory.
Vertical Blanking Interval Mode
this mode, only transfers vertical blanking interval (VBI) data.
Entire Field Mode
this mode, entire incoming stream read through PPI. This includes active video, control preamble sequences, ancillary data that embedded horizontal vertical blanking intervals. Data transfer starts immediately after synchronization Field
Deep Sleep Operating Mode-Maximum Dynamic Power Savings
deep sleep mode maximizes power savings disabling clocks processor cores (CCLK) synchronous peripherals (SCLK). Asynchronous peripherals will able access internal resources external memory. This powereddown mode only exited assertion reset (RESET). BYPASS disabled, processor will transition full-on mode. BYPASS enabled, processor will transition active mode.
DYNAMIC POWER MANAGEMENT
ADSP-BF561 provides four power management modes power management state, each with different performance/power profile. addition, dynamic power management provides control functions dynamically alter processor core supply voltage, further reducing power dissipation. Control clocking each ADSP-BF561 peripherals also reduces power consumption. Table summary power settings each mode.
Hibernate State-Maximum Static Power Savings
hibernate state maximizes static power savings disabling voltage clocks processor core (CCLK) synchronous peripherals (SCLK). internal voltage regulator processor shut writing b#00 FREQ bits VR_CTL register. This disables both CCLK SCLK. Furthermore, sets internal power supply voltage (VDDINT) provide lowest static power dissipation. critical information stored internally (memory contents, register contents, etc.) must written nonvolatile storage device prior removing power processor state
Full-On Operating Mode-Maximum Performance
full-on mode, enabled bypassed, providing capability maximum operational frequency. This default execution state which maximum performance achieved. processor cores enabled peripherals full speed.
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preserved. Since VDDEXT still supplied this mode, external pins three-state, unless otherwise specified. This allows other devices that connected processor have power still applied without drawing unwanted current. internal supply regulator woken asserting RESET pin.
VOLTAGE REGULATION
ADSP-BF561 processor provides on-chip voltage regulator that generate appropriate VDDINT voltage levels from VDDEXT supply. Operating Conditions Page regulator tolerances acceptable VDDEXT ranges specific models. Figure shows typical external components required complete power management system. regulator controls internal logic voltage levels programmable with voltage regulator control register (VR_CTL) increments reduce standby power consumption, internal voltage regulator programmed remove power processor core while keeping power (VDDEXT) supplied. While hibernate state, VDDEXT still applied, thus eliminating need external buffers. voltage regulator activated from this power-down state asserting RESET, which will then initiate boot sequence. regulator also disabled bypassed user's discretion. internal voltage regulation feature available speed grade models automotive grade models. External voltage regulation required ensure correct operation these parts.
VDDEXT (LOW-INDUCTANCE)
Power Savings
shown Table ADSP-BF561 supports different power domains. multiple power domains maximizes flexibility, while maintaining compliance with industry standards conventions. isolating internal logic ADSP-BF561 into power domain, separate from I/O, processor take advantage Dynamic Power Management, without affecting devices. There sequencing requirements various power domains. Table ADSP-BF561 Power Domains
Power Domain internal logic Range VDDINT VDDEXT
power dissipated processor largely function clock frequency processor square operating voltage. example, reducing clock frequency results reduction dynamic power dissipation, while reducing voltage reduces dynamic power dissipation more than 40%. Further, these power savings additive, that clock frequency supply voltage both reduced, power savings dramatic. dynamic power management feature ADSP-BF561 allows both processor's input voltage (VDDINT) clock frequency (fCCLK) dynamically controlled. savings power dissipation modeled using power savings factor power savings calculations. power savings factor calculated power savings factor CCLKRED DDINTRED DDINTNOM CCLKNOM where variables equations are: fCCLKNOM nominal core clock frequency fCCLKRED reduced core clock frequency VDDINTNOM nominal internal supply voltage VDDINTRED reduced internal supply voltage tNOM duration running fCCLKNOM tRED duration running fCCLKRED percent power savings calculated power savings power savings factor 100%
DECOUPLING CAPACITORS VDDEXT
100µF 100nF 100µF FDS9431A 10µF 100µF ZHCS1000 10µH
VDDINT
VROUT
SHORT LOWINDUCTANCE WIRE NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH FDS9431A.
VROUT
Figure Voltage Regulator Circuit
Voltage Regulator Layout Guidelines
Regulator external component placement, board routing, bypass capacitors have significant effect noise injected into other analog circuits on-chip. VROUT1-0 traces voltage regulator external components should considered noise sources when doing board layout should routed placed near sensitive circuits components board. internal power supplies should well bypassed with bypass capacitors placed close ADSP-BF561 processors possible.
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ADSP-BF561
further details on-chip voltage regulator related board design guidelines, Switching Regulator Design Considerations ADSP-BF533 Blackfin Processors (EE-228) applications note Analog Devices site (www.analog.com)-use site search "EE-228". shown Figure core clock (CCLK) system peripheral clock (SCLK) derived from input clock (CLKIN) signal. on-chip capable multiplying CLKIN signal user-programmable multiplication factor. default multiplier modified software instruction sequence. frequency changes effected simply writing PLL_DIV register.
"FINE" ADJUSTMENT REQUIRES SEQUENCING "COARSE" ADJUSTMENT ON-THE-FLY
CLOCK SIGNALS
ADSP-BF561 processor clocked external crystal, sine wave input, buffered, shaped clock derived from external clock oscillator. external clock used, should compatible signal must halted, changed, operated below specified frequency during normal operation. This signal connected processor's CLKIN pin. When external clock used, XTAL must left unconnected. Alternatively, because ADSP-BF561 processor includes on-chip oscillator circuit, external crystal used. fundamental frequency operation, circuit shown Figure parallel-resonant, fundamental frequency, microprocessor-grade crystal connected across CLKIN XTAL pins. on-chip resistance between CLKIN XTAL range. Further parallel resistors typically recommended. capacitors series resistor shown Figure fine tune phase amplitude sine frequency. capacitor resistor values shown Figure typical values only. capacitor values dependent upon crystal manufacturer's load capacitance recommendations physical layout. resistor value depends drive level specified crystal manufacturer. System designs should verify customized values based careful investigation multiple devices over allowed temperature range. third-overtone crystal used frequencies above MHz. circuit then modified ensure crystal operation only third overtone, adding tuned inductor circuit shown Figure
CLKIN
CCLK
SCLK
SCLK CCLK SCLK 133MHz
Figure Frequency Modification Methods
on-chip peripherals clocked system clock (SCLK). system clock frequency programmable means SSEL3-0 bits PLL_DIV register. values programmed into SSEL fields define divide ratio between output (VCO) system clock. SCLK divider values through Table illustrates typical system clock ratios. Table Example System Clock Ratios
Signal Name SSEL3-0 0001 0110 1010 Divider Ratio VCO/SCLK 10:1 Example Frequency Ratios (MHz) SCLK
Blackfin CLKOUT CIRCUITRY
maximum frequency system clock fSCLK. Note that divisor ratio must chosen limit system clock frequency maximum fSCLK. SSEL value changed dynamically without lock latencies writing appropriate values divisor register (PLL_DIV). core clock (CCLK) frequency also dynamically changed means CSEL1-0 bits PLL_DIV register. Supported CCLK divider ratios shown Table This programmable core clock capability useful fast core frequency modifications.
CLKIN
XTAL OVERTONE OPERATION ONLY:
18pF*
18pF*
NOTE: VALUES MARKED WITH MUST CUSTOMIZED DEPENDING CRYSTAL LAYOUT. PLEASE ANALYZE CAREFULLY.
Figure External Crystal Connections
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ADSP-BF561
Table Core Clock Ratios
Signal Name CSEL1-0 Divider Ratio VCO/CCLK Example Frequency Ratios (MHz) CCLK
host device from transmitting while boot busy, Blackfin processor asserts GPIO pin, called host wait (HWAIT), signal host device send more bytes until flag deasserted. flag chosen user this information transferred Blackfin processor bits 10:5 FLAG header. Boot from serial EEPROM (16-, 24-bit addressable) uses output select single EPROM device, submits read command address 0x0000, begins clocking data into beginning instruction memory. 16-, 24-bit addressable SPI-compatible EPROM must used. each boot modes, boot loading protocol used transfer program data blocks from external memory device their specified memory locations. Multiple memory blocks loaded boot sequence. Once blocks loaded, Core program execution commences from start instruction SRAM (0xFFA0 0000). Core remains heldoff state until SICA_SYSCR cleared Core After that, Core will start execution address 0xFF60 0000. addition, reset configuration register application code bypass normal boot sequence during software reset. this case, processor jumps directly beginning instruction memory.
maximum clock time when change programmed PLL_CTL register maximum time change internal voltage internal voltage regulator also reset value PLL_LOCKCNT register 0x200. This value should programmed ensure wakeup time when either voltage changed MSEL value programmed. value should programmed ensure wakeup time when both voltage MSEL value changed. time base PLL_LOCKCNT register period CLKIN.
BOOTING MODES
ADSP-BF561 three mechanisms (listed Table automatically loading internal instruction memory, external memory after reset. fourth mode provided execute from external memory, bypassing boot sequence. Table Booting Modes
BMODE1-0 Description Execute from 16-bit external memory (Bypass Boot ROM) Boot from 8-bit/16-bit flash Boot from host slave mode Boot from serial EEPROM (16-, 24-bit address range)
INSTRUCTION DESCRIPTION
Blackfin processor family assembly language instruction employs algebraic syntax that designed ease coding readability. instructions have been specifically tuned provide flexible, densely encoded instruction that compiles very small final memory size. instruction also provides fully featured multifunction instructions that allow programmer many processor core resources single instruction. Coupled with many features more often seen microcontrollers, this instruction very efficient when compiling source code. addition, architecture supports both user (algorithm/application code) supervisor (O/S kernel, device drivers, debuggers, ISRs) mode operation-allowing multiple levels access core processor resources. assembly language, which takes advantage processor's unique architecture, offers following advantages: Seamlessly integrated DSP/CPU features optimized both 8-bit 16-bit operations. multi-issue load/store modified Harvard architecture, which supports 16-bit four 8-bit plus load/store plus pointer updates cycle. registers, I/O, memory mapped into unified byte memory space providing simplified programming model. Microcontroller features, such arbitrary bit-field manipulation, insertion, extraction; integer operations 16-, 32-bit data types; separate user kernel stack pointers.
BMODE pins reset configuration register, sampled during power-on resets software initiated resets, implement following modes: Execute from 16-bit external memory Execution starts from address 0x2000 0000 with 16-bit packing. boot bypassed this mode. configuration settings slowest device possible (3-cycle hold time, 15-cycle access times, 4-cycle setup). Note that, bypass mode, only Core execute instructions from external memory. Boot from 8-bit/16-bit external flash memory 8-bit/16-bit flash boot routine located boot memory space using Asynchronous Memory Bank configuration settings slowest device possible (3-cycle hold time; 15-cycle access times; 4-cycle setup). Boot from host device Blackfin processor operates slave mode configured receive bytes .LDR file from host (master) agent. hold
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ADSP-BF561
Code density enhancements, which include intermixing 16-bit 32-bit instructions mode switching, code segregation). Frequently used instructions encoded 16-bits. VisualDSP++ lets programmers define manage software development. dialog boxes property pages programmers configure manage development tools, including color syntax highlighting VisualDSP++ editor. These capabilities permit programmers Control development tools process inputs generate outputs. Maintain one-to-one correspondence with tool's command line switches. VisualDSP++ Kernel (VDK) incorporates scheduling resource management tailored specifically address memory timing constraints embedded, real-time programming. These capabilities enable engineers develop code more effectively, eliminating need start from very beginning when developing application code. features include threads, critical unscheduled regions, semaphores, events, device flags. also supports priority-based, pre-emptive, cooperative, time-sliced scheduling approaches. addition, designed scalable. application does specific feature, support code that feature excluded from target system. Because library, developer decide whether not. integrated into VisualDSP++ development environment, also used with standard command line tools. When used, development environment assists developer with many error prone tasks assists managing system resources, automating generation various VDK-based objects, visualizing system state when debugging application that uses VDK. Expert Linker used visually manipulate placement code data embedded system. Memory utilization viewed color-coded graphical form. Code data easily moved different areas processor external memory with drag mouse. Runtime stack heap usage examined. Expert Linker fully compatible with existing Linker Definition File (LDF), allowing developer move between graphical textual environments. Analog Devices emulators IEEE 1149.1 JTAG test access port ADSP-BF561 monitor control target board processor during emulation. emulator provides fullspeed emulation, allowing inspection modification memory, registers, processor stacks. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect loading timing target system. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting Blackfin processor family. Third party software tools include libraries, real-time operating systems, block diagram design tools.
DEVELOPMENT TOOLS
ADSP-BF561 supported with complete CROSSCORE® software hardware development tools, including Analog Devices emulators VisualDSP++® development environment. same emulator hardware that supports other Analog Devices processors also fully emulates ADSP-BF561. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy assembler that based algebraic syntax, archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ runtime library that includes mathematical functions. point these tools C/C++ code efficiency. compiler been developed efficient translation C/C++ code Blackfin assembly. Blackfin processor architectural features that improve efficiency compiled C/C++ code. VisualDSP++ debugger number important features. Data visualization enhanced plotting package that offers significant level flexibility. This graphical representation user data enables programmer quickly determine performance algorithm. algorithms grow complexity, this capability have increasing significance designer's development schedule, increasing productivity. Statistical profiling enables programmer nonintrusively poll processor running program. This feature, unique VisualDSP++, enables software developer passively gather important code execution metrics without interrupting real-time characteristics program. Essentially, developer identify bottlenecks software quickly efficiently. using profiler, programmer focus those areas program that impact performance take corrective action. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information). Insert breakpoints. conditional breakpoints registers, memory, stacks. Trace instruction execution. Perform linear statistical profiling program execution. Fill, dump, graphically plot contents memory. Perform source level debugging. Create custom debugger windows.
CROSSCORE registered trademark Analog Devices, Inc. VisualDSP++ registered trademark Analog Devices, Inc.
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ADSP-BF561
EZ-KIT Lite Evaluation Board
evaluation ADSP-BF561 processors, ADSP-BF561 EZ-KIT Lite® board available from Analog Devices. Order part number ADDS-BF561-EZLITE. board comes with on-chip emulation capabilities equipped enable software development. Multiple daughter cards available.
RELATED DOCUMENTS
following publications that describe ADSP-BF561 processors (and related processors) ordered from Analog Devices sales office accessed electronically website: Getting Started With Blackfin Processors ADSP-BF561 Blackfin Processor Hardware Reference ADSP-BF53x/BF56x Blackfin Processor Programming Reference ADSP-BF561 Blackfin Processor Anomaly List
DESIGNING EMULATOR-COMPATIBLE PROCESSOR BOARD
Analog Devices family emulators tools that every system developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) ADSP-BF561. emulator uses access internal features processor, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. processor must halted send data commands, once operation been completed emulator, processor running full speed with impact system timing. these emulators, target board must include header that connects processor's JTAG port emulator. details target board design issues, including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, Analog Devices JTAG Emulation Technical Reference (EE-68) Analog Devices website (www.analog.com)-use site search "EE-68." This document updated regularly keep pace with improvements emulator support.
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ADSP-BF561
DESCRIPTIONS
ADSP-BF561 definitions listed Table order maintain maximum function reduce package size count, some pins have multiple functions. cases where function reconfigurable, default state shown plain text, while alternate functionality shown italics. pins three-stated during immediately after reset, except external memory interface, asynchronous memory control, synchronous memory control pins. These pins Table Descriptions
Name EBIU ADDR25-2 DATA31-0 ABE3-0/SDQM3-0 EBIU (ASYNC) AMS3-0 ARDY EBIU (SDRAM) SRAS SCAS SCKE SCLK0/CLKOUT SCLK1 SA10 SMS3-0 Type Function Address Async/Sync Access Data Async/Sync Access Byte Enables/Data Masks Async/Sync Access Request (This should pulled HIGH used.) Grant Grant Hang Bank Select Hardware Ready Control (This should pulled HIGH used.) Output Enable Write Enable Read Enable Address Strobe Column Address Strobe Write Enable Clock Enable Clock Output Clock Output SDRAM Bank Select Driver Type1
driven high, with exception CLKOUT, which toggles system clock rate. However active, memory pins also three-stated. pins have their input buffers disabled, with exception pins that need pull-ups pull-downs unused, noted Table
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ADSP-BF561
Table Descriptions (Continued)
Name PF/SPI/TIMER PF0/SPISS/TMR0 PF1/SPISEL1/TMR1 PF2/SPISEL2/TMR2 PF3/SPISEL3/TMR3 PF4/SPISEL4/TMR4 PF5/SPISEL5/TMR5 PF6/SPISEL6/TMR6 PF7/SPISEL7/TMR7 PF10 PF11 PF12 PF13 PF14 PF15/EXT PPI0 PPI0D15-8/PF47-40 PPI0D7-0 PPI0CLK PPI0SYNC1/TMR8 PPI0SYNC2/TMR9 PPI0SYNC3 PPI1 PPI1D15-8/PF39-32 PPI1D7-0 PPI1CLK PPI1SYNC1/TMR10 PPI1SYNC2/TMR11 PPI1SYNC3 SPORT0 RSCLK0/PF28 RFS0/PF19 DR0PRI DR0SEC/PF20 TSCLK0/PF29 TFS0/PF16 DT0PRI/PF18 DT0SEC/PF17 Type Function Programmable Flag/Slave Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag/SPI Select/Timer Programmable Flag Programmable Flag Programmable Flag Programmable Flag Programmable Flag Programmable Flag Programmable Flag Programmable Flag/External Timer Clock Input Data/Programmable Flag Pins Data Pins Clock Sync/Timer Sync/Timer Sync Data/Programmable Flag Pins Data Pins Clock Sync/Timer Sync/Timer Sync Sport0 Receive Serial Clock/Programmable Flag Sport0 Receive Frame Sync/Programmable Flag Sport0 Receive Data Primary Sport0 Receive Data Secondary/Programmable Flag Sport0 Transmit Serial Clock/Programmable Flag Sport0 Transmit Frame Sync/Programmable Flag Sport0 Transmit Data Primary/Programmable Flag Sport0 Transmit Data Secondary/Programmable Flag Driver Type1
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ADSP-BF561
Table Descriptions (Continued)
Name SPORT1 RSCLK1/PF30 RFS1/PF24 DR1PRI DR1SEC/PF25 TSCLK1/PF31 TFS1/PF21 DT1PRI/PF23 DT1SEC/PF22 MOSI MISO UART RX/PF27 TX/PF26 JTAG TRST Clock CLKIN XTAL Mode Controls RESET NMI0 NMI1 BMODE1-0 SLEEP BYPASS Voltage Regulator VROUT1-0 Supplies VDDEXT VDDINT Connection
Type Function Sport1 Receive Serial Clock/Programmable Flag Sport1 Receive Frame Sync/Programmable Flag Sport1 Receive Data Primary Sport1 Receive Data Secondary/Programmable Flag Sport1 Transmit Serial Clock/Programmable Flag Sport1 Transmit Frame Sync/Programmable Flag Sport1 Transmit Data Primary/Programmable Flag Sport1 Transmit Data Secondary/Programmable Flag Master Slave Master Slave (This should pulled HIGH through resistor booting port.) Clock UART Receive/Programmable Flag UART Transmit/Programmable Flag Emulation Output JTAG Clock JTAG Serial Data JTAG Serial Data JTAG Mode Select JTAG Reset (This should pulled JTAG used.) Clock/Crystal Input (This needs level clocking.) Crystal Connection Reset (This always active during core power-on.) Nonmaskable Interrupt Core (This should pulled when used.) Nonmaskable Interrupt Core (This should pulled when used.) Boot Mode Strap (These pins must pulled state required desired boot mode.) Sleep BYPASS Control (Pull-up pull-down Required.) External Drive Power Supply Power Supply Power Supply Return
Driver Type1
Refer Figure Page Figure Page
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ADSP-BF561
SPECIFICATIONS
Component specifications subject change without notice.
OPERATING CONDITIONS
Parameter VDDINT Internal Supply Voltage1 VDDINT Internal Supply Voltage3 VDDINT Internal Supply Voltage3 VDDEXT External Supply Voltage VDDEXT External Supply Voltage High Level Input Voltage4, Level Input Voltage5 Junction Temperature Junction Temperature Junction Temperature Junction Temperature Junction Temperature
Conditions automotive speed grade models2 speed grade models2 Automotive grade models2 automotive grade models2 Automotive grade models2
0.95 2.25 -0.3 256-Ball CSP_BGA TAMBIENT +70°C 256-Ball CSP_BGA TAMBIENT +70°C 256-Ball CSP_BGA TAMBIENT =-40°C +85°C 297-Ball PBGA TAMBIENT +70°C 297-Ball PBGA TAMBIENT -40°C +85°C
Nominal 1.25 1.35 1.25 2.5,
1.375 1.4185 1.375 +0.6 +105 +115 +115
Unit
Internal voltage (VDDINT) regulator tolerance +10% models. Ordering Guide Page internal voltage regulation feature available. External voltage regulation required ensure correct operation. ADSP-BF561 tolerant (always accepts maximum VIH), voltage compliance outputs, VOH) depends input VDDEXT, because (maximum) approximately equals VDDEXT (maximum). This tolerance applies bidirectional input only pins. Applies signal pins.
Table Table describe timing requirements ADSP-BF561 clocks (tCCLK 1/fCCLK). Take care selecting MSEL, SSEL, CSEL ratios exceed maximum core clock, system clock, Voltage Controlled Oscillator
(VCO) operating frequencies, described Absolute Maximum Ratings Page Table describes phase-locked loop operating conditions.
Table Core Clock (CCLK) Requirements-500 Speed Grade Models1
Parameter fCCLK CCLK Frequency (VDDINT 1.25 Vminimum)2 fCCLK CCLK Frequency (VDDINT 1.1875 Vminimum) CCLK Frequency (VDDINT 1.045 Vminimum) fCCLK fCCLK CCLK Frequency (VDDINT 0.95 Vminimum) fCCLK CCLK Frequency (VDDINT 0.855 Vminimum)3 fCCLK CCLK Frequency (VDDINT minimum)3
Unit
Ordering Guide Page External Voltage regulation required automotive grade models (see Ordering Guide Page ensure correct operation. applicable automotive grade models. Ordering Guide Page
Table Core Clock (CCLK) Requirements-600 Speed Grade Models1
Parameter fCCLK CCLK Frequency (VDDINT 1.2825 minimum)2 fCCLK CCLK Frequency (VDDINT 1.1875 minimum) fCCLK CCLK Frequency (VDDINT 1.045 minimum) fCCLK CCLK Frequency (VDDINT 0.95 minimum) CCLK Frequency (VDDINT 0.855 minimum) fCCLK fCCLK CCLK Frequency (VDDINT minimum)
Unit
Ordering Guide Page External voltage regulator required ensure proper operation MHz.
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ADSP-BF561
Table Phase-Locked Loop Operating Conditions
Parameter Voltage Controlled Oscillator (VCO) Frequency Maximum fCCLK Unit
Table System Clock (SCLK) Requirements
Parameter1 fSCLK fSCLK
CLKOUT/SCLK Frequency (VDDINT 1.14 CLKOUT/SCLK Frequency (VDDINT 1.14
VDDEXT 1.8V/2.5V/3.3V 1332
Unit
tSCLK 1/fSCLK) must greater than equal tCCLK. Rounded number. Guaranteed tSCLK Table Page
ELECTRICAL CHARACTERISTICS
Parameter IIHP IIL4 IOZH IOZL4 IDDHIBERNATE IDDDEEPSLEEP8 IDD_TYP8, IDD_TYP8, IDD_TYP8,
High Level Output Voltage1 Level Output Voltage1 High Level Input Current2 High Level Input Current JTAG3 Level Input Current2 Three-State Leakage Current5 Three-State Leakage Current5 Input Capacitance6 VDDEXT Current Hibernate Mode VDDINT Current Deep Sleep Mode VDDINT Current VDDINT Current VDDINT Current
Test Conditions VDDEXT -0.5 VDDEXT VDDEXT Maximum, Maximum VDDEXT Maximum, Maximum VDDEXT Maximum, VDDEXT Maximum, Maximum VDDEXT Maximum, MHz, TAMBIENT 25°C, CLKIN=0 MHz, VDDEXT 3.65 with Voltage Regulator (VDDINT VDDINT TJUNCTION 25°C VDDINT fCCLK MHz, TJUNCTION 25°C VDDINT 1.25 fCCLK MHz, TJUNCTION 25°C VDDINT 1.35 fCCLK MHz, TJUNCTION 25°C
Typical
10.0 50.0 10.0 10.0 10.0
Unit
Applies output bidirectional pins. Applies input pins except JTAG inputs. Applies JTAG input pins (TCK, TDI, TMS, TRST). Absolute value. Applies three-statable pins. Applies signal pins. Guaranteed, tested. Maximum current drawn. Estimating Power ADSP-BF561 Blackfin Processors (EE-293) Analog Devices website (www.analog.com)-use site search "EE-293". Both cores executing dual MAC, instructions with moderate data activity.
System designers should refer Estimating Power ADSP-BF561 (EE-293), which provides detailed information optimizing designs lowest power. topics discussed this section described detail EE-293. Total power dissipation components: Static, including leakage current Dynamic, transistor switching characteristics Many operating conditions also affect power dissipation, including temperature, voltage, operating frequency, processor activity. Electrical Characteristics Page shows current dissipation internal circuitry (VDDINT).
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ADSP-BF561
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed Table cause permanent damage device. These stress ratings only. Functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Table Absolute Maximum Ratings
Parameter Internal (Core) Supply Voltage (VDDINT) External (I/O) Supply Voltage (VDDEXT) Input Voltage1 Output Voltage Swing Load Capacitance2 Storage Temperature Range Junction Temperature Under Bias
PACKAGE INFORMATION
information presented Figure Table provides details about package branding Blackfin processors. complete listing product availability, Ordering Guide Page
ADSP-BF561 tppZccc vvvvvv.x yyww country_of_origin
Value -0.3 +1.42 -0.5 +3.8 -0.5 +3.8 -0.5 VDDEXT +150
Figure Product Information Package
Table Package Brand Information
Brand vvvvvv.x yyww Field Description Temperature Range Package Type RoHS Compliant Part Ordering Guide Assembly Code Silicon Revision Date Code
Applies 100% transient duty cycle. other duty cycles Table proper SDRAM controller operation, maximum load capacitance ADDR19-1, DATA15-0, ABE1-0/SDQM1-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, SMS.
Table Maximum Duty Cycle Input Transient Voltage1
-0.50 -0.70 -0.80 -0.90 -1.00
(V)2 3.80 4.00 4.10 4.20 4.30
Maximum Duty Cycle 100%
SENSITIVITY
Applies signal pins with exception CLKIN, XTAL, VROUT1-0. Only listed options apply particular design.
(electrostatic discharge) sensitive device.
Charged devices circuit boards discharge without detection. Although this product features patented proprietary protection circuitry, damage occur devices subjected high energy ESD. Therefore, proper precautions should taken avoid performance degradation loss functionality.
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ADSP-BF561
TIMING SPECIFICATIONS
Clock Reset Timing
Table Figure describe clock reset operations. Absolute Maximum Ratings Page combinations CLKIN clock multipliers must result core/system clocks exceeding maximum limits allowed processor, including system clock restrictions related supply voltage. Table Clock Reset Timing
Parameter Timing Requirements tCKIN CLKIN PLL) Period1, tCKINL CLKIN Pulse tCKINH CLKIN High Pulse tWRST RESET Asserted Pulse Width Low4
25.0 10.0 10.0 tCKIN
100.0
Unit
PLL_CTL register tCLKIN divided before going PLL, then tCLKIN maximum period tCLKIN minimum period 12.5 Applies bypass mode nonbypass mode. Combinations CLKIN frequency clock multiplier must exceed allowed fVCO, fCCLK, fSCLK settings discussed Table Page through Table Page Applies after power-up sequence complete. power-up, processor's internal phase-locked loop requires more than 2,000 CLKIN cycles, while RESET asserted, assuming stable power supplies CLKIN (not including startup time external clock oscillator).
tCKIN
CLKIN
tCKINL
RESET
tCKINH tWRST
Figure Clock Reset Timing
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ADSP-BF561
Asynchronous Memory Read Cycle Timing
Table Asynchronous Memory Read Cycle Timing
Parameter Timing Requirements tSDAT DATA31-0 Setup Before CLKOUT tHDAT DATA31-0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics Output Delay After CLKOUT1 Output Hold After CLKOUT
Unit
Output pins include AMS3-0, ABE3-0, ADDR25-2, AOE, ARE.
SETUP CYCLES
PROGRAMMED READ ACCESS CYCLES
ACCESS EXTENDED CYCLES
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ABE, ADDRESS
SARDY
ARDY
tHARDY
HARDY
SARDY
SDAT HDAT
DATA15-0
READ
Figure Asynchronous Memory Read Cycle Timing
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ADSP-BF561
Asynchronous Memory Write Cycle Timing
Table Asynchronous Memory Write Cycle Timing
Parameter Timing Requirements tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDDAT DATA31-0 Disable After CLKOUT DATA31-0 Enable After CLKOUT tENDAT Output Delay After CLKOUT1 Output Hold After CLKOUT
Unit
Output pins include AMS3-0, ABE3-0, ADDR25-2, DATA31-0, AOE, AWE.
SETUP CYCLES
PROGRAMMED WRITE ACCESS CYCLES
ACCESS EXTENDED CYCLE
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ABE, ADDRESS
SARDY
ARDY
HARDY
DATA15-0 WRITE DATA
tSARDY
Figure Asynchronous Memory Write Cycle Timing
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ADSP-BF561
SDRAM Interface Timing
Table SDRAM Interface Timing
Parameter Timing Requirements tSSDAT DATA Setup Before CLKOUT tHSDAT DATA Hold After CLKOUT Switching Characteristics tDCAD Command, ADDR, Data Delay After CLKOUT1 Command, ADDR, Data Hold After CLKOUT1 tHCAD tDSDAT Data Disable After CLKOUT tENSDAT Data Enable After CLKOUT tSCLK2 CLKOUT Period when +105°C tSCLK2 CLKOUT Period when +105°C tSCLKH CLKOUT Width High CLKOUT Width tSCLKL
Unit
Command pins include: SRAS, SCAS, SWE, SDQM, SMS3-0, SA10, SCKE. These limits specific SDRAM interface only.
tSCLK
CLKOUT
tSCLKH
SSDAT tHSDAT
DATA (IN)
SCLKL
DCAD tENSDAT
DATA(OUT)
tHCAD
tDCAD
CMND ADDR (OUT)
tHCAD
NOTE: COMMAND SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure SDRAM Interface Timing
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ADSP-BF561
External Port Request Grant Cycle Timing
Table Figure describe external port request grant operations. Table External Port Request Grant Cycle Timing
Parameter1, Timing Requirements Asserted CLKOUT High Setup CLKOUT High Deasserted Hold Time Switching Characteristics CLKOUT AMSx, Address ARE/AWE Disable CLKOUT AMSx, Address ARE/AWE Enable tDBG CLKOUT High Asserted Setup tEBG CLKOUT High Deasserted Hold Time tDBH CLKOUT High Asserted Setup CLKOUT High Deasserted Hold Time tEBH
Unit
These preliminary timing parameters that based worst-case operating conditions. loads these timing parameters
CLKOUT
AMSx
ADDR25-2 ABE3-0
tDBG
tEBG
tDBH
tEBH
Figure External Port Request Grant Cycle Timing
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ADSP-BF561
Parallel Peripheral Interface Timing
Table Figure through Figure Page describe default Parallel Peripheral Interface operations. Table Parallel Peripheral Interface Timing
Parameter Timing Requirements tPCLKW PPIxCLK Width1 tPCLK PPIxCLK Period1 External Frame Sync Setup Before PPIxCLK tSFSPE tHFSPE External Frame Sync Hold After PPIxCLK tSDRPE Receive Data Setup Before PPIxCLK tHDRPE Receive Data Hold After PPIxCLK Switching Characteristics tDFSPE Internal Frame Sync Delay After PPIxCLK Internal Frame Sync Hold After PPIxCLK tHOFSPE tDDTPE Transmit Data Delay After PPIxCLK tHDTPE Transmit Data Hold After PPIxCLK
PLL_CTL register set, then Figure Page Figure Page apply.
13.3
Unit
modes that internally generated frame sync, PPIxCLK frequency cannot exceed fSCLK/2. modes with frame syncs external frame syncs, PPIxCLK cannot exceed fSCLK should equal greater than PPIxCLK.
FRAME SYNC DRIVEN POLC PPIxCLK
DATA0 SAMPLED
PPIxCLK POLC tDFSPE POLS PPIxSYNC11 POLS
HOFSPE
POLS PPIxSYNC2 POLS tSDRPE tHDRPE
PPIx_DATA
Figure Mode with Internal Frame Sync Timing (Default)
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ADSP-BF561
FRAME SYNC SAMPLED DATA0
DATA0 SAMPLED PPIxCLK POLC PPIxCLK POLC
DATA1 SAMPLED
tSFSPE POLS PPIxSYNC1 POLS
HFSPE
POLS PPIxSYNC2 POLS
SDRPE
HDRPE
PPIx_DATA
Figure Mode with External Frame Sync Timing (Default)
FRAME SYNC DRIVEN
DATA0 DRIVEN
PPIxCLK POLC PPIxCLK POLC tHOFSPE POLS PPIxSYNC1 POLS
DFSPE
POLS PPIxSYNC2 POLS
DDTPE
tHDTPE
PPIx_DATA
DATA0
Figure Mode with Internal Frame Sync Timing (Default)
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ADSP-BF561
FRAME SYNC SAMPLED PPIxCLK POLC PPIxCLK POLC tHFSPE POLS PPxSYNC1 POLS
SFSPE
DATA0 DRIVEN
POLS PPIxSYNC2 POLS
HDTPE
PPIx_DATA
DATA0
tDDTPE
Figure Mode with External Frame Sync Timing (Default)
DATA SAMPLING/ FRAME SYNC SAMPLING EDGE PPIxCLK POLC PPIxCLK POLC
DATA SAMPLING/ FRAME SYNC SAMPLING EDGE
tSFSPE POLS PPIxSYNC1 POLS
HFSPE
POLS PPIxSYNC2 POLS tSDRPE tHDRPE
PPIx_DATA
Figure Mode with External Frame Sync Timing (Bit PLL_CTL Set)
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ADSP-BF561
DATA DRIVING/ FRAME SYNC SAMPLING EDGE PPIxCLK POLC PPIxCLK POLC POLS PPIxSYNC1 POLS
SFSPE HFSPE
DATA DRIVING/ FRAME SYNC SAMPLING EDGE
POLS PPIxSYNC2 POLS tDDTPE PPIx_DATA
HDTPE
Figure Mode with External Frame Sync Timing (Bit PLL_CTL Set)
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ADSP-BF561
Serial Ports
Table through Table Page Figure Page through Figure Page describe Serial Port operations. Table Serial Ports-External Clock
Parameter Timing Requirements tSFSE TFSx/RFSx Setup Before TSCLKx/RSCLKx1 tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx1 tSDRE Receive Data Setup Before RSCLKx1 tHDRE Receive Data Hold After RSCLKx1 tSCLKW TSCLKx/RSCLKx Width tSCLK TSCLKx/RSCLKx Period Switching Characteristics tDFSE TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tDDTE Transmit Data Delay After TSCLKx2 tHDTE Transmit Data Hold After TSCLKx2
15.0
Unit
10.0 10.0
Referenced sample edge. Referenced drive edge.
Table Serial Ports-Internal Clock
Parameter Timing Requirements tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1 tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx1 Receive Data Setup Before RSCLKx1 tSDRI tHDRI Receive Data Hold After RSCLKx1 tSCLKW TSCLKx/RSCLKx Width tSCLK TSCLKx/RSCLKx Period Switching Characteristics tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2 tDDTI Transmit Data Delay After TSCLKx2 tHDTI Transmit Data Hold After TSCLKx2 tSCLKIW TSCLKx/RSCLKx Width
-2.0 15.0
Unit
-1.0 -2.0
Referenced sample edge. Referenced drive edge.
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ADSP-BF561
DATA RECEIVE-INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA RECEIVE-EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
RSCLKx RSCLKx
tSCLKEW
tDFSI tHOFSI
RFSx
tDFSE tSFSI tHFSI
RFSx
tHOFSE
tSFSE
tHFSE
tSDRI
tHDRI
tSDRE
tHDRE
NOTE: EITHER RISING EDGE FALLING EDGE RSCLKx TSCLKx USED ACTIVE SAMPLING EDGE. DATA TRANSMIT-INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA TRANSMIT-EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
TSCLKx TSCLKx
tSCLKEW
tDFSI tHOFSI
TFSx
tDFSE tSFSI tHFSI
TFSx
tHOFSE
tSFSE
tHFSE
tDDTI tHDTI
tDDTE tHDTE
NOTE: EITHER RISING EDGE FALLING EDGE RSCLKx TSCLKx USED ACTIVE SAMPLING EDGE.
Figure Serial Ports
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ADSP-BF561
Table Serial Ports-Enable Three-State
Parameter Switching Characteristics Data Enable Delay from External TSCLKx1 tDTENE tDDTTE Data Disable Delay from External TSCLKx1 tDTENI Data Enable Delay from Internal TSCLKx1 tDDTTI Data Disable Delay from Internal TSCLKx1
Unit
10.0 -2.0
Referenced drive edge.
Table External Late Frame Sync
Parameter Switching Characteristics tDDTLFSE Data Delay from Late External TFSx External RFSx with tDTENLFS Data Enable from Late
10.0
Unit
TFSx enable TFSx valid follow tDTENLFS tDDTLFSE. external RFSx/TFSx setup RSCLKx/TSCLKx tSCLKE/2, then tDDTTE/I tDTENE/I apply; otherwise tDDTLFSE tDTENLFS apply.
EXTERNAL WITH DRIVE RSCLKx SAMPLE DRIVE
tSFSE/I
tHOFSE/I
RFSx
tDTENLFS
tDDTTE/I tDTENE/I
tDDTLFSE
LATE EXTERNAL DRIVE TSCLKx SAMPLE DRIVE
tSFSE/I
tHOFSE/I
TFSx
tDTENLFS
tDDTTE/I tDTENE/I
tDDTLFSE
Figure External Late Frame Sync
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ADSP-BF561
Serial Peripheral Interface (SPI) Port- Master Timing
Table Figure describe port master operations. Table Serial Peripheral Interface (SPI) Port-Master Timing
Parameter Timing Requirements Data Input Valid Edge (Data Input Setup) tSSPIDM tHSPIDM Sampling Edge Data Input Invalid Switching Characteristics tSDSCIM SPISELx First Edge tSPICHM Serial Clock High Period tSPICLM Serial Clock Period Serial Clock Period tSPICLK tHDSM Last Edge SPISELx High tSPITDM Sequential Transfer Delay tDDSPIDM Edge Data Valid (Data Delay) tHDSPIDM Edge Data Invalid (Data Hold) -1.5 tSCLK tSCLK tSCLK tSCLK tSCLK tSCLK -1.0 Unit
+4.0
SPIxSELy (OUTPUT)
tSDSCIM
SCKx (CPOL (OUTPUT)
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tSPICLM
SCKx (CPOL (OUTPUT)
tSPICHM
tHDSPIDM
MOSIx (OUTPUT) CPHA=1 MISOx (INPUT) VALID
tDDSPIDM
tSSPIDM
VALID
tHSPIDM
tHDSPIDM
MOSIx (OUTPUT) CPHA=0 MISOx (INPUT)
tDDSPIDM
tSSPIDM
VALID
tHSPIDM
VALID
Figure Serial Peripheral Interface (SPI) Port-Master Timing
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ADSP-BF561
Serial Peripheral Interface (SPI) Port- Slave Timing
Table Figure describe port slave operations. Table Serial Peripheral Interface (SPI) Port-Slave Timing
Parameter Timing Requirements Serial Clock High Period tSPICHS tSPICLS Serial Clock Period tSPICLK Serial Clock Period tHDS Last Edge SPISS Asserted tSPITDS Sequential Transfer Delay tSDSCI SPISS Assertion First Edge Data Input Valid Edge (Data Input Setup) tSSPID tHSPID Sampling Edge Data Input Invalid Switching Characteristics tDSOE SPISS Assertion Data Active tDSDHI SPISS Deassertion Data High Impedance tDDSPID Edge Data Valid (Data Delay) Edge Data Invalid (Data Hold) tHDSPID tSCLK tSCLK tSCLK tSCLK tSCLK tSCLK Unit
SPIxSS (INPUT)
tSPICHS
SCKx (CPOL (INPUT)
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
SCKx (CPOL (INPUT)
tSPICLS
tSPICHS
tDDSPID tDSOE
MISOx (OUTPUT) CPHA=1 MOSIx (INPUT)
tHDSPID
tDDSPID
tDSDHI
tSSPID
VALID
tHSPID
VALID
tDSOE
MISOx (OUTPUT) CPHA=0 MOSIx (INPUT) VALID
tHDSPID
tDDSPID
tHDSPID
tDSDHI
tHSPID tSSPID
VALID
Figure Serial Peripheral Interface (SPI) Port-Slave Timing
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ADSP-BF561
Universal Asynchronous Receiver Transmitter (UART) Port-Receive Transmit Timing
Figure describes UART port receive transmit operations. maximum baud rate SCLK/16. shown Figure there some latency between generation internal UART interrupts external data operations. These latencies negligible data transmission rates UART.
CLKOUT (SAMPLE CLOCK)
DATA8-5 STOP
RECEIVE INTERNAL UART RECEIVE INTERRUPT
UART RECEIVE DATA STOP; CLEARED FIFO READ
START DATA WRITTEN BUFFER INTERNAL UART TRANSMIT INTERRUPT UART TRANSMIT PROGRAM; CLEARED WRITE TRANSMIT DATA8-5 STOP2-1
TRANSMIT
Figure UART Port-Receive Transmit Timing
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ADSP-BF561
Programmable Flags Cycle Timing
Table Figure describe programmable flag operations. Table Programmable Flags Cycle Timing
Parameter Timing Requirement tWFI Flag Input Pulse Width Switching Characteristic tDFO Flag Output Delay from CLKOUT tSCLK Unit
CLKOUT
tDFO
(OUTPUT) FLAG OUTPUT
tWFI
(INPUT) FLAG INPUT
Figure Programmable Flags Cycle Timing
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ADSP-BF561
Timer Cycle Timing
Table Figure describe timer expired operations. input signal asynchronous width capture mode external clock mode absolute maximum input frequency fSCLK/2 MHz. Table Timer Cycle Timing
Parameter Timing Characteristics Timer Pulse Width Input Low1 (Measured SCLK Cycles) Timer Pulse Width Input High1 (Measured SCLK Cycles) Switching Characteristic tHTO Timer Pulse Width Output2 (Measured SCLK Cycles)
Unit SCLK SCLK
(232-1)
SCLK
minimum pulse widths apply TMRx input pins width capture external clock modes. They also apply PPIxCLK input pins output mode. minimum time tHTO cycle, maximum time tHTO equals (232-1) cycles.
CLKOUT
tHTO
TMRx (PWM OUTPUT MODE)
TMRx (WIDTH CAPTURE EXTERNAL CLOCK MODES)
Figure Timer PWM_OUT Cycle Timing
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ADSP-BF561
JTAG Test Emulation Port Timing
Table Figure describe JTAG port operations. Table JTAG Port Timing
Parameter Timing Parameters tTCK Period tSTAP TDI, Setup Before High tHTAP TDI, Hold After High tSSYS System Inputs Setup Before High1 tHSYS System Inputs Hold After High1 tTRSTW TRST Pulse Width2 (Measured Cycles) Switching Characteristics tDTDO Delay from tDSYS System Outputs Delay After Low3
Unit
System Inputs= DATA31-0, ARDY, PF47-0, PPI0CLK, PPI1CLK, RSCLK0-1, RFS0-1, DR0PRI, DR0SEC, TSCLK0-1, TFS0-1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RESET, NMI0, NMI1, BMODE1-0, PPIxD7-0. maximum System Outputs DATA31-0, ADDR25-2, ABE3-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS3-0, PF47-0, RSCLK0-1, RFS0-1, TSCLK0-1, TFS0-1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, BGH, PPIxD7-0.
tTCK
tSTAP
tHTAP
tDTDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUTS
Figure JTAG Port Timing
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ADSP-BF561
OUTPUT DRIVE CURRENTS
Figure through Figure Page show typical current voltage characteristics output drivers ADSP-BF561 processor. curves represent current drive capability output drivers function output voltage. Refer Table Page identify driver type pin.
VDDEXT 2.75V VDDEXT 2.50V VDDEXT 2.25V VDDEXT 2.75V VDDEXT 2.50V VDDEXT 2.25V
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
-100 -150
SOURCE VOLTAGE
Figure Drive Current (Low VDDEXT)
-100 VDDEXT 3.65V VDDEXT 2.95V VDDEXT 3.30V
-150
SOURCE CURRENT (mA)
SOURCE VOLTAGE
Figure Drive Current (Low VDDEXT)
VDDEXT 3.65V VDDEXT 3.30V VDDEXT 2.95V
SOURCE CURRENT (mA)
-100 -150 SOURCE VOLTAGE
Figure Drive Current (High VDDEXT)
-100 VDDEXT 2.75V VDDEXT 2.50V VDDEXT 2.25V
-150
SOURCE VOLTAGE SOURCE CURRENT (mA)
Figure Drive Current (High VDDEXT)
SOURCE VOLTAGE
Figure Drive Current (Low VDDEXT)
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ADSP-BF561
SOURCE CURRENT (mA) -100 VDDEXT 3.65V VDDEXT 3.30V VDDEXT 2.95V
POWER DISSIPATION
Many operating conditions affect power dissipation. System designers should refer Estimating Power ADSP-BF561 Blackfin Processors (EE-293) Analog Devices website (www.analog.com)-use site search "EE-293." This document provides detailed information optimizing your design lowest power. ADSP-BF561 Blackfin Processor Hardware Reference Manual definitions various operating modes instructions minimize system power.
TEST CONDITIONS
timing parameters appearing this data sheet were measured under conditions described this section. Figure shows measurement point measurements (except output enable/disable). measurement point VMEAS VDDEXT (nominal) V/3.3
INPUT OUTPUT
SOURCE VOLTAGE
Figure Drive Current (High VDDEXT)
SOURCE CURRENT (mA) -100 VDDEXT 2.75V VDDEXT 2.50V VDDEXT 2.25V
VMEAS
VMEAS
Figure Voltage Reference Levels Measurements (Except Output Enable/Disable)
Output Enable Time Measurement
Output pins considered enabled when they have made transition from high impedance state point when they start driving. output enable time tENA interval from point when reference signal reaches high voltage level point when output starts driving shown right side Figure Page time tENA_MEASURED interval, from when reference signal switches, when output voltage reaches VTRIP(high) VTRIP(low). VTRIP(high) VTRIP(low) VDDEXT (nominal) V/3.3 Time tTRIP interval from when output starts driving when output reaches VTRIP(high) VTRIP(low) trip voltage. Time tENA calculated shown equation: ENA_MEASURED TRIP
SOURCE VOLTAGE
Figure Drive Current (Low VDDEXT)
VDDEXT 3.65V VDDEXT 3.30V VDDEXT 2.95V
SOURCE CURRENT (mA)
multiple pins (such data bus) enabled, measurement value that first start driving.
-100
Output Disable Time Measurement
Output pins considered disabled when they stop driving, into high impedance state, start decay from their output high voltage. output disable time tDIS difference between tDIS_MEASURED tDECAY shown left side Figure Page DIS_MEASURED DECAY
-150 SOURCE VOLTAGE
Figure Drive Current (High VDDEXT)
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ADSP-BF561
RISE FALL TIME (10% 90%)
time voltage decay dependent capacitive load load current This decay time approximated equation: DECAY time tDECAY calculated with test loads with equal VDDEXT (nominal) V/3.3 time tDIS_MEASURED interval from when reference signal switches, when output voltage decays from measured output high output voltage.
RISE TIME FALL TIME
Example System Hold Time Calculation
determine data output hold time particular system, first calculate tDECAY using equation given above. Choose difference between ADSP-BF561 processor's output voltage input threshold device requiring hold time. total capacitance (per data line), total leakage three-state current (per data line). hold time will tDECAY plus various output disable times specified Timing Specifications Page (for example tDSDAT SDRAM write cycle shown SDRAM Interface Timing Page 26).
LOAD CAPACITANCE (pF)
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT (min)
RISE FALL TIME (10% 90%)
RISE TIME FALL TIME
REFERENCE SIGNAL
tDIS_MEASURED tDIS
(MEASURED) (MEASURED)
tENA_MEASURED tENA
VOH(MEASURED)
(MEASURED)
(MEASURED)
VTRIP(HIGH) VTRIP(LOW) VOL(MEASURED)
LOAD CAPACITANCE (pF)
tDECAY
tTRIP
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT (max)
RISE FALL TIME (10% 90%)
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING HIGH IMPEDANCE STATE
Figure Output Enable/Disable
RISE TIME FALL TIME
Capacitive Loading
Output delays holds based standard capacitive loads: pins (see Figure 37). VLOAD VDDEXT (nominal) V/3.3 Figure through Figure Page show output rise time varies with capacitance. delay hold specifications given should derated factor derived from these figures. graphs these figures linear outside ranges shown.
OUTPUT 30pF VLOAD
LOAD CAPACITANCE (pF)
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT (min)
Figure Equivalent Device Loading Measurements (Includes Fixtures)
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ADSP-BF561
DDEXT
RISE FALL TIME (10% 90%) RISE TIME FALL TIME LOAD CAPACITANCE (pF) RISE FALL TIME (10% 90%)
RISE TIME FALL TIME
LOAD CAPACITANCE (pF)
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT (max)
RISE FALL TIME (10% 90%)
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT (min)
RISE FALL TIME (10% 90%) RISE TIME
RISE TIME
FALL TIME
FALL TIME
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT (min)
RISE FALL TIME (10% 90%) RISE TIME FALL TIME LOAD CAPACITANCE (pF)
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT (max)
ENVIRONMENTAL CONDITIONS
determine junction temperature application printed circuit board use: CASE where: junction temperature TCASE case temperature measured customer center package. from Table Page through Table Page power dissipation (see Power Dissipation Page method calculate PD). Values provided package comparison printed circuit board design considerations. used first order approximation equation: where: ambient temperature
Figure Typical Rise Fall Times (10% 90%) versus Load Capacitance Driver VDDEXT (max)
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ADSP-BF561
Table through Table airflow measurements comply with JEDEC standards JESD51-2 JESD51-6, junction-to-board measurement complies with JESD51-8. junction-to-case measurement complies with MIL-STD-883 (Method 1012.1). measurements 2S2P JEDEC test board. Thermal resistance Table through Table figure merit relating performance package board convective environment. represents thermal resistance under conditions airflow. represents heat extracted from periphery board. represents correlation between TCASE. Values provided package comparison printed circuit board design considerations. Table Thermal Characteristics BC-256-4 Package
Parameter Condition Linear Airflow Linear Airflow Linear Airflow Applicable Linear Airflow Linear Airflow Linear Airflow Typical 18.1 15.9 15.1 3.72 0.11 0.18 0.18 Unit
Table Thermal Characteristics BC-256-1 Package
Parameter Condition Linear Airflow Linear Airflow Linear Airflow Applicable Applicable Linear Airflow Linear Airflow Linear Airflow Typical 25.6 22.4 21.6 18.9 4.85 0.15 Unit
Table Thermal Characteristics B-297 Package
Parameter Condition Linear Airflow Linear Airflow Linear Airflow Applicable Applicable Linear Airflow Linear Airflow Linear Airflow Typical 20.6 17.8 17.4 16.3 7.15 0.37 Unit
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ADSP-BF561
256-BALL CSP_BGA BALL ASSIGNMENT
Table lists 256-Ball CSP_BGA ball assignment ball number. Table Page lists ball assignment alphabetically signal. Table 256-Ball CSP_BGA Ball Assignment (Numerically Ball Number)
Ball Signal VDDEXT ADDR22 ADDR18 ADDR14 ADDR11 AMS3 AMS0 ARDY SMS2 SCLK0 SCLK1 ABE2 ABE3 ADDR06 ADDR03 VDDEXT ADDR24 ADDR23 ADDR19 ADDR17 ADDR12 ADDR10 AMS1 SMS1 SCKE ADDR08 ADDR05 ADDR02 DATA04 PPI0SYNC1 ADDR25 PPI0CLK ADDR20 ADDR16 ADDR13 AMS2 Ball Signal SMS3 SA10 ABE0 ADDR07 ADDR04 DATA0 DATA05 PPI0D15 PPI0SYNC3 PPI0SYNC2 ADDR21 ADDR15 ADDR09 SMS0 SRAS SCAS ABE1 DATA02 DATA01 DATA03 DATA07 PPI0D11 PPI0D13 PPI0D12 PPI0D14 PPI1CLK VDDINT VDDINT VDDINT VDDINT DATA06 DATA13 DATA09 DATA12 Ball Signal CLKIN PPI0D10 RESET BYPASS VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT DATA11 DATA08 DATA10 DATA16 XTAL VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT DATA17 DATA14 DATA15 DATA18 VROUT0 VDDINT VDDINT Ball Signal DATA21 DATA19 DATA23 VROUT1 PPI0D8 PPI0D7 PPI0D9 VDDINT VDDINT DATA20 DATA22 DATA24 PPI0D6 PPI0D5 PPI0D4 PPI1SYNC3 VDDEXT VDDEXT VDDEXT DATA26 DATA25 DATA27 Ball Signal PPI0D3 PPI0D2 PPI0D1 PPI0D0 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT DT0PRI DATA31 DATA28 PPI1SYNC2 PPI1D15 PPI1D14 PPI1D9 VDDINT VDDINT VDDINT VDDINT VDDINT RSCLK0 DR0PRI TSCLK0 DATA29 PPI1SYNC1 PPI1D10 PPI1D7 PPI1D5 PF04 PF09 PF12
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ADSP-BF561
Table 256-Ball CSP_BGA Ball Assignment (Numerically Ball Number) (Continued)
Ball Signal BMODE1 BMODE0 DR1SEC DT1SEC RFS0 DATA30 PPI1D13 PPI1D8 PPI1D6 PPI1D0 Ball Signal PF01 PF06 PF08 PF15 NMI1 NMI0 RFS1 TFS1 DR0SEC DT0SEC Ball Signal PPI1D12 PPI1D11 PPI1D4 PPI1D1 PF02 PF07 PF11 PF14 TRST SLEEP MOSI Ball Signal RSCLK1 TSCLK1 TFS0 VDDEXT PPI1D3 PPI1D2 PF03 PF05 PF10 PF13 Ball Signal MISO DR1PRI DT1PRI VDDEXT
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ADSP-BF561
Table 256-Ball CSP_BGA Ball Assignment (Alphabetically Signal)
Signal ABE0 ABE1 ABE2 ABE3 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 AMS0 AMS1 AMS2 AMS3 ARDY BMODE0 BMODE1 Ball Signal BYPASS CLKIN DATA0 DATA01 DATA02 DATA03 DATA04 DATA05 DATA06 DATA07 DATA08 DATA09 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI Ball Signal DT0SEC DT1PRI DT1SEC Ball Signal MISO MOSI NMI0 NMI1 PF01 PF02 PF03 PF04 PF05 PF06 PF07 PF08 PF09 PF10 PF11 PF12 PF13 PF14 PF15 PPI0CLK PPI0D0 PPI0D1 PPI0D2 PPI0D3 PPI0D4 PPI0D5 PPI0D6 PPI0D7 PPI0D8 PPI0D9 PPI0D10 PPI0D11 PPI0D12 Ball Signal PPI0D13 PPI0D14 PPI0D15 PPI0SYNC1 PPI0SYNC2 PPI0SYNC3 PPI1CLK PPI1D0 PPI1D1 PPI1D2 PPI1D3 PPI1D4 PPI1D5 PPI1D6 PPI1D7 PPI1D8 PPI1D9 PPI1D10 PPI1D11 PPI1D12 PPI1D13 PPI1D14 PPI1D15 PPI1SYNC1 PPI1SYNC2 PPI1SYNC3 RESET RFS0 RFS1 RSCLK0 RSCLK1 SA10 SCAS SCKE SCLK0 SCLK1 SLEEP SMS0 Ball
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ADSP-BF561
Table 256-Ball CSP_BGA Ball Assignment (Alphabetically Signal) (Continued)
Signal SMS1 SMS2 SMS3 SRAS TFS0 TFS1 TRST Ball Signal TSCLK0 TSCLK1 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Ball Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Ball Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT Ball Signal VDDINT VDDINT VDDINT VDDINT VDDINT VROUT0 VROUT1 XTAL Ball
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ADSP-BF561
Figure lists view 256-Ball CSP_BGA ball configuration. Figure lists bottom view.
BALL CORNER
KEY: VDDINT VDDEXT VROUT
VIEW
Figure 256-Ball CSP_BGA Ball Configuration (Top View)
BALL CORNER
KEY: VDDINT VDDEXT VROUT
BOTTOM VIEW
Figure 256-Ball CSP_BGA Ball Configuration (Bottom View)
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ADSP-BF561
256-BALL CSP_BGA BALL ASSIGNMENT
Table lists 256-Ball CSP_BGA ball assignment ball number. Table Page lists ball assignment alphabetically signal. Table 256-Ball CSP_BGA Ball Assignment (Numerically Ball Number)
Ball Signal VDDEXT ADDR24 ADDR20 VDDEXT ADDR14 ADDR10 AMS3 VDDEXT SMS3 SCLK0 SCLK1 ABE2 ABE3 VDDEXT PPI1CLK ADDR22 ADDR18 ADDR16 ADDR12 VDDEXT AMS1 SMS1 SCKE VDDEXT ABE1 ADDR06 ADDR04 DATA0 PPI0SYNC2 PPI0CLK ADDR25 ADDR19 ADDR11 AMS0 Ball Signal SMS2 SRAS ADDR07 DATA1 DATA3 PPI0D13 PPI0D15 PPI0SYNC3 ADDR23 ADDR09 ARDY SCAS SA10 VDDEXT ADDR02 DATA5 DATA6 PPI0D11 PPI0D12 PPI0SYNC1 ADDR15 ADDR13 AMS2 VDDINT SMS0 ABE0 DATA2 DATA4 DATA7 VDDEXT Ball Signal CLKIN VDDEXT RESET PPI0D10 ADDR21 ADDR17 VDDINT VDDINT ADDR08 DATA10 DATA8 DATA12 DATA9 DATA11 XTAL VDDEXT BYPASS PPI0D14 VDDINT ADDR05 ADDR03 DATA15 DATA14 DATA13 VDDEXT PPI0D9 PPI0D7 PPI0D5 VDDINT VDDINT Ball Signal VDDINT DATA16 DATA18 DATA20 DATA17 DATA19 VROUT0 VROUT1 PPI0D2 PPI0D3 PPI0D1 VDDEXT VDDINT VDDINT VDDINT DATA30 DATA22 DATA21 DATA23 PPI0D6 PPI0D4 PPI0D8 PPI1SYNC1 PPI1D14 VDDEXT VDDINT VDDINT DATA28 DATA26 DATA24 DATA25 VDDEXT Ball Signal PPI0D0 PPI1SYNC2 PPI1SYNC3 VDDEXT PPI1D11 VDDINT VDDEXT DR0PRI TFS0 DATA27 DATA29 PPI1D15 PPI1D13 PPI1D9 VDDINT BMODE0 DR1PRI VDDEXT DATA31 DT0PRI PPI1D12 PPI1D10 PPI1D3 PPI1D1 PF13
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ADSP-BF561
Table 256-Ball CSP_BGA Ball Assignment (Numerically Ball Number) (Continued)
Ball Signal BMODE1 MOSI RFS1 DT0SEC TSCLK0 PPI1D8 PPI1D5 Ball Signal PF11 PF15 TRST NMI0 RSCLK1 TFS1 RSCLK0 DR0SEC Ball Signal PPI1D7 PPI1D6 PPI1D2 PPI1D0 PF10 PF14 NMI1 MISO Ball Signal TX/PF26 TSCLK1 DT1PRI RFS0 VDDEXT PPI1D4 VDDEXT VDDEXT PF12 VDDEXT Ball Signal SLEEP VDDEXT RX/PF27 DR1SEC DT1SEC VDDEXT
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ADSP-BF561
Table 256-Ball CSP_BGA Ball Assignment (Alphabetically Signal)
Signal ABE0 ABE1 ABE2 ABE3 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 AMS0 AMS1 AMS2 AMS3 ARDY BMODE0 BMODE1 Ball Signal BYPASS CLKIN DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI Ball Signal DT0SEC DT1PRI DT1SEC Ball Signal MISO MOSI NMI0 NMI1 PF10 PF11 PF12 PF13 PF14 PF15 PPI0CLK PPI0D0 PPI0D1 PPI0D2 PPI0D3 PPI0D4 PPI0D5 PPI0D6 PPI0D7 PPI0D8 PPI0D9 PPI0D10 PPI0D11 Ball
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ADSP-BF561
Table 256-Ball CSP_BGA Ball Assignment (Alphabetically Signal) (Continued)
Signal PPI0D12 PPI0D13 PPI0D14 PPI0D15 PPI0SYNC1 PPI0SYNC2 PPI0SYNC3 PPI1CLK PPI1D0 PPI1D1 PPI1D2 PPI1D3 PPI1D4 PPI1D5 PPI1D6 PPI1D7 PPI1D8 PPI1D9 PPI1D10 PPI1D11 PPI1D12 PPI1D13 PPI1D14 PPI1D15 Ball Signal PPI1SYNC1 PPI1SYNC2 PPI1SYNC3 RESET RFS0 RFS1 RSCLK0 RSCLK1 SA10 SCAS SCKE SCLK0 SCLK1 SLEEP SMS0 SMS1 SMS2 SMS3 SRAS Ball Signal TFS0 TFS1 TRST TSCLK0 TSCLK1 TX/PF26 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Ball Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VROUT0 VROUT1 XTAL Ball
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ADSP-BF561
Figure lists view 256-Ball CSP_BGA ball configuration. Figure lists bottom view.
BALL CORNER
KEY: VDDINT VDDEXT VROUT
VIEW
Figure 256-Ball CSP_BGA Ball Configuration (Top View)
BALL CORNER
KEY: VDDINT VDDEXT VROUT
BOTTOM VIEW
Figure 256-Ball CSP_BGA Ball Configuration (Bottom View)
Rev. Page February 2009
ADSP-BF561
297-BALL PBGA BALL ASSIGNMENT
Table lists 297-Ball PBGA ball assignment numerically ball number. Table Page lists ball assignment alphabetically signal. Table 297-Ball PBGA Ball Assignment (Numerically Ball Number)
Ball Signal ADDR25 ADDR23 ADDR21 ADDR19 ADDR17 ADDR15 ADDR13 ADDR11 ADDR09 AMS3 AMS1 SMS0 SMS2 SRAS SCAS SCLK0 SCLK1 ABE0 ABE2 ADDR08 ADDR06 PPI1CLK ADDR24 ADDR22 ADDR20 ADDR18 ADDR16 ADDR14 ADDR12 ADDR10 AMS2 AMS0 ARDY Ball Signal SMS1 SMS3 SCKE SA10 ABE1 ABE3 ADDR07 ADDR05 PPI0SYNC3 PPI0CLK ADDR04 ADDR03 PPI0SYNC1 PPI0SYNC2 ADDR02 DATA1 PPI0D15 PPI0D14 DATA0 DATA3 PPI0D13 PPI0D12 DATA2 DATA5 Ball Signal PPI0D11 PPI0D10 DATA4 DATA7 BYPASS RESET DATA6 DATA9 CLKIN VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT DATA8 DATA11 XTAL VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT DATA10 DATA13 VDDEXT Ball Signal VDDINT DATA12 DATA15 VROUT0 VDDEXT VDDINT DATA14 DATA17 VROUT1 PPI0D9 VDDEXT VDDINT DATA16 DATA19 PPI0D7 PPI0D8 VDDEXT
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ADSP-BF561
Table 297-Ball PBGA Ball Assignment (Numerically Ball Number) (Continued)
Ball Signal VDDINT DATA18 DATA21 PPI0D5 PPI0D6 VDDEXT VDDINT DATA20 DATA23 PPI0D3 PPI0D4 VDDEXT VDDINT DATA22 DATA25 PPI0D1 PPI0D2 VDDEXT Ball AA01 AA02 AA25 AA26 AB01 AB02 AB03 AB24 AB25 AB26 AC01 AC02 AC03 Signal VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT DATA24 DATA27 PPI1SYNC3 PPI0D0 DATA26 DATA29 PPI1SYNC1 PPI1SYNC2 DATA28 DATA31 PPI1D15 PPI1D14 DATA30 DT0PRI PPI1D13 PPI1D12 DT0SEC TSCLK0 PPI1D11 PPI1D10 TFS0 DR0PRI PPI1D9 PPI1D8 Ball AC04 AC23 AC24 AC25 AC26 AD01 AD02 AD03 AD04 AD05 AD22 AD23 AD24 AD25 AD26 AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 Signal DR0SEC RFS0 PPI1D7 PPI1D6 RSCLK0 PPI1D5 PPI1D3 PPI1D1 PF10 PF12 PF14 TRST BMODE1 BMODE0 MISO MOSI Ball AE21 AE22 AE23 AE24 AE25 AE26 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal RFS1 DR1SEC TFS1 PPI1D4 PPI1D2 PPI1D0 PF11 PF13 PF15 NMI1 SLEEP NMI0 RSCLK1 DR1PRI TSCLK1 DT1SEC DT1PRI
Rev. Page February 2009
ADSP-BF561
Table 297-Ball PBGA Ball Assignment (Alphabetically Signal)
Signal ABE0 ABE1 ABE2 ABE3 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 AMS0 AMS1 AMS2 AMS3 ARDY BMODE0 BMODE1 Ball AE18 AE17 Signal BYPASS CLKIN DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI Ball AB26 AC25 AF22 AE23 Signal DT0SEC DT1PRI DT1SEC Ball AA25 AF25 AF24 AE16 Signal Ball AB03 AB24 AC03 AC04 AC23 AC24 AD03 AD04 AD05 AD22 AD23 AD24 AE02 AE25 AF01
Rev. Page February 2009
ADSP-BF561
Table 297-Ball PBGA Ball Assignment (Alphabetically Signal) (Continued)
Signal MISO MOSI NMI0 NMI1 PF10 PF11 PF12 PF13 PF14 PF15 PPI0CLK PPI0D0 PPI0D1 PPI0D2 PPI0D3 PPI0D4 PPI0D5 PPI0D6 Ball AF26 AE19 AE20 AD25 AE13 AE26 AF18 AF13 AE05 AF05 AE06 AF06 AE07 AF07 AE08 AF08 AE09 AF09 AE10 AF10 AE11 AF11 AE12 AF12 Signal PPI0D7 PPI0D8 PPI0D9 PPI0D10 PPI0D11 PPI0D12 PPI0D13 PPI0D14 PPI0D15 PPI0SYNC1 PPI0SYNC2 PPI0SYNC3 PPI1CLK PPI1D0 PPI1D1 PPI1D2 PPI1D3 PPI1D4 PPI1D5 PPI1D6 PPI1D7 PPI1D8 PPI1D9 PPI1D10 PPI1D11 PPI1D12 PPI1D13 PPI1D14 PPI1D15 PPI1SYNC1 PPI1SYNC2 PPI1SYNC3 RESET RFS0 RFS1 Ball AF04 AE04 AF03 AE03 AF02 AE01 AD02 AD01 AC02 AC01 AB02 AB01 AA02 AA01 AC26 AE22 Signal RSCLK0 RSCLK1 SA10 SCAS SCKE SCLK0 SCLK1 SLEEP SMS0 SMS1 SMS2 SMS3 SRAS TFS0 TFS1 TRST TSCLK0 TSCLK1 TX/PF26 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT Ball AD26 AF21 AE21 AF19 AF17 AF14 AF15 AE14 AB25 AE24 AF16 AE15 AA26 AF23 AF20 Signal VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VROUT0 VROUT1 XTAL Ball
Rev. Page February 2009
ADSP-BF561
Figure lists view 297-Ball PBGA ball configuration. Figure lists bottom view.
KEY: VDDINT VDDEXT VROUT
VIEW
Figure 297-Ball PBGA Ball Configuration (Top View)
KEY: VDDINT VDDEXT VROUT
BOTTOM VIEW
Figure 297-Ball PBGA Ball Configuration (Bottom View)
Rev. Page February 2009
ADSP-BF561
OUTLINE DIMENSIONS
Dimensions outline dimension figures shown millimeters.
17.00 BALL CORNER
15.00 1.00 BALL PITCH
BALL CORNER
VIEW
BOTTOM VIEW
1.90* 1.76 1.61
SIDE VIEW DETAIL 0.45
0.20 COPLANARITY *NOTES COMPLIES WITH JEDEC REGISTERED OUTLINE MO-192-AAF-1, WITH EXCEPTION PACKAGE HEIGHT. MINIMUM BALL HEIGHT 0.45
SEATING PLANE 0.70 0.60 0.50 BALL DIAMETER DETAIL
Figure 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) (BC-256-4)
Rev. Page February 2009
ADSP-BF561
12.10 12.00 11.90 CORNER INDEX AREA
BALL INDICATOR 9.75 VIEW 0.65
*1.70 1.51 1.36
DETAIL
BOTTOM VIEW *1.31
DETAIL
1.21 1.10 *0.30 0.25
SEATING PLANE
0.45 COPLANARITY 0.40 0.10 0.35 BALL DIAMETER
*COMPLIANT JEDEC STANDARDS MO-225 WITH EXCEPTION DIMENSIONS INDICATED ASTERISK.
Figure 256-Ball Chip Scale Package Ball Grid Array (CSP_BGA) (BC-256-1)
27.20 27.00 26.80
CORNER INDEX AREA
BALL CORNER 24.20 24.00 23.80 VIEW 25.00 BOTTOM VIEW
1.00
2.43 2.23 2.03
8.00 DETAIL
DETAIL
0.61 0.56 0.51
1.22 1.17 1.12
0.50 0.40
0.70 0.60 0.50 BALL DIAMETER
COPLANARITY 0.20 SEATING PLANE
COMPLIANT JEDEC STANDARDS MS-034-AAL-1
Figure 297-Ball Plastic Ball Grid Array (PBGA) (B-297)
Rev. Page February 2009
ADSP-BF561
SURFACE MOUNT DESIGN
Table provided design. industrystandard design recommendations, refer IPC-7351, Generic Requirements Surface Mount Design Land Pattern Standard. Table Data with Surface Mount Design
Package 256-Ball CSP_BGA (BC-256-1) 256-Ball CSP_BGA (BC-256-4) 297-Ball PBGA (B-297) Ball Attach Type Solder Mask Defined Solder Mask Defined Solder Mask Defined Solder Mask Opening 0.30 diameter 0.43 diameter 0.43 diameter Ball Size 0.43 diameter 0.55 diameter 0.58 diameter
AUTOMOTIVE PRODUCTS
Some ADSP-BF561 models available automotive applications with controlled manufacturing. Note that these special models have specifications that differ from general release models. Table Automotive Products
Product Family1 ADBF561WBBZ5xx ADBF561WBBCZ5xx
automotive grade products shown Table available automotive applications. Contact your local account representative authorized product distributor specific product ordering information. Note that automotive products RoHS compliant.
Temperature Range2 -40°C +85°C -40°C +85°C
Speed Grade (Max)3
Package Description 297-Ball PBGA 256-Ball CSP_BGA
Package Option B-297 BC-256-4
denotes silicon revision. Referenced temperature ambient temperature. internal voltage regulation feature available. External voltage regulation required ensure correct operation.
ORDERING GUIDE
Temperature Range1 +70°C +70°C +70°C +70°C +70°C +70°C +70°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C +70°C +70°C -40°C +85°C Speed Grade (Max) Package Description 256-Ball CSP_BGA 256-Ball CSP_BGA 256-Ball CSP_BGA 297-Ball PBGA 297-Ball PBGA 297-Ball PBGA 297-Ball PBGA 297-Ball PBGA 297-Ball PBGA 297-Ball PBGA 297-Ball PBGA 256-Ball CSP_BGA 256-Ball CSP_BGA 256-Ball CSP_BGA Package Option BC-256-1 BC-256-1 BC-256-1 B-297 B-297 B-297 B-297 B-297 B-297 B-297 B-297 BC-256-4 BC-256-4 BC-256-4
Model ADSP-BF561SKBCZ-6V2 ADSP-BF561SKBCZ-5V2 ADSP-BF561SKBCZ5002 ADSP-BF561SKB500 ADSP-BF561SKB600 ADSP-BF561SKBZ5002 ADSP-BF561SKBZ6002 ADSP-BF561SBB600 ADSP-BF561SBB500 ADSP-BF561SBBZ6002 ADSP-BF561SBBZ5002 ADSP-BF561SKBCZ-6A2 ADSP-BF561SKBCZ-5A2 ADSP-BF561SBBCZ-5A2
Referenced temperature ambient temperature. RoHS compliant part.
Rev. Page February 2009
ADSP-BF561
©2009 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D04696-0-2/09(D)
Rev. Page February 2009
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