PERIPHERALS High-speed On-the-Go (OTG) with integrated SD/SDIO co
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Blackfin Embedded Processor
PERIPHERALS
High-speed On-the-Go (OTG) with integrated SD/SDIO controller ATA/ATAPI-6 controller synchronous serial ports (SPORTs) serial peripheral interfaces (SPI-compatible) UARTs, with automatic flow control (controller area network) 2.0B interfaces (2-wire interface) controllers 16-bit asynchronous host interface Multiple enhanced parallel peripheral interfaces (EPPIs), supporting ITU-R BT.656 video formats 18-/24-bit connections Media transceiver (MXVR) connection MOST network Pixel compositor overlays, alpha blending, color conversion eleven 32-bit timers/counters with support Real-time clock (RTC) watchdog timer Up/down counter with support rotary encoder general-purpose (GPIOs) On-chip capable frequency multiplication Debug/JTAG interface
FEATURES
high-performance Blackfin processor 16-bit MACs, 40-bit ALUs, four 8-bit video ALUs RISC-like register instruction model Wide range operating voltages flexible booting options Programmable on-chip voltage regulator 400-ball CSP_BGA, RoHS compliant package
MEMORY
324K bytes on-chip memory comprised instruction SRAM/cache; dedicated instruction SRAM; data SRAM/cache; dedicated data SRAM; scratchpad SRAM External sync memory controller supporting either SDRAM mobile SDRAM External async memory controller supporting 8-/16-bit async memories burst flash devices NAND flash controller memory-to-memory pairs, with ext. requests Memory management unit providing memory protection Code security with Lockbox® secure technology 128-bit AES/ ARC4 data encryption One-time-programmable (OTP) memory
(0-1)
VOLTAGE REGULATOR
JTAG TEST EMULATION
WATCHDOG TIMER
(0-1) TIMERS(0-10)
PORTS
SRAM INSTR INSTR SRAM DATA SRAM
HOST INTERRUPTS UART (0-1) UART (2-3) (0-1) DAB1 16-BIT DAB0 SPORT (0-1) SDIO ATAPI EPPI (0-2) NAND FLASH CONTROLLER PIXEL COMPOSITOR SPORT (2-3)
PORTS
COUNTER KEYPAD
MXVR
32-BIT
BOOT DDR/MDDR
EXTERNAL PORT NOR, DDR, MDDR ASYNC
Figure ADSP-BF549 Functional Block Diagram
Blackfin Blackfin logo registered trademarks Analog Devices, Inc.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
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TABLE CONTENTS
General Description Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Controllers Real-Time Clock Watchdog Timer Timers Up/Down Counter Thumbwheel Interface Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Controller Area Network (CAN) Controller Interface Ports Pixel Compositor (PIXC) Enhanced Parallel Peripheral Interface (EPPI) On-the-Go Dual-Role Device Controller ATA/ATAPI-6 Interface Keypad Interface Secure Digital (SD)/SDIO Controller Code Security Media Transceiver Layer (MXVR) Dynamic Power Management Voltage Regulation Clock Signals Booting Modes Instruction Description Development Tools Designing Emulator-Compatible Processor Board MXVR Board Layout Guidelines Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Timing Specifications Clock Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM/Mobile SDRAM Clock Control Cycle Timing SDRAM/Mobile SDRAM Timing SDRAM/Mobile SDRAM Write Cycle Timing External Port Request Grant Cycle Timing NAND Flash Controller Interface Timing Synchronous Burst Timing External Request Timing Enhanced Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface (SPI) Port-Master Timing Serial Peripheral Interface (SPI) Port-Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports-Receive Transmit Timing General-Purpose Port Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing SD/SDIO Controller Timing MXVR Timing HOSTDP Timing-Host Read Cycle HOSTDP Timing-Host Write Cycle ATA/ATAPI-6 Interface Timing On-The-Go-Dual-Role Device Controller Timing JTAG Test Emulation Port Timing Output Drive Currents Thermal Characteristics 400-Ball CSP_BGA Package Outline Dimensions Automotive Products Ordering Guide
REVISION HISTORY
2/09-Rev.A Rev. specifications mobile DDR.
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GENERAL DESCRIPTION
ADSP-BF54x Blackfin® processors members Blackfin family products, incorporating Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine dual-MAC state-of-the-art signal processing engine, advantages clean, orthogonal RISC-like microprocessor instruction set, single-instruction, multiple-data (SIMD) multimedia capabilities into single instruction-set architecture. Specific performance, memory configurations, features ADSP-BF54x Blackfin processors shown Table Table ADSP-BF54x Processor Features
EBIU (async) ADSP-BF549 ADSP-BF548 ADSP-BF547 ADSP-BF544 Processor Features ADSP-BF542 NAND flash controller ATAPI Host port (HOSTDP) SD/SDIO controller EPPI0 EPPI1 EPPI2 SPORT0 SPORT1 SPORT2 SPORT3 SPI0 SPI1 SPI2 UART0 UART1 UART2 UART3 High-Speed CAN0 CAN1 TWI0 TWI1 Timer Timer 8-10 Up/Down counter Keypad interface MXVR GPIOs
This customer-configurable.
Specific peripherals ADSP-BF54x Blackfin processors shown Table Table Specific Peripherals ADSP-BF54x Processors
ADSP-BF549 ADSP-BF548 ADSP-BF547 ADSP-BF544 Module ADSP-BF542
Lockbox® 1code security 128-bit AES/ ARC4 data encryption SD/SDIO controller Pixel compositor 24-bit EPPI0 with 16-bit EPPI1, 8-bit EPPI2 Host port NAND flash controller ATAPI High-Speed Keypad interface MXVR ports ports ports UART ports SPORTs Up/Down counter Timers General-Purpose pins Memory Instruction SRAM/Cache Configura- Instruction SRAM tions Data SRAM/Cache Bytes) Data SRAM Scratchpad SRAM ROM2 Boot ROM2 Maximum Core Instruction Rate (MHz)
Lockbox registered trademark Analog Devices, Inc.
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ADSP-BF54x Blackfin processors completely code- pin-compatible. They differ only with respect their performance, on-chip memory, selection peripherals. Specific performance, memory, feature configurations shown Table integrating rich industry-leading system peripherals memory, Blackfin processors platform choice next-generation applications that require RISC-like programmability, multimedia support, leading-edge signal processing integrated package. memory spaces, including external (either standard mobile, depending device) asynchronous memory. Multiple on-chip buses running provide enough bandwidth keep processor core running along with activity on-chip external peripherals. ADSP-BF54x Blackfin processors include on-chip voltage regulator support dynamic power management capability. voltage regulator provides range core voltage levels when supplied from VDDEXT. voltage regulator bypassed user's discretion.
POWER ARCHITECTURE
Blackfin processors provide world-class power management performance. Blackfin processors designed power voltage design methodology feature on-chip dynamic power management, ability vary both voltage frequency operation significantly lower overall power consumption. Reducing both voltage frequency result substantial reduction power consumption compared reducing only frequency operation. This translates into longer battery life portable appliances.
BLACKFIN PROCESSOR CORE
shown Figure Page Blackfin processor core contains 16-bit multipliers, 40-bit accumulators, 40-bit ALUs, four video ALUs, 40-bit shifter. computation units process 16-, 32-bit data from register file. compute register file contains eight 32-bit registers. When performing compute operations 16-bit operand data, register file operates independent 16-bit registers. operands compute operations come from multiported register file instruction constant fields. Each perform 16-bit 16-bit multiply each cycle, accumulating results into 40-bit accumulators. Signed unsigned formats, rounding, saturation supported. ALUs perform traditional arithmetic logical operations 32-bit data. addition, many special instructions included accelerate various signal processing tasks. These include operations such field extract population count, modulo multiply, divide primitives, saturation rounding, sign/exponent detection. video instructions include byte alignment packing operations, 16-bit 8-bit adds with clipping, 8-bit average operations, 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided compare/select vector search instructions. certain instructions, 16-bit operations performed simultaneously register pairs 16-bit high half 16-bit half compute register). also using second ALU, quad 16-bit operations possible. 40-bit shifter perform shifts rotates used support normalization, field extract, field deposit instructions. program sequencer controls flow instruction execution, including instruction alignment decoding. program flow control, sequencer supports relative indirect conditional jumps (with static branch prediction), subroutine calls. Hardware provided support zero-overhead looping. architecture fully interlocked, meaning that programmer need manage pipeline when executing instructions with data dependencies. address arithmetic unit provides addresses simultaneous dual fetches from memory. contains multiported register file consisting four sets 32-bit index, modify,
SYSTEM INTEGRATION
ADSP-BF54x Blackfin processors highly integrated system-on-a-chip solutions next generation embedded network connected applications. combining industrystandard interfaces with high-performance signal processing core, users develop cost-effective solutions quickly without need costly external components. system peripherals include high-speed (On-the-Go) controller with integrated PHY, 2.0B controllers, controllers, UART ports, ports, serial ports (SPORTs), ATAPI controller, SD/SDIO controller, real-time clock, watchdog timer, controller, multiple enhanced parallel peripheral interfaces.
BLACKFIN PROCESSOR PERIPHERALS
ADSP-BF54x processors contain rich peripherals connected core several high bandwidth buses, providing flexibility system configuration well excellent overall system performance (see Figure Page generalpurpose peripherals include functions such UARTs, SPI, TWI, timers with pulse width modulation (PWM) pulse measurement capability, general-purpose pins, real-time clock, watchdog timer. This functions satisfies wide variety typical system support needs augmented system expansion capabilities part. ADSPBF54x processors contain dedicated network communication modules high-speed serial parallel ports, interrupt controller flexible management interrupts from onchip peripherals external sources, power management control functions tailor performance power characteristics processor system many application scenarios. peripherals, except general-purpose I/O, CAN, TWI, real-time clock, timers, supported flexible structure. There also separate memory channels dedicated data transfers between processor's various
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length, base registers (for circular buffering), eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support modified Harvard architecture combination with hierarchical memory structure. Level (L1) memories those that typically operate full processor speed with little latency. level, instruction memory holds instructions only. data memories hold data, dedicated scratchpad data memory stores stack local variable information. addition, multiple memory blocks provided, offering configurable SRAM cache. memory management unit (MMU) provides memory protection individual tasks that operating core protect system registers from unintended access. architecture provides three modes operation: user mode, supervisor mode, emulation mode. User mode restricted access certain system resources, thus providing protected software environment, while supervisor mode unrestricted access system core resources. Blackfin processor instruction been optimized that 16-bit opcodes represent most frequently used instructions, resulting excellent compiled code density. Complex instructions encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support limited multi-issue capability, where 32-bit instruction issued parallel with 16-bit instructions, allowing programmer many core resources single instruction cycle. Blackfin processor assembly language uses algebraic syntax ease coding readability. architecture been optimized conjunction with C/C++ compiler, resulting fast efficient software implementations.
ADDRESS ARITHMETIC UNIT
MEMORY
DAG1 DAG0
PREG
R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H
R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L BARREL SHIFTER
ASTAT SEQUENCER
ALIGN DECODE LOOP BUFFER
CONTROL UNIT
DATA ARITHMETIC UNIT
Figure Blackfin Processor Core
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MEMORY ARCHITECTURE
ADSP-BF54x processors view memory single unified byte address space, using 32-bit addresses. resources, including internal memory, external memory, control registers, occupy separate sections this common address space. memory portions this address space arranged hierarchical structure provide good cost/performance balance some very fast, low-latency on-chip memory cache SRAM, larger, lower-cost performance off-chip memory systems. Figure Page on-chip memory system highest-performance memory available Blackfin processor. off-chip memory system, accessed through external interface unit (EBIU), provides expansion with flash memory, SRAM, double-rate SDRAM (standard mobile DDR), optionally accessing 768M bytes physical memory. Most ADSP-BF54x Blackfin processors also include SRAM memory array which provides 128K bytes highspeed SRAM, operating half frequency core with slightly longer latency than memory banks (for information memory each processor, Table memory unified instruction data memory hold mixture code data required system design. Blackfin cores share dedicated latency 64-bit data path port into SRAM memory. memory controllers (DMAC1 DMAC0) provide high-bandwidth data-movement capability. They perform block transfers code data between internal memory external memory spaces.
0xFFFF FFFF CORE REGISTERS BYTES) FFE0 0000 SYSTEM REGISTERS BYTES) FFC0 0000 RESERVED FFB0 1000 SCRATCHPAD SRAM BYTES) 0xFFB0 0000 RESERVED 0xFFA2 4000 (64K BYTE) 0xFFA1 4000 INSTRUCTION SRAM CACHE (16K BYTES) RESERVED FFA0 C000 INSTRUCTION BANK (16K BYTES) FFA0 8000 INSTRUCTION BANK (32K BYTES) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK SRAM CACHE (16K BYTES) FF90 4000 DATA BANK SRAM BYTES) 0xFF90 0000 RESERVED 0xFF80 8000 DATA BANK SRAM CACHE (16K BYTES) 0xFF80 4000 DATA BANK SRAM BYTES) FF80 0000 RESERVED 0xFEB2 0000 SRAM (128K BYTES) 0xFEB0 0000 RESERVED 0xEF00 1000 BYTES) 0xEF00 0000 RESERVED ASYNC MEMORY BANK (64M BYTES) 2C00 0000 ASYNC MEMORY BANK (64M BYTES) 0x2800 0000 ASYNC MEMORY BANK (64M BYTES) 2400 0000 ASYNC MEMORY BANK (64M BYTES) 0x2000 0000 LAST PAGE RESERVED BANK BYTES 256M BYTES) BANK BYTES 256M BYTES) 0000 0000 EXTERNAL MEMORY 0x3000 0000 INTERNAL MEMORY 0xFFA1 0000
Internal (On-Chip) Memory
ADSP-BF54x processors have several blocks on-chip memory providing high-bandwidth access core. first block instruction memory, consisting bytes SRAM, which bytes configured four-way set-associative cache SRAM. This memory accessed full processor speed. second on-chip memory block data memory, consisting bytes SRAM, which bytes configured two-way set-associative cache SRAM. This memory block accessed full processor speed. third memory block byte scratchpad SRAM, which runs same speed memories. only accessible data SRAM cannot configured cache memory. fourth memory block factory programmed instruction ROM, operating full processor speed. This customer-configurable. fifth memory block SRAM, providing 128K bytes unified instruction data memory, operating half frequency core. Finally, there byte boot connected memory. operates full SCLK rate.
Figure Internal/External Memory Map1
ADSP-BF544 processors, SRAM Bytes (0xFEB0000 0xFEB0FFFF). ADSP-BF542 processors, there SRAM.
External (Off-Chip) Memory
Through external interface unit (EBIU), ADSP-BF54x Blackfin processors provide glueless connectivity external 16-bit wide memories, such mobile SDRAM, SRAM, flash, NAND flash, FIFO devices. provide best performance, system mobile interface completely separate from other parallel interfaces. Furthermore, controller supports either standard memory mobile memory. Ordering Guide Page details. Throughout this document, references "DDR" intended cover both standard mobile standards.
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memory controller gluelessly manage banks double-rate synchronous dynamic memory (DDR mobile SDRAM). 16-bit interface operates SCLK frequency, enabling maximum throughput 532M bytes/s. mobile controller augmented with queuing mechanism that performs efficient bursts into mobile DDR. controller industry standard mobile SDRAM controller with each bank supporting from 512M device sizes 16-bit widths. controller supports 256M bytes external bank. With external banks, controller supports 512M bytes total. Each bank independently programmable contiguous with adjacent banks regardless sizes different banks their placement. Traditional 16-bit asynchronous memories, such SRAM, EPROM, flash devices, connected four byte asynchronous memory banks, represented four memory select strobes. Alternatively, these strobes function bank-specific read write strobes preventing further glue logic when connecting asynchronous FIFO devices. Ordering Guide Page list specific products that provide support memory. addition, external connect advanced flash device technologies, such Page-mode flash devices Synchronous burst-mode flash devices NAND flash devices Customers should consult Ordering Guide when selecting specific ADSP-BF54x component intended application. Products that provide support mobile memory noted ordering guide footnotes. NAND Flash Controller (NFC) ADSP-BF54x Blackfin processors provide NAND Flash Controller (NFC) part external interface. NAND flash devices provide high-density, low-cost memory. However, NAND flash devices also have long random access times, invalid blocks, lower reliability over device lifetimes. Because this, NAND flash often used read-only code storage. this case, code stored NAND flash then transferred faster memory (such SRAM) before execution. Another common NAND flash storage multimedia files other large data segments. this case, software file system used manage reading writing NAND flash device. file system selects memory segments storage with goal avoiding blocks equally distributing memory accesses across address locations. Hardware features include: Support page program, page read, block erase NAND flash devices, with accesses aligned page boundaries. Error checking correction (ECC) hardware that facilitates error detection correction. single 8-bit 16-bit external interface commands, addresses, data. Support (single level cell) NAND flash devices unlimited size, with page sizes bytes bytes. Larger page sizes supported software. ability release external interface pins during long accesses. Support internal requests bits bits. engine transfer data between internal memory NAND flash device.
One-Time-Programmable Memory
ADSP-BF54x Blackfin processors have bits onetime-programmable (OTP) non-volatile memory that programmed developer only time. includes array logic support read access programming. Additionally, pages write protected. enables developers store both public private data on-chip. addition storing public private data applications requiring security, also allows developers store completely user-definable data such customer product address. using this feature, generic parts shipped, which then programmed protected developer within this non-volatile memory. memory accessed through provided on-chip ROM.
Memory Space
ADSP-BF54x Blackfin processors define separate space. resources mapped through flat 32-bit address space. On-chip devices have their control registers mapped into memory-mapped registers (MMRs) addresses near byte address space. These separated into smaller blocks, containing control MMRs core functions other containing registers needed setup control on-chip peripherals outside core. MMRs accessible only supervisor mode appear reserved space on-chip peripherals.
Booting
ADSP-BF54x Blackfin processors contain small on-chip boot kernel, which configures appropriate peripheral booting. ADSP-BF54x Blackfin processors configured boot from boot memory space, processor starts executing from on-chip boot ROM. more information, Booting Modes Page
Event Handling
event controller ADSP-BF54x Blackfin processors handles asynchronous synchronous events processors. ADSP-BF54x Blackfin processors provide event handling that supports both nesting prioritization. Nesting allows multiple event service routines active simultaneously. Prioritization ensures that servicing
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higher-priority event takes precedence over servicing lowerpriority event. controller provides support five different types events: Emulation. emulation event causes processor enter emulation mode, allowing command control processor JTAG interface. Reset. This event resets processor. Non-maskable interrupt (NMI). event generated software watchdog timer input signal processor. event frequently used power-down indicator initiate orderly shutdown system. Exceptions. Events that occur synchronously program flow (that exception taken before instruction allowed complete). Conditions such data alignment violations undefined instructions cause exceptions. Interrupts. Events that occur asynchronously program flow. They caused input pins, timers, other peripherals, well explicit software instruction. Each event type associated register hold return address associated return-from-event instruction. When event triggered, state processor saved supervisor stack. ADSP-BF54x Blackfin processor event controller consists stages, core event controller (CEC) system interrupt controller (SIC). core event controller works with system interrupt controller prioritize control system events. Conceptually, interrupts from peripherals enter into then routed directly into general-purpose interrupts CEC. Table Core Event Controller (CEC)
Priority Highest) Event Class Emulation/Test Control Reset Nonmaskable Interrupt Exception Reserved Hardware Error Core Timer General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt Entry IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
interrupt events writing appropriate values into interrupt assignment registers (SIC_IARx). Table describes inputs into default mappings into CEC. Table System Interrupt Controller (SIC)
Peripheral Source Wakeup DMAC0 Status (Generic) EPPI0 Error SPORT0 Error SPORT1 Error SPI0 Status UART0 Status Real-Time Clock DMA12 (EPPI0) DMA0 (SPORT0 DMA1 (SPORT0 DMA2 (SPORT1 DMA3 (SPORT1 DMA4 (SPI0) DMA6 (UART0 DMA7 (UART0 Timer Timer Timer Reset) IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 Core
Core Event Controller (CEC)
supports nine general-purpose interrupts (IVG15-7), addition dedicated interrupt exception events. these general-purpose interrupts, lowest-priority interrupts (IVG15-14) recommended reserved software interrupt handlers, leaving seven prioritized interrupt inputs support peripherals ADSP-BF54x Blackfin processors. Table describes inputs CEC, identifies their names event vector table (EVT), lists their priorities.
System Interrupt Controller (SIC)
system interrupt controller provides mapping routing events from many peripheral interrupt sources prioritized general-purpose interrupt inputs CEC. Although ADSP-BF54x Blackfin processors provide default mapping, user alter mappings priorities
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Table System Interrupt Controller (SIC) (Continued)
Peripheral Source (PINT0) (PINT1) MDMA Stream MDMA Stream Software Watchdog Timer DMAC1 Status (Generic) SPORT2 Error SPORT3 Error MXVR Synchronous Data SPI1 Status SPI2 Status UART1 Status UART2 Status CAN0 Status DMA18 (SPORT2 DMA19 (SPORT2 DMA20 (SPORT3 DMA21 (SPORT3 DMA13 (EPPI1) DMA14 (EPPI2, Host DMA) DMA5 (SPI1) DMA23 (SPI2) DMA8 (UART1 DMA9 (UART1 DMA10 (ATAPI DMA11 (ATAPI TWI0 TWI1 CAN0 Receive CAN0 Transmit MDMA Stream MDMA Stream MXVR Status MXVR Control Message MXVR Asynchronous Packet EPPI1 Error EPPI2 Error UART3 Status Host Status Reset) IVG12 IVG12 IVG13 IVG13 IVG13 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG9 IVG9 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 IVG11 IVG13 IVG13 IVG11 IVG11 IVG11 IVG7 IVG7 IVG7 IVG7 Core
Table System Interrupt Controller (SIC) (Continued)
Peripheral Source Reserved Pixel Compositor (PIXC) Status Status ATAPI Status CAN1 Status DMAR0 Block DMAR1 Block DMAR0 Overflow Error DMAR1 Overflow Error DMA15 (PIXC IN0) DMA16 (PIXC IN1) DMA17 (PIXC OUT) DMA22 (SDH/NFC) Counter (CNT) Keypad (KEY) CAN1 CAN1 Mask Mask Reserved USB_INT0 USB_INT1 USB_INT2 USB_DMAINT OTPSEC Reserved Reserved Reserved Reserved Reserved Reserved Timer Timer Timer Timer Timer Timer Timer Reset) IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG8 IVG8 IVG8 IVG8 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 Core
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Table System Interrupt Controller (SIC) (Continued)
Peripheral Source Timer (PINT2) (PINT3) Reset) IVG11 IVG12 IVG12 Core
source triggered interrupt. indicates peripheral asserting interrupt, cleared indicates peripheral asserting event. interrupt wakeup enable registers (SIC_IWRx). enabling corresponding this register, peripheral configured wake processor, should core idled Sleep mode when event generated. (For more information, Dynamic Power Management Page 17.) Because multiple interrupt sources single generalpurpose interrupt, multiple pulse assertions occur simultaneously, before during interrupt processing interrupt event already detected this interrupt input. IPEND register contents monitored interrupt acknowledgement. appropriate ILAT register when interrupt rising edge detected. (Detection requires core clock cycles.) cleared when respective IPEND register set. IPEND indicates that event entered into processor pipeline. this point recognizes queues next rising edge event corresponding event input. minimum latency from rising edge transition generalpurpose interrupt IPEND output asserted three core clock cycles; however, latency much higher, depending activity within state processor.
Event Control
ADSP-BF54x Blackfin processors provide user with very flexible mechanism control processing events. CEC, three registers used coordinate control events. Each register bits wide: interrupt latch register (ILAT). ILAT register indicates when events have been latched. appropriate when processor latched event cleared when event been accepted into system. This register updated automatically controller, written only when corresponding IMASK cleared. interrupt mask register (IMASK). IMASK register controls masking unmasking individual events. When IMASK register, that event unmasked processed when asserted. cleared IMASK register masks event, preventing processor from servicing event even though event latched ILAT register. This register read written while supervisor mode. Note that general-purpose interrupts globally enabled disabled with instructions, respectively. interrupt pending register (IPEND). IPEND register keeps track nested events. IPEND register indicates that event currently active nested some level. This register updated automatically controller read while supervisor mode. allows further control event processing providing three 32-bit interrupt control status registers. Each register contains corresponding each peripheral interrupt events shown Table Page interrupt mask registers (SIC_IMASKx). These registers control masking unmasking each peripheral interrupt event. When register, that peripheral event unmasked processed system when asserted. cleared register masks peripheral event, preventing processor from servicing event. interrupt status registers (SIC_ISRx). multiple peripherals mapped single event, these registers allow software determine which peripheral event
CONTROLLERS
ADSP-BF54x Blackfin processors have multiple, independent channels that support automated data transfers with minimal overhead processor core. transfers occur between ADSP-BF54x processors' internal memories DMA-capable peripherals. Additionally, transfers accomplished between DMA-capable peripherals external devices connected external memory interfaces, including asynchronous memory controllers. While controller MXVR have their dedicated controllers, other on-chip peripherals managed centralized controllers, called DMAC1 (32-bit) DMAC0 (16-bit). Both operate SCLK domain. Each controller manages independent peripheral channels, well independent memory streams. DMAC1 controller masters high-bandwidth peripherals over dedicated 32-bit access (DAB32). Similarly, DMAC0 controller masters most serial interfaces over 16-bit DAB16 bus. Individual channels have fixed access priority buses. priority peripherals managed flexible peripheral-to-DMA channel assignment scheme. four controllers same 32-bit exchange data with memory. This includes ROM, excludes scratchpad memory. Fine granulation memory special buffers minimize potential memory conflicts when memory accessed simultaneously core. Similarly, there dedicated buses between external interface unit (EBIU) three controllers (DMAC1, DMAC0, USB) that arbitrate accesses external memories boot ROM.
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ADSP-BF54x Blackfin processors' controllers support both 1-dimensional (1D) 2-dimensional (2D) transfers. transfer initialization implemented from registers from sets parameters called descriptor blocks. capability supports arbitrary column sizes elements elements, arbitrary column step sizes ±32K elements. Furthermore, column step size less than step size, allowing implementation interleaved data streams. This feature especially useful video applications where data deinterleaved fly. Examples types supported ADSP-BF54x Blackfin processors' controllers include: single, linear buffer that stops upon completion circular, auto-refreshing buffer that interrupts each full fractionally full buffer using linked list descriptors using array descriptors, specifying only base address within common page addition dedicated peripheral channels, DMAC1 DMAC0 controllers each feature memory channel pairs transfers between various memories ADSP-BF54x Blackfin processors. This enables transfers blocks data between memories-including external DDR, ROM, SRAM, flash memory-with minimal processor intervention. Like peripheral DMAs, memory transfers controlled very flexible descriptor-based methodology standard register-based autobuffer mechanism. memory channels DMAC1 controller (MDMA2 MDMA3) controlled optionally external request input pins. When used conjunction with External Interface Unit (EBIU), this handshaked memory (HMDMA) scheme used efficiently exchange data with block-buffered FIFO-style devices connected externally. Users select whether request pins control source destination side memory DMA. allows control number data transfers memory DMA. number transfers edge programmable. This feature programmed allow memory have increased priority external relative core. configuration words order send/receive data valid internal external memory location. host port controller includes following features: Allows external master configure read/write data transfers read port status Uses flexible asynchronous memory protocol external interface Allows 16-bit external data interface host device Supports half-duplex operation Supports little/big endian data transfers Acknowledge mode allows flow control host transactions Interrupt mode guarantees burst FIFO depth host transactions
REAL-TIME CLOCK
ADSP-BF54x Blackfin processors' real-time clock (RTC) provides robust digital watch features, including current time, stopwatch, alarm. clocked 32.768 crystal external ADSP-BF54x Blackfin processors. peripheral dedicated power supply pins that remain powered clocked even when rest processor low-power state. provides several programmable interrupt options, including interrupt second, minute, hour, clock ticks, interrupt programmable stopwatch countdown, interrupt programmed alarm time. 32.768 input clock frequency divided down signal prescaler. counter function timer consists four counters: 60-second counter, 60-minute counter, 24-hour counter, 32,768-day counter. When enabled, alarm function generates interrupt when output timer matches programmed value alarm control register. There alarms. first alarm time day. second alarm time that day. stopwatch function counts down from programmed value with one-second resolution. When stopwatch enabled counter underflows, interrupt generated. Like other peripherals, wake ADSP-BF54x processor from sleep mode upon generation wakeup event. Additionally, wakeup event wake ADSP-BF54x processors from deep sleep mode, wake on-chip internal voltage regulator from hibernate state.
Host Port Interface
host port (HOSTDP) facilitates host device external ADSP-BF54x Blackfin processors master transfer data back forth. host device always masters transactions, processor always slave device. HOSTDP enabled through peripheral access bus. Once port been enabled, transactions controlled external host. external host programs standard
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Connect pins RTXI RTXO with external components shown Figure timer units used conjunction with four UARTs controllers measure width pulses data stream provide software auto-baud detect function respective serial channels. timers generate interrupts processor core, providing periodic events synchronization either system clock count external signals. addition general-purpose programmable timers, another timer also provided processor core. This extra timer clocked internal processor clock typically used system tick clock generation periodic operating system interrupts.
RTXI
RTXO
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UP/DOWN COUNTER THUMBWHEEL INTERFACE
32-bit up/down counter provided that sense 2-bit quadrature binary codes typically emitted industrial drives manual thumb wheels. counter also operate general-purpose up/down count modes. Then count direction either controlled level-sensitive input edge detectors. third input provide flexible zero marker support alternatively used input push-button signal thumb wheels. three pins have programmable debouncing circuit. internal signal forwarded timer unit enables timer measure intervals between count events. Boundary registers enable auto-zero operation simple system warning interrupts when programmable count values exceeded.
Figure External Components
WATCHDOG TIMER
ADSP-BF54x processors include 32-bit timer that used implement software watchdog function. software watchdog improve system reliability forcing processor known state through generation hardware reset, non-maskable interrupt (NMI), general-purpose interrupt timer expires before being reset software. programmer initializes count value timer, enables appropriate interrupt, then enables timer. Thereafter, software must reload counter before counts zero from programmed value. This protects system from remaining unknown state where software, which would normally reset timer, stopped running external noise condition software error. configured generate hardware reset, watchdog timer resets both core ADSP-BF54x processors' peripherals. After reset, software determine watchdog source hardware reset interrogating status watchdog timer control register. timer clocked system clock (SCLK) maximum frequency fSCLK.
SERIAL PORTS (SPORTS)
ADSP-BF54x Blackfin processors incorporate four dual-channel synchronous serial ports (SPORT0, SPORT1, SPORT2, SPORT3) serial multiprocessor communications. SPORTs support following features: capable operation. Bidirectional operation. Each SPORT sets independent transmit receive pins, enabling eight channels stereo audio. Buffered (8-deep) transmit receive ports. Each port data register transferring data words from other processor components shift registers shifting data data registers. Clocking. Each transmit receive port either external serial clock generate own, frequencies ranging from (fSCLK/131,070) (fSCLK/2) Word length. Each SPORT supports serial data words from bits length, transferred most-significant-bit first least-significant-bit first. Framing. Each transmit receive port with without frame sync signals each data word. Frame sync signals generated internally externally, active high low, with either pulse widths early late frame sync.
TIMERS
There timer units ADSP-BF54x Blackfin processors. unit provides eight general-purpose programmable timers, other unit provides three. Each timer external that configured either pulse width modulator (PWM) timer output, input clock timer, mechanism measuring pulse widths periods external events. These timers synchronized external clock input TMRx pins, external clock TMRCLK input pin, internal SCLK.
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Companding hardware. Each SPORT perform A-law -law companding according recommendation G.711. Companding selected transmit and/or receive channel SPORT without additional latencies. operations with single-cycle overhead. Each SPORT receive transmit multiple buffers memory data automatically. processor link chain sequences transfers between SPORT memory. Interrupts. Each transmit receive port generates interrupt upon completing transfer data word after transferring entire data buffer buffers through DMA. Multichannel capability. Each SPORT supports channels 1024-channel window compatible with H.100, H.110, MVIP-90, HMVIP standards. includes support five eight data bits, stop bits, none, even, parity. Each UART port supports modes operation: (programmed I/O). processor sends receives data writing reading I/O-mapped UART registers. data double-buffered both transmit receive. (direct memory access). controller transfers both transmit receive data. This reduces number frequency interrupts required transfer data from memory. Each UART dedicated channels, transmit receive. These channels have lower default priority than most channels because their relatively service rates. Flexible interrupt timing options available transmit side. Each UART port's baud rate, serial data format, error code generation status, interrupts programmable: Supporting rates ranging from (fSCLK/1,048,576) (fSCLK) bits second. Supporting data formats from seven bits frame. Both transmit receive operations configured generate maskable interrupts processor. UART port's clock rate calculated SCLK UART Clock Rate EDBO UART_Divisor Where 16-bit UART divisor comes from UARTx_DLH register (most significant bits) UARTx_DLL register (least significant eight bits), EDBO UARTx_GCTL register. conjunction with general-purpose timer functions, autobaud detection supported. UART1 UART3 feature pair UARTxRTS (request send) UARTxCTS (clear send) signals hardware flow purposes. transmitter hardware automatically prevented from sending further data when UARTxCTS input deasserted. receiver automatically de-assert UARTxRTS output when enhanced receive FIFO exceeds certain high-water level. capabilities UARTs further extended with support Infrared Data Association (IrDA®) Serial Infrared Physical Layer Link Specification (SIR) protocol.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
ADSP-BF54x Blackfin processors have three SPIcompatible ports that allow processor communicate with multiple SPI-compatible devices. Each port uses three pins transferring data: data pins (master output slave input, SPIxMOSI, master input-slave output, SPIxMISO) clock (serial clock, SPIxSCK). chip select input (SPIxSS) lets other devices select processor, three chip select output pins port SPIxSELy processor select other devices. select pins reconfigured general-purpose pins. Using these pins, ports provide full-duplex, synchronous serial interface, which supports both master/slave modes multimaster environments. port's baud rate clock phase/polarities programmable, integrated controller, configurable support transmit receive data streams. SPI's controller only service unidirectional accesses given time. port's clock rate calculated SCLK Clock Rate SPI_BAUD Where 16-bit SPI_BAUD register contains value 65,535. During transfers, port transmits receives simultaneously serially shifting data serial data lines. serial clock line synchronizes shifting sampling data serial data lines.
CONTROLLER AREA NETWORK (CAN)
ADSP-BF54x Blackfin processors offer controllers that communication controllers that implement controller area network (CAN) 2.0B (active) protocol. This protocol asynchronous communications protocol used both industrial automotive control systems. protocol well suited control applications capability communicate reliably over network since protocol incorporates checking, message error tracking, fault node confinement.
UART PORTS (UARTS)
ADSP-BF54x Blackfin processors provide four fullduplex universal asynchronous receiver/transmitter (UART) ports. Each UART port provides simplified UART interface other peripherals hosts, supporting full-duplex, DMA-supported, asynchronous transfers serial data. UART port
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ADSP-BF54x Blackfin processors' controllers offer following features: mailboxes receive only, transmit only, configurable receive transmit). Dedicated acceptance masks each mailbox. Additional data filtering first bytes. Support both standard (11-bit) extended (29bit) identifier (ID) message formats. Support remote frames. Active passive network support. wakeup from hibernation mode (lowest static power consumption mode). Interrupts, including: complete, complete, error global. electrical characteristics each network connection very demanding, interface typically divided into parts: controller transceiver. This allows single controller support different drivers networks. ADSP-BF54x Blackfin processors' module represents only controller part interface. controller interface supports connection high-speed, fault-tolerant, single-wire transceivers. additional crystal required supply clock, clock derived from processor system clock (SCLK) through programmable divider.
General-Purpose (GPIO)
Every Port Port function GPIO pin, resulting GPIO count 154. While unlikely that GPIO pins will used application, pins have multiple functions, richness GPIO functionality guarantees unrestrictive usage. Every that used function configured GPIO mode individual basis. After reset, pins GPIO mode default. Since neither GPIO output input drivers active default, unused pins left unconnected. GPIO data direction control registers provide flexible write-one-to-set write-one-toclear mechanisms that independent software threads need protect against each other because expensive readmodify-write operations when accessing same port.
Interrupts
Every port ADSP-BF54x Blackfin processors request interrupts either edge-sensitive level-sensitive manner with programmable polarity. Interrupt functionality decoupled from GPIO operation. Four system-level interrupt channels (PINT0, PINT1, PINT2 PINT3) reserved this purpose. Each these interrupt channels manage interrupt pins. assignment from interrupt performed pin-by-pin basis. Rather, groups eight pins (half ports) flexibly assigned interrupt channels. Every interrupt channel features special 32-bit memory-mapped registers that enables half-port assignment interrupt management. This only includes masking, identification, clearing requests, also enables access respective states interrupt latches regardless whether interrupt masked not. Most control registers feature multiple address entries write-one-to-set write-one-to-clear them individually.
CONTROLLER INTERFACE
ADSP-BF54x Blackfin processors include 2-wire interface (TWI) modules providing simple exchange method control data between multiple devices. modules compatible with widely used standard. modules offer capabilities simultaneous master slave operation support both 7-bit addressing multimedia data arbitration. Each interface uses pins transferring clock (SCLx) data (SDAx), supports protocol speeds 400K bits/sec. interface pins compatible with logic levels. Additionally, ADSP-BF54x Blackfin processors' modules fully compatible with serial camera control (SCCB) functionality easier control various CMOS camera sensor devices.
PIXEL COMPOSITOR (PIXC)
pixel compositor (PIXC) provides image overlays with transparent-color support, alpha blending, color space conversion capabilities output LCDs NTSC/PAL video encoders. provides control allow data streams from separate data buffers combined, blended, converted into appropriate forms both panels digital video outputs. main image buffer provides basic background image, which presented data stream. overlay image buffer allows user multiple foreground text, graphics, video objects main image video data stream.
PORTS
Because their rich peripherals, ADSP-BF54x Blackfin processors group many peripheral signals ports-referred Port Port Most ports contain pins, though some have fewer. Many associated pins shared multiple signals. ports function multiplexer controls. Every port memory-mapped registers control port muxing GPIO functionality.
ENHANCED PARALLEL PERIPHERAL INTERFACE (EPPI)
ADSP-BF54x Blackfin processors provide three enhanced parallel peripheral interfaces (EPPIs), supporting data widths bits. EPPI supports direct connection panels, parallel analog-to-digital digital-to-analog converters, video encoders decoders, image sensor modules other general-purpose peripherals.
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following features supported EPPI module: Programmable data length: bits, bits, bits, bits, bits, bits, bits clock. Bidirectional half-duplex port. Clock provided externally generated internally. Various framed non-framed operating modes. Frame syncs generated internally supplied external device. Various general-purpose modes with zero three frame syncs both receive transmit directions. ITU-656 status word error detection correction ITU-656 receive modes. ITU-656 preamble status word decode. Three different modes ITU-656 receive modes: active video only, vertical blanking only, entire field mode. Horizontal vertical windowing frame sync modes. Optional packing unpacking data to/from bits from/to bits. packing/unpacking enabled, endianness changed change order packing/unpacking bytes/words. Optional sign extension zero fill receive modes. During receive modes, alternate even data samples filtered out. Programmable clipping data values 8-bit transmit modes. RGB888 converted RGB666 RGB565 transmit modes. Various de-interleaving/interleaving modes receiving/transmitting 4:2:2 YCrCb data. FIFO watermarks urgent features. Clock gating external device asserting clock gating control signal. Configurable data enable (DEN) output available Frame Sync clock (USB_XI) provided through dedicated external crystal crystal oscillator. Table related timing requirements. using fundamental mode crystal provide clock, connect crystal between USB_XI USB_XO with circuit similar that shown Figure parallel-resonant, fundamental mode, microprocessor-grade crystal. third-overtone crystal used, follow circuit guidelines outlined Clock Signals Page third-overtone crystals. On-the-Go dual-role device controller includes Phase Locked Loop with programmable multipliers generate necessary internal clocking frequency USB. multiplier value should programmed based USB_XI clock frequency achieve necessary internal clock high-speed operation. example, USB_XI crystal frequency MHz, USB_PLLOSC_CTRL register should programmed with multiplier value generate internal clock.
ATA/ATAPI-6 INTERFACE
ATAPI interface connects CD/DVD drives ATAPI-6 compliant. controller implements peripheral mode, multi-DMA mode, Ultra mode. modes enable faster data transfer reduced host management. ATAPI controller supports PIO, multi-DMA, ultra ATAPI accesses. features include: Supports modes Supports multiword modes Supports ultra modes UDMA 100) Programmable timing interface unit Supports CompactFlash cards using true mode default, ATAPI_A0-2 address signals ATAPI_D0-15 data signals shared asynchronous memory interface with asynchronous memory NAND flash controllers. data address signals remapped GPIO ports respectively, setting PORTF_MUX[1:0] b#01.
ON-THE-GO DUAL-ROLE DEVICE CONTROLLER
dual-role device controller (USBDRC) provides low-cost connectivity solution consumer mobile devices such cell phones, digital still cameras, players, allowing these devices transfer data using point-to-point connection without need host. USBDRC module operate traditional peripheral-only mode well host mode presented On-the-Go (OTG) supplement specification. host mode, module supports transfers high speed (480 Mbps), full speed Mbps), speed (1.5 Mbps) rates. Peripheral-only mode supports high- full-speed transfer rates.
KEYPAD INTERFACE
keypad interface 16-pin interface module that used detect pressed (maximum) keypad matrix. size input keypad matrix programmable. interface capable filtering bounce input pins, which common keypad applications. width filtered bounce programmable. module capable generating interrupt request core once identifies that been pressed. interface supports press-release-press mode infrastructure press-hold mode. former mode identifies press, release press consecutive presses same key, whereas latter mode checks input key's state periodic intervals determine number times same
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meant pressed. possible detect when multiple keys pressed simultaneously provide limited resolution capability when this happens. Interrupts generated when user-defined amount synchronous data been sent received processor when asynchronous packets control messages have been sent received. MXVR peripheral wake ADSP-BF549 Blackfin processor from sleep mode when wakeup preamble received over network based other MXVR interrupt event. Additionally, detection network activity MXVR used wake ADSP-BF549 Blackfin processor from hibernate state. These features allow ADSP-BF549 processor operate low-power state when there network activity when data currently being received transmitted MXVR. MXVR clock provided through dedicated external crystal crystal oscillator. frequency external crystal crystal oscillator 1024 kHz, 44.1 kHz, kHz. using crystal provide MXVR clock, parallel-resonant, fundamental mode, microprocessor-grade crystal.
SECURE DIGITAL (SD)/SDIO CONTROLLER
SD/SDIO controller serial interface that stores data data rate bytes second using 4-bit data line. SD/SDIO controller supports memory mode only. interface supports power modes performs error checking CRC.
CODE SECURITY
OTP/security system, consisting blend hardware software, provides customers with flexible rich code security features with Lockbox secure technology. features include: memory Unique chip Code authentication Secure mode operation security scheme based upon concept authentication digital signatures using standards-based algorithms provides secure processing environment which execute code protect assets. Lockbox Secure Technology Disclaimer Page
MEDIA TRANSCEIVER LAYER (MXVR)
ADSP-BF549 Blackfin processors provide media transceiver (MXVR) layer, allowing processor connected directly MOST® network through FOT. Figure Page example MXVR MOST connection. MXVR fully compatible with industry-standard standalone MOST controller devices, supporting 22.579 Mbps 24.576 Mbps data transfer. offers faster lock times, greater jitter immunity, sophisticated scheme data transfers. high-speed internal interface core memory allows full bandwidth network utilized. MXVR operate either network master network slave. MXVR supports synchronous data, asynchronous packets, control messages using dedicated channels that operate autonomously from processor core moving data from and/or memory. Synchronous data transferred from synchronous data physical channels MOST through eight programmable channels. synchronous data channels operate various modes including modes that trigger operation when data patterns detected receive data stream. Furthermore, channels support asynchronous traffic, others support control message traffic.
MOST registered trademark Standard Microsystems, Corp.
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1.25V VDDINT ADSP-BF549 600Z VDDMP 0.01 GNDMP PH5/MTX PH6/MRX 24.576MHz PC4/RFS0 MLF_P 330pF PC1/MMCLK PC5/MBCLK PC3/TSCLK0 PC7/RSCLK0 MLF_M PC2/DT0PRI PH7/MRXON PG11/MTXON
5.0V
600Z RXVCC RXGND MOST
600Z XN4114 TXVCC TXGND TX_DATA RX_DATA STATUS
MOST NETWORK
L/RCLK MCLK BCLK
AUDIO
AUDIO CHANNELS
0.047
SDATA
Figure MXVR MOST Connection
DYNAMIC POWER MANAGEMENT
ADSP-BF54x Blackfin processors provide five operating modes, each with different performance/power profile. addition, dynamic power management provides control functions dynamically alter processor core supply voltage, further reducing power dissipation. Control clocking each ADSP-BF54x Blackfin processors' peripherals also reduces power consumption. Table summary power settings each mode.
ADSP-BF54x Blackfin Processor Hardware Reference. disabled, must re-enabled before transitioning full-on sleep modes. Table Power Settings
Mode/State Bypassed
System Clock (SCLK) Enabled Enabled Enabled Disabled Disabled
Core Clock (CCLK)
Full-On Operating Mode Maximum Performance
full-on mode, enabled bypassed, providing capability maximum operational frequency. This power-up default execution state which maximum performance achieved. processor core enabled peripherals full speed.
Full Active Sleep Deep Sleep Hibernate
Enabled Enabled/ Disabled Enabled Disabled Disabled
Enabled Enabled Disabled Disabled Disabled
Active Operating Mode Moderate Power Savings
active mode, enabled bypassed. Because bypassed, processor's core clock (CCLK) system clock (SCLK) input clock (CLKIN) frequency. access available appropriately configured memories. active mode, possible disable control input setting PLL_OFF control register. This register accessed with user-callable routine on-chip called bfrom_SysControl(). more information, "Dynamic Power Management" chapter
Sleep Operating Mode High Dynamic Power Savings
sleep mode reduces dynamic power dissipation disabling clock processor core (CCLK). system clock (SCLK), however, continue operate this mode. Typically external event activity will wake processor. sleep mode, assertion wakeup event enabled SIC_IWRx register causes processor sense value BYPASS control register (PLL_CTL). BYPASS disabled, processor transitions full mode. BYPASS enabled, processor transitions active mode. sleep mode, system access memory supported.
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Core Power
Deep Sleep Operating Mode Maximum Dynamic Power Savings
deep sleep mode maximizes dynamic power savings disabling clocks processor core (CCLK) synchronous peripherals (SCLK). Asynchronous peripherals, such RTC, still running will able access internal resources external memory. This powereddown mode only exited assertion reset interrupt (RESET) asynchronous interrupt generated RTC. deep sleep mode, asynchronous interrupt causes processor transition active mode. Assertion RESET while deep sleep mode causes processor transition full mode. Table Power Domains (Continued)
Power Domain internal logic crystal Internal voltage regulator MXVR logic other Range VDDUSB VDDVR VDDMP VDDEXT
VOLTAGE REGULATION
ADSP-BF54x Blackfin processors provide on-chip voltage regulator that generate processor core voltage levels from external supply (see specifications Operating Conditions Page 34). Figure Page shows typical external components required complete power management system. regulator controls internal logic voltage levels programmable with voltage regulator control register (VR_CTL) increments This register accessed using bfrom_SysControl() function on-chip ROM. reduce standby power consumption, internal voltage regulator programmed remove power processor core while keeping power supplied. While hibernate state, VDDEXT, VDDRTC, VDDDDR, VDDUSB, VDDVR still applied, eliminating need external buffers. voltage regulator activated from this power-down state assertion RESET pin, which then initiates boot sequence. regulator also disabled bypassed user's discretion. speed grade models automotive grade models, internal voltage regulator must used VDDVR must tied VDDEXT. additional information regarding design voltage regulator circuit, Switching Regulator Design Considerations ADSPBF533 Blackfin Processors (EE-228).
Hibernate State Maximum Static Power Savings
hibernate state maximizes static power savings disabling voltage clocks processor core (CCLK) synchronous peripherals (SCLK). internal voltage regulator processor shut using bfrom_SysControl() function on-chip ROM. This sets internal power supply voltage (VDDINT) provide greatest power savings mode. critical information stored internally (memory contents, register contents, must written non-volatile storage device prior removing power processor state preserved. Since VDDEXT still supplied this mode, external pins three-state, unless otherwise specified. This allows other devices that connected processor have power still applied without drawing unwanted current. internal supply regulator woken CAN, MXVR, keypad, up/down counter, USB, some GPIO pins. also woken real-time clock wakeup event asserting RESET pin. Waking from hibernate state initiates hardware reset sequence. With exception VR_CTL registers, internal registers memories lose their content hibernate state. State variables held external SRAM memory.
2.7V 3.6V INPUT VOLTAGE RANGE
VDDVR (LOW-INDUCTANCE)
DECOUPLING CAPACITORS VDDVR
Power Domains
shown Table ADSP-BF54x Blackfin processors support different power domains. multiple power domains maximizes flexibility while maintaining compliance with industry standards conventions. isolating internal logic ADSP-BF54x Blackfin processors into power domain separate from other I/O, processors take advantage dynamic power management without affecting other devices. There sequencing requirements various power domains. Table Power Domains
Power Domain internal logic, except RTC, DDR, internal logic crystal external memory supply Range VDDINT VDDRTC VDDDDR
Figure Voltage Regulator Circuit
100nF 100F FDS9431A 100F ZHCS1000 VDDINT
SHORT LOWINDUCTANCE WIRE NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH FDS9431A.
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CLOCK SIGNALS
ADSP-BF54x Blackfin processors clocked external crystal, sine wave input, buffered, shaped clock derived from external clock oscillator. external clock used, should TTL-compatible signal must halted, changed, operated below specified frequency during normal operation. This signal connected processor's CLKIN pin. When external clock used, XTAL must left unconnected. Alternatively, because ADSP-BF54x Blackfin processors include on-chip oscillator circuit, external crystal used. fundamental frequency operation, circuit shown Figure parallel-resonant, fundamental frequency, microprocessor-grade crystal connected across CLKIN XTAL pins. on-chip resistance between CLKIN XTAL range. Typically, further parallel resistors recommended. capacitors series resistor shown Figure fine-tune phase amplitude sine frequency. 1MOhm pull-up resistor XTAL guarantees that clock circuit properly held inactive when processor hibernate state. capacitor resistor values shown Figure typical values only. capacitor values dependent upon crystal manufacturers' load capacitance recommendations physical layout. resistor value depends drive level specified crystal manufacturer. System designs should verify customized values based careful investigations multiple devices over temperature range. shown Figure design procedure third-overtone operation discussed detail Application Note, Using Third Overtone Crystals (EE-168). Blackfin core runs different clock rate than on-chip peripherals. shown Figure Page core clock (CCLK) system peripheral clock (SCLK) derived from input clock (CLKIN) signal. on-chip capable multiplying CLKIN signal programmable multiplication factor (bounded specified minimum maximum frequencies). default multiplier modified software instruction sequence. This sequence managed bfrom_SysControl() function on-chip ROM. On-the-fly CCLK SCLK frequency changes applied using bfrom_SysControl() function on-chip ROM. Whereas maximum allowed CCLK SCLK rates depend applied voltages VDDINT VDDEXT, always permitted frequency specified part's speed grade. CLKOUT reflects SCLK frequency off-chip world. functions reference many timing specifications. While inactive default, enabled using EBIU_AMGCTL register.
DYNAMIC MODIFICATION REQUIRES SEQUENCING
DYNAMIC MODIFICATION ON-THE-FLY
BLACKFIN
CCLK
CLKIN
0.5x
1:15 SCLK
CLKOUT CIRCUITRY CLKBUF CLKIN XTAL VDDEXT
SCLK SCLK
CCLK 133MHz
Figure Frequency Modification Methods
OVERTONE OPERATION ONLY
NOTE: VALUES MARKED WITH MUST CUSTOMIZED DEPENDING CRYSTAL LAYOUT. PLEASE ANALYZE CAREFULLY.
on-chip peripherals clocked system clock (SCLK). system clock frequency programmable means SSEL3-0 bits PLL_DIV register. values programmed into SSEL fields define divide ratio between output
Figure External Crystal Connections
third-overtone crystal used frequencies above MHz. circuit then modified ensure crystal operation only third overtone adding tuned inductor circuit
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(VCO) system clock. SCLK divider values through Table illustrates typical system clock ratios. default ratio Table Example System Clock Ratios
Example Frequency Ratios (MHz) SCLK
Table Booting Modes (Continued)
BMODE3-0 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Boot from serial memory (EEPROM flash) Boot from host Boot from UART host Reserved Reserved Boot from SDRAM/Mobile SDRAM Boot from memory Reserved Boot from 16-bit NAND flash memory Boot from 16-bit host Boot from 8-bit host
Signal Name SSEL3-0 0010 0110 1010
Divider Ratio VCO/SCLK 10:1
Note that divisor ratio must chosen limit system clock frequency maximum fSCLK. SSEL value dynamically changed without lock latencies writing appropriate values divisor register (PLL_DIV) using bfrom_SysControl() function on-chip ROM. core clock (CCLK) frequency also dynamically changed means CSEL1-0 bits PLL_DIV register. Supported CCLK divider ratios shown Table default ratio This programmable core clock capability useful fast core frequency modifications. maximum CCLK frequency only depends part's speed grade, also depends applied VDDINT voltage. Table Page details. Table Core Clock Ratios
Example Frequency Ratios (MHz) CCLK
Signal Name CSEL1-0
Divider Ratio VCO/CCLK
boot modes listed Table provide number mechanisms automatically loading processor's internal external memories after reset. default, boot modes slowest allowed configuration settings. Default settings altered initialization code feature boot time proper programming pre-boot time. Some boot modes require boot host wait (HWAIT) signal, which GPIO output signal that driven toggled boot kernel boot time. pulled high through external pull-up resistor, HWAIT signal behaves active high will driven when processor ready data. Conversely, when pulled low, HWAIT driven high when processor ready data. When boot sequence completes, HWAIT used other purposes. default, HWAIT functionality GPIO port (PB11). However, PB11 otherwise utilized system, alternate boot host wait (HWAITA) signal enabled GPIO port (PH7) programming OTP_ALTERNATE_HWAIT PBS00L memory page. BMODE pins reset configuration register, sampled during power-on resets software-initiated resets, implement following modes: Idle-no boot mode (BMODE 0x0)-In this mode, processor goes into idle state. idle boot mode helps recover from illegal operating modes, case memory misconfigured. Boot from 16-bit external flash memory- (BMODE 0x1)-In this mode, boot kernel loads first block header from address 0x2000 0000 and, depending instructions contained header, boot kernel performs 16-bit boot starts program execution address provided header. default, configuration settings slowest device possible (3cycle hold time; 15-cycle access times; 4-cycle setup). ARDY enabled default. can, however, enabled programming. Similarly, interface behavior timings customized through programming. This includes activation burst-mode pagemode operation. this mode, asynchronous interface signals enabled port muxing level.
BOOTING MODES
ADSP-BF54x Blackfin processors have many mechanisms (listed Table automatically loading internal external memory after reset. boot mode specified four BMODE input pins dedicated this purpose. There categories boot modes: master slave. master boot modes, processor actively loads data from parallel serial memories. slave boot modes, processor receives data from external host device. Table Booting Modes
BMODE3-0 0000 0001 0010 0011 0100 Description Idle-no boot Boot from 16-bit external flash memory Boot from 16-bit asynchronous FIFO Boot from serial memory (EEPROM flash) Boot from host device
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Boot from 16-bit asynchronous FIFO (BMODE 0x2)-In this mode, boot kernel starts booting from address 0x2030 0000. Every 16-bit word that boot kernel read from FIFO must requested pulse DMAR1 pin. Boot from serial memory, EEPROM flash (BMODE 0x3)-8-, 16-, 32-bit addressable devices supported. processor uses GPIO select single EEPROM flash device uses SPI0 submit read command successive address bytes (0x00) until valid 16-, 24-, 32-bit addressable device detected. Pull-up resistors required SPI0SEL1 SPI0MISO pins. default, value 0x85 written SPI0_BAUD register. Boot from host device (BMODE 0x4)-The processor operates slave mode (using SPI0) configured receive bytes .LDR file from host (master) agent. HWAIT signal must interrogated host before every transmitted byte. pull-up resistor required SPI0SS input. pull-down resistor serial clock (SPI0SCK) improve signal quality booting robustness. Boot from serial memory, EEPROM flash (BMODE 0x5)-The processor operates master mode (using TWI0) selects slave with unique 0xA0. processor submits successive read commands memory device starting two-byte internal address 0x0000 begins clocking data into processor. memory device should comply with Philips Specification version have capability autoincrement internal address counter such that contents memory device read sequentially. default, prescale value CLKDIV value 0x0811 used. Unless altered settings, memory that takes address bytes assumed. Development tools ensure that data that booted memories that cannot accessed Blackfin core written intermediate storage place then copied final destination memory DMA. Boot from host (BMODE 0x6)-The host agent selects slave with unique 0x5F. processor (using TWI0) replies with acknowledgement, host then download boot stream. host agent should comply with Philips Specification version 2.1. multiplexer used select processor time when booting multiple processors from single TWI. Boot from UART host (BMODE 0x7)-In this mode, processor uses UART1 booting source. Using autobaud handshake sequence, boot-stream-formatted program downloaded host. host agent selects rate within UART's clocking capabilities. When performing autobaud, UART expects (0x40) character (eight data bits, start bit, stop bit, parity bit) UART1RX determine rate. then replies with acknowledgement, which composed four bytes (0xBF, value UART1_DLL, value UART1_DLH, finally 0x00). host then download boot stream. processor deasserts UART1RTS output hold host; UART1CTS functionality enabled boot time. Boot from (DDR) SDRAM (BMODE 0xA)-In this mode, boot kernel starts booting from address 0x0000 0010. This warm boot scenario only. SDRAM expected contain valid boot stream SDRAM controller must have been configured settings. Boot from 8-bit 16-bit external NAND flash memory (BMODE 0xD)-In this mode, auto detection NAND flash device performed. processor configures PORTJ GPIO pins enable ND_CE ND_RB signals, respectively. correct device operation, pull-up resistors required both ND_CE (PJ1) ND_RB (PJ2) signals. default, value 0x0033 written NFC_CTL register. booting procedure always starts booting from byte block NAND flash device. this boot mode, HWAIT signal does toggle. respective GPIO remains high-impedance state. NAND flash boot supports following features: Device auto detection Error detection correction maximum reliability boot stream size limitation Peripheral channel providing efficient transfer data (excluding parity data) Software-configurable boot mode booting from boot streams expanding multiple blocks, including blocks Software-configurable boot mode booting from multiple copies boot stream allowing handling blocks uncorrectable errors Configurable timing memory Small page NAND flash devices must have 512-byte page size, pages block, 16-byte spare area size configuration eight bits. default, read requests from NAND flash followed four address cycles. NAND flash device requires only three address cycles, then device must capable ignoring additional address cycle. small page NAND flash device must comply with following command set:
Reset: 0xFF Read lower half page: 0x00 Read upper half page: 0x01 Read spare area: 0x50
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large page NAND flash devices, 4-byte electronic signature read order configure kernel booting. This allows support multiple large page devices. fourth byte electronic signature must comply with specifications Table configuration from Table that also complies with command listed below directly supported boot kernel. There restrictions page size block size imposed small-page boot kernel. Large page devices must support following command set:
Reset: 0xFF Read Electronic Signature: 0x90 Read: 0x00, 0x30 (confirm command)
16-bit NAND flash memory devices must only support issuing command address cycles lower eight bits data bus. Devices that full 16-bit command address cycles supported.
Table Byte Electronic Signature Specification
Page Size (excluding spare area) D1:D0 Spare Area Size Block Size (excluding spare area) D5:4 Width Used Configuration bytes bytes bytes bytes bytes/512 bytes bytes/512 bytes bytes 128K bytes 256K bytes 512K bytes
Large page devices must support react NAND flash command 0x50. This small page NAND flash command used device auto detection. default, boot kernel will always issue five address cycles; therefore, large page device requires only four cycles, device must capable ignoring additional address cycle.
Boot from memory (BMODE 0xB)-This provides standalone booting method. boot stream loaded from on-chip memory. default, boot stream expected start from page 0x40 occupy public memory page 0xDF (2560 bytes). Since start page programmable, maximum size boot stream extended 3072 bytes. Boot from 16-bit host (BMODE 0xE)-In this mode, host port configured 16-bit acknowledge mode with little endian data format. Unlike other modes, host responsible interpreting boot stream. writes data blocks individually into host port. Before configuring settings each block, host either poll ALLOW_CONFIG HOST_STATUS wait interrupted HWAIT signal. When using HWAIT, host must still check ALLOW_CONFIG least once before beginning configure host port. After completing configuration, host required poll READY HOST_STATUS before beginning transfer data. When host sends HIRQ control command, boot kernel issues CALL instruction address 0xFFA0 0000. host's responsibility ensure valid code been placed this address. routine address 0xFFA0 0000 simple initialization routine configure internal resources, such SDRAM controller, which then
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returns using instruction. routine also final application, which will never return boot kernel. Boot from 8-bit host (BMODE 0xF)-In this mode, host port configured 8-bit interrupt mode with little endian data format. Unlike other modes, host responsible interpreting boot stream. writes data blocks individually host port. Before configuring settings each block, host either poll ALLOW_CONFIG HOST_STATUS wait interrupted HWAIT signal. When using HWAIT, host must still check ALLOW_CONFIG least once before beginning configure host port. host will receive interrupt from HOST_ACK signal every time allowed send next FIFO depth's worth (sixteen 32-bit words) information. When host sends HIRQ control command, boot kernel issues CALL instruction address 0xFFA0 0000. host's responsibility ensure valid code been placed this address. routine address 0xFFA0 0000 simple initialization routine configure internal resources, such SDRAM controller, which then returns using instruction. routine also final application, which will never return boot kernel. each boot modes, 16-byte header first read from external memory device. header specifies number bytes transferred memory destination address. Multiple memory blocks loaded boot sequence. Once blocks loaded, program execution commences from address stored EVT1 register. Prior booting, pre-boot routine interrogates memory. Individual boot modes customized disabled based programming. External hardware, especially booting hosts, monitor HWAIT signal determine when pre-boot finished boot kernel starts boot process. However, HWAIT signal does toggle NAND boot mode. programming memory, user instruct preboot routine also customize PLL, voltage regulator, controller, and/or asynchronous memory interface controller. boot kernel differentiates between regular hardware reset wakeup-from-hibernate event speed booting later case. Bits system reset configuration (SYSCR) register used bypass pre-boot routine and/or boot kernel case software reset. They also used simulate wakeup-from-hibernate boot software reset case. boot process further customized "initialization code." This piece code that loaded executed prior regular application boot. Typically, this used configure controller speed booting managing PLL, clock frequencies, wait states, and/or serial rates. boot also features C-callable function entries that called user application time. This enables second-stage boot booting management schemes implemented with ease.
INSTRUCTION DESCRIPTION
Blackfin processor family assembly language instruction employs algebraic syntax designed ease coding readability. instructions have been specifically tuned provide flexible, densely encoded instruction that compiles very small final memory size. instruction also provides fully featured multifunction instructions that allow programmer many processor core resources single instruction. Coupled with many features more often seen microcontrollers, this instruction very efficient when compiling source code. addition, architecture supports both user (algorithm/application code) supervisor (O/S kernel, device drivers, debuggers, ISRs) modes operation, allowing multiple levels access core processor resources. assembly language, which takes advantage processor's unique architecture, offers following advantages: Seamlessly integrated DSP/MCU features optimized both 8-bit 16-bit operations. multi-issue load/store modified-Harvard architecture, which supports 16-bit four 8-bit load/store pointer updates cycle. registers, I/O, memory mapped into unified byte memory space, providing simplified programming model. Microcontroller features, such arbitrary bit-field manipulation, insertion, extraction; integer operations 16-, 32-bit data-types; separate user supervisor stack pointers. Code density enhancements, which include intermixing 32-bit instructions mode switching, code segregation). Frequently used instructions encoded bits.
DEVELOPMENT TOOLS
ADSP-BF54x Blackfin processors supported with complete CROSSCORE® software hardware development tools, including Analog Devices emulators VisualDSP++® development environment. same emulator hardware that supports other Blackfin processors also fully emulates ADSP-BF54x Blackfin processors.
EZ-KIT Lite® Evaluation Board
evaluation ADSP-BF54x Blackfin processors, ADSP-BF548 EZ-KIT Lite board available from Analog Devices. Order part number ADZS-BF548-EZLITE. board comes with on-chip emulation capabilities equipped enable software development. Multiple daughter cards available.
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DESIGNING EMULATOR-COMPATIBLE PROCESSOR BOARD
Analog Devices family emulators tools that every system developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG test access port (TAP) each JTAG processor. emulator uses access internal features processor, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. processor must halted send data commands, once operation been completed emulator, processor running full speed with impact system timing. these emulators, target board must include header that connects processor's JTAG port emulator. details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, Analog Devices JTAG Emulation Technical Reference (EE-68) Analog Devices site under www.analog.com/ee-notes. This document updated regularly keep pace with improvements emulator support. Trace capacitance plus load capacitance should equal load capacitance specification crystal. Avoid routing other switching signals near crystal components avoid crosstalk. When possible, shield traces components with ground. VDDMP/GNDMP-MXVR power domain: Route VDDMP GNDMP with wide traces isolated power planes. Drive VDDMP same level VDDINT. Place ferrite bead between VDDINT power plane VDDMP noise isolation. Locally bypass VDDMP with 0.01 decoupling capacitors GNDMP. Avoid routing switching signals near VDDMP GNDMP traces avoid crosstalk. Fiber optic transceiver (FOT) connections: Keep traces between ADSP-BF549 processor short possible. receive data trace connecting receive data output ADSP-BF549 PH6/MRX input should have series termination resistor placed close receive data output pin. Typically, edge rate receive data signal driven very slow, further degradation edge rate desirable. transmit data trace connecting ADSP-BF549 PH5/MTX output transmit data input should have series termination resistor placed close ADSP-BF549 PH5/MTX pin. receive data trace transmit data trace between ADSP-BF549 processor should routed close each other parallel over long distances avoid crosstalk.
MXVR BOARD LAYOUT GUIDELINES
MXVR Loop Filter network connected between MLF_P MLF_M pins following manner: Capacitors: 0.047 (PPS type, tolerance recommended) (PPS type, tolerance recommended) Resistor: tolerance) network should located physically close MLF_P MLF_M pins board. network should shielded using GNDMP traces. Avoid routing other switching signals near network avoid crosstalk. driven with external clock oscillator should driven with clock output clock oscillator running frequency 49.152 45.1584 MHz. should left unconnected. Avoid routing other switching signals near oscillator clock output trace avoid crosstalk. When possible, shield traces with ground. MXI/MXO with external crystal: crystal must fundamental mode crystal running frequency 49.152 45.1584 MHz. crystal load capacitors should placed physically close pins board. Board trace capacitance each lead should more than
RELATED DOCUMENTS
following publications that describe ADSP-BF54x Blackfin processors (and related processors) ordered from Analog Devices sales office accessed electronically www.analog.com: ADSP-BF54x Blackfin Processor Hardware Reference, Volume Volume Blackfin Processor Programming Reference Blackfin Anomaly List
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LOCKBOX SECURE TECHNOLOGY DISCLAIMER
Analog Devices products containing Lockbox Secure Technology warranted Analog Devices detailed Analog Devices Standard Terms Conditions Sale. knowledge, Lockbox secure technology, when used accordance with data sheet hardware reference manual specifications, provides secure method implementing code data safeguards. However, Analog Devices does guarantee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS EXPRESS IMPLIED WARRANTIES THAT LOCKBOX SECURE TECHNOLOGY CANNOT BREACHED, COMPROMISED OTHERWISE CIRCUMVENTED EVENT SHALL ANALOG DEVICES LIABLE LOSS, DAMAGE, DESTRUCTION RELEASE DATA, INFORMATION, PHYSICAL PROPERTY INTELLECTUAL PROPERTY.
DESCRIPTIONS
ADSP-BF54x Blackfin processors' multiplexing scheme listed Table definitions listed Table Table Multiplexing
Primary Function (Number Pins)1, Port GPIO pins)
First Peripheral Function SPORT2 pins) SPORT3 pins)
Second Peripheral Function TMR4 pin) TMR5 pin) TMR6 pin) TMR7 pin)
Third Peripheral Function TACI7 pin) TACLK7-0 pins)
Fourth Peripheral Function
Interrupt Capability Interrupts pins)
Port GPIO pins)
TWI1 pins) UART2 pins) UART2 pins) UART3 pins) SPI2 SEL1-3 pins) TMR0-2 pins) SPI2 pins) TMR3 pin) SPORT0 pins) pins) MXVR MMCLK, MBCLK pins)
TACI2-3 pins)
Interrupts pins)
HWAIT pin) Interrupts pins)3 Interrupts pins)
Port GPIO pins)
Port GPIO pins)
PPI1 D0-15 pins)
Host D0-15 pins)
SPORT1 pins) PPI2 D0-7 pins)
PPI0 D18- pins) Keypad pins)
Interrupts pins) Interrupts pins)
Port GPIO pins)
SPI0 pins)
UART0 pin) UART0 pin) UART0 pins) PPI1 CLK,FS pins) TWI0 pins)
Keypad pins) Keypad pin)
TACI0 pin)
Interrupts pins)
Interrupts pins)
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Table Multiplexing (Continued)
Primary Function (Number Pins)1, Port GPIO pins) Port GPIO pins)
First Peripheral Function PPI0 D0-15 pins)
Second Peripheral Function ATAPI D0-15A
Third Peripheral Function
Fourth Peripheral Function
Interrupt Capability Interrupts pins) Interrupts pins) Interrupts pins)
PPI0 CLK,FS pins) DATA 16-17 pins) SPI1 SEL1-3 pins) SPI1 pins) CAN0 pins) CAN1 pins)
TMRCLK pin) ATAPI A0-2A Host pins) MXVR MTXON pin)
PPI2 CLK,FS pins) TACI4-5 pins)
pin) Interrupts pins)
Port GPIO pins)
UART1 pins) ATAPI_RESET pin) HOST_ADDR pin) HOST_ACK pin) MXVR MRX, MTX, MRXON/GPW pins)4
PPI0-1_FS3 pins) TMR8 pin) TMR9 pin) TMR10 pin)
TACI1 pin) PPI2_FS3 pin) Counter Down/Gate pin) Counter Up/Dir pin) DMAR pins)
Interrupts pins)
TACI8-10 pins) TACLK8-10 pins) HWAITA Interrupts pins) Interrupts pins) Interrupts pins)
Addr pins) Port GPIO pins) Async Addr10-25 pins)
Port GPIO pins)
Async MISC
Interrupts pins) Interrupts pins)
Port connections inputs outputs after power depending model boot mode chosen. port connections always power inputs some period time require resistive termination safe condition used outputs system. total interrupts once available from ports through configurable byte-wide blocks. functionality available when MXVR present unused.
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ADSP-BF54x processor definitions listed Table multiplexing scheme, Table Table Descriptions
Name Port GPIO/SPORT2-3/TMR4-7 PA0/TFS2 PA1/DT2SEC/TMR4 PA2/DT2PRI PA3/TSCLK2 PA4/RFS2 PA5/DR2SEC/TMR5 PA6/DR2PRI PA7/RSCLK2/TACLK0 PA8/TFS3/TACLK1 PA9/DT3SEC/TMR6 PA10/DT3PRI/TACLK2 PA11/TSCLK3/TACLK3 PA12/RFS3/TACLK4 PA13/DR3SEC/TMR7/TACLK5 PA14/DR3PRI/TACLK6 PA15/RSCLK3/TACLK7 TACI7 Port GPIO/TWI1/UART2-3/SPI2/TMR0-3 PB0/SCL1 PB1/SDA1 PB2/UART3RTS PB3/UART3CTS PB4/UART2TX PB5/UART2RX/TACI2 PB6/UART3TX PB7/UART3RX/TACI3 PB8/SPI2SS/TMR0 PB9/SPI2SEL1/TMR1 PB10 SPI2SEL2/TMR2 PB11/SPI2SEL3/TMR3/ HWAIT PB12/SPI2SCK PB13/SPI2MOSI PB14/SPI2MISO I/O1 Function (First/Second/Third/Fourth) GPIO/SPORT2 Transmit Frame Sync GPIO/SPORT2 Transmit Data Secondary/Timer GPIO/SPORT2 Transmit Data Primary GPIO/SPORT2 Transmit Serial Clock GPIO/SPORT2 Receive Frame Sync GPIO/SPORT2 Receive Data Secondary/Timer GPIO/SPORT2 Receive Data Primary GPIO/SPORT2 Receive Serial Clock/Alternate Input Clock GPIO/SPORT3 Transmit Frame Sync/Alternate Input Clock GPIO/SPORT3 Transmit Data Secondary/Timer GPIO/SPORT3 Transmit Data Primary/Alternate Input Clock GPIO/SPORT3 Transmit Serial Clock/Alternate Input Clock GPIO/SPORT3 Receive Frame Sync/Alternate Input Clock GPIO/SPORT3 Receive Data Secondary/Timer 7/Alternate Input Clock GPIO/SPORT3 Receive Data Primary/Alternate Input Clock GPIO/SPORT3 Receive Serial Clock/Alt Input Clock Capture Input GPIO/TWI1 Serial Clock (Open-drain output: requires pull-up resistor.) GPIO/TWI1 Serial Data (Open-drain output: requires pull-up resistor.) GPIO/UART3 Request Send GPIO/UART3 Clear Send GPIO/UART2 Transmit GPIO/UART2 Receive/Alternate Capture Input GPIO/UART3 Transmit GPIO/UART3 Receive/Alternate Capture Input GPIO/SPI2 Slave Select Input/Timer GPIO/SPI2 Slave Select Enable 1/Timer GPIO/SPI2 Slave Select Enable 2/Timer GPIO/SPI2 Slave Select Enable 3/Timer 3/Boot Host Wait GPIO/SPI2 Clock GPIO/SPI2 Master Slave GPIO/SPI2 Master Slave Driver Type2
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Table Descriptions (Continued)
Name Port GPIO/SPORT0/SD Controller/MXVR (MOST) PC0/TFS0 PC1/DT0SEC/MMCLK PC2/DT0PRI PC3/TSCLK0 PC4/RFS0 PC5/DR0SEC/MBCLK PC6/DR0PRI PC7/RSCLK0 PC8/SD_D0 PC9/SD_D1 PC10/SD_D2 PC11/SD_D3 PC12/SD_CLK PC13/SD_CMD Port GPIO/PPI0-2/SPORT 1/Keypad/Host PD0/PPI1_D0/HOST_D8/ TFS1/PPI0_D18 PD1/PPI1_D1/HOST_D9/ DT1SEC/PPI0_D19 PD2/PPI1_D2/HOST_D10/ DT1PRI/PPI0_D20 PD3/PPI1_D3/HOST_D11/ TSCLK1/PPI0_D21 PD6/PPI1_D6/HOST_D14/DR1PRI PD7/PPI1_D7/HOST_D15/RSCLK1 PD8/PPI1_D8/HOST_D0/ PPI2_D0/KEY_ROW0 I/O1 Function (First/Second/Third/Fourth) GPIO/SPORT0 Transmit Frame Sync GPIO/SPORT0 Transmit Data Secondary/MXVR Master Clock GPIO/SPORT0 Transmit Data Primary GPIO/SPORT0 Transmit Serial Clock GPIO/SPORT0 Receive Frame Sync GPIO/SPORT0 Receive Data Secondary/MXVR Clock GPIO/SPORT0 Receive Data Primary GPIO/SPORT0 Receive Serial Clock GPIO/SD Data GPIO/SD Data GPIO/SD Data GPIO/SD Data GPIO/SD Clock Output GPIO/SD Command GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Frame Sync/PPI0 Data GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Data Secondary/PPI0 Data GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Data Primary/PPI0 Data GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Serial Clock/PPI0 Data GPIO/PPI1 Data/Host DMA/SPORT1 Receive Frame Sync/PPI0 Data GPIO/PPI1 Data/Host DMA/SPORT1 Receive Data Secondary/PPI0 Data GPIO/PPI1 Data/Host DMA/SPORT1 Receive Data Primary GPIO/PPI1 Data /Host DMA/SPORT1 Receive Serial Clock GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Input GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Input GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Input GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Input GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output Driver Type2
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Table Descriptions (Continued)
Name Port PE0/SPI0SCK/KEY_COL73 PE1/SPI0MISO/KEY_ROW63 PE2/SPI0MOSI/KEY_COL6 PE3/SPI0SS/KEY_ROW5 PE4/SPI0SEL1/KEY_COL3 PE5/SPI0SEL2/KEY_ROW4 PE6/SPI0SEL3/KEY_COL4 PE7/UART0TX/KEY_ROW7 PE8/UART0RX/TACI0 PE9/UART1RTS PE10/UART1CTS PE11/PPI1_CLK PE12/PPI1_FS1 PE13/PPI1_FS2 PE14/SCL0 PE15/SDA0 Port GPIO/PPI0/Alternate ATAPI Data PF0/PPI0_D0/ATAPI_D0A PF1/PPI0_D1/ATAPI_D1A PF2/PPI0_D2/ATAPI_D2A PF3/PPI0_D3/ATAPI_D3A PF4/PPI0_D4/ATAPI_D4A PF5/PPI0_D5/ATAPI_D5A PF6/PPI0_D6/ATAPI_D6A PF7/PPI0_D7/ATAPI_D7A PF8/PPI0_D8/ATAPI_D8A PF9/PPI0_D9/ATAPI_D9A PF10/PPI0_D10/ATAPI_D10A PF11/PPI0_D11/ATAPI_D11A PF12/PPI0_D12/ATAPI_D12A PF13/PPI0_D13/ATAPI_D13A PF14/PPI0_D14/ATAPI_D14A PF15/PPI0_D15/ATAPI_D15A I/O1 Function (First/Second/Third/Fourth) GPIO/SPI0 Clock/Keypad Column Output GPIO/SPI0 Master Slave Out/Keypad Input GPIO/SPI0 Master Slave In/Keypad Column Output GPIO/SPI0 Slave Select Input/Keypad Input GPIO/SPI0 Slave Select Enable 1/Keypad Column Output GPIO/SPI0 Slave Select Enable 2/Keypad Input GPIO/SPI0 Slave Select Enable 3/Keypad Column Output GPIO/UART0 Transmit/Keypad Input GPIO/UART0 Receive/Alternate Capture Input GPIO/UART1 Request Send GPIO/UART1 Clear Send GPIO PPI1Clock GPIO/PPI1 Frame Sync GPIO/PPI1 Frame Sync GPIO/TWI0 Serial Clock (Open-drain output: requires pull-up resistor.) GPIO/TWI0 Serial Data (Open-drain output: requires pull-up resistor.) GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data GPIO/PPI0 Data/Alternate ATAPI Data Driver Type2
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Table Descriptions (Continued)
Name Port GPIO/PPI0/SPI1/PPI2/Up-Down Counter/CAN0-1/Host DMA/MXVR (MOST)/ATAPI PG0/PPI0_CLK/TMRCLK PG1/PPI0_FS1 PG2/PPI0_FS2/ATAPI_A0A PG3/PPI0_D16/ATAPI_A1A PG4/PPI0_D17/ATAPI_A2A PG6/SPI1SEL2/HOST_RD/PPI2_FS1 PG7/SPI1SEL3/HOST_WR/PPI2_CLK PG8/SPI1SCK PG9/SPI1MISO PG10/SPI1MOSI PG11/SPI1SS/MTXON PG12/CAN0TX PG13/CAN0RX/TACI4 PG14/CAN1TX PG15/CAN1RX/TACI5 Port Counter/TMR8-10/Host DMA/MXVR (MOST) PH0/UART1TX/PPI1_FS3_DEN PH1/UART1RX/PPI0_FS3_DEN/TACI1 PH3/HOST_ADDR/TMR9/CDG PH4/HOST_ACK/TMR10/CUD PH5/MTX/DMAR0/TACI8 TACLK8 PH6/MRX/DMAR1/TACI9 TACLK9 PH7/MRXON/GPW/TACI10 TACLK10/HWAITA PH8/A46 PH9/A56 PH10/A66 PH11/A76 PH12/A86 PH13/A96 I/O1 Function (First/Second/Third/Fourth) Driver Type2
GPIO/PPI0 Clock/External Timer Reference GPIO/PPI0 Frame Sync GPIO/PPI0 Frame Sync 2/Alternate ATAPI Address GPIO/PPI0 Data/Alternate ATAPI Address GPIO/PPI0 Data/Alternate ATAPI Address GPIO/SPI1 Slave Select/Host Chip Enable/PPI2 Frame Sync 2/Counter Zero Marker GPIO/SPI1 Slave Select/ Host Read/PPI2 Frame Sync GPIO/SPI1 Slave Select/Host Write/PPI2 Clock GPIO/SPI1 Clock GPIO/SPI1 Master Slave GPIO/SPI1 Master Slave GPIO/SPI1 Slave Select Input/MXVR Transmit GPIO/CAN0 Transmit GPIO/CAN0 Receive/Alternate Capture Input GPIO/CAN1 Transmit GPIO/CAN1 Receive/Alternate Capture Input
GPIO/UART1 Transmit/PPI1 Frame Sync GPIO/UART Receive/ PPI0 Frame Sync 3/Alternate Capture Input GPIO/ATAPI Interface Hard Reset Signal/Timer 8/PPI2 Frame Sync GPIO/HOST Address/Timer 9/Count Down Gate GPIO/HOST Acknowledge/Timer 10/Count Direction GPIO/MXVR Transmit Data/Ext. Request/Alt Capt. /Alt GPIO/MXVR Receive Data/Ext. Request/Alt Capt. /Alt GPIO/MXVR Receive /Alt Capt. /Alt 10/Alternate Boot Host Wait GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access
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Table Descriptions (Continued)
Name Port GPIO/AMC PI0/A106 PI1/A116 PI2/A126 PI3/A136 PI4/A146 PI5/A156 PI6/A166 PI7/A176 PI8/A186 PI9/A196 PI10/A206 PI11/A216 PI12/A226 PI13/A236 PI14/A246 PI15/A25/NR_CLK6 Port GPIO/AMC/ATAPI PJ0/ARDY/WAIT PJ1/ND_CE7 PJ2/ND_RB PJ3/ATAPI_DIOR PJ4/ATAPI_DIOW PJ5/ATAPI_CS0 PJ6/ATAPI_CS1 PJ7/ATAPI_DMACK PJ8/ATAPI_DMARQ PJ9/ATAPI_INTRQ PJ10/ATAPI_IORDY PJ11/BR8 PJ12/BG6 PJ13/BGH6 I/O1 Function (First/Second/Third/Fourth) GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access GPIO/Address Async Access/ clock GPIO/ Async Ready/NOR Wait GPIO/NAND Chip Enable GPIO/NAND Ready Busy GPIO/ATAPI Read GPIO/ATAPI Write GPIO/ATAPI Chip Select/Command Block GPIO/ATAPI Chip Select GPIO/ATAPI Acknowledge GPIO/ATAPI Request GPIO/Interrupt Request from Device GPIO/ATAPI Ready Handshake GPIO/Bus Request GPIO/Bus Grant GPIO/Bus Grant Hang Driver Type2
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Table Descriptions (Continued)
Name Memory Interface DA0-12 DBA0-1 DQ0-15 DQS0-1 DQM0-1 DCLK0-1 DCLK0-1 DCS0-1 DCLKE9 DRAS DCAS DDR_VREF DDR_VSSR Asynchronous Memory Interface A1-3 D0-15/ND_D0-15/ATAPI_D0-15 AMS0-3 ABE0 /ND_CLE ABE1/ND_ALE AOE/NR_ADV ATAPI Controller Pins ATAPI_PDIAG High-Speed Pins USB_DP USB_DM USB_XI USB_XO USB_ID10 USB_VBUS11 USB_VREF USB_RSET MXVR (MOST) Interface MLF_P MLF_M Mode Control Pins BMODE0-3 I/O1 Function (First/Second/Third/Fourth) Address Bank Active Strobe Data Data Strobe Data Mask Reads Writes Output Clock Complementary Output Clock Chip Selects Clock Enable Address Strobe Column Address Strobe Write Enable Voltage Reference Voltage Reference Shield (Must connected GND.) Address Async ATAPI Addresses Data Async, NAND ATAPI Accesses Bank Selects (Pull high with resistor when used chip select.) Byte Enables:Data Masks Asynchronous Access/NAND Command Latch Enable Byte Enables:Data Masks Asynchronous Access/NAND Address Latch Enable Output Enable/NOR Address Data Valid Read Enable/NOR Output Enable Write Enable Determines 80-pin cable connected host. (Pull when unused.) (Pull when unused.) Clock XTAL Input (Pull high when unused.) Clock XTAL Output (Leave unconnected when unused.) (Pull high when unused.) VBUS (Pull high when unused.) Voltage Reference (Connect through capacitor leave unconnected when used.) Resistance (Connect through unpopulated resistor pad.) MXVR Frame Sync (Leave unconnected when unused.) MXVR Loop Filter Plus (Leave unconnected when unused.) MXVR Loop Filter Minus (Leave unconnected when unused.) MXVR Crystal Input (Pull high when unused.) MXVR Crystal Output (Pull high when unused.) Boot Mode Strap Driver Type2
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Table Descriptions (Continued)
Name JTAG Port Pins TRST Voltage Regulator VROUT0, VROUT1 Real Time Clock RTXO RTXI Clock (PLL) Pins CLKIN CLKOUT XTAL CLKBUF EXT_WAKE RESET Supplies VDDINT VDDEXT12 VDDDDR12 VDDUSB12 VDDRTC12 VDDVR13 VDDMP12 GNDMP12
I/O1 Function (First/Second/Third/Fourth) JTAG Serial Data JTAG Serial Data JTAG Reset (Pull when unused.) JTAG Mode Select JTAG Clock Emulation Output External FET/BJT Drivers (Always connect together reduce signal impedance.) Crystal Output (Leave unconnected when unused.) Crystal Input (Pull high when unused.) Clock/Crystal Input Clock Output Crystal Output Buffered Oscillator Output External Wakeup from Hibernate Output Reset Non-maskable Interrupt (Pull high when unused.) Internal Power Supply External Power Supply External Power Supply External Power Supply Clock Supply Internal Voltage Regulator Power Supply (Connect VDDEXT when unused.) Ground MXVR Power Supply. (Must driven same level VDDINT. Connect VDDINT when unused when MXVR present.) MXVR Ground (Connect when unused when MXVR present.)
Driver Type2
Input, Output, =Power, Ground, Crystal, Analog. Refer Table Page through Table Page driver types. memory boot, SPI0SCK should have pulldown, SPI0MISO should have pullup, SPI0SEL1 used with pullup. HWAIT/HWAITA should pulled high configure polarity. Booting Modes Page functionality available when MXVR present unused. This should used GPIO booting mode This should always enabled ND_CE software pulled high with resistor when using NAND flash. This should always enabled software pulled high enable Async access. This must pulled through 10kOhm resistor self-refresh mode desired during hibernate state deep-sleep mode. used device mode only, USB_ID should either pulled high left unconnected. This output only during initialization session request pulses. Therefore, host mode type mode requires that external voltage source more specification, applied this pin. Other modes require that this external voltage disabled. ensure proper operation, power pins should driven their specified level even associated peripheral used application. This must always connected. internal voltage regulator being used, this connected VDDEXT. Otherwise should powered according VDDVR specification. automotive grade models, internal voltage regulator must used this must tied VDDEXT.
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SPECIFICATIONS
Component specifications subject change without notice.
OPERATING CONDITIONS
Parameter VDDINT1, Internal Supply Voltage Internal Supply Voltage Internal Supply Voltage External Supply Voltage External Supply Voltage External Supply Voltage External Supply Voltage MXVR Supply Voltage MXVR Supply Voltage Real Time Clock Supply Voltage Real Time Clock Supply Voltage Memory Supply Voltage Memory Supply Voltage Internal Voltage Regulator Supply Voltage High Level Input Voltage5, High Level Input Voltage7 High Level Input Voltage7 High Level Input Voltage8 High Level Input Voltage8, High Level Input Voltage11 Level Input Voltage5, Level Input Voltage13 Level Input Voltage13 Level Input Voltage7 Level Input Voltage7 Level Input Voltage9, DDR_VREF Input Voltage Junction Temperature (400/533 MHz) Conditions Nonautomotive grade models Automotive grade models Mobile SDRAM models Nonautomotive Nonautomotive Automotive grade models Nonautomotive grade models Automotive grade models Nonautomotive grade models Automotive grade models SDRAM models Mobile SDRAM models 1.14 2.25 2.25 VDDR_VREF 0.15 VDDR_VREF 0.125 VBUSTWI10 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0.49 VDDDDR Nominal 1.43 1.38 1.31 2.75 1.43 1.38 1.95 VDDDDR VDDDDR 5.25 VDDR_VREF 0.15 VDDR_VREF 0.125 VBUSTWI10 0.51 VDDDDR +105 Unit
VDDEXT3
VDDUSB VDDMP VDDRTC VDDDDR VDDVR4 VIHDDR VIH5V13 VIHTWI VIHUSB VIL5V VILDDR VILTWI VDDR_VREF TJ15
1.875
VDDEXT maximum SDRAM models Mobile SDRAM models VDDEXT maximum VDDEXT maximum VDDEXT minimum I/O, VDDEXT minimum I/O, VDDEXT minimum SDRAM models Mobile SDRAM models VDDEXT minimum
0.50 VDDDDR
400-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @TAMBIENT Junction Temperature (600 MHz) 400-Ball Chip Scale Package Ball Grid Array (CSP_BGA) @TAMBIENT
Table Page frequency/voltage specifications. VDDINT maximum 1.10 during one-time-programmable (OTP) memory programming operations. VDDEXT minimum maximum during memory programming operations. internal voltage regulator supported speed grade models automotive grade models. external voltage regulator must used. Bidirectional pins (D15-0, PA15-0, PB14-0, PC15-0, PD15-0, PE15-0, PF15-0, PG15-0, PH13-0, PI15-0, PJ14-0) input pins (ATAPI_PDIAG, USB_ID, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, BMODE3-0) ADSP-BF54x Blackfin processors V-tolerant (always accept maximum VIH). Voltage compliance outputs, VOH) limited VDDEXT supply voltage. regulator generate VDDINT levels 0.90 1.30 with tolerance. Parameter value applies input bidirectional pins except PB1-0, PE15-14, PG15-11, PH7-6, DQ0-15, DQS0-1. Parameter value applies pins DQ0-15 DQS0-1. PB1-0, PE15-14, PG15-11, PH7-6 V-tolerant (always accept maximum when power applied VDDEXT pins). Voltage compliance output VOH) limited VDDEXT supply voltage. 5.0V tolerant (always accept 5.5V maximum VIH). Voltage compliance outputs (VOH) limited VDDEXT supply voltage.
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pulled VBUSTWI. VBUSTWI independent from necessarily equal VDDEXT. Parameter value applies USB_DP, USB_DM, USB_VBUS pins. Absolute Maximum Ratings Page Parameter value applies input bidirectional pins, except PB1-0, PE15-14, PG15-11, PH7-6. Parameter value applies pins PG15-11 PH7-6. Parameter value applies pins PB1-0 PE15-14. Consult specification version proper resistor value other open drain electrical parameters. must range: 55°C during memory programming operations.
Table Table describe voltage/frequency requirements ADSP-BF54x Blackfin processors' clocks. Take care selecting MSEL, SSEL, CSEL ratios exceed maximum core clock system clock. Table describes phase-locked loop operating conditions. Table Core Clock Requirements-533 Speed Grade1
Parameter fCCLK fCCLK fCCLK fCCLK fCCLK fCCLK
Core Clock Frequency Core Clock Frequency Core Clock Frequency Core Clock Frequency Core Clock Frequency Core Clock Frequency
Condition VDDINT 1.30 minimum VDDINT 1.20 minimum VDDINT 1.14 minimum VDDINT 1.045 minimum VDDINT 0.95 minimum VDDINT 0.90 Vminimum
Internal Regulator Setting2 N/A2 1.25 1.20 1.10 1.00 0.95
Unit
Ordering Guide Page 111. internal voltage regulator supported automotive grade speed grade models
Table Core Clock Requirements-400 Speed Grade1 Parameter
fCCLK fCCLK fCCLK fCCLK
Condition Core Clock Frequency Core Clock Frequency Core Clock Frequency Core Clock Frequency VDDINT 1.14 minimum VDDINT 1.045 minimum VDDINT 0.95 minimum VDDINTT 0.90 minimum
Internal Regulator Setting2 1.20 1.10 1.00 0.95
Unit
Ordering Guide Page internal voltage regulator supported automotive grade models
Table Phase-Locked Loop Operating Conditions
Parameter fVCO Maximum fCCLK Unit
Voltage Controlled Oscillator (VCO) Frequency
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Table System Clock Requirements
SDRAM Models 1332 Mobile SDRAM Models 1203 1332 N/A4 N/A4
Parameter fSCLK fSCLK
Condition VDDINT 1.14 VDDINT 1.14
Unit
fSCLK must less than equal fCCLK. Rounded number. Actual test specification SCLK period Table Page Rounded number. Actual test specification SCLK period 8.33 VDDINT must greater than equal 1.14 mobile SDRAM models. Operating Conditions Page
ELECTRICAL CHARACTERISTICS
Non-Automotive MHz1 1.74 Other Devices2 1.74
Parameter
Test Conditions High Level Output VDDEXT Voltage I/O3 -0.5 VDDEXT 2.25 High Level Output Voltage I/O3 -0.5 High Level Output Voltage SDRAM4 High Level Output Voltage Mobile SDRAM4 Level Output Voltage I/O3 Level Output Voltage I/O3 Level Output Voltage SDRAM4 Level Output Voltage Mobile SDRAM4 High Level Input Current5 High Level Input Current6 High Level Input Current SDRAM7 High Level Input Current Mobile SDRAM7 Level Input Current Three-State Leakage Current10 Three-State Leakage Current10 VDDDDR -8.1 VDDDDR -0.1 VDDEXT VDDEXT 2.25 VDDDDR VDDDDR VDDEXT =3.6 VDDEXT =3.6 VDDDDR =2.7 0.51 VDDDDR VDDDDR =1.95 0.51 VDDDDR VDDEXT =3.6 VDDEXT =3.6 VDDEXT =3.6
Unit
VOHDDR
1.62
1.62
0.56
0.56
VOLDDR
0.18
0.18
IIHP IIHDDR_VREF
10.0 50.0 30.0
10.0 50.0 30.0
30.0
30.0
IIL8 IOZH9 IOZL11
10.0 10.0 10.0
10.0 10.0 10.0
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Parameter Test Conditions MHz, TAMBIENT 25°C, VDDINT fCCLK MHz, fSCLK MHz, 25°C, 0.00 VDDINT fSCLK MHz, 25°C VDDINT fCCLK MHz, 25°C, 0.47 VDDINT 1.10 fCCLK MHz, 25°C, 1.00 VDDINT 1.20 fCCLK MHz, 25°C, 1.00 VDDINT 1.25 fCCLK MHz, 25°C, 1.00 VDDINT 1.30 fCCLK MHz, 25°C, 1.00 VDDEXT VDDVR VDDUSB 3.30 VDDDDR 25°C, CLKIN= with voltage regulator (VDDINT VDDRTC 25°C VDDUSB 25°C, Full Speed Transmit VDDUSB 25°C, High-Speed Transmit fCCLK MHz, fSCLK fCCLK MHz, fSCLK Non-Automotive MHz1 Other Devices2 Unit
Input Capacitance
IDDDEEPSLEEP13
VDDINT Current Deep Sleep Mode
IDDSLEEP IDD-IDLE
VDDINT Current Sleep Mode VDDINT Current Idle
IDD-TYP
VDDINT Current
IDD-TYP
VDDINT Current
IDD-TYP
VDDINT Current
IDD-TYP
VDDINT Current
IDDHIBERNATE13, Hibernate State Current
IDDRTC IDDUSB-FS
VDDRTC Current VDDUSB Current Full/Low Speed Mode VDDUSB Current HighSpeed Mode
IDDUSB-HS
IDDDEEPSLEEP13, VDDINT Current Deep Sleep Mode IDDSLEEP13, VDDINIT Current Sleep Mode
Table IDDDEEPSLEEP (0.77 VDDINT fSCLK)16 IDDSLEEP (Table ASF)
Table IDDDEEPSLEEP mA16 (0.77 VDDINT fSCLK)16 IDDSLEEP (Table ASF)
IDDINT15,
VDDINT Current
fCCLK MHz, fSCLK
Applies non-automotive speed grade models. Ordering Guide.
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Applies speed grade models automotive speed grade models. Ordering Guide. Applies output bidirectional pins, except USB_VBUS pins listed table note Applies pins DA0-12, DBA0-1, DQ0-15, DQS0-1, DQM0-1, DCLK1-2, DCLK1-2, DCS0-1, DCLKE, DRAS, DCAS, DWE. Applies input pins except JTAG inputs. Applies JTAG input pins (TCK, TDI, TMS, TRST). Applies DDR_VREF pin. Absolute value. pins (DQ0-15, DQS0-1), test conditions VDDDDR Maximum, VDDDDR Maximum. Applies three-statable pins. pins (DQ0-15, DQS0-1), test conditions VDDDDR Maximum, Guaranteed, tested ADSP-BF54x Blackfin Processor Hardware Reference Manual definition sleep, deep sleep, hibernate operating modes. Includes current VDDEXT, VDDUSB, VDDVR, VDDDDR supplies. Clock inputs tied high low. Guaranteed maximum specifications. Unit VDDINT (volts). Unit fSCLK MHz. Example: would 0.77 122.9 adder. Table list IDDINT power vectors covered.
Total power dissipation components: Static, including leakage current Dynamic, transistor switching characteristics Many operating conditions also affect power dissipation, including temperature, voltage, operating frequency, processor activity. Electrical Characteristics Page shows current dissipation internal circuitry (VDDINT). IDDDEEPSLEEP specifies static power dissipation function voltage (VDDINT) temperature (see Table Table 18), IDDINT specifies
total power specification listed test conditions, including dynamic component function voltage (VDDINT) frequency (Table 20). There parts dynamic component. first part transistor switching core clock (CCLK) domain. This part subject activity scaling factor (ASF) which represents application code running processor core L1/L2 memories (Table 19). combined with CCLK frequency VDDINT dependent data Table calculate this part. second part transistor switching system clock (SCLK) domain, which included IDDINT specification equation.
Table Static Current Non-Automotive Speed Grade Devices (mA)1 Voltage (VDDINT)2
(°C)2
0.09 11.9 20.1 31.2 47.0 58.6 80.7 107.0 153.9 171.7
0.95 13.5 22.3 34.2 51.0 63.1 86.6 114.3 163.0 181.5
1.00 15.5 24.7 37.5 55.5 68.3 93.0 122.5 173.3 192.7
1.05 17.7 27.8 41.3 60.6 74.1 100.2 131.5 184.8 205.1
1.10 20.3 31.1 45.6 66.0 80.3 108.1 141.2 197.0 218.3
1.15 23.3 34.9 50.3 72.0 87.1 116.7 151.7 210.0 232.4
1.20 26.8 39.3 55.7 78.8 94.9 125.9 163.1 224.1 247.5
1.25 30.6 44.2 61.7 86.1 103.0 136.0 175.3 239.0 263.6
1.30 35.0 49.6 68.2 94.2 112.0 146.8 188.5 255.1 280.9
1.35 39.9 55.7 75.4 102.9 122.0 158.7 202.7 272.4 299.3
1.38 43.2 59.8 80.3 108.9 128.4 166.4 211.8 283.4 308.7
1.40 45.5 62.5 83.6 112.8 132.8 171.6 218.0 290.8 314.9
1.43 49.5 67.2 88.6 118.2 140.0 179.5 226.7 300.6 325.7
Values guaranteed maximum IDDDEEPSLEEP non-automotive speed-grade devices. Valid temperature voltage ranges model-specific. Operating Conditions Page
Table Static Current Automotive MHz/600 Speed Grade Devices (mA)1
Voltage (VDDINT)2 (°C) 0.90 19.7 45.2 80.0 124.2
0.95 22.1 49.9 87.5 134.8
1.00 24.8 55.2 96.2 147.1
1.05 27.9 61.3 105.8 160.7
1.10 31.4 67.9 116.4 175.3
1.15 35.4 75.3 127.9 191.2
1.20 39.9 83.5 140.4 208.6
1.25 45.0 92.6 154.1 227.3
1.30 50.6 102.6 169.2 247.6
1.35 57.0 113.6 185.4 269.6
1.38 61.2 121.0 196.1 284.0
1.40 64.0 125.8 203.3 293.6
1.43 70.4 135.0 218.0 312.0
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Table Static Current Automotive MHz/600 Speed Grade Devices (mA)1 (Continued)
Voltage (VDDINT)2 (°C) 0.90 154.6 209.8 281.8 366.5 403.8
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