high performance Blackfin processor Three 16-bit MACs, 40-bit ALUs, fo
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Blackfin Embedded Processor
high performance Blackfin processor Three 16-bit MACs, 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register instruction model ease programming compiler-friendly support Advanced debug, trace, performance monitoring Wide range operating voltages. Operating Conditions Page Programmable on-chip voltage regulator 182-ball 208-ball CSP_BGA packages
PERIPHERALS
IEEE 802.3-compliant 10/100 Ethernet (ADSP-BF536 ADSP-BF537 only) Controller area network (CAN) 2.0B interface Parallel peripheral interface (PPI), supporting ITU-R video data formats dual-channel, full-duplex synchronous serial ports (SPORTs), supporting stereo channels peripheral DMAs, mastered Ethernet memory-to-memory DMAs with external request lines Event handler with interrupt inputs Serial peripheral interface (SPI) compatible UARTs with IrDA support 2-wire interface (TWI) controller Eight 32-bit timer/counters with support Real-time clock (RTC) watchdog timer 32-bit core timer general-purpose I/Os (GPIOs), with high current drivers On-chip capable frequency multiplication Debug/JTAG interface
MEMORY
132K bytes on-chip memory Instruction SRAM/cache instruction SRAM Data SRAM/cache plus additional dedicated data SRAM Scratchpad SRAM (see Table Page available memory configurations) External memory controller with glueless support SDRAM asynchronous 8-bit 16-bit memories Flexible booting options from external flash, memory from SPI, TWI, UART host devices Memory management unit providing memory protection
VOLTAGE REGULATOR
JTAG TEST EMULATION
PERIPHERAL ACCESS
WATCHDOG TIMER
INSTRUCTION MEMORY DATA MEMORY
INTERRUPT CONTROLLER SPORT0 CONTROLLER
EXTERNAL
PORT
SPORT1 UART0-1 TIMER7-0 ETHERNET (See Table
GPIO PORT
CORE EXTERNAL ACCESS
GPIO PORT
EXTERNAL PORT FLASH, SDRAM CONTROL BOOT
GPIO PORT
Figure Functional Block Diagram
Blackfin Blackfin logo registered trademarks Analog Devices, Inc.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
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TABLE CONTENTS
Features Memory Peripherals Table Contents Revision History General Description Portable Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) Controller Interface 10/100 Ethernet Ports Parallel Peripheral Interface (PPI) Dynamic Power Management Voltage Regulation Clock Signals Booting Modes Instruction Description Development Tools Designing Emulator-Compatible Processor Board Related Documents Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Sensitivity Package Information Timing Specifications Output Drive Currents Test Conditions Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
REVISION HISTORY
2/09-Rev. Rev. revision data sheet never released publicly. following revisions include those from both revision from revision Revised IDDSLEEP, IDDDEEPSLEEP, IDDINT specifications. Electrical Characteristics Removed Power Dissipation section. Estimating Power ADSP-BF534/BF536/BF537 Blackfin Processors (EE-297) Table Table Added tNOBOOT specification Clock Reset Timing Removed DATA15-0 from footnote Asynchronous Memory Write Cycle Timing Revised SDRAM tENSDAT specification. SDRAM Interface Timing Revised serial ports internal clock timing specifications tSFSI tSDRI. Serial Ports Revised master timing specifications diagram. Serial Peripheral Interface Port-Master Timing Revised slave timing specifications diagram. Serial Peripheral Interface Port-Slave Timing Revised timer cycle timing specifications tTIS tTOD. Timer Cycle Timing Revised Figure Figure (added pin).
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GENERAL DESCRIPTION
processors members Blackfin® family products, incorporating Analog Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin processors combine dual-MAC, state-of-the-art signal processing engine, advantages clean, orthogonal RISC-like microprocessor instruction set, single-instruction, multiple-data (SIMD) multimedia capabilities into single instruction-set architecture. processors completely code compatible. They differ only with respect their performance, on-chip memory, presence Ethernet module. Specific performance, memory, feature configurations shown Table Table Processor Comparison
ADSP-BF534 ADSP-BF536 ADSP-BF537
PORTABLE POWER ARCHITECTURE
Blackfin processors provide world-class power management performance. They produced with power voltage design methodology feature on-chip dynamic power management, which ability vary both voltage frequency operation significantly lower overall power consumption. This capability result substantial reduction power consumption, compared with just varying frequency operation. This allows longer battery life portable appliances.
SYSTEM INTEGRATION
Blackfin processor highly integrated system-on-a-chip solution next generation embedded network-connected applications. combining industry-standard interfaces with high performance signal processing core, cost-effective applications developed quickly, without need costly external components. system peripherals include IEEE-compliant 802.3 10/100 Ethernet (ADSP-BF536 ADSP-BF537 only), 2.0B controller, controller, UART ports, port, serial ports (SPORTs), nine general-purpose 32-bit timers (eight with capability), real-time clock, watchdog timer, parallel peripheral interface (PPI).
Features Ethernet SPORTs UARTs Timers Watchdog Timers Parallel Peripheral Interface GPIOs Instruction SRAM/Cache Instruction SRAM Memory Data Configuration SRAM/Cache Data SRAM Scratchpad Boot Maximum Speed Grade Package Options: CSP_BGA CSP_BGA
bytes bytes bytes bytes bytes bytes 208-Ball 182-Ball
bytes
bytes
BLACKFIN PROCESSOR PERIPHERALS
processors contain rich peripherals connected core several high bandwidth buses, providing flexibility system configuration well excellent overall system performance (see Figure processors contain dedicated network communication modules high speed serial parallel ports, interrupt controller flexible management interrupts from on-chip peripherals external sources, power management control functions tailor performance power characteristics processor system many application scenarios. peripherals, except general-purpose I/O, CAN, TWI, real-time clock, timers, supported flexible structure. There also separate memory channels dedicated data transfers between processor's various memory spaces, including external SDRAM asynchronous memory. Multiple on-chip buses running provide enough bandwidth keep processor core running along with activity on-chip external peripherals. Blackfin processors include on-chip voltage regulator support processors' dynamic power management capability. voltage regulator provides range core voltage levels when supplied from VDDEXT. voltage regulator bypassed user's discretion.
bytes bytes bytes bytes bytes bytes 208-Ball 182-Ball bytes bytes bytes 208-Ball 182-Ball
integrating rich industry-leading system peripherals memory, Blackfin processors platform choice next-generation applications that require RISC-like programmability, multimedia support, leading-edge signal processing integrated package.
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BLACKFIN PROCESSOR CORE
shown Figure Blackfin processor core contains 16-bit multipliers, 40-bit accumulators, 40-bit ALUs, four video ALUs, 40-bit shifter. computation units process 16-, 32-bit data from register file. compute register file contains eight 32-bit registers. When performing compute operations 16-bit operand data, register file operates independent 16-bit registers. operands compute operations come from multiported register file instruction constant fields. Each perform 16-bit 16-bit multiply each cycle, accumulating results into 40-bit accumulators. Signed unsigned formats, rounding, saturation supported. ALUs perform traditional arithmetic logical operations 16-bit 32-bit data. addition, many special instructions included accelerate various signal processing tasks. These include operations such field extract population count, modulo multiply, divide primitives, saturation rounding, sign/exponent detection. video instructions include byte alignment packing operations, 16-bit 8-bit adds with clipping, 8-bit average operations, 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided compare/select vector search instructions. certain instructions, 16-bit operations performed simultaneously register pairs 16-bit high half 16-bit half compute register). second used, quad 16-bit operations possible. 40-bit shifter perform shifts rotates, used support normalization, field extract, field deposit instructions. program sequencer controls flow instruction execution, including instruction alignment decoding. program flow control, sequencer supports relative indirect conditional jumps (with static branch prediction), subroutine calls. Hardware provided support zero-overhead looping. architecture fully interlocked, meaning that programmer need manage pipeline when executing instructions with data dependencies.
ADDRESS ARITHMETIC UNIT
MEMORY
DAG1 DAG0
PREG
R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H
R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L BARREL SHIFTER
ASTAT SEQUENCER
ALIGN DECODE LOOP BUFFER
CONTROL UNIT
DATA ARITHMETIC UNIT
Figure Blackfin Processor Core
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address arithmetic unit provides addresses simultaneous dual fetches from memory. contains multiported register file consisting four sets 32-bit index, modify, length, base registers (for circular buffering), eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support modified Harvard architecture combination with hierarchical memory structure. Level (L1) memories those that typically operate full processor speed with little latency. level, instruction memory holds instructions only. data memories hold data, dedicated scratchpad data memory stores stack local variable information. addition, multiple memory blocks provided, offering configurable SRAM cache. memory management unit (MMU) provides memory protection individual tasks that operating core protect system registers from unintended access. architecture provides three modes operation: user mode, supervisor mode, emulation mode. User mode restricted access certain system resources, thus providing protected software environment, while supervisor mode unrestricted access system core resources. Blackfin processor instruction been optimized that 16-bit opcodes represent most frequently used instructions, resulting excellent compiled code density. Complex instructions encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support limited multi-issue capability, where 32-bit instruction issued parallel with 16-bit instructions, allowing programmer many core resources single instruction cycle. Blackfin processor assembly language uses algebraic syntax ease coding readability. architecture been optimized conjunction with C/C++ compiler, resulting fast efficient software implementations. memory controller provides high bandwidth datamovement capability. perform block transfers code data between internal memory external memory spaces.
Internal (On-Chip) Memory
processors have three blocks on-chip memory providing high-bandwidth access core. first block instruction memory, consisting bytes SRAM, which bytes configured four-way set-associative cache. This memory accessed full processor speed. second on-chip memory block data memory, consisting banks bytes each. Each memory bank configurable, offering both cache SRAM functionality. This memory block accessed full processor speed. third memory block byte scratchpad SRAM, which runs same speed memories, only accessible data SRAM, cannot configured cache memory.
External (Off-Chip) Memory
External memory accessed EBIU. This 16-bit interface provides glueless connection bank synchronous DRAM (SDRAM) well four banks asynchronous memory devices including flash, EPROM, ROM, SRAM, memory mapped devices. PC133-compliant SDRAM controller programmed interface 512M bytes SDRAM. separate open each SDRAM internal bank, SDRAM controller supports internal SDRAM banks, improving overall performance. asynchronous memory controller programmed control four banks devices with very flexible timing parameters wide variety devices. Each bank occupies byte segment regardless size devices used, that these banks only contiguous each fully populated with byte memory.
MEMORY ARCHITECTURE
processors view memory single unified byte address space, using 32-bit addresses. resources, including internal memory, external memory, control registers, occupy separate sections this common address space. memory portions this address space arranged hierarchical structure provide good cost/performance balance some very fast, latency on-chip memory cache SRAM, larger, lower cost, performance off-chip memory systems. (See Figure on-chip memory system highest performance memory available Blackfin processor. off-chip memory system, accessed through external interface unit (EBIU), provides expansion with SDRAM, flash memory, SRAM, optionally accessing 516M bytes physical memory.
Memory Space
processors define separate space. resources mapped through flat 32-bit address space. On-chip devices have their control registers mapped into memory-mapped registers (MMRs) addresses near byte address space. These separated into smaller blocks, which contains control MMRs core functions, other which contains registers needed setup control onchip peripherals outside core. MMRs accessible only supervisor mode appear reserved space onchip peripherals.
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ADSP-BF534/ADSP-BF537 MEMORY
0xFFFF FFFF CORE REGISTERS BYTES) 0xFFE0 0000 SYSTEM REGISTERS BYTES) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM BYTES) 0xFFB0 0000 0xFFA1 4000 INSTRUCTION SRAM/CACHE (16K BYTES) 0xFFA1 0000 RESERVED 0xFFA0 C000 INSTRUCTION BANK SRAM (16K BYTES) 0xFFA0 8000 INSTRUCTION BANK SRAM (32K BYTES) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK SRAM/CACHE (16K BYTES) 0xFF90 4000 DATA BANK SRAM (16K BYTES) 0xFF90 0000 RESERVED 0xFF80 8000 DATA BANK SRAM/CACHE (16K BYTES) 0xFF80 4000 DATA BANK SRAM (16K BYTES) 0xFF80 0000 RESERVED BOOT BYTES) 0xEF00 0000 RESERVED 0x2040 0000 ASYNC MEMORY BANK BYTES) 0x2030 0000 ASYNC MEMORY BANK BYTES) 0x2020 0000 ASYNC MEMORY BANK BYTES) 0x2010 0000 ASYNC MEMORY BANK BYTES) 0x2000 0000 SDRAM MEMORY (16M BYTES 512M BYTES) 0x0000 0000
EXTERNAL MEMORY INTERNAL MEMORY
ADSP-BF536 MEMORY
0xFFFF FFFF CORE REGISTERS BYTES) 0xFFE0 0000 SYSTEM REGISTERS BYTES) 0xFFC0 0000 RESERVED 0xFFB0 1000 0xFFB0 0000 RESERVED 0xFFA1 4000 INSTRUCTION SRAM/CACHE (16K BYTES) 0xFFA1 0000 RESERVED 0xFFA0 C000 INSTRUCTION BANK SRAM (16K BYTES) 0xFFA0 8000 INSTRUCTION BANK SRAM (32K BYTES) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK SRAM/CACHE (16K BYTES) 0xFF90 4000 RESERVED 0xFF90 0000 RESERVED 0xFF80 8000 DATA BANK SRAM/CACHE (16K BYTES) 0xFF80 4000 RESERVED 0xFF80 0000 RESERVED BOOT BYTES) 0xEF00 0000 RESERVED 0x2040 0000 ASYNC MEMORY BANK BYTES) 0x2030 0000 ASYNC MEMORY BANK BYTES) 0x2020 0000 ASYNC MEMORY BANK BYTES) 0x2010 0000 ASYNC MEMORY BANK BYTES) 0x2000 0000 SDRAM MEMORY (16M BYTES 512M BYTES) 0x0000 0000
EXTERNAL MEMORY INTERNAL MEMORY
SCRATCHPAD SRAM BYTES)
RESERVED
0xEF00 0800
0xEF00 0800
Figure Memory Maps
Booting
Blackfin processor contains small on-chip boot kernel, which configures appropriate peripheral booting. Blackfin processor configured boot from boot memory space, processor starts executing from on-chip boot ROM. more information, Booting Modes Page
Nonmaskable Interrupt (NMI) event generated software watchdog timer input signal processor. event frequently used power-down indicator initiate orderly shutdown system. Exceptions Events that occur synchronously program flow other words, exception taken before instruction allowed complete). Conditions such data alignment violations undefined instructions cause exceptions. Interrupts Events that occur asynchronously program flow. They caused input pins, timers, other peripherals, well explicit software instruction. Each event type associated register hold return address associated return-from-event instruction. When event triggered, state processor saved supervisor stack. Blackfin processor event controller consists stages: core event controller (CEC) system interrupt controller (SIC). core event controller works with system interrupt controller prioritize control system events.
Event Handling
event controller Blackfin processor handles asynchronous synchronous events processor. Blackfin processor provides event handling that supports both nesting prioritization. Nesting allows multiple event service routines active simultaneously. Prioritization ensures that servicing higher priority event takes precedence over servicing lower priority event. controller provides support five different types events: Emulation emulation event causes processor enter emulation mode, allowing command control processor JTAG interface. Reset This event resets processor.
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Conceptually, interrupts from peripherals enter into SIC, then routed directly into general-purpose interrupts CEC. Table System Interrupt Controller (SIC)
Peripheral Interrupt Event Wakeup Error (Generic) DMAR0 Block Interrupt DMAR1 Block Interrupt DMAR0 Overflow Error DMAR1 Overflow Error Error Ethernet Error (ADSP-BF536 ADSP-BF537 only) SPORT Error SPORT Error Error Error UART0 Error UART1 Error Real-Time Clock Channel (PPI) Channel (SPORT Channel (SPORT Channel (SPORT Channel (SPORT Channel (SPI) Channel (UART0 Channel (UART0 Channel (UART1 Channel (UART1 Channel (Ethernet ADSP-BF536 ADSP-BF537 only) Port Interrupt Channel (Ethernet ADSP-BF536 ADSP-BF537 only) Port Interrupt Timer Timer Timer Timer Timer Timer Timer Timer Port Interrupt Port Interrupt Default Mapping IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 Peripheral Interrupt
Core Event Controller (CEC)
supports nine general-purpose interrupts (IVG15-7), addition dedicated interrupt exception events. these general-purpose interrupts, lowest priority interrupts (IVG15-14) recommended reserved software interrupt handlers, leaving seven prioritized interrupt inputs support peripherals Blackfin processor. Table describes inputs CEC, identifies their names event vector table (EVT), lists their priorities. Table Core Event Controller (CEC)
Priority Highest) Event Class Emulation/Test Control Reset Nonmaskable Interrupt Exception Reserved Hardware Error Core Timer General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt Entry IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
System Interrupt Controller (SIC)
system interrupt controller provides mapping routing events from many peripheral interrupt sources prioritized general-purpose interrupt inputs CEC. Although processor provides default mapping, user alter mappings priorities interrupt events writing appropriate values into interrupt assignment registers (IAR). Table describes inputs into default mappings into CEC.
Event Control
Blackfin processor provides very flexible mechanism control processing events. CEC, three registers used coordinate control events. Each register bits wide: interrupt latch register (ILAT) Indicates when events have been latched. appropriate when processor latched event cleared when
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Table System Interrupt Controller (SIC) (Continued)
Peripheral Interrupt Event Channels (Memory Stream Channels (Memory Stream Software Watchdog Timer Port Interrupt Default Mapping IVG13 IVG13 IVG13 IVG13 Peripheral Interrupt
event already detected this interrupt input. IPEND register contents monitored interrupt acknowledgement. appropriate ILAT register when interrupt rising edge detected (detection requires core clock cycles). cleared when respective IPEND register set. IPEND indicates that event entered into processor pipeline. this point recognizes queues next rising edge event corresponding event input. minimum latency from rising edge transition generalpurpose interrupt IPEND output asserted three core clock cycles; however, latency much higher, depending activity within state processor.
event been accepted into system. This register updated automatically controller, written only when corresponding IMASK cleared. interrupt mask register (IMASK) Controls masking unmasking individual events. When IMASK register, that event unmasked processed when asserted. cleared IMASK register masks event, preventing processor from servicing event even though event latched ILAT register. This register read written while supervisor mode. (Note that general-purpose interrupts globally enabled disabled with instructions, respectively.) interrupt pending register (IPEND) IPEND register keeps track nested events. IPEND register indicates event currently active nested some level. This register updated automatically controller read while supervisor mode. allows further control event processing providing three 32-bit interrupt control status registers. Each register contains corresponding each peripheral interrupt events shown Table Page interrupt mask register (SIC_IMASK) Controls masking unmasking each peripheral interrupt event. When register, that peripheral event unmasked processed system when asserted. cleared register masks peripheral event, preventing processor from servicing event. interrupt status register (SIC_ISR) multiple peripherals mapped single event, this register allows software determine which peripheral event source triggered interrupt. indicates peripheral asserting interrupt, cleared indicates peripheral asserting event. interrupt wake-up enable register (SIC_IWR) enabling corresponding this register, peripheral configured wake processor, should core idled when event generated. (For more information, Dynamic Power Management Page 13.) Because multiple interrupt sources single generalpurpose interrupt, multiple pulse assertions occur simultaneously, before during interrupt processing interrupt
CONTROLLERS
Blackfin processors have multiple, independent channels that support automated data transfers with minimal overhead processor core. transfers occur between processor's internal memories DMAcapable peripherals. Additionally, transfers accomplished between DMA-capable peripherals external devices connected external memory interfaces, including SDRAM controller asynchronous memory controller. DMA-capable peripherals include Ethernet (ADSP-BF536 ADSP-BF537 only), SPORTs, port, UARTs, PPI. Each individual DMA-capable peripheral least dedicated channel. controller supports both one-dimensional (1-D) two-dimensional (2-D) transfers. transfer initialization implemented from registers from sets parameters called descriptor blocks. capability supports arbitrary column sizes elements elements, arbitrary column step sizes ±32K elements. Furthermore, column step size less than step size, allowing implementation interleaved data streams. This feature especially useful video applications where data deinterleaved fly. Examples types supported controller include single, linear buffer that stops upon completion circular, auto-refreshing buffer that interrupts each full fractionally full buffer using linked list descriptors using array descriptors, specifying only base address within common page. addition dedicated peripheral channels, there memory channels provided transfers between various memories processor system. This enables transfers blocks data between memories-including external SDRAM, ROM, SRAM, flash memory-with minimal processor intervention. Memory transfers controlled very flexible descriptor-based methodology standard register-based autobuffer mechanism.
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processors also have external controller capability dual external request pins when used conjunction with external interface unit (EBIU). This functionality used when high speed interface required external FIFOs high bandwidth communications peripherals such 2.0. allows control number data transfers memDMA. number transfers edge programmable. This feature programmed allow memDMA have increased priority external relative core.
RTXI RTXO
REAL-TIME CLOCK
real-time clock (RTC) provides robust digital watch features, including current time, stopwatch, alarm. clocked 32.768 crystal external processor. peripheral dedicated power supply pins that remain powered clocked even when rest processor power state. provides several programmable interrupt options, including interrupt second, minute, hour, clock ticks, interrupt programmable stopwatch countdown, interrupt programmed alarm time. 32.768 input clock frequency divided down signal prescaler. counter function timer consists four counters: 60-second counter, 60-minute counter, 24-hour counter, 32,768-day counter. When enabled, alarm function generates interrupt when output timer matches programmed value alarm control register. There alarms: first alarm time day, while second alarm time that day. stopwatch function counts down from programmed value, with one-second resolution. When stopwatch enabled counter underflows, interrupt generated. Like other peripherals, wake processor from sleep mode upon generation wake-up event. Additionally, wake-up event wake processor from deep sleep mode, wake on-chip internal voltage regulator from hibernate operating mode. Connect pins RTXI RTXO with external components shown Figure
SUGGESTED COMPONENTS: ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12pF LOAD (SURFACE-MOUNT PACKAGE) 22pF 22pF NOTE: SPECIFIC CRYSTAL SPECIFIED CONTACT CRYSTAL MANUFACTURER DETAILS. SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE 3pF.
Figure External Components
configured generate hardware reset, watchdog timer resets both core processor peripherals. After reset, software determine watchdog source hardware reset interrogating status watchdog timer control register. timer clocked system clock (SCLK), maximum frequency fSCLK.
TIMERS
There nine general-purpose programmable timer units processor. Eight timers have external that configured either pulse-width modulator (PWM) timer output, input clock timer, mechanism measuring pulse widths periods external events. These timers synchronized external clock input several other associated pins, external clock input PPI_CLK input pin, internal SCLK. timer units used conjunction with UARTs controller measure width pulses data stream provide software auto-baud detect function respective serial channels. timers generate interrupts processor core providing periodic events synchronization, either system clock count external signals. addition eight general-purpose programmable timers, ninth timer also provided. This extra timer clocked internal processor clock typically used system tick clock generating periodic interrupts operating system.
WATCHDOG TIMER
processors include 32-bit timer that used implement software watchdog function. software watchdog improve system availability forcing processor known state through generation system reset, nonmaskable interrupt (NMI), general-purpose interrupt, timer expires before being reset software. programmer initializes count value timer, enables appropriate interrupt, then enables timer. Thereafter, software must reload counter before counts zero from programmed value. This protects system from remaining unknown state where software, which would normally reset timer, stopped running external noise condition software error.
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SERIAL PORTS (SPORTs)
processors incorporate dual-channel synchronous serial ports (SPORT0 SPORT1) serial multiprocessor communications. SPORTs support following features: capable operation. Bidirectional operation Each SPORT sets independent transmit receive pins, enabling eight channels stereo audio. Buffered (8-deep) transmit receive ports Each port data register transferring data words from other processor components shift registers shifting data data registers. Clocking Each transmit receive port either external serial clock generate own, frequencies ranging from (fSCLK/131,070) (fSCLK/2) Word length Each SPORT supports serial data words from bits bits length, transferred most significant first least significant first. Framing Each transmit receive port with without frame sync signals each data word. Frame sync signals generated internally externally, active high low, with either pulse widths early late frame sync. Companding hardware Each SPORT perform A-law -law companding according recommendation G.711. Companding selected transmit and/or receive channel SPORT without additional latencies. operations with single-cycle overhead Each SPORT automatically receive transmit multiple buffers memory data. processor link chain sequences transfers between SPORT memory. Interrupts Each transmit receive port generates interrupt upon completing transfer data word after transferring entire data buffer, buffers, through DMA. Multichannel capability Each SPORT supports channels 1024-channel window compatible with H.100, H.110, MVIP-90, HMVIP standards. port provides full-duplex, synchronous serial interface, which supports both master/slave modes multimaster environments. port's baud rate clock phase/polarities programmable, integrated controller, configurable support transmit receive data streams. SPI's controller only service unidirectional accesses given time. port's clock rate calculated SCLK Clock Rate SPI_BAUD where 16-bit SPI_BAUD register contains value 65,535. During transfers, port simultaneously transmits receives serially shifting data serial data lines. serial clock line synchronizes shifting sampling data serial data lines.
UART PORTS
processors provide full-duplex universal asynchronous receiver transmitter (UART) ports, which fully compatible with PCstandard UARTs. Each UART port provides simplified UART interface other peripherals hosts, supporting full-duplex, DMA-supported, asynchronous transfers serial data. UART port includes support five eight data bits, stop bits, none, even, parity. Each UART port supports modes operation: (programmed I/O) processor sends receives data writing reading mapped UART registers. data double-buffered both transmit receive. (direct memory access) controller transfers both transmit receive data. This reduces number frequency interrupts required transfer data from memory. UART dedicated channels, transmit receive. These channels have lower default priority than most channels because their relatively service rates. Each UART port's baud rate, serial data format, error code generation status, interrupts programmable: Supporting rates ranging from (fSCLK/1,048,576) (fSCLK/16) bits second. Supporting data formats from bits bits frame. Both transmit receive operations configured generate maskable interrupts processor. UART port's clock rate calculated SCLK UART Clock Rate UARTx_Divisor where 16-bit UARTx_Divisor comes from UARTx_DLH register (most significant bits) UARTx_DLL register (least significant bits).
SERIAL PERIPHERAL INTERFACE (SPI) PORT
processors have SPI-compatible port that enables processor communicate with multiple SPI-compatible devices. interface uses three pins transferring data: data pins (Master Output-Slave Input, MOSI, Master InputSlave Output, MISO) clock (serial clock, SCK). chip select input (SPISS) lets other devices select processor, seven chip select output pins (SPISEL7-1) processor select other devices. select pins reconfigured programmable flag pins. Using these pins,
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conjunction with general-purpose timer functions, autobaud detection supported. capabilities UARTs further extended with support infrared data association (IrDA®) serial infrared physical layer link specification (SIR) protocol.
10/100 ETHERNET
ADSP-BF536 ADSP-BF537 processors offer capability directly connect network embedded fast Ethernet Media Access Controller (MAC) that supports both 10-BaseT Mbps) 100-BaseT (100 Mbps) operation. 10/100 Ethernet peripheral fully compliant IEEE 802.3-2002 standard, provides programmable features designed minimize supervision, use, message processing rest processor system. Some standard features Support RMII protocols external PHYs. Full duplex half duplex modes. Data framing encapsulation: generation detection preamble, length padding, FCS. Media access management half-duplex operation): collision contention handling, including control retransmission collision frames back-off timing. Flow control full-duplex operation): generation detection PAUSE frames. Station management: generation MDC/MDIO frames read-write access registers. SCLK operating range down (active sleep operating modes). Internal loopback from Some advanced features Buffered crystal output external support single crystal system. Automatic checksum computation header payload fields frames. Independent 32-bit descriptor-driven channels. Frame status delivery memory DMA, including frame completion semaphores, efficient buffer queue management software. support separate descriptors header payload eliminate buffer copy operations. Convenient frame alignment modes support even 32-bit alignment encapsulated packet data memory after 14-byte header. Programmable Ethernet event interrupt supports combination selected frame status conditions. interrupt condition. Wake-up frame detected. selected management counter(s) half-full. descriptor error. management statistics counters with selectable clear-on-read behavior programmable interrupts half maximum value.
CONTROLLER AREA NETWORK (CAN)
processors offer controller that communication controller implementing 2.0B (active) protocol. This protocol asynchronous communications protocol used both industrial automotive control systems. protocol wellsuited control applications capability communicate reliably over network, since protocol incorporates checking message error tracking, fault node confinement. controller offers following features: mailboxes (eight receive only, eight transmit only, configurable receive transmit). Dedicated acceptance masks each mailbox. Additional data filtering first bytes. Support both standard (11-bit) extended (29-bit) identifier (ID) message formats. Support remote frames. Active passive network support. wake-up from hibernation mode (lowest static power consumption mode). Interrupts, including: complete, complete, error, global. electrical characteristics each network connection very demanding interface typically divided into parts: controller transceiver. This allows single controller support different drivers networks. module represents only controller part interface. controller interface supports connection highspeed, fault-tolerant, single-wire transceivers.
CONTROLLER INTERFACE
processors include 2-wire interface (TWI) module providing simple exchange method control data between multiple devices. compatible with widely used I2C® standard. module offers capabilities simultaneous master slave operation, support both 7-bit addressing multimedia data arbitration. interface utilizes pins transferring clock (SCL) data (SDA) supports protocol speeds kbps. interface pins compatible with logic levels. Additionally, processor's module fully compatible with serial camera control (SCCB) functionality easier control various CMOS camera sensor devices.
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Programmable address filters, including 64-bit address hash table multicast and/or unicast frames, programmable filter modes broadcast, multicast, unicast, control, damaged frames. Advanced power management supporting unattended transfer frames status to/from external memory during power sleep mode. System wake-up from sleep operating mode upon magic packet four user-definable wake-up frame filters. Support 802.3Q tagged VLAN frames. Programmable clock rate preamble suppression. RMII operation, unused pins configured GPIO pins other purposes. GPIO pins defined inputs configured generate hardware interrupts, while output pins triggered software interrupts. GPIO interrupt sensitivity registers GPIO interrupt sensitivity registers specify whether individual pins level- edge-sensitive specify-if edge-sensitive- whether just rising edge both rising falling edges signal significant. register selects type sensitivity, register selects which edges significant edge-sensitivity.
PARALLEL PERIPHERAL INTERFACE (PPI)
processor provides parallel peripheral interface (PPI) that connect directly parallel converters, video encoders decoders, other general-purpose peripherals. consists dedicated input clock pin, three frame synchronization pins, data pins. input clock supports parallel data rates half system clock rate synchronization signals configured either inputs outputs. supports variety general-purpose ITU-R modes operation. general-purpose mode, provides half-duplex, bidirectional data transfer with bits data. three frame synchronization signals also provided. ITU-R mode, provides half-duplex bidirectional transfer 10-bit video data. Additionally, on-chip decode embedded start-of-line (SOL) start-offield (SOF) preamble packets supported.
PORTS
processors group many peripheral signals four ports-Port Port Port Port Most associated pins shared multiple signals. ports function multiplexer controls. Eight pins (Port F7-0) offer high source/high sink current capabilities.
General-Purpose (GPIO)
processors have bidirectional, general-purpose (GPIO) pins allocated across three separate GPIO modules- PORTFIO, PORTGIO, PORTHIO, associated with Port Port Port respectively. Port does provide GPIO functionality. Each GPIO-capable shares functionality with other processor peripherals multiplexing scheme; however, GPIO functionality default state device upon power-up. Neither GPIO output input drivers active default. Each general-purpose port individually controlled manipulation port control, status, interrupt registers: GPIO direction control register Specifies direction each individual GPIO input output. GPIO control status registers processors employ "write modify" mechanism that allows combination individual GPIO pins modified single instruction, without affecting level other GPIO pins. Four control registers provided. register written order values, register written order clear values, register written order toggle values, register written order specify value. Reading GPIO status register allows software interrogate sense pins. GPIO interrupt mask registers GPIO interrupt mask registers allow each individual GPIO function interrupt processor. Similar GPIO control registers that used clear individual values, GPIO interrupt mask register sets bits enable interrupt function, other GPIO interrupt mask register clears bits disable interrupt function.
General-Purpose Mode Descriptions
general-purpose modes intended suit wide variety data capture transmission applications. Three distinct submodes supported: Input mode Frame syncs data inputs into PPI. Frame capture mode Frame syncs outputs from PPI, data inputs. Output mode Frame syncs data outputs from PPI. Input Mode Input mode intended applications, well video communication with hardware signaling. simplest form, PPI_FS1 external frame sync input that controls when read data. PPI_DELAY allows delay PPI_CLK cycles) between reception this frame sync initiation data reads. number input data samples user programmable defined contents PPI_COUNT register. supports 8-bit 10-bit through 16-bit data, programmable PPI_CONTROL register.
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Frame Capture Mode Frame capture mode allows video source(s) slave (for frame capture example). ADSP-BF534/ ADSP-BF536/ADSP-BF537 processors control when read from video source(s). PPI_FS1 HSYNC output PPI_FS2 VSYNC output. Output Mode Output mode used transmitting video other data with three output frame syncs. Typically, single frame sync appropriate data converter applications, whereas three frame syncs could used sending video with hardware signaling.
Full-On Operating Mode-Maximum Performance
full-on mode, enabled bypassed, providing capability maximum operational frequency. This power-up default execution state which maximum performance achieved. processor core enabled peripherals full speed.
Active Operating Mode-Moderate Dynamic Power Savings
active mode, enabled bypassed. Because bypassed, processor's core clock (CCLK) system clock (SCLK) input clock (CLKIN) frequency. this mode, CLKIN CCLK multiplier ratio changed, although changes realized until full-on mode entered. access available appropriately configured memories. active mode, possible disable through control register (PLL_CTL). disabled, must re-enabled before transitioning full-on sleep modes.
ITU-R Mode Descriptions
ITU-R modes intended suit wide variety video capture, processing, transmission applications. Three distinct submodes supported: Active video only mode Vertical blanking only mode Entire field mode Active Video Mode Active video only mode used when only active video portion field interest blanking intervals. does read data between active video (EAV) start active video (SAV) preamble symbols, data present during vertical blanking intervals. this mode, control byte sequences stored memory; they filtered PPI. After synchronizing start Field ignores incoming samples until sees code. user specifies number active video lines frame PPI_COUNT register). Vertical Blanking Interval Mode this mode, only transfers vertical blanking interval (VBI) data. Entire Field Mode this mode, entire incoming stream read through PPI. This includes active video, control preamble sequences, ancillary data that embedded horizontal vertical blanking intervals. Data transfer starts immediately after synchronization Field Data transferred from synchronous channels through eight engines that work autonomously from processor core.
Sleep Operating Mode-High Dynamic Power Savings
sleep mode reduces dynamic power dissipation disabling clock processor core (CCLK). system clock (SCLK), however, continue operate this mode. Typically external event activity wakes processor. When sleep mode, asserting wake-up causes processor sense value BYPASS control register (PLL_CTL). BYPASS disabled, processor transitions full mode. BYPASS enabled, processor transitions active mode. System access memory supported sleep mode. Table Power Settings
Bypassed Enabled Enabled/ Disabled Enabled Disabled Core Clock (CCLK) Enabled Enabled System Clock (SCLK) Enabled Enabled Internal Power (VDDINT)
Mode Full Active
Sleep Deep Sleep Hibernate Disabled
Disabled Enabled Disabled Disabled Disabled Disabled
DYNAMIC POWER MANAGEMENT
processors provide five operating modes, each with different performance power profile. addition, dynamic power management provides control functions dynamically alter processor core supply voltage, further reducing power dissipation. Control clocking each peripherals also reduces power consumption. Table summary power settings each mode. Also, Table Table Table
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Deep Sleep Operating Mode-Maximum Dynamic Power Savings
deep sleep mode maximizes dynamic power savings disabling clocks processor core (CCLK) synchronous peripherals (SCLK). Asynchronous peripherals, such RTC, still running cannot access internal resources external memory. This powered-down mode only exited assertion reset interrupt (RESET) asynchronous interrupt generated RTC. When deep sleep mode, asynchronous interrupt causes
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processor transition active mode. Assertion RESET while deep sleep mode causes processor transition full-on mode. reduction power dissipation, while reducing voltage reduces power dissipation more than 40%. Further, these power savings additive, that clock frequency supply voltage both reduced, power savings dramatic, shown following equations. power savings factor (PSF) calculated DDINTRED CCLKRED CCLKNOM DDINTNOM where: fCCLKNOM nominal core clock frequency fCCLKRED reduced core clock frequency VDDINTNOM nominal internal supply voltage VDDINTRED reduced internal supply voltage tNOM duration running fCCLKNOM tRED duration running fCCLKRED percent power savings calculated power savings 100%
Hibernate State-Maximum Static Power Savings
hibernate state maximizes static power savings disabling voltage clocks processor core (CCLK) synchronous peripherals (SCLK). internal voltage regulator processor shut writing b#00 FREQ bits VR_CTL register. This disables both CCLK SCLK. Furthermore, sets internal power supply voltage (VDDINT) provide greatest power savings. preserve processor state, prior removing power, critical information stored internally (memory contents, register contents, etc.) must written nonvolatile storage device. Since VDDEXT still supplied this state, external pins three-state, unless otherwise specified. This allows other devices that connected processor still have power applied without drawing unwanted current. Ethernet modules wake internal supply regulator. does connect PHYINT signal external device, pulled other device wake processor regulator also woken real-time clock wake-up event asserting RESET pin. hibernate wake-up events initiate hardware reset sequence. Individual sources enabled VR_CTL register. With exception VR_CTL registers, internal registers memories lose their content hibernate state. State variables held external SRAM SDRAM. SCKELOW VR_CTL register controls whether SDRAM operates self-refresh mode, which allows retain content while processor reset.
VOLTAGE REGULATION
processors provide on-chip voltage regulator that generate appropriate VDDINT voltage levels from VDDEXT supply. Operating Conditions Page regulator tolerances acceptable VDDEXT ranges specific models.
VDDEXT (LOW-INDUCTANCE)
Power Savings
shown Table processors support three different power domains which maximizes flexibility, while maintaining compliance with industry standards conventions. isolating internal logic processor into power domain, separate from other I/O, processor take advantage dynamic power management, without affecting other devices. There sequencing requirements various power domains. Table Power Domains
Power Domain internal logic, except internal logic crystal other Range VDDINT VDDRTC VDDEXT
DECOUPLING CAPACITORS VDDEXT
100F 100nF 100F FDS9431A 100F ZHCS1000
VDDINT
VROUT
SHORT LOWINDUCTANCE WIRE NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH FDS9431A.
VROUT
dynamic power management feature allows both processor's input voltage (VDDINT) clock frequency (fCCLK) dynamically controlled. power dissipated processor largely function clock frequency square operating voltage. example, reducing clock frequency results
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Figure Voltage Regulator Circuit
Figure shows typical external components required complete power management system. regulator controls internal logic voltage levels programmable with voltage regulator control register (VR_CTL) increments
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reduce standby power consumption, internal voltage regulator programmed remove power processor core while keeping power supplied. While hibernate state, VDDEXT still applied, eliminating need external buffers. voltage regulator activated from this power-down state asserting RESET pin, which then initiates boot sequence. regulator also disabled bypassed user's discretion. additional information voltage regulation, Switching Regulator Design Considerations ADSP-BF533 Blackfin Processors (EE-228).
BLACKFIN CLKOUT CIRCUITRY CLKBUF
VDDEXT CLKIN XTAL
CLOCK SIGNALS
processors clocked external crystal, sine wave input, buffered, shaped clock derived from external clock oscillator. external clock used, should compatible signal must halted, changed, operated below specified frequency during normal operation. This signal connected processor's CLKIN pin. When external clock used, XTAL must left unconnected. Alternatively, because processors include on-chip oscillator circuit, external crystal used. fundamental frequency operation, circuit shown Figure parallel-resonant, fundamental frequency, microprocessorgrade crystal connected across CLKIN XTAL pins. on-chip resistance between CLKIN XTAL range. Further parallel resistors typically recommended. capacitors series resistor shown Figure fine-tune phase amplitude sine frequency. capacitor resistor values shown Figure typical values only. capacitor values dependent upon crystal manufacturers' load capacitance recommendations physical layout. resistor value depends drive level specified crystal manufacturer. user should verify customized values based careful investigations multiple devices over temperature range. third-overtone crystal used frequencies above MHz. circuit then modified ensure crystal operation only third overtone, adding tuned inductor circuit shown Figure design procedure third-overtone operation discussed detail application note Using Third Overtone Crystals with ADSP-218x (EE-168). CLKBUF output pin, buffer version input clock. This particularly useful Ethernet applications limit number required clock sources system. this type application, single crystal applied directly processors. output CLKBUF then connected external Ethernet RMII device. Because default multiplier, providing CLKIN exceeds recommended operating conditions lower speed grades. Because this restriction, RMII requiring clock input cannot clocked directly from CLKBUF lower speed grades. this case, either provide separate clock source, RMII
18pF*
18pF* OVERTONE OPERATION ONLY
NOTE: VALUES MARKED WITH MUST CUSTOMIZED DEPENDING CRYSTAL LAYOUT. PLEASE ANALYZE CAREFULLY
Figure External Crystal Connections
with clock input options. CLKBUF output active default disabled using VR_CTL register power savings. Blackfin core runs different clock rate than on-chip peripherals. shown Figure core clock (CCLK) system peripheral clock (SCLK) derived from input clock (CLKIN) signal. on-chip capable multiplying CLKIN signal programmable multiplication factor (bounded specified minimum maximum frequencies). default multiplier modified software instruction sequence PLL_CTL register. On-the-fly CCLK SCLK frequency changes effected simply writing PLL_DIV register. Whereas maximum allowed CCLK SCLK rates depend applied voltages VDDINT VDDEXT, always permitted frequency specified part's speed grade. CLKOUT reflects SCLK frequency off-chip world. belongs SDRAM interface, functions reference signal other timing specifications well. While active default, disabled using EBIU_SDGCTL EBIU_AMGCTL registers.
FINE ADJUSTMENT REQUIRES SEQUENCING COURSE ADJUSTMENT ON-THE-F
CLKIN 0.5x
CCLK
SCLK
SCLK CCLK SCLK 133MHz
Figure Frequency Modification Methods
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on-chip peripherals clocked system clock (SCLK). system clock frequency programmable means SSEL3-0 bits PLL_DIV register. values programmed into SSEL fields define divide ratio between output (VCO) system clock. SCLK divider values through Table illustrates typical system clock ratios. Note that divisor ratio must chosen limit system clock frequency maximum fSCLK. SSEL value changed dynamically without lock latencies writing appropriate values divisor register (PLL_DIV). Table Example System Clock Ratios
Example Frequency Ratios (MHz) Divider Ratio VCO:SCLK SCLK 10:1
Table Booting Modes
BMODE2-0 Description Execute from 16-bit external memory (bypass boot ROM) Boot from 8-bit 16-bit memory (EPROM/flash) Reserved Boot from serial memory (EEPROM/flash) Boot from host (slave mode) Boot from serial memory (EEPROM/flash) Boot from host (slave mode) Boot from UART host (slave mode)
Signal Name SSEL3-0 0001 0110 1010
BMODE pins reset configuration register, sampled during power-on resets software-initiated resets, implement following modes: Execute from 16-bit external memory Execution starts from address 0x2000 0000 with 16-bit packing. boot bypassed this mode. configuration settings slowest device possible (3-cycle hold time; 15-cycle access times; 4-cycle setup). Boot from 8-bit 16-bit external flash memory 8-bit 16-bit flash boot routine located Boot memory space using asynchronous memory bank configuration settings slowest device possible (3-cycle hold time; 15-cycle access times; 4-cycle setup). Boot evaluates first byte boot stream address 0x2000 0000. 0x40, 8-bit boot performed. 0x60 byte assumes 16-bit memory device performs 8-bit DMA. 0x20 byte also assumes 16-bit memory performs 16-bit DMA. Boot from serial memory (EEPROM flash) 16-, 24-bit addressable devices supported well AT45DB041, AT45DB081, AT45DB161, AT45DB321, AT45DB642, AT45DB1282 DataFlash® devices from Atmel. uses PF10/SPI SSEL1 output select single EEPROM/flash device, submits read command successive address bytes (0x00) until valid 16-, 24-bit, Atmel addressable device detected, begins clocking data into processor. Boot from host device Blackfin processor operates slave mode configured receive bytes .LDR file from host (master) agent. hold host device from transmitting while boot busy, Blackfin processor asserts GPIO pin, called host wait (HWAIT), signal host device send more bytes until flag deasserted. flag chosen user this information transferred Blackfin processor bits 10:5 FLAG header. Boot from UART Using autobaud handshake sequence, boot-stream-formatted program downloaded host. host agent selects baud rate within UART's clocking capabilities. When performing autobaud, UART expects (boot stream) character
core clock (CCLK) frequency also dynamically changed means CSEL1-0 bits PLL_DIV register. Supported CCLK divider ratios shown Table This programmable core clock capability useful fast core frequency modifications. Table Core Clock Ratios
Example Frequency Ratios (MHz) Divider Ratio VCO:CCLK CCLK
Signal Name CSEL1-0
maximum CCLK frequency only depends part's speed grade (see Ordering Guide Page 65), also depends applied VDDINT voltage (see Table Table Table Page details). maximal system clock rate (SCLK) depends chip package applied VDDEXT voltage (see Table Page 24).
BOOTING MODES
processor mechanisms (listed Table automatically loading internal external memory after reset. seventh mode provided execute from external memory, bypassing boot sequence.
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bits data, start bit, stop bit, parity bit) determine rate. then replies with acknowledgement that composed bytes: 0xBF, value UART_DLL, value UART_DLH, 0x00. host then download boot stream. When processor needs hold host, deasserts CTS. Therefore, host must monitor this signal. Boot from serial memory (EEPROM/flash) Blackfin processor operates master mode selects slave with unique 0xA0. submits successive read commands memory device starting 2-byte internal address 0x0000 begins clocking data into processor. memory device should comply with Philips Specification version have capability auto-increment internal address counter such that contents memory device read sequentially. Boot from host host agent selects slave with unique 0x5F. processor replies with acknowledgement host then download boot stream. host agent should comply with Philips Specification version 2.1. multiplexer used select processor time when booting multiple processors from single TWI. each boot modes, 10-byte header first brought from external device. header specifies number bytes transferred memory destination address. Multiple memory blocks loaded boot sequence. Once blocks loaded, program execution commences from start instruction SRAM. addition, reset configuration register application code bypass normal boot sequence during software reset. this case, processor jumps directly beginning instruction memory. augment boot modes, secondary software loader added provide additional booting mechanisms. This secondary loader could provide capability boot from flash, variable baud rate, other sources. boot modes except bypass, program execution starts from on-chip memory address 0xFFA0 0000. assembly language, which takes advantage processor's unique architecture, offers following advantages: Seamlessly integrated DSP/MCU features optimized both 8-bit 16-bit operations. multi-issue load/store modified-Harvard architecture, which supports 16-bit four 8-bit load/store pointer updates cycle. registers, I/O, memory mapped into unified byte memory space, providing simplified programming model. Microcontroller features, such arbitrary bit-field manipulation, insertion, extraction; integer operations 16-, 32-bit data-types; separate user supervisor stack pointers. Code density enhancements, which include intermixing 16-bit 32-bit instructions mode switching, code segregation). Frequently used instructions encoded bits.
DEVELOPMENT TOOLS
Blackfin processors supported with complete CROSSCORE® software hardware development tools, including Analog Devices emulators VisualDSP++® development environment. same emulator hardware that supports other Analog Devices processors also fully emulates Blackfin processor family. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy assembler that based algebraic syntax, archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ runtime library that includes mathematical functions. point these tools C/C++ code efficiency. compiler been developed efficient translation C/C++ code Blackfin assembly. Blackfin processor architectural features that improve efficiency compiled C/C++ code. VisualDSP++ debugger number important features. Data visualization enhanced plotting package that offers significant level flexibility. This graphical representation user data enables programmer quickly determine performance algorithm. algorithms grow complexity, this capability have increasing significance designer's development schedule, increasing productivity. Statistical profiling enables programmer nonintrusively poll processor running program. This feature, unique VisualDSP++, enables software developer passively gather important code execution metrics without interrupting real-time characteristics program. Essentially, developer identify bottlenecks software quickly
INSTRUCTION DESCRIPTION
Blackfin processor family assembly language instruction employs algebraic syntax designed ease coding readability. instructions have been specifically tuned provide flexible, densely encoded instruction that compiles very small final memory size. instruction also provides fully featured multifunction instructions that allow programmer many processor core resources single instruction. Coupled with many features more often seen microcontrollers, this instruction very efficient when compiling source code. addition, architecture supports both user (algorithm/application code) supervisor (O/S kernel, device drivers, debuggers, ISRs) modes operation, allowing multiple levels access core processor resources.
CROSSCORE registered trademark Analog Devices, Inc. VisualDSP++ registered trademark Analog Devices, Inc.
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efficiently. using profiler, programmer focus those areas program that impact performance take corrective action. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers View mixed C/C++ assembly code (interleaved source object information). Insert breakpoints. conditional breakpoints registers, memory, stacks. Trace instruction execution. Perform linear statistical profiling program execution. Fill, dump, graphically plot contents memory. Perform source level debugging. Create custom debugger windows. VisualDSP++ lets programmers define manage software development. dialog boxes property pages programmers configure manage development tools, including color syntax highlighting VisualDSP++ editor. These capabilities permit programmers Control development tools process inputs generate outputs. Maintain one-to-one correspondence with tool's command line switches. VisualDSP++ Kernel (VDK) incorporates scheduling resource management tailored specifically address memory timing constraints embedded, real-time programming. These capabilities enable engineers develop code more effectively, eliminating need start from very beginning when developing application code. features include threads, critical unscheduled regions, semaphores, events, device flags. also supports priority-based, pre-emptive, cooperative, time-sliced scheduling approaches. addition, designed scalable. application does specific feature, support code that feature excluded from target system. Because library, developer decide whether not. integrated into VisualDSP++ development environment, also used with standard command line tools. When used, development environment assists developer with many error prone tasks assists managing system resources, automating generation various VDK-based objects, visualizing system state when debugging application that uses VDK. expert linker used visually manipulate placement code data embedded system. Memory utilization viewed color-coded graphical form. Code data easily moved different areas processor external memory with drag mouse. Runtime stack heap usage examined. expert linker fully compatible with existing linker definition file (LDF), allowing developer move between graphical textual environments. Analog Devices emulators IEEE 1149.1 JTAG test access port Blackfin monitor control target board processor during emulation. emulator provides full-speed emulation, allowing inspection modification memory, registers, processor stacks. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting Blackfin processor family. Third party software tools include libraries, real-time operating systems, block diagram design tools.
EZ-KIT Lite® Evaluation Board
evaluation processors, ADSP-BF537 EZ-KIT Lite board available from Analog Devices. Order part number ADDS-BF537-EZLITE. board comes with on-chip emulation capabilities equipped enable software development. Multiple daughter cards available.
DESIGNING EMULATOR-COMPATIBLE PROCESSOR BOARD
Analog Devices family emulators tools that every system developer needs order test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG processor. emulator uses access internal features processor, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. processor must halted send data commands, once operation been completed emulator, processor system running full speed with impact system timing. these emulators, target board must include header that connects processor's JTAG port emulator. details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, Analog Devices JTAG Emulation Technical Reference (EE-68) Analog Devices website under www.analog.com/ee-notes. This document updated regularly keep pace with improvements emulator support.
RELATED DOCUMENTS
following publications that describe ADSP-BF534/ ADSP-BF536/ADSP-BF537 processors (and related processors) ordered from Analog Devices sales office accessed electronically website: Getting Started with Blackfin Processors ADSP-BF537 Blackfin Processor Hardware Reference ADSP-BF53x/ADSP-BF56x Blackfin Processor Programming Reference Blackfin Processor Anomaly List
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DESCRIPTIONS
processors definitions listed Table order maintain maximum functionality reduce package size count, some pins have dual, multiplexed functions. cases where function reconfigurable, default state shown plain text, while alternate function shown italics. Pins shown with asterisk after their name offer high source/high sink current capabilities. pins three-stated during immediately after reset, with exception external memory interface, asynchronous synchronous memory control, buffered XTAL output (CLKBUF). external memory interface, Table Descriptions
Name Memory Interface ADDR19-1 DATA15-0 ABE1-0/SDQM1-0 Asynchronous Memory Control AMS3-0 ARDY Synchronous Memory Control SRAS SCAS SCKE CLKOUT SA10 Type Function Address Async Access Data Async/Sync Access Byte Enables/Data Masks Async/Sync Access Request (This should pulled high when used.) Grant Grant Hang Bank Select Hardware Ready Control Output Enable Read Enable Write Enable Address Strobe Column Address Strobe Write Enable Clock Enable (This three-stated during hibernate.) Clock Output Bank Select Driver Type1
control address lines driven high, with exception CLKOUT, which toggles system clock rate. however asserted, then memory pins also threestated. pins have their input buffers disabled with exception pins noted data sheet that need pull-ups pulldowns unused. (serial data) (serial clock) pins open drain therefore require pull-up resistor. Consult version specification proper resistor value.
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Table Descriptions (Continued)
Name Port GPIO/UART1-0/Timer7-0/SPI/ External Request/PPI High Source/High Sink Pin) PF0* GPIO/UART0 TX/DMAR0 PF1* GPIO/UART0 RX/DMAR1/TACI1 PF2* GPIO/UART1 TX/TMR7 PF3* GPIO/UART1 RX/TMR6/TACI6 PF4* GPIO/TMR5/SPI SSEL6 PF5* GPIO/TMR4/SPI SSEL5 PF6* GPIO/TMR3/SPI SSEL4 PF7* GPIO/TMR2/PPI GPIO/TMR1/PPI GPIO/TMR0/PPI PF10 GPIO/SPI SSEL1 PF11 GPIO/SPI MOSI PF12 GPIO/SPI MISO PF13 GPIO/SPI PF14 GPIO/SPI SS/TACLK0 PF15 GPIO/PPI CLK/TMRCLK Port GPIO/PPI/SPORT1 GPIO/PPI GPIO/PPI GPIO/PPI GPIO/PPI GPIO/PPI GPIO/PPI GPIO/PPI GPIO/PPI GPIO/PPI D8/DR1SEC GPIO/PPI D9/DT1SEC PG10 GPIO/PPI D10/RSCLK1 PG11 GPIO/PPI D11/RFS1 PG12 GPIO/PPI D12/DR1PRI PG13 GPIO/PPI D13/TSCLK1 PG14 GPIO/PPI D14/TFS1 PG15 GPIO/PPI D15/DT1PRI Type Function Driver Type1
GPIO/UART0 Transmit/DMA Request GPIO/UART0 Receive/DMA Request 1/Timer1 Alternate Input Capture GPIO/UART1 Transmit/Timer7 GPIO/UART1 Receive/Timer6/Timer6 Alternate Input Capture GPIO/Timer5/SPI Slave Select Enable GPIO/Timer4/SPI Slave Select Enable GPIO/Timer3/SPI Slave Select Enable GPIO/Timer2/PPI Frame Sync GPIO/Timer1/PPI Frame Sync GPIO/Timer0/PPI Frame Sync GPIO/SPI Slave Select Enable GPIO/SPI Master Slave GPIO/SPI Master Slave (This should pulled high through resistor booting port.) GPIO/SPI Clock GPIO/SPI Slave Select/Alternate Timer0 Clock Input GPIO/PPI Clock/External Timer Reference GPIO/PPI Data GPIO/PPI Data GPIO/PPI Data GPIO/PPI Data GPIO/PPI Data GPIO/PPI Data GPIO/PPI Data GPIO/PPI Data GPIO/PPI Data 8/SPORT1 Receive Data Secondary GPIO/PPI Data 9/SPORT1 Transmit Data Secondary GPIO/PPI Data 10/SPORT1 Receive Serial Clock GPIO/PPI Data 11/SPORT1 Receive Frame Sync GPIO/PPI Data 12/SPORT1 Receive Data Primary GPIO/PPI Data 13/SPORT1 Transmit Serial Clock GPIO/PPI Data 14/SPORT1 Transmit Frame Sync GPIO/PPI Data 15/SPORT1 Transmit Data Primary
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Table Descriptions (Continued)
Name Port GPIO/10/100 Ethernet ADSP-BF534, these pins GPIO only) GPIO/ETxD0 GPIO/ETxD1 GPIO/ETxD2 GPIO/ETxD3 GPIO/ETxEN GPIO/MII TxCLK/RMII REF_CLK GPIO/MII PHYINT/RMII MDINT GPIO/COL GPIO/ERxD0 GPIO/ERxD1 PH10 GPIO/ERxD2 PH11 GPIO/ERxD3 PH12 GPIO/ERxDV/TACLK5 PH13 GPIO/ERxCLK/TACLK6 PH14 GPIO/ERxER/TACLK7 PH15 GPIO/MII CRS/RMII CRS_DV Port SPORT0/TWI/SPI Select/CAN MDIO DR0SEC/CANRX/TACI0 DT0SEC/CANTX/SPI SSEL7 RSCLK0/TACLK2 RFS0/TACLK3 DR0PRI/TACLK4 TSCLK0/TACLK1 PJ10 TFS0/SPI SSEL3 PJ11 DT0PRI/SPI SSEL2 Real-Time Clock RTXI RTXO Type Function Driver Type1
GPIO/Ethernet RMII Transmit GPIO/Ethernet RMII Transmit GPIO/Ethernet Transmit GPIO/Ethernet Transmit GPIO/Ethernet RMII Transmit Enable GPIO/Ethernet Transmit Clock/RMII Reference Clock GPIO/Ethernet Interrupt/RMII Management Data Interrupt (This should pulled high when used hibernate wake-up.) GPIO/Ethernet Collision GPIO/Ethernet RMII Receive GPIO/Ethernet RMII Receive GPIO/Ethernet Receive GPIO/Ethernet Receive GPIO/Ethernet Receive Data Valid/Alternate Timer5 Input Clock GPIO/Ethernet Receive Clock/Alternate Timer6 Input Clock GPIO/Ethernet RMII Receive Error/Alternate Timer7 Input Clock GPIO/Ethernet Carrier Sense/Ethernet RMII Carrier Sense Receive Data Valid
Ethernet Management Channel Clock ADSP-BF534 processors, connect this pin.) Ethernet Management Channel Serial Data ADSP-BF534 processors, this ground.) Serial Clock (This open-drain output requires pull-up resistor.) Serial Data (This open-drain output requires pull-up resistor.) SPORT0 Receive Data Secondary/CAN Receive/Timer0 Alternate Input Capture SPORT0 Transmit Data Secondary/CAN Transmit/SPI Slave Select Enable SPORT0 Receive Serial Clock/Alternate Timer2 Clock Input SPORT0 Receive Frame Sync/Alternate Timer3 Clock Input SPORT0 Receive Data Primary/Alternate Timer4 Clock Input SPORT0 Transmit Serial Clock/Alternate Timer1 Clock Input SPORT0 Transmit Frame Sync/SPI Slave Select Enable SPORT0 Transmit Data Primary/SPI Slave Select Enable Crystal Input (This should pulled when used.) Crystal Output
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Table Descriptions (Continued)
Name JTAG Port TRST Clock CLKIN XTAL CLKBUF Mode Controls RESET BMODE2-0 Voltage Regulator VROUT0 VROUT1 Supplies VDDEXT VDDINT VDDRTC
Type Function JTAG Clock JTAG Serial Data JTAG Serial Data JTAG Mode Select JTAG Reset (This should pulled JTAG port used.) Emulation Output Clock/Crystal Input Crystal Output Buffered XTAL Output Reset Nonmaskable Interrupt (This should pulled high when used.) Boot Mode Strap External Drive External Drive Power Supply Internal Power Supply Real-Time Clock Power Supply External Ground
Driver Type1
Output Drive Currents Page more information about each driver types.
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SPECIFICATIONS
Note that component specifications subject change without notice.
OPERATING CONDITIONS
Parameter VDDINT Internal Supply Voltage1 VDDINT VDDINT VDDINT VDDEXT VDDEXT VDDRTC VIHCLKIN VIH5V VIH5V VIL5V VIL5V
Internal Supply Voltage1 Internal Supply Voltage1 Internal Supply Voltage1 External Supply Voltage External Supply Voltage Real-Time Clock Power Supply Voltage High Level Input Voltage3, High Level Input Voltage5 Tolerant Pins, High Level Input Voltage6 Tolerant Pins, High Level Input Voltage7 Level Input Voltage3, Tolerant Pins, Level Input Voltage6 Tolerant Pins, Level Input Voltage7 Junction Temperature Junction Temperature Junction Temperature Junction Temperature Junction Temperature
Conditions automotive MHz, MHz, speed grade models2 automotive speed grade models2 automotive speed grade models2 Automotive grade models +105°C automotive grade models2 automotive grade models2 Automotive grade models +105°C automotive grade models2
0.95 2.25 2.25
Nominal 1.25
1.32 1.375 1.43 1.32 +0.6 VDDEXT +0.8 +120 +105 +105 +100
Unit
VDDEXT Maximum VDDEXT Maximum
VDDEXT -0.3 -0.3 -0.3
VDDEXT Maximum VDDEXT Minimum
VDDEXT Minimum 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) TAMBIENT -40°C +105°C 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) TAMBIENT -40°C +85°C 208-Ball Chip Scale Package Ball Grid Array (CSP_BGA) TAMBIENT +70°C 182-Ball Chip Scale Package Ball Grid Array (CSP_BGA) TAMBIENT -40°C +85°C 182-Ball Chip Scale Package Ball Grid Array (CSP_BGA) TAMBIENT +70°C
regulator generate VDDINT levels 0.85 with +10% tolerance, 1.25 with +10% tolerance, with +10% tolerance. required VDDINT function speed grade operating frequency. Table Table Table details. Ordering Guide Page Bidirectional pins (DATA15-0, PF15-0, PG15-0, PH15-0, TFS0, TSCLK0, RSCLK0, RFS0, MDIO) input pins (BR, ARDY, DR0PRI, DR0SEC, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, BMODE2-0) V-tolerant (always accept maximum VIH). Voltage compliance outputs, VOH) limited VDDEXT supply voltage. Parameter value applies input bidirectional pins except CLKIN, SDA, SCL. Parameter value applies CLKIN only. Applies pins PJ2/SCL PJ3/SDA which tolerant (always accept maximum VIH). Voltage compliance outputs, VOH) limited VDDEXT supply voltage. Applies PJ4/DR0SEC/CANRX/TACI0 which tolerant (always accepts maximum VIH). Voltage compliance outputs, VOH) limited VDDEXT supply voltage. Parameter value applies input bidirectional pins except SCL.
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Table through Table describe voltage/frequency requirements processor clocks. Take care selecting MSEL, SSEL, CSEL ratios exceed maximum core clock system clock. Table describes phase-locked loop operating conditions.
Table Core Clock Requirements-500 MHz, MHz, Speed Grades1
Parameter fCCLK Core Clock Frequency (VDDINT =1.30 Minimum)2 fCCLK Core Clock Frequency (VDDINT 1.20 Minimum)3 fCCLK Core Clock Frequency (VDDINT =1.14 Minimum) Core Clock Frequency (VDDINT =1.045 Minimum) fCCLK fCCLK Core Clock Frequency (VDDINT 0.95 Minimum) fCCLK Core Clock Frequency (VDDINT 0.85 Minimum) fCCLK Core Clock Frequency (VDDINT Minimum)
Internal Regulator Setting 1.30 1.25 1.20 1.10 1.00 0.90 0.85
Unit
Ordering Guide Page Applies models only. Ordering Guide Page Applies models only. Ordering Guide Page
Table Core Clock Requirements-400 Speed Grade1
120°C 105°C Internal Regulator Setting 1.20 1.10 1.00 0.90 0.85 All2 Other
Parameter fCCLK Core Clock Frequency (VDDINT =1.14 Minimum) fCCLK Core Clock Frequency (VDDINT =1.045 Minimum) fCCLK Core Clock Frequency (VDDINT 0.95 Minimum) fCCLK Core Clock Frequency (VDDINT 0.85 Minimum) fCCLK Core Clock Frequency (VDDINT Minimum)
Unit
Ordering Guide Page Operating Conditions Page
Table Core Clock Requirements-300 Speed Grade1
Parameter fCCLK Core Clock Frequency (VDDINT =1.14 Minimum) fCCLK Core Clock Frequency (VDDINT =1.045 Minimum) fCCLK Core Clock Frequency (VDDINT 0.95 Minimum) Core Clock Frequency (VDDINT 0.85 Minimum) fCCLK fCCLK Core Clock Frequency (VDDINT Minimum)
Internal Regulator Setting 1.20 1.10 1.00 0.90 0.85
Unit
Ordering Guide Page
Table Phase-Locked Loop Operating Conditions
Parameter fVCO
Voltage Controlled Oscillator (VCO) Frequency
Speed Grade1
Unit
Ordering Guide Page
Table System Clock Requirements
Parameter fSCLK1 fSCLK1
Condition VDDEXT VDDINT 1.14 VDDEXT VDDINT 1.14
1332
Unit
fSCLK must less than equal fCCLK subject additional restrictions SDRAM interface operation. Table Page Rounded number. Actual test specification SCLK period Table Page
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ELECTRICAL CHARACTERISTICS
MHz/400 MHz1 Parameter Test Conditions High Level VDDEXT V/3.0 VDDEXT Output Voltage 10%, -0.5 VOH4 VDDEXT VDDEXT 10%, VDDEXT V/3.0 10%, VDDEXT VDDEXT V/3.0 VDDEXT 10%, -2.0 IOH6 IOH7 VOL3 VOL4 High Level VDDEXT Output Current VDDEXT Level VDDEXT V/3.0 Output Voltage 10%, VDDEXT 10%, VDDEXT V/3.0 10%, VDDEXT V/3.0 10%, Level Output Current High Level Input VDDEXT =3.6 Current8 High Level Input VDDEXT =3.6 Current9 Level Input VDDEXT =3.6 Current2 High Level Input VDDEXT Current JTAG10 Three-State VDDEXT Leakage Current11 Three-State VDDEXT =3.6 Leakage Current12 Three-State VDDEXT Leakage Current5 Input MHz, TAMBIENT 25°C, Capacitance13, -144 MHz/533 MHz/600 MHz2 VDDEXT VDDEXT VDDEXT VDDEXT -144
Unit
VOL5 IOL6 IOL7 IIH5V IIHP IOZH
IOZH5V
IOZL
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Parameter IDDDEEPSLEEP15 VDDINT Current Deep Sleep Mode IDDSLEEP VDDINT Current Sleep Mode IDD-IDLE VDDINT Current Idle IDD-TYP VDDINT Current IDD-TYP IDD-TYP IDD-TYP IDDHIBERNATE15, Test Conditions VDDINT fCCLK MHz, 25°C, 0.00 MHz/400 MHz1 MHz/533 MHz/600 MHz2 Unit
IDDRTC IDDDEEPSLEEP15
IDDSLEEP15, IDDINT18
VDDINT fSCLK MHz, 25°C VDDINT fCCLK MHz, 25°C, 0.43 VDDINT 1.14 fCCLK MHz, 25°C, 1.00 VDDINT Current VDDINT 1.14 fCCLK MHz, 25°C, 1.00 VDDINT Current VDDINT 1.20 fCCLK MHz, 25°C, 1.00 VDDINT Current VDDINT 1.30 fCCLK MHz, 25°C, 1.00 VDDEXT Current VDDEXT 3.60 CLKIN=0 MHz, Hibernate State maximum, with voltage regulator (VDDINT VDDRTC Current VDDRTC 25°C VDDINT Current fCCLK MHz, fSCLK Deep Sleep Mode VDDINT Current fCCLK MHz, fSCLK Sleep Mode VDDINT Current fCCLK MHz, fSCLK
19.5
Table
Table
IDDDEEPSLEEP (0.14 VDDINT fSCLK) IDDSLEEP (Table ASF)
IDDDEEPSLEEP (0.14 VDDINT fSCLK) IDDSLEEP (Table ASF)
Applies speed grade models. Ordering Guide Page Applies MHz, MHz, speed grade models. Ordering Guide Page Applies output bidirectional pins except port pins, port pins, port pins. Applies port pins PF7-0. Applies port pins PF15-8, port pins, port pins. Maximum combined current Port F7-0. Maximum total current port port port pins. Applies input pins except PJ4. Applies input only. Applies JTAG input pins (TCK, TDI, TMS, TRST). Applies three-statable pins. Applies bidirectional pins PJ3. Applies signal pins. Guaranteed, tested. ADSP-BF537 Blackfin Processor Hardware Reference Manual definition sleep, deep sleep, hibernate operating modes. CLKIN must tied VDDEXT during hibernate. equations, fSCLK parameter system clock MHz. Table list IDDINT power vectors covered.
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System designers should refer Estimating Power ADSP-BF534/BF536/BF537 Blackfin Processors (EE-297), which provides detailed information optimizing designs lowest power. topics discussed this section described detail EE-297. Total power dissipation components: Static, including leakage current Dynamic, transistor switching characteristics Many operating conditions also affect power dissipation, including temperature, voltage, operating frequency, processor activity. Electrical Characteristics Page shows current dissipation internal circuitry (VDDINT). IDDDEEPSLEEP specifies static power dissipation function voltage (VDDINT) temperature (see Table Table 15), IDDINT specifies total power specification listed test conditions, including dynamic component function voltage (VDDINT) frequency (Table 18). dynamic component also subject Activity Scaling Factor (ASF) which represents application code running processor (Table 17).
Table Static Current-500 MHz, MHz, Speed Grade Devices (mA)1
(°C)
0.80 17.0 35.0 53.0 76.7 110.1 150.1 202.3 223.8
0.85 19.2 39.2 59.2 84.6 120.0 164.5 219.2 241.4
0.90 21.9 44.3 65.3 93.6 130.9 178.7 236.5 260.4
0.95 25.0 50.8 71.9 103.1 142.2 193.2 255.8 282.0
1.00 28.2 56.1 79.1 113.7 156.5 210.4 277.8 303.4
1.05 12.0 32.1 63.3 88.0 123.9 171.3 228.9 299.8 328.7
Voltage (VDDINT) 1.10 1.15 14.6 17.3 36.9 41.8 69.1 76.4 96.6 108.0 136.3 148.3 185.2 201.7 247.7 268.8 323.8 351.2 354.5 381.7
1.20 20.3 47.7 84.7 120.0 162.8 220.6 291.4 378.8 410.8
1.25 24.1 53.8 93.5 130.7 178.4 239.7 314.1 407.5 443.6
1.30 27.1 61.0 104.5 142.6 194.4 259.8 341.1 440.4 477.8
1.32 1.375 28.6 36.3 63.8 73.2 109.1 123.4 148.5 166.5 201.4 223.7 268.8 295.9 351.2 384.6 453.4 494.3 492.2 535.1
1.43 44.4 84.1 138.8 185.6 247.5 325.2 420.3 538.2 581.5
Values guaranteed maximum IDDDEEPSLEEP specifications.
Table Static Current-300 Speed Grade Devices (mA)1
(°C) 1152 1202
0.80 12.2 17.2 25.7 37.6 53.7 75.1 84.5 103.8 115.5
0.85 13.5 19.0 27.8 41.3 58.3 82.3 91.2 111.8 123.6
0.90 14.8 20.6 30.9 44.8 63.7 88.5 98.2 120.3 132.2
0.95 16.4 22.9 33.7 48.9 69.0 95.8 106.0 127.6 141.9
1.00 10.9 18.2 25.9 37.3 53.9 75.9 104.0 114.2 138.0 152.3
Voltage (VDDINT) 1.05 1.10 12.3 13.8 19.9 22.7 28.2 31.6 41.4 44.8 58.6 63.9 82.9 90.5 112.5 121.8 123.0 132.4 148.5 159.6 163.7 175.6
1.15 15.5 25.6 34.9 50.0 69.7 98.4 130.6 143.3 171.4 189.3
1.20 10.5 17.5 28.4 38.9 54.8 76.9 106.4 141.3 155.0 184.6 202.8
1.25 12.5 19.6 31.8 42.9 59.4 84.0 115.3 153.2 167.4 198.8 217.7
1.30 13.9 21.7 35.7 47.6 66.1 92.2 124.6 164.8 179.8 213.4 232.3
1.32 14.8 23.1 37.2 49.5 68.4 94.9 128.1 169.7 185.4 219.6 238.6
Values guaranteed maximum IDDDEEPSLEEP specifications. Applies automotive grade models only.
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Table Activity Scaling Factors
IDDINT Power Vector1 IDD-PEAK IDD-HIGH IDD-TYP IDD-APP IDD-NOP IDD-IDLE
Activity Scaling Factor (ASF)2 1.33 1.29 1.00 0.88 0.72 0.43
EE-297 power vector definitions. values determined using 10:1 CCLK:SCLK ratio.
Table Dynamic Current (mA, with 1.0)1
Voltage (VDDINT) Frequency 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.32 1.375 1.43 (MHz) 11.0 13.7 19.13 18.2 18.67 19.13 19.6 21.2 24.1 25.5 28.5 28.6 28.85 29.2 27.9 22.7 30.8 28.4 29.3 30.8 32.9 35.3 37.8 40.6 43.5 43.7 44.1 45.8 36.9 42.6 55.0 49.2 51.5 55.0 58.3 62.9 67.0 69.7 73.0 74.0 75.7 80.7 61.5 79.2 70.4 74.6 79.2 84.4 90.7 94.3 99.1 103.9 105.5 108.0 113.4 92.4 97.2 104.3 109.8 116.5 121.9 128.0 134.6 136.6 139.8 145.1 142.3 149.3 157.5 164.7 166.7 169.8 176.9 158.6 167.0 174.3 176.6 180.1 187.9 193.7 196.5 200.7 210.0
values guaranteed stand-alone maximum specifications, they must combined with static current equations Electrical Characteristics Page
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ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed Table cause permanent damage device. These stress ratings only. Functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Table Absolute Maximum Ratings
Parameter Internal (Core) Supply Voltage (VDDINT) External (I/O) Supply Voltage (VDDEXT) Input Voltage1 Input Voltage1, Output Voltage Swing Load Capacitance3 Storage Temperature Range Junction Temperature Underbias
PACKAGE INFORMATION
information presented Figure Table provide details about package branding Blackfin processors. complete listing product availability, Ordering Guide Page
ADSP-BF5xx tppZccc vvvvvv.x #yyww country_of_origin
Rating -0.3 +1.43 -0.3 +3.8 -0.5 +3.6 -0.5 +5.5 -0.5 VDDEXT -65°C +150°C +125°C
Figure Product Information Package
Table Package Brand Information
Brand vvvvvv.x yyww Field Description Temperature Range Package Type RoHS Compliant Designation Ordering Guide Assembly Code Silicon Revision RoHS Compliant Designation Date Code
Applies only when VDDEXT within specifications. When VDDEXT outside specifications, range VDDEXT Applies tolerant pins SCL, SDA, PJ4. duty cycles, Table proper SDRAM controller operation, maximum load capacitance ADDR19-1, DATA15-0, ABE1-0/SDQM1-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, SMS.
Table Maximum Duty Cycle Input1 Transient Voltage
-0.50 -0.70 -0.80 -0.90 -1.00
(V)2 +3.80 +4.00 +4.10 +4.20 +4.30
Maximum Duty Cycle 100%
Applies signal pins with exception CLKIN, XTAL, VROUT1-0. Only listed options apply particular design.
SENSITIVITY
(electrostatic discharge) sensitive device.
Charged devices circuit boards discharge without detection. Although this product features patented proprietary protection circuitry, damage occur devices subjected high energy ESD. Therefore, proper precautions should taken avoid performance degradation loss functionality.
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TIMING SPECIFICATIONS
Clock Reset Timing
Table Clock Input Reset Timing
Parameter Timing Requirements tCKIN CLKIN Period1, tCKINL CLKIN Pulse CLKIN High Pulse tCKINH tBUFDLAY CLKIN CLKBUF Delay tWRST RESET Asserted Pulse Width Low5 tNOBOOT RESET Deassertion First External Access Delay6
20.0 tCKIN tCKIN
100.0
Unit
tCKIN
Combinations CLKIN frequency clock multiplier must exceed allowed fVCO, fCCLK, fSCLK settings discussed Table through Table Since default multiplying CLKIN frequency speed grade parts full CLKIN period range. Applies bypass mode bypass mode. CLKIN frequency must change fly. PLL_CTL register set, then maximum tCKIN period Applies after power-up sequence complete. power-up, processor's internal phase-locked loop requires more than 2000 CLKIN cycles while RESET asserted, assuming stable power supplies CLKIN (not including start-up time external clock oscillator). Applies when processor configured Boot Mode (BMODE2-0 b#000).
CKIN
CLKIN
CKINL
CKINH
BUFDLAY
BUFDLAY
CLKBUF
WRST
RESET
NOBOOT
Figure Clock Reset Timing
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Asynchronous Memory Read Cycle Timing
Table Asynchronous Memory Read Cycle Timing
Parameter Timing Requirements tSDAT DATA15-0 Setup Before CLKOUT tHDAT DATA15-0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics Output Delay After CLKOUT1 Output Hold After CLKOUT
Unit
Output pins include AMS3-0, ABE1-0, ADDR19-1, AOE, ARE.
SETUP CYCLES
PROGRAMMED READ ACCESS CYCLES
ACCESS EXTENDED CYCLES
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ADDRESS
tSARDY
ARDY
tHARDY tHARDY
tSARDY
tSDAT tHDAT
DATA15-0
READ
Figure Asynchronous Memory Read Cycle Timing
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Asynchronous Memory Write Cycle Timing
Table Asynchronous Memory Write Cycle Timing
Parameter Timing Requirements tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDDAT DATA15-0 Disable After CLKOUT tENDAT DATA15-0 Enable After CLKOUT Output Delay After CLKOUT1 Output Hold After CLKOUT
Unit
Output pins include AMS3-0, ABE1-0, ADDR19-1, AOE, AWE.
SETUP CYCLES
PROGRAMMED WRITE ACCESS CYCLES
ACCESS EXTENDED CYCLE
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ADDRESS
SARDY
ARDY
HARDY
tSARDY ENDAT
DATA15-0 WRITE DATA
DDAT
Figure Asynchronous Memory Write Cycle Timing
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External Port Request Grant Cycle Timing
Table Figure describe external port request grant operations. Table External Port Request Grant Cycle Timing
Parameter1, Timing Requirements Asserted CLKOUT Setup CLKOUT Deasserted Hold Time Switching Characteristics CLKOUT AMSx, Address, ARE/AWE Disable CLKOUT AMSx, Address, ARE/AWE Enable tDBG CLKOUT High Asserted Setup tEBG CLKOUT High Deasserted Hold Time tDBH CLKOUT High Asserted Setup tEBH CLKOUT High Deasserted Hold Time
Unit
These timing parameters based worst-case operating conditions. loads these timing parameters
CLKOUT
AMSx
ADDR19-1 ABE1-0
tDBG
tEBG
tDBH
tEBH
Figure External Port Request Grant Cycle Timing
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SDRAM Interface Timing
Table SDRAM Interface Timing
Parameter Timing Requirements tSSDAT DATA15-0 Setup Before CLKOUT tHSDAT DATA15-0 Hold After CLKOUT Switching Characteristics tDCAD COMMAND1, ADDR19-1, DATA15-0 Delay After CLKOUT tHCAD COMMAND1, ADDR19-1, DATA15-0 Hold After CLKOUT tDSDAT DATA15-0 Disable After CLKOUT DATA15-0 Enable After CLKOUT tENSDAT tSCLK2 CLKOUT Period when +105°C tSCLK CLKOUT Period when +105°C tSCLKH CLKOUT Width High tSCLKL CLKOUT Width
Unit
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. These limits specific SDRAM interface only. addition, CLKOUT must always comply with limits Table Page
tSCLK
CLKOUT
tSCLKH
tSSDAT tHSDAT
DATA15-0 (IN)
tSCLKL
tDCAD tENSDAT
DATA15-0 (OUT)
tDSDAT tHCAD
tDCAD
COMMAND ADDR19-1 (OUT)
tHCAD
NOTE: COMMAND SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure SDRAM Interface Timing
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External Request Timing
Table Figure describe external request operations. Table External Request Timing
Parameter Timing Requirements DMARx Asserted CLKOUT High Setup CLKOUT High DMARx Deasserted Hold Time tDMARACT DMARx Active Pulse Width tDMARINACT DMARx Inactive Pulse Width tSCLK 1.75 tSCLK Unit
CLKOUT
DMAR0/1 (ACTIVE LOW)
tDMARINACT
tDMARACT
DMAR0/1 (ACTIVE HIGH)
tDMARACT
tDMARINACT
Figure External Request Timing
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Parallel Peripheral Interface Timing
Table Figure Page Figure Page Figure Page describe parallel peripheral interface operations. Table Parallel Peripheral Interface Timing
Parameter Timing Requirements PPI_CLK Width1 tPCLKW tPCLK PPI_CLK Period1 Timing Requirements-GP Input Frame Capture Modes tSFSPE External Frame Sync Setup Before PPI_CLK (Nonsampling Edge Sampling Edge tHFSPE External Frame Sync Hold After PPI_CLK tSDRPE Receive Data Setup Before PPI_CLK tHDRPE Receive Data Hold After PPI_CLK Switching Characteristics-GP Output Frame Capture Modes tDFSPE Internal Frame Sync Delay After PPI_CLK tHOFSPE Internal Frame Sync Hold After PPI_CLK tDDTPE Transmit Data Delay After PPI_CLK tHDTPE Transmit Data Hold After PPI_CLK
15.0
Unit
PPI_CLK frequency cannot exceed fSCLK/2.
FRAME SYNC DRIVEN POLC PPI_CLK
DATA0 SAMPLED
PPI_CLK POLC tHOFSPE POLS PPI_FS1 POLS
DFSPE
POLS PPI_FS2 POLS tSDRPE tHDRPE
PPI_DATA
Figure Mode with Internal Frame Sync Timing
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DATA0 SAMPLED PPI_CLK POLC PPI_CLK POLC
DATA1 SAMPLED
tSFSPE POLS PPI_FS1 POLS
tHFSPE
POLS PPI_FS2 POLS tSDRPE PPI_DATA tHDRPE
Figure Mode with External Frame Sync Timing
FRAME SYNC DRIVEN
DATA0 DRIVEN
PPI_CLK POLC PPI_CLK POLC POLS PPI_FS1 POLS
HOFSPE DFSPE
POLS PPI_FS2 POLS
DDTPE
HDTPE
PPI_DATA
DATA0
Figure Mode with Internal Frame Sync Timing
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DATA DRIVING/ FRAME SYNC SAMPLING EDGE PPI_CLK POLC PPI_CLK POLC tHFSPE tSFSPE POLS PPI_FS1 POLS DATA DRIVING/ FRAME SYNC SAMPLING EDGE
POLS PPI_FS2 POLS tDDTPE PPI_DATA
HDTPE
Figure Mode with External Frame Sync Timing
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Serial Ports
Table through Table Page Figure Page through Figure Page describe serial port operations. Table Serial Ports-External Clock
Parameter Timing Requirements tSFSE TFSx/RFSx Setup Before TSCLKx/RSCLKx1 tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx1 tSDRE Receive Data Setup Before RSCLKx1 tSCLKEW TSCLKx/RSCLKx Width TSCLKx/RSCLKx Period tSCLKE Switching Characteristics tDFSE tHOFSE tDDTE tHDTE
15.0
Unit 15.0
TFSx/RFSx Delay After TSCLKx/RSCLK (Internally Generated TFSx/RFSx)2 TFSx/RFSx Hold After TSCLKx/RSCLK (Internally Generated TFSx/RFSx)2 Transmit Data Delay After TSCLKx2 Transmit Data Hold After TSCLKx2
10.0 10.0
Referenced sample edge. Referenced drive edge.
Table Serial Ports-Internal Clock
2.25 VDDEXT 2.70 0.80 VDDINT 0.95 -1.5 -1.5 -1.0 -1.0 -1.0 -1.0 2.70 VDDEXT 3.60 0.95 VDDINT 1.43 -1.5 -1.5
Parameter Timing Requirements tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx4 tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx4 Receive Data Setup Before RSCLKx4 tSDRI tHDRI Receive Data Hold After RSCLKx4 Switching Characteristics tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)5 tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)5 tDDTI Transmit Data Delay After TSCLKx5 tHDTI Transmit Data Hold After TSCLKx5 tSCLKIW TSCLKx/RSCLKx Width
Unit
Applies automotive-grade devices when operated within either these voltage ranges. Applies automotive-grade devices when operated within these voltage ranges. automotive-grade devices within these specifications. Referenced sample edge. Referenced drive edge.
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Table Serial Ports-Enable Three-State
Parameter Switching Characteristics tDTENE Data Enable Delay from External TSCLKx1 Data Disable Delay from External TSCLKx1 tDDTTE tDTENI Data Enable Delay from Internal TSCLKx1 tDDTTI Data Disable Delay from Internal TSCLKx1
Unit
10.0 -2.0
Referenced drive edge.
Table External Late Frame Sync
Parameter Switching Characteristics Data Delay from Late External TFSx External RFSx with tDDTLFSE tDTENLFS Data Enable from Late
10.0
Unit
TFSx enable TFSx valid follow tDDTENFS tDDTLFS. external RFSx/TFSx setup RSCLKx/TSCLKx tSCLKE/2, then tDDTE/I tDTENE/I apply, otherwise tDDTLFSE tDTENLFS apply.
DATA RECEIVE-INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
DATA RECEIVE-EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
RSCLKx RSCLKx
tSCLKEW
tDFSI tHOFSI
RFSx
tDFSE tSFSI tHFSI
RFSx
tHOFSE
tSFSE
tHFSE
tSDRI
tHDRI
tSDRE
tHDRE
NOTE: EITHER RISING EDGE FALLING EDGE RSCLKx TSCLKx USED ACTIVE SAMPLING EDGE. DATA TRANSMIT-INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT-EXTERNAL CLOCK DRIVE EDGE
SAMPLE EDGE
SAMPLE EDGE
tSCLKIW
TSCLKx TSCLKx
tSCLKEW
tDFSI tHOFSI
TFSx
tDFSE tSFSI tHFSI
TFSx
tHOFSE
tSFSE
tHFSE
tDDTI tHDTI
tDDTE tHDTE
NOTE: EITHER RISING EDGE FALLING EDGE RSCLKx TSCLKx USED ACTIVE SAMPLING EDGE.
Figure Serial Ports
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EXTERNAL WITH DRIVE RSCLKx SAMPLE DRIVE
tSFSE/I
tHOFSE/I
RFSx
tDTENLFS
tDDTTE/I tDTENE/
tDDTLFSE
LATE EXTERNAL DRIVE TSCLKx SAMPLE DRIVE
tSFSE/I
tHOFSE/I
TFSx
tDTENLFS
tDDTTE/I tDTENE/I
tDDTLFSE
Figure External Late Frame Sync
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Serial Peripheral Interface Port-Master Timing
Table Figure describe port master operations. Table Serial Peripheral Interface (SPI) Port-Master Timing
2.25 VDDEXT 2.70 0.80 VDDINT 0.95 -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 -1.0 -1.0 2.70 VDDEXT 3.60 0.95 VDDINT 1.43 -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 tSCLK -1.5
Parameter Timing Requirements tSSPIDM Data Input Valid Edge (Data Input Setup) tHSPIDM Sampling Edge Data Input Invalid Switching Characteristics tSDSCIM SPISELx First Edge tSPICHM Serial Clock High Period Serial Clock Period tSPICLM tSPICLK Serial Clock Period tHDSM Last Edge SPISELx High tSPITDM Sequential Transfer Delay tDDSPIDM Edge Data Valid (Data Delay) tHDSPIDM Edge Data Invalid (Data Hold)
Unit
Applies automotive-grade devices when operated within either these voltage ranges. Applies automotive-grade devices when operated within these voltage ranges. automotive-grade devices within these specifications.
SPIxSELy (OUTPUT)
tSDSCIM
SCKx (CPOL (OUTPUT)
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tSPICLM
SCKx (CPOL (OUTPUT)
tSPICHM
tHDSPIDM
MOSIx (OUTPUT) CPHA=1 MISOx (INPUT) VALID
tDDSPIDM
tSSPIDM
VALID
tHSPIDM
tHDSPIDM
MOSIx (OUTPUT) CPHA=0 MISOx (INPUT)
tDDSPIDM
tSSPIDM
VALID
tHSPIDM
VALID
Figure Serial Peripheral Interface (SPI) Port-Master Timing
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Serial Peripheral Interface Port-Slave Timing
Table Figure describe port slave operations. Table Serial Peripheral Interface (SPI) Port-Slave Timing
Parameter Timing Requirements tSPICHS Serial Clock High Period tSPICLS Serial Clock Period Serial Clock Period tSPICLK tHDS Last Edge SPISS Asserted tSPITDS Sequential Transfer Delay tSDSCI SPISS Assertion First Edge tSSPID Data Input Valid Edge (Data Input Setup) tHSPID Sampling Edge Data Input Invalid Switching Characteristics tDSOE SPISS Assertion Data Active tDSDHI SPISS Deassertion Data High Impedance tDDSPID Edge Data Valid (Data Delay) tHDSPID Edge Data Invalid (Data Hold) tSCLK -1.5 tSCLK -1.5 tSCLK tSCLK -1.5 tSCLK -1.5 tSCLK -1.5 Unit
SPIxSS (INPUT)
tSPICHS
SCKx (CPOL (INPUT)
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
SCKx (CPOL (INPUT)
tSPICLS
tSPICHS
tDDSPID tDSOE
MISOx (OUTPUT) CPHA=1 MOSIx (INPUT)
tHDSPID
tDDSPID
tDSDHI
tSSPID
VALID
tHSPID
VALID
tDSOE
MISOx (OUTPUT) CPHA=0 MOSIx (INPUT) VALID
tHDSPID
tDDSPID
tHDSPID
tDSDHI
tHSPID tSSPID
VALID
Figure Serial Peripheral Interface (SPI) Port-Slave Timing
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Universal Asynchronous Receiver-Transmitter (UART) Ports-Receive Transmit Timing
Figure describes UART ports receive transmit operations. maximum baud rate SCLK/16. shown Figure there some latency between generation internal UART interrupts external data operations. These latencies negligible data transmission rates UART.
(SAMPLE CLOCK
DATA (5-8) STOP
RECEIVE INTERNAL UART RECEIVE INTERRUPT
UART RECEIVE DATA STOP; CLEARED FIFO READ
START DATA (5-8) STOP
TRANSMIT INTERNAL UART TRANSMIT INTERRUPT UART TRANSMIT PROGRAM; CLEARED WRITE TRANSMIT
Figure UART Ports-Receive Transmit Timing
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General-Purpose Port Timing
Table Figure describe general-purpose port operations. Table General-Purpose Port Timing
Parameter Timing Requirement tWFI General-Purpose Port Input Pulse Width Switching Characteristic tGPOD General-Purpose Port Output Delay from CLKOUT tSCLK Unit
CLKOUT
tGPOD
OUTPUT
tWFI
INPUT
Figure General-Purpose Port Timing
Timer Clock Timing
Table Figure describe timer clock timing. Table Timer Clock Timing
Parameter Switching Characteristic Timer Output Update Delay After PPI_CLK High tTODP Unit
CLOCK
tTODP
TIMER OUTPUT
Figure Timer Clock Timing
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Timer Cycle Timing
Table Figure describe timer expired operations. input signal asynchronous "width capture mode" "external clock mode" absolute maximum input frequency (fSCLK/2) MHz. Table Timer Cycle Timing
2.25 VDDEXT 2.70 0.80 VDDINT 0.95 tSCLK tSCLK tSCLK 2.70 VDDEXT 3.60 0.95 VDDINT 1.43 tSCLK tSCLK (232-1) tSCLK tSCLK (232-1) tSCLK
Parameter Timing Characteristics Timer Pulse Width Input (Measured SCLK Cycles)4 Timer Pulse Width Input High (Measured SCLK Cycles)4 tTIS Timer Input Setup Time Before CLKOUT Low5 Timer Input Hold Time After CLKOUT Low5 tTIH Switching Characteristics tHTO Timer Pulse Width Output (Measured SCLK Cycles) tTOD Timer Output Update Delay After CLKOUT High
Unit
Applies automotive-grade devices when operated within either these voltage ranges. Applies automotive-grade devices when operated within these voltage ranges. automotive-grade devices within these specifications. minimum pulse widths apply TMRx signals width capture external clock modes. They also apply PF15 PPI_CLK signals output mode. Either valid setup hold time valid pulse width sufficient. There need resynchronize programmable flag inputs.
CLKOUT tTOD
TIMER OUTPUT tHTO tTIS TIMER INPUT tWH, tTIH
Figure Timer Cycle Timing
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JTAG Test Emulation Port Timing
Table Figure describe JTAG port operations. Table JTAG Port Timing
Parameter Timing Parameters tTCK Period tSTAP TDI, Setup Before High TDI, Hold After High tHTAP tSSYS System Inputs Setup Before High1 tHSYS System Inputs Hold After High1 tTRSTW TRST Pulse Width2 (Measured Cycles) Switching Characteristics tDTDO Delay From System Outputs Delay After Low3 tDSYS
Unit
System Inputs DATA15-0, ARDY, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15-0, PG15-0, PH15-0, MDIO, TCK, TRST, RESET, NMI, RTXI, BMODE2-0. maximum System Outputs DATA15-0, ADDR19-1, ABE1-0, BGH, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, MDC, MDIO, TSCLK0, TFS0, RFS0, RSCLK0, DT0PRI, DT0SEC, PF15-0, PG15-0, PH15-0, RTXO, TDO, EMU, XTAL, VROUT1-0.
tTCK
tSTAP
tHTAP
tDTDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUTS
Figure JTAG Port Timing
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10/100 Ethernet Controller Timing
Table through Table Figure through Figure describe 10/100 Ethernet controller operations. This feature only available ADSP-BF536 ADSP-BF537 processors. Table 10/100 Ethernet Controller Timing: Receive Signal
Parameter1 fERXCLK tERXCLKW tERXCLKIS tERXCLKIH
ERxCLK Frequency (fSCLK SCLK Frequency) ERxCLK Width (tERxCLK ERxCLK Period) Input Valid ERxCLK Rising Edge (Data Setup) ERxCLK Rising Edge Input Invalid (Data Hold)
None tERxCLK
fSCLK tERxCLK
Unit
inputs synchronous ERxCLK ERxD3-0, ERxDV, ERxER.
Table 10/100 Ethernet Controller Timing: Transmit Signal
Parameter1 fETXCLK tETXCLKW tETXCLKOV tETXCLKOH
ETxCLK Frequency (fSCLK SCLK Frequency) ETxCLK Width (tETXCLK ETxCLK Period) ETxCLK Rising Edge Output Valid (Data Valid) ETxCLK Rising Edge Output Invalid (Data Hold)
None tETxCLK
fSCLK tETxCLK
Unit
outputs synchronous ETxCLK ETxD3-0.
Table 10/100 Ethernet Controller Timing: RMII Receive Signal
Parameter1 fREFCLK tREFCLKW tREFCLKIS tREFCLKIH
REF_CLK Frequency (fSCLK SCLK Frequency) REF_CLK Width (tREFCLK REFCLK Period) Input Valid RMII REF_CLK Rising Edge (Data Setup) RMII REF_CLK Rising Edge Input Invalid (Data Hold)
None tREFCLK
fSCLK tREFCLK
Unit
RMII inputs synchronous RMII REF_CLK ERxD1-0, RMII CRS_DV, ERxER.
Table 10/100 Ethernet Controller Timing: RMII Transmit Signal
Parameter1 tREFCLKOV tREFCLKOH
RMII REF_CLK Rising Edge Output Valid (Data Valid) RMII REF_CLK Rising Edge Output Invalid (Data Hold)
Unit
RMII outputs synchronous RMII REF_CLK ETxD1-0.
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February 2009
Table 10/100 Ethernet Controller Timing: MII/RMII Asynchronous Signal
Parameter1, tECOLH tECOLL tECRSH tECRSL
Pulse Width High Pulse Width Pulse Width High Pulse Width
tETxCLK tERxCLK tETxCLK tERxCLK tETxCLK tETxCLK
Unit
MII/RMII asynchronous signals COL, CRS. These signals applicable both RMII modes. asynchronous input synchronized separately both ETxCLK ERxCLK, must have minimum pulse width high least times period slower clocks. asynchronous input synchronized ETxCLK, must have minimum pulse width high least times period ETxCLK.
Table 10/100 Ethernet Controller Timing: Station Management
Parameter1 tMDIOS tMDCIH tMDCOV tMDCOH
MDIO Input Valid Rising Edge (Setup) Rising Edge MDIO Input Invalid (Hold) Falling Edge MDIO Output Valid Falling Edge MDIO Output Invalid (Hold)
Unit
MDC/MDIO 2-wire serial bidirectional port controlling more external PHYs. output clock whose minimum period programmable multiple system clock SCLK. MDIO bidirectional data line.
tERXCLK
ERxCLK
tERXCLKW
ERxD3- ERxDV ERxER
tERXCLKIS
tERXCLKIH
Figure 10/100 Ethernet Controller Timing: Receive Signal
tETXCLK
TxCLK
tETXCLKW tETXCLKOH
ETxD3-0 ETxEN
tETXCLKOV
Figure 10/100 Ethernet Controller Timing: Transmit Signal
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tREFCLK
RMII_REF_CLK
tREFCLKW
ERxD1-0 ERxDV ERxER
tREFCLKIS
tREFCLKIH
Figure 10/100 Ethernet Controller Timing: RMII Receive Signal
tREFCLK
RMII REF_CLK
tREFCLKOH
ETxD1-0 ETxEN
tREFCLKOV
Figure 10/100 Ethernet Controller Timing: RMII Transmit Signal
CRS,
tECRSH tECOLH
tECRSL tECOLL
Figure 10/100 Ethernet Controller Timing: Asynchronous Signal
(OUTPUT)
tMDCOH
MDIO (OUTPUT)
tMDCOV
MDIO (INPUT)
tMDIOS
tMDCIH
Figure 10/100 Ethernet Controller Timing: Station Management
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OUTPUT DRIVE CURRENTS
Figure through Figure show typical current-voltage characteristics output drivers processors. curves represent current drive capability output drivers function output voltage. Table Page information about which driver type corresponds particular pin.
SOURCE CURRENT (mA)
95°C 2.50V 2.75V -40°C
SOURCE CURRENT (mA)
2.25V 95°C 2.50V 25°C 2.75V -40°C
-100
-150
-100
SOURCE VOLTAGE
Figure Drive Current (Low VDDEXT)
SOURCE CURRENT (mA)
SOURCE TAGE
3.0V 95°C 3.3V 25°C 3.6V 40°C
Figure Drive Current (Low VDDEXT)
-100
3.0V 95°C 3.3V 25°C 3.6V -40°C
SOURCE CURRENT (mA)
-150 -200
SOURCE VOLTAGE
-100
Figure Drive Current (High VDDEXT)
-150
2.25V 95°C 2.50V 25°C 2.75V -40°C
SOURCE CURRENT (mA)
SOURCE VOLTAGE
Figure Drive Current (High VDDEXT)
SOURCE VOLTAGE
Figure Drive Current (Low VDDEXT)
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SOURCE CURRENT (mA)
3.0V 3.3V 3.6V -40°C
SOURCE CURRENT (mA)
2.25V 2.50V 2.75V 40°C
SOURCE VOLTAGE
SOURCE TAGE
Figure Drive Current (High VDDEXT)
Figure Drive Current (Low VDDEXT)
SOURCE CURRENT (mA)
2.25V 95°C 2.50V 25°C 2.75V -40°C
SOURCE CURRENT (mA)
95°C 25°C 3.6V -40°C
SOURCE VOLTAGE
SOURCE VOLTAGE
Figure Drive Current (Low VDDEXT)
Figure Drive Current (High VDDEXT)
3.0V
SOURCE CURRENT (mA)
3.3V 3.6V -40°C
SOURCE CURRENT (mA)
2.25V 95°C 2.50V 25°C 2.75V -40°
-100
-150
SOURCE VOLTAGE
SOURCE VOLTAGE
Figure Drive Current (High VDDEXT)
Figure Drive Current (Low VDDEXT)
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Output Disable Time
3.0V 95°C 3.3V 25°C 3.6V -40°C
SOURCE CURRENT (mA)
Output pins considered disabled when they stop driving, into high impedance state, start decay from their output high voltage. time voltage decay dependent capacitive load, load current, This decay time approximated equation: DECAY output disable time tDIS difference between tDIS_MEASURED tDECAY shown Figure time tDIS_MEASURED interval from when reference signal switches when output voltage decays from measured output-high output-low voltage. time tDECAY calculated with test loads with equal
SOURCE VOLTAGE
Figure Drive Current (High VDDEXT)
TEST CONDITIONS
timing parameters appearing this data sheet were measured under conditions described this section. Figure shows measurement point measurements (other than output enable/disable). measurement point VMEAS VDDEXT/2.
REFERENCE SIGNAL
tDIS_MEASURED tDIS
(MEASURED) (MEASURED)
tENA_MEASURED tENA
VOH(MEASURED)
(MEASURED)
VTRIP (HIGH) VTRIP (LOW) (MEASURED)
(MEASURED)
INPUT OUTPUT
VMEAS
VMEAS
tDECAY
tTRIP
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING HIGH IMPEDANCE STATE
Figure Voltage Reference Levels Measurements (Except Output Enable/Disable)
Output Enable Time
Output pins considered enabled when they have made transition from high impedance state point when they start driving. output enable time tENA interval from point when reference signal reaches high voltage level point when output starts driving shown Output Enable/Disable diagram (Figure 47). time tENA_MEASURED interval from when reference signal switches when output voltage reaches (output high) (output low). Time tTRIP interval from when output starts driving when output reaches trip voltage. Time tENA calculated shown equation: ENA_MEASURED TRIP multiple pins (such data bus) enabled, measurement value that first start driving.
Figure Output Enable/Disable
Example System Hold Time Calculation
determine data output hold time particular system, first calculate tDECAY using equation given above. Choose difference between processor's output voltage input threshold device requiring hold time. typical total capacita
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