high performance Blackfin processor 16-bit MACs, 40-bit ALUs, four 8-b
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Blackfin Embedded Processor
high performance Blackfin processor 16-bit MACs, 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register instruction model ease programming compiler-friendly support Advanced debug, trace, performance monitoring Accepts wide range supply voltages internal operations. Specifications Page Programmable on-chip voltage regulator (ADSP-BF523/ ADSP-BF525/ADSP-BF527 processors only) 289-ball 208-ball CSP_BGA packages
PERIPHERALS
high speed on-the-go (OTG) with Integrated IEEE 802.3-compliant 10/100 Ethernet Parallel peripheral interface (PPI), supporting ITU-R video data formats Host port (HOSTDP) dual-channel, full-duplex synchronous serial ports (SPORTs), supporting eight stereo channels peripheral DMAs, mastered Ethernet memory-to-memory DMAs with external request lines Event handler with interrupt inputs Serial peripheral interface (SPI) compatible port UARTs with IrDA support 2-wire interface (TWI) controller Eight 32-bit timers/counters with support 32-bit up/down counter with rotary support Real-time clock (RTC) watchdog timer 32-bit core timer general-purpose I/Os (GPIOs), with programmable hysteresis NAND flash controller (NFC) Debug/JTAG interface On-chip capable frequency multiplication
MEMORY
132K bytes on-chip memory (See Table Page memory size details) External memory controller with glueless support SDRAM asynchronous 8-bit 16-bit memories Flexible booting options from external flash, SPI, memory from host devices including SPI, TWI, UART Code security with Lockbox Secure Technology one-time-programmable (OTP) memory Memory management unit providing memory protection
WATCHDOG TIMER
MEMORY
VOLTAGE REGULATOR*
JTAG TEST EMULATION PERIPHERAL
COUNTER SPORT0
ACCESS
INSTRUCTION MEMORY DATA MEMORY
SPORT1 INTERRUPT CONTROLLER UART1 UART0 CONTROLLER ACCESS TIMER7-1 TIMER0 GPIO PORT GPIO PORT GPIO PORT
EXTERNAL PORT FLASH, SDRAM CONTROL
BOOT
EMAC HOST PORT
*REGULATOR ONLY AVAILABLE PROCESSORS
Figure Processor Block Diagram
Blackfin Blackfin logo registered trademarks Analog Devices, Inc.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
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TABLE CONTENTS
General Description Portable Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Controllers Host Port Real-Time Clock Watchdog Timer Timers Up/Down Counter Thumbwheel Interface Serial Ports Serial Peripheral Interface (SPI) Port UART Ports Controller Interface 10/100 Ethernet Ports Parallel Peripheral Interface (PPI) On-The-Go Dual-Role Device Controller Code Security with Lockbox Secure Technology Dynamic Power Management Voltage Regulation Voltage Regulation Clock Signals Booting Modes Instruction Description Development Tools Designing Emulator-Compatible Processor Board (Target) Related Documents Lockbox Secure Technology Disclaimer Signal Descriptions Specifications Preliminary Operating Conditions Operating Conditions Electrical Characteristics Absolute Maximum Ratings Sensitivity Package Information Timing Specifications Output Drive Currents Test Conditions Environmental Conditions 289-Ball CSP_BGA Ball assignment 208-Ball CSP_BGA Ball assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
REVISION HISTORY
4/09-Revision Initial Version
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GENERAL DESCRIPTION
ADSP-BF52x processors members Blackfin family products, incorporating Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin® processors combine dual-MAC state-of-the-art signal processing engine, advantages clean, orthogonal RISC-like microprocessor instruction set, single-instruction, multiple-data (SIMD) multimedia capabilities into single instruction-set architecture. ADSP-BF52x processors completely code compatible with other Blackfin processors. ADSP-BF523/ ADSP-BF525/ADSP-BF527 processors offer performance MHz. processors offer performance reduced static power consumption. Differences with respect peripheral combinations shown Table Table Processor Comparison
ADSP-BF522 ADSP-BF524 ADSP-BF526 ADSP-BF523 ADSP-BF525 ADSP-BF527
integrating rich industry-leading system peripherals memory, Blackfin processors platform choice next-generation applications that require RISC-like programmability, multimedia support, leading-edge signal processing integrated package.
PORTABLE POWER ARCHITECTURE
Blackfin processors provide world-class power management performance. They produced with power voltage design methodology feature on-chip dynamic power management, which ability vary both voltage frequency operation significantly lower overall power consumption. This capability result substantial reduction power consumption, compared with just varying frequency operation. This allows longer battery life portable appliances.
SYSTEM INTEGRATION
ADSP-BF52x processors highly integrated system-on-achip solutions next generation embedded network connected applications. combining industry-standard interfaces with high performance signal processing core, costeffective applications developed quickly, without need costly external components. system peripherals include IEEE-compliant 802.3 10/100 Ethernet MAC, high speed controller, controller, NAND flash controller, UART ports, port, serial ports (SPORTs), eight general purpose 32-bit timers with capability, core timer, real-time clock, watchdog timer, Host (HOSTDP) interface, parallel peripheral interface (PPI).
Feature Host Ethernet Internal Voltage Regulator SPORTs UARTs Timers Watchdog Timers Parallel Peripheral Interface GPIOs Instruction SRAM Instruction SRAM/Cache Data SRAM Data SRAM/Cache Scratchpad Boot Maximum Instruction Rate1 Maximum System Clock Speed2 Package Options Memory (bytes)
289-Ball CSP_BGA 208-Ball CSP_BGA
PROCESSOR PERIPHERALS
ADSP-BF52x processors contain rich peripherals connected core several high bandwidth buses, providing flexibility system configuration well excellent overall system performance (see block diagram Page These Blackfin processors contain dedicated network communication modules high speed serial parallel ports, interrupt controller flexible management interrupts from on-chip peripherals external sources, power management control functions tailor performance power characteristics processor system many application scenarios. peripherals, except general-purpose I/O, TWI, real-time clock, timers, supported flexible structure. There also separate memory channels dedicated data transfers between processor's various memory spaces, including external SDRAM asynchronous memory. Multiple on-chip buses running provide enough bandwidth keep processor core running along with activity on-chip external peripherals. processors include on-chip voltage regulator support processor's dynamic power management capability. voltage
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Maximum instruction rate available with every possible SCLK selection. specifications references ADSP-BF522/ADSP-BF524/ ADSP-BF526 Blackfin processors perliminary subect change.
processors pre-production. Preliminary technical data only available these processors subject change without notice. Ordering Guide Page availability.
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regulator provides range core voltage levels when supplied from VDDEXT. voltage regulator bypassed user's discretion. compute register file contains eight 32-bit registers. When performing compute operations 16-bit operand data, register file operates independent 16-bit registers. operands compute operations come from multiported register file instruction constant fields. Each perform 16-bit 16-bit multiply each cycle, accumulating results into 40-bit accumulators. Signed unsigned formats, rounding, saturation supported.
BLACKFIN PROCESSOR CORE
shown Figure Blackfin processor core contains 16-bit multipliers, 40-bit accumulators, 40-bit ALUs, four video ALUs, 40-bit shifter. computation units process 16-, 32-bit data from register file.
ADDRESS ARITHMETIC UNIT
MEMORY
DAG1 DAG0
PREG
ASTAT
SEQUENCER R7.H R6.H R5.H R4.H R3.H R2.H R1.H R0.H R7.L R6.L R5.L R4.L R3.L R2.L R1.L R0.L BARREL SHIFTER DECODE ALIGN
LOOP BUFFER
CONTROL UNIT
DATA ARITHMETIC UNIT
Figure Blackfin Processor Core
ALUs perform traditional arithmetic logical operations 16-bit 32-bit data. addition, many special instructions included accelerate various signal processing tasks. These include operations such field extract population count, modulo multiply, divide primitives, saturation rounding, sign/exponent detection. video instructions include byte alignment packing operations, 16-bit 8-bit adds with clipping, 8-bit average operations, 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided compare/select vector search instructions. certain instructions, 16-bit operations performed simultaneously register pairs 16-bit high half 16-bit half compute register). second used, quad 16-bit operations possible.
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40-bit shifter perform shifts rotates used support normalization, field extract, field deposit instructions. program sequencer controls flow instruction execution, including instruction alignment decoding. program flow control, sequencer supports relative indirect conditional jumps (with static branch prediction), subroutine calls. Hardware provided support zero-overhead looping. architecture fully interlocked, meaning that programmer need manage pipeline when executing instructions with data dependencies. address arithmetic unit provides addresses simultaneous dual fetches from memory. contains multiported register file consisting four sets 32-bit index, modify,
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length, base registers (for circular buffering), eight additional 32-bit pointer registers (for C-style indexed stack manipulation). Blackfin processors support modified Harvard architecture combination with hierarchical memory structure. Level (L1) memories those that typically operate full processor speed with little latency. level, instruction memory holds instructions only. data memories hold data, dedicated scratchpad data memory stores stack local variable information. addition, multiple memory blocks provided, offering configurable SRAM cache. memory management unit (MMU) provides memory protection individual tasks that operating core protect system registers from unintended access. architecture provides three modes operation: user mode, supervisor mode, emulation mode. User mode restricted access certain system resources, thus providing protected software environment, while supervisor mode unrestricted access system core resources. Blackfin processor instruction been optimized that 16-bit opcodes represent most frequently used instructions, resulting excellent compiled code density. Complex instructions encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support limited multi-issue capability, where 32-bit instruction issued parallel with 16-bit instructions, allowing programmer many core resources single instruction cycle. Blackfin processor assembly language uses algebraic syntax ease coding readability. architecture been optimized conjunction with C/C++ compiler, resulting fast efficient software implementations. unit (EBIU), provides expansion with SDRAM, flash memory, SRAM, optionally accessing 132M bytes physical memory.
0xFFFF FFFF CORE REGISTERS BYTES) 0xFFE0 0000 SYSTEM REGISTERS BYTES) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM BYTES) 0xFFB0 0000 RESERVED 0xFFA1 4000 INSTRUCTION SRAM CACHE (16K BYTES) 0xFFA1 0000 0xFFA0 C000 INSTRUCTION BANK SRAM (16K BYTES) 0xFFA0 8000 INSTRUCTION BANK SRAM (32K BYTES) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK SRAM CACHE (16K BYTES) 0xFF90 4000 DATA BANK SRAM (16K BYTES) 0xFF90 0000 RESERVED 0xFF80 8000 DATA BANK SRAM CACHE (16K BYTES) 0xFF80 4000 DATA BANK SRAM (16K BYTES) 0xFF80 0000 RESERVED 0xEF00 8000 BOOT (32K BYTES) RESERVED 0x2040 0000 ASYNC MEMORY BANK BYTES) 0x2030 0000 ASYNC MEMORY BANK BYTES) 0x2020 0000 ASYNC MEMORY BANK BYTES) 0x2010 0000 ASYNC MEMORY BANK BYTES) 0x2000 0000 RESERVED 0x08 0000 SDRAM MEMORY (16M BYTES 128M BYTES) 0x0000 0000
EXTER MEMORY INTERNAL MEMORY
RESERVED
0xEF00 0000
MEMORY ARCHITECTURE
Blackfin processor views memory single unified byte address space, using 32-bit addresses. resources, including internal memory, external memory, control registers, occupy separate sections this common address space. memory portions this address space arranged hierarchical structure provide good cost/performance balance some very fast, low-latency on-chip memory cache SRAM, larger, lower-cost performance off-chip memory systems. Figure on-chip memory system highest-performance memory available Blackfin processor. off-chip memory system, accessed through external interface
Figure Internal/External Memory
memory controller provides high-bandwidth datamovement capability. perform block transfers code data between internal memory external memory spaces.
Internal (On-Chip) Memory
processor three blocks on-chip memory providing high-bandwidth access core. first block instruction memory, consisting bytes SRAM, which bytes configured four-way set-associative cache. This memory accessed full processor speed. second on-chip memory block data memory, consisting banks bytes each. Each memory bank configurable, offering both cache SRAM functionality. This memory block accessed full processor speed. third memory block byte scratchpad SRAM which runs same speed memories, only accessible data SRAM cannot configured cache memory.
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External (Off-Chip) Memory
External memory accessed EBIU. This 16-bit interface provides glueless connection bank synchronous DRAM (SDRAM), well four banks asynchronous memory devices including flash, EPROM, ROM, SRAM, memory mapped devices. SDRAM controller programmed interface 128M bytes SDRAM. separate open each SDRAM internal bank SDRAM controller supports internal SDRAM banks, improving overall performance. asynchronous memory controller programmed control four banks devices with very flexible timing parameters wide variety devices. Each bank occupies byte segment regardless size devices used, that these banks only contiguous each fully populated with byte memory. enables developers store both public private data on-chip. addition storing public private data applications requiring security, also allows developers store completely user-definable data such customer product address, etc. Hence, generic parts shipped, which then programmed protected developer within this non-volatile memory.
Memory Space
processor does define separate space. resources mapped through flat 32-bit address space. On-chip devices have their control registers mapped into memory-mapped registers (MMRs) addresses near byte address space. These separated into smaller blocks, which contains control MMRs core functions, other which contains registers needed setup control on-chip peripherals outside core. MMRs accessible only supervisor mode appear reserved space on-chip peripherals.
NAND Flash Controller (NFC)
ADSP-BF52x processors provide NAND flash controller (NFC). NAND flash devices provide high-density, low-cost memory. However, NAND flash devices also have long random access times, invalid blocks, lower reliability over device lifetimes. Because this, NAND flash often used readonly code storage. this case, code stored NAND flash then transferred faster memory (such SDRAM SRAM) before execution. Another common NAND flash storage multimedia files other large data segments. this case, software file system used manage reading writing NAND flash device. file system selects memory segments storage with goal avoiding blocks equally distributing memory accesses across address locations. Hardware features include: Support page program, page read, block erase NAND flash devices, with accesses aligned page boundaries. Error checking correction (ECC) hardware that facilitates error detection correction. single 8-bit external interface commands, addresses, data. Support (single level cell) NAND flash devices unlimited size, with page sizes bytes. Larger page sizes supported software. Capability releasing external interface pins during long accesses. Support internal requests bits. engine transfer data between internal memory NAND flash device.
Booting
processor contains small on-chip boot kernel, which configures appropriate peripheral booting. processor configured boot from boot memory space, processor starts executing from on-chip boot ROM. more information, Booting Modes Page
Event Handling
event controller processor handles asynchronous synchronous events processor. processor provides event handling that supports both nesting prioritization. Nesting allows multiple event service routines active simultaneously. Prioritization ensures that servicing higher-priority event takes precedence over servicing lowerpriority event. controller provides support five different types events: Emulation emulation event causes processor enter emulation mode, allowing command control processor JTAG interface. RESET This event resets processor. Nonmaskable Interrupt (NMI) event generated software watchdog timer input signal processor. event frequently used power-down indicator initiate orderly shutdown system. Exceptions Events that occur synchronously program flow other words, exception taken before instruction allowed complete). Conditions such data alignment violations undefined instructions cause exceptions. Interrupts Events that occur asynchronously program flow. They caused input signals, timers, other peripherals, well explicit software instruction.
One-Time Programmable Memory
processor bits one-time programmable nonvolatile memory that programmed developer only time. includes array logic support read access programming. Additionally, pages write protected.
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Each event type associated register hold return address associated return-from-event instruction. When event triggered, state processor saved supervisor stack. processor event controller consists stages, core event controller (CEC) system interrupt controller (SIC). core event controller works with system interrupt controller prioritize control system events. Conceptually, interrupts from peripherals enter into then routed directly into general-purpose interrupts CEC. inputs support peripherals processor. Table describes inputs CEC, identifies their names event vector table (EVT), lists their priorities. Table Core Event Controller (CEC)
Priority Highest) Event Class Emulation/Test Control RESET Nonmaskable Interrupt Exception Reserved Hardware Error Core Timer General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt General-Purpose Interrupt Entry IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
Core Event Controller (CEC)
supports nine general-purpose interrupts (IVG15-7), addition dedicated interrupt exception events. these general-purpose interrupts, lowest-priority interrupts (IVG15-14) recommended reserved software interrupt handlers, leaving seven prioritized interrupt
System Interrupt Controller (SIC)
system interrupt controller provides mapping routing events from many peripheral interrupt sources prioritized general-purpose interrupt inputs CEC. Although processor provides default mapping, user alter mappings priorities interrupt events writing appropriate values into interrupt assignment registers (SIC_IARx). Table describes inputs into default mappings into CEC. Table System Interrupt Controller (SIC)
Peripheral Interrupt Event Wakeup Interrupt Error (generic) DMAR0 Block Interrupt DMAR1 Block Interrupt DMAR0 Overflow Error DMAR1 Overflow Error Error Status SPORT0 Status SPORT1 Status Reserved Reserved UART0 Status UART1 Status General Purpose Interrupt RESET) IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 Peripheral Interrupt Default Core Interrupt Registers IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR0 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0
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Table System Interrupt Controller (SIC) (Continued)
Peripheral Interrupt Event Channel (PPI/NFC) Channel (SPORT0 Channel (SPORT0 Channel (SPORT1 Channel (SPORT1 Channel (SPI) Channel (UART0 Channel (UART0 Channel (UART1 Channel (UART1 Memory Interrupt Counter Channel (MAC RX/HOSTDP) Port Interrupt Channel (MAC TX/NFC) Port Interrupt Timer Timer Timer Timer Timer Timer Timer Timer Port Interrupt Port Interrupt MDMA Stream MDMA Stream Software Watchdog Timer Port Interrupt Port Interrupt Status Status HOSTDP Status Host Read Done USB_EINT Interrupt USB_INT0 Interrupt USB_INT1 Interrupt USB_INT2 Interrupt USB_DMAINT Interrupt General Purpose Interrupt RESET) IVG8 IVG8 IVG9 IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 IVG11 IVG11 IVG11 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG12 IVG13 IVG13 IVG13 IVG13 IVG13 IVG7 IVG7 IVG7 IVG7 IVG10 IVG10 IVG10 IVG10 IVG10 Peripheral Interrupt Default Core Interrupt Registers IAR1 IMASK0, ISR0, IWR0 IAR1 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR2 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR3 IMASK0, ISR0, IWR0 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR4 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR5 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1 IAR6 IMASK1, ISR1, IWR1
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Event Control
processor provides very flexible mechanism control processing events. CEC, three registers used coordinate control events. Each register bits wide. interrupt latch register (ILAT) Indicates when events have been latched. appropriate when processor latched event cleared when event been accepted into system. This register updated automatically controller, written only when corresponding IMASK cleared. interrupt mask register (IMASK) Controls masking unmasking individual events. When IMASK register, that event unmasked processed when asserted. cleared IMASK register masks event, preventing processor from servicing event even though event latched ILAT register. This register read written while supervisor mode. (Note that generalpurpose interrupts globally enabled disabled with instructions, respectively.) interrupt pending register (IPEND) IPEND register keeps track nested events. IPEND register indicates event currently active nested some level. This register updated automatically controller read while supervisor mode. allows further control event processing providing three pairs 32-bit interrupt control status registers. Each register contains corresponding each peripheral interrupt events shown Table Page interrupt mask registers (SIC_IMASKx) Control masking unmasking each peripheral interrupt event. When these registers, that peripheral event unmasked processed system when asserted. cleared register masks peripheral event, preventing processor from servicing event. interrupt status registers (SIC_ISRx) multiple peripherals mapped single event, these registers allow software determine which peripheral event source triggered interrupt. indicates peripheral asserting interrupt, cleared indicates peripheral asserting event. interrupt wakeup enable registers (SIC_IWRx) enabling corresponding these registers, peripheral configured wake processor, should core idled sleep mode when event generated. more information Dynamic Power Management Page Because multiple interrupt sources single generalpurpose interrupt, multiple pulse assertions occur simultaneously, before during interrupt processing interrupt event already detected this interrupt input. IPEND register contents monitored interrupt acknowledgement. appropriate ILAT register when interrupt rising edge detected (detection requires core clock cycles). cleared when respective IPEND register set. IPEND indicates that event entered into processor pipeline. this point recognizes queues next rising edge event corresponding event input. minimum latency from rising edge transition generalpurpose interrupt IPEND output asserted three core clock cycles; however, latency much higher, depending activity within state processor.
CONTROLLERS
processor multiple, independent channels that support automated data transfers with minimal overhead processor core. transfers occur between processor's internal memories DMA-capable peripherals. Additionally, transfers accomplished between DMA-capable peripherals external devices connected external memory interfaces, including SDRAM controller asynchronous memory controller. DMA-capable peripherals include Ethernet MAC, NFC, HOSTDP, USB, SPORTs, port, UARTs, PPI. Each individual DMA-capable peripheral least dedicated channel. processor controller supports both one-dimensional (1-D) two-dimensional (2-D) transfers. transfer initialization implemented from registers from sets parameters called descriptor blocks. capability supports arbitrary column sizes elements elements, arbitrary column step sizes ±32K elements. Furthermore, column step size less than step size, allowing implementation interleaved data streams. This feature especially useful video applications where data deinterleaved fly. Examples types supported processor controller include: single, linear buffer that stops upon completion. circular, auto-refreshing buffer that interrupts each full fractionally full buffer. using linked list descriptors. using array descriptors, specifying only base address within common page. addition dedicated peripheral channels, there memory channels provided transfers between various memories processor system. This enables transfers blocks data between memories-including external SDRAM, ROM, SRAM, flash memory-with minimal processor intervention. Memory transfers controlled very flexible descriptor-based methodology standard register-based autobuffer mechanism. processor also external controller capability dual external request pins when used conjunction with external interface unit (EBIU). This functionality
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used when high speed interface required external FIFOs high bandwidth communications peripherals such 2.0. allows control number data transfers memory DMA. number transfers edge programmable. This feature programmed allow memory have increased priority external relative core. peripheral dedicated power supply pins that remain powered clocked even when rest processor power state. provides several programmable interrupt options, including interrupt second, minute, hour, clock ticks, interrupt programmable stopwatch countdown, interrupt programmed alarm time. 32.768 input clock frequency divided down signal prescaler. counter function timer consists four counters: 60-second counter, 60-minute counter, 24-hour counter, 32,768-day counter. When enabled, alarm function generates interrupt when output timer matches programmed value alarm control register. There alarms: first alarm time day. second alarm time that day. stopwatch function counts down from programmed value, with one-second resolution. When stopwatch enabled counter underflows, interrupt generated. Like other peripherals, wake processor from sleep mode upon generation wake-up event. Additionally, wakeup event wake processor from deep sleep mode cause transition from hibernate state.
HOST PORT
host port interface allows external host master transfer data device. host device masters transactions Blackfin processor slave. host port enabled through interface. Once enabled, controlled external host, which then program send/receive data valid internal external memory location. host port interface controller following features. Allows external master configure read/write data transfers read port status. Uses asynchronous memory protocol external interface. 8-/16-bit external data interface host device. Half duplex operation. Little-/big-endian data transfer. Acknowledge mode allows flow control host transactions. Interrupt mode guarantees burst FIFO depth host transactions.
WATCHDOG TIMER
processor includes 32-bit timer that used implement software watchdog function. software watchdog improve system availability forcing processor known state through generation hardware reset, nonmaskable interrupt (NMI), general-purpose interrupt, timer expires before being reset software. programmer initializes count value timer, enables appropriate interrupt, then enables timer. Thereafter, software must reload counter before counts zero from programmed value. This protects system from remaining unknown state where software, which would normally reset timer, stopped running external noise condition software error. configured generate hardware reset, watchdog timer resets both core processor peripherals. After reset, software determine watchdog source hardware reset interrogating status watchdog timer control register. timer clocked system clock (SCLK), maximum frequency fSCLK.
REAL-TIME CLOCK
real-time clock (RTC) provides robust digital watch features, including current time, stopwatch, alarm. clocked 32.768 crystal external Blackfin processor. Connect pins RTXI RTXO with external components shown Figure
RTXI RTXO
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TIMERS
There nine general-purpose programmable timer units processors. Eight timers have external that configured either pulse width modulator (PWM) timer output, input clock timer, mechanism measuring pulse widths periods external events. These timers synchronized external clock input several other associated pins, external clock input PPI_CLK input pin, internal SCLK.
Figure External Components
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timer units used conjunction with UARTs measure width pulses data stream provide software auto-baud detect function respective serial channels. timers generate interrupts processor core providing periodic events synchronization, either system clock count external signals. addition eight general-purpose programmable timers, ninth timer also provided. This extra timer clocked internal processor clock typically used system tick clock generation operating system periodic interrupts. Companding hardware Each SPORT perform A-law -law companding according recommendation G.711. Companding selected transmit and/or receive channel SPORT without additional latencies. operations with single-cycle overhead Each SPORT automatically receive transmit multiple buffers memory data. processor link chain sequences transfers between SPORT memory. Interrupts Each transmit receive port generates interrupt upon completing transfer data word after transferring entire data buffer, buffers, through DMA. Multichannel capability Each SPORT supports channels 1024-channel window compatible with H.100, H.110, MVIP-90, HMVIP standards.
UP/DOWN COUNTER THUMBWHEEL INTERFACE
32-bit up/down counter provided that sense 2-bit quadrature binary codes typically emitted industrial drives manual thumb wheels. counter also operate general-purpose up/down count modes. Then, count direction either controlled level-sensitive input edge detectors. third input provide flexible zero marker support alternatively used input push-button signal thumb wheels. three pins have programmable debouncing circuit. internal signal forwarded timer unit enables timer measure intervals between count events. Boundary registers enable auto-zero operation simple system warning interrupts when programmable count values exceeded.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
processors have SPI-compatible port that enables processor communicate with multiple SPI-compatible devices. interface uses three pins transferring data: data pins (Master Output-Slave Input, MOSI, Master InputSlave Output, MISO) clock (serial clock, SCK). chip select input (SPISS) lets other devices select processor, seven chip select output pins (SPISEL7-1) processor select other devices. select pins reconfigured general-purpose pins. Using these pins, port provides full-duplex, synchronous serial interface, which supports both master/slave modes multimaster environments. port's baud rate clock phase/polarities programmable, integrated channel, configurable support transmit receive data streams. SPI's channel only service unidirectional accesses given time. port's clock rate calculated SCLK Clock Rate SPI_BAUD Where 16-bit SPI_BAUD register contains value 65,535. During transfers, port simultaneously transmits receives serially shifting data serial data lines. serial clock line synchronizes shifting sampling data serial data lines.
SERIAL PORTS
processors incorporate dual-channel synchronous serial ports (SPORT0 SPORT1) serial multiprocessor communications. SPORTs support following features: capable operation. Bidirectional operation Each SPORT sets independent transmit receive pins, enabling eight channels stereo audio. Buffered (8-deep) transmit receive ports Each port data register transferring data words from other processor components shift registers shifting data data registers. Clocking Each transmit receive port either external serial clock generate own, frequencies ranging from (fSCLK/131,070) (fSCLK/2) Word length Each SPORT supports serial data words from bits length, transferred most-significant-bit first least-significant-bit first. Framing Each transmit receive port with without frame sync signals each data word. Frame sync signals generated internally externally, active high low, with either pulse widths early late frame sync.
UART PORTS
processors provide full-duplex universal asynchronous receiver/transmitter (UART) ports, which fully compatible with PC-standard UARTs. Each UART port provides simplified UART interface other peripherals hosts, supporting full-duplex, DMA-supported, asynchronous transfers serial
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data. UART port includes support five eight data bits, stop bits, none, even, parity. Each UART port supports modes operation: (programmed I/O) processor sends receives data writing reading mapped UART registers. data double-buffered both transmit receive. (direct memory access) controller transfers both transmit receive data. This reduces number frequency interrupts required transfer data from memory. UART dedicated channels, transmit receive. These channels have lower default priority than most channels because their relatively service rates. Each UART port's baud rate, serial data format, error code generation status, interrupts programmable: Supporting rates ranging from (fSCLK/1,048,576) (fSCLK/16) bits second. Supporting data formats from seven bits frame. Both transmit receive operations configured generate maskable interrupts processor. UART port's clock rate calculated SCLK UART Clock Rate UART_Divisor Where 16-bit UART_Divisor comes from UART_DLH (most significant bits) UART_DLL (least significant bits) registers. conjunction with general-purpose timer functions, autobaud detection supported. capabilities UARTs further extended with support infrared data association (IrDA®) serial infrared physical layer link specification (SIR) protocol. provides programmable features designed minimize supervision, use, message processing rest processor system. Some standard features are: Support RMII protocols external PHYs. Full duplex half duplex modes. Data framing encapsulation: generation detection preamble, length padding, FCS. Media access management half-duplex operation): collision contention handling, including control retransmission collision frames back-off timing. Flow control full-duplex operation): generation detection PAUSE frames. Station management: generation MDC/MDIO frames read-write access registers. SCLK operating range down (active sleep operating modes). Internal loopback from Some advanced features are: Buffered crystal output external support single crystal system. Automatic checksum computation header payload fields frames. Independent 32-bit descriptor-driven channels. Frame status delivery memory DMA, including frame completion semaphores, efficient buffer queue management software. support separate descriptors header payload eliminate buffer copy operations. Convenient frame alignment modes support even 32-bit alignment encapsulated packet data memory after 14-byte header. Programmable Ethernet event interrupt supports combination selected frame status conditions. interrupt condition. Wake-up frame detected. selected management counter(s) halffull. descriptor error. management statistics counters with selectable clear-on-read behavior programmable interrupts half maximum value. Programmable address filters, including 64-bin address hash table multicast and/or unicast frames, programmable filter modes broadcast, multicast, unicast, control, damaged frames.
CONTROLLER INTERFACE
processors include 2-wire interface (TWI) module providing simple exchange method control data between multiple devices. compatible with widely used I2C® standard. module offers capabilities simultaneous master slave operation support both 7-bit addressing multimedia data arbitration. interface utilizes pins transferring clock (SCL) data (SDA) supports protocol speeds 400k bits/sec. interface pins compatible with logic levels. Additionally, module fully compatible with serial camera control (SCCB) functionality easier control various CMOS camera sensor devices.
10/100 ETHERNET
ADSP-BF526 ADSP-BF527 processors offer capability directly connect network embedded Fast Ethernet Media Access Controller (MAC) that supports both 10-BaseT (10M bits/sec) 100-BaseT (100M bits/sec) operation. 10/100 Ethernet peripheral processor fully compliant IEEE 802.3-2002 standard
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Advanced power management supporting unattended transfer frames status to/from external memory during power sleep mode. System wakeup from sleep operating mode upon magic packet four user-definable wakeup frame filters. Support 802.3Q tagged VLAN frames. Programmable clock rate preamble suppression. RMII operation, seven unused pins configured GPIO pins other purposes. edges signal significant. register selects type sensitivity, register selects which edges significant edge-sensitivity.
PARALLEL PERIPHERAL INTERFACE (PPI)
processor provides parallel peripheral interface (PPI) that connect directly parallel analog-to-digital digital-toanalog converters, video encoders decoders, other general-purpose peripherals. consists dedicated input clock pin, three frame synchronization pins, data pins. input clock supports parallel data rates half system clock rate, synchronization signals configured either inputs outputs. supports variety general-purpose ITU-R modes operation. general-purpose mode, provides half-duplex, bidirectional data transfer with bits data. three frame synchronization signals also provided. ITU-R mode, provides half-duplex bidirectional transfer 10-bit video data. Additionally, on-chip decode embedded start-of-line (SOL) start-offield (SOF) preamble packets supported.
PORTS
Because rich peripherals, processor groups many peripheral signals four ports-Port Port Port Port Most associated pins shared multiple signals. ports function multiplexer controls.
General-Purpose (GPIO)
processor bidirectional, general-purpose (GPIO) pins allocated across three separate GPIO modules-PORTFIO, PORTGIO, PORTHIO, associated with Port Port Port respectively. Port does provide GPIO functionality. Each GPIO-capable shares functionality with other processor peripherals multiplexing scheme; however, GPIO functionality default state device upon power-up. Neither GPIO output input drivers active default. Each general-purpose port individually controlled manipulation port control, status, interrupt registers: GPIO direction control register Specifies direction each individual GPIO input output. GPIO control status registers processor employs "write modify" mechanism that allows combination individual GPIO pins modified single instruction, without affecting level other GPIO pins. Four control registers provided. register written order values, register written order clear values, register written order toggle values, register written order specify value. Reading GPIO status register allows software interrogate sense pins. GPIO interrupt mask registers GPIO interrupt mask registers allow each individual GPIO function interrupt processor. Similar GPIO control registers that used clear individual values, GPIO interrupt mask register sets bits enable interrupt function, other GPIO interrupt mask register clears bits disable interrupt function. GPIO pins defined inputs configured generate hardware interrupts, while output pins triggered software interrupts. GPIO interrupt sensitivity registers GPIO interrupt sensitivity registers specify whether individual pins level- edge-sensitive specify-if edge-sensitive- whether just rising edge both rising falling
General-Purpose Mode Descriptions
general-purpose modes intended suit wide variety data capture transmission applications. Three distinct submodes supported: Input mode Frame syncs data inputs into PPI. Frame capture mode Frame syncs outputs from PPI, data inputs. Output mode Frame syncs data outputs from PPI. Input Mode Input mode intended applications, well video communication with hardware signaling. simplest form, PPI_FS1 external frame sync input that controls when read data. PPI_DELAY allows delay PPI_CLK cycles) between reception this frame sync initiation data reads. number input data samples user programmable defined contents PPI_COUNT register. supports 8-bit 10-bit through 16-bit data, programmable PPI_CONTROL register. Frame Capture Mode Frame capture mode allows video source(s) slave (for frame capture example). ADSP-BF52x processors control when read from video source(s). PPI_FS1 HSYNC output, PPI_FS2 VSYNC output. Output Mode Output mode used transmitting video other data with three output frame syncs. Typically, single frame sync appropriate data converter applications, whereas three frame syncs could used sending video with hardware signaling.
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ITU-R Mode Descriptions
ITU-R modes intended suit wide variety video capture, processing, transmission applications. Three distinct submodes supported: Active video only mode Vertical blanking only mode Entire field mode Active Video Mode Active video only mode used when only active video portion field interest blanking intervals. does read data between active video (EAV) start active video (SAV) preamble symbols, data present during vertical blanking intervals. this mode, control byte sequences stored memory; they filtered PPI. After synchronizing start Field ignores incoming samples until sees code. user specifies number active video lines frame PPI_COUNT register). Vertical Blanking Interval Mode this mode, only transfers vertical blanking interval (VBI) data. Entire Field Mode this mode, entire incoming stream read through PPI. This includes active video, control preamble sequences, ancillary data that embedded horizontal vertical blanking intervals. Data transfer starts immediately after synchronization Field Data transferred from synchronous channels through eight engines that work autonomously from processor core.
CODE SECURITY WITH LOCKBOX SECURE TECHNOLOGY
security system consisting blend hardware software provides customers with flexible rich code security features with LockboxSecure Technology. features include: memory Unique chip Code authentication Secure mode operation security scheme based upon concept authentication digital signatures using standards-based algorithms provides secure processing environment which execute code protect assets. Lockbox Secure Technology Disclaimer Page
DYNAMIC POWER MANAGEMENT
processor provides five operating modes, each with different performance/power profile. addition, dynamic power management provides control functions dynamically alter processor core supply voltage, further reducing power dissipation. When configured core supply voltage, processor enters hibernate state. Control clocking each processor peripherals also reduces power consumption. Table summary power settings each mode. Table Power Settings
Bypassed Mode/State Full-On Enabled Active Enabled/ Disabled Sleep Enabled Deep Sleep Disabled Hibernate Disabled Core Clock (CCLK) Enabled Enabled System Clock (SCLK) Enabled Enabled Core Power
ON-THE-GO DUAL-ROLE DEVICE CONTROLLER
clock (USB_XI) provided through dedicated external crystal crystal oscillator. Universal Serial (USB) On-The-Go-Receive Transmit Timing Page related timing requirements. using crystal provide clock, parallel-resonant, fundamental mode, microprocessor-grade crystal. on-the-go dual-role device controller includes phase locked loop with programmable multipliers generate necessary internal clocking frequency USB. multiplier value should programmed based USB_XI frequency achieve necessary internal clock high speed operation. example, USB_XI crystal frequency MHz, USB_PLLOSC_CTRL register should programmed with multiplier value generate internal clock.
Disabled Enabled Disabled Disabled Disabled Disabled
Full-On Operating Mode-Maximum Performance
full-on mode, enabled bypassed, providing capability maximum operational frequency. This power-up default execution state which maximum performance achieved. processor core enabled peripherals full speed.
Active Operating Mode-Moderate Dynamic Power Savings
active mode, enabled bypassed. Because bypassed, processor's core clock (CCLK) system clock (SCLK) input clock (CLKIN) frequency. access available appropriately configured memories. active mode, possible disable control input setting PLL_OFF control register. This register accessed with user-callable routine
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on-chip called bfrom_SysControl(). disabled, control input must re-enabled before transitioning full-on sleep modes. more information about controls, "Dynamic Power Management" chapter ADSP-BF52x Blackfin Processor Hardware Reference. Ethernet modules wake internal supply regulator (ADSP-BF525 ADSP-BF527 only) signal external regulator wake using EXT_WAKE0 EXT_WAKE1. PG15 does connect PHYINT signal external device, PG15 pulled other device wake processor processor also woken real-time clock wakeup event asserting RESET pin. hibernate wake-up events initiate hardware reset sequence. Individual sources enabled VR_CTL register. EXT_WAKEx signals provided indicate occurrence wake-up events. long VDDEXT applied, VR_CTL register maintains state during hibernation. other internal registers memories, however, lose their content hibernate state. State variables held external SRAM SDRAM. SCKELOW VR_CTL register controls whether SDRAM operates self-refresh mode, which allows retain content while processor hibernate through subsequent reset sequence.
Sleep Operating Mode-High Dynamic Power Savings
sleep mode reduces dynamic power dissipation disabling clock processor core (CCLK). system clock (SCLK), however, continue operate this mode. Typically, external event activity wakes processor. When sleep mode, asserting wakeup enabled SIC_IWRx registers causes processor sense value BYPASS control register (PLL_CTL). BYPASS disabled, processor transitions full-on mode. BYPASS enabled, processor transitions active mode. System access memory supported sleep mode.
Power Savings
shown Table processor supports different power domains, which maximizes flexibility while maintaining compliance with industry standards conventions. isolating internal logic processor into power domain, separate from other I/O, processor take advantage dynamic power management without affecting other devices. There sequencing requirements various power domains, domains must powered according appropriate Specifications table processor Operating Conditions; even feature/peripheral used. Table Power Domains
Power Domain internal logic, except RTC, Memory, USB, internal logic crystal Memory logic logic logic other Range VDDINT VDDRTC VDDMEM VDDUSB VDDOTP VDDEXT
Deep Sleep Operating Mode-Maximum Dynamic Power Savings
deep sleep mode maximizes dynamic power savings disabling clocks processor core (CCLK) synchronous peripherals (SCLK). Asynchronous peripherals, such RTC, still running cannot access internal resources external memory. This powered-down mode only exited assertion reset interrupt (RESET) asynchronous interrupt generated RTC. When deep sleep mode, asynchronous interrupt causes processor transition Active mode. Assertion RESET while deep sleep mode causes processor transition full mode.
Hibernate State-Maximum Static Power Savings
hibernate state maximizes static power savings disabling voltage clocks processor core (CCLK) synchronous peripherals (SCLK). internal voltage regulator only) processor shut writing b#00 FREQ bits VR_CTL register, using bfrom_SysControl() function. This setting sets internal power supply voltage (VDDINT) provide lowest static power dissipation. critical information stored internally (for example, memory contents, register contents, other information) must written volatile storage device prior removing power processor state preserved. Writing b#00 FREQ bits also causes EXT_WAKE0 EXT_WAKE1 transition low, which used signal external voltage regulator shut down. Since VDDEXT VDDMEM still supplied this mode, external pins three-state, unless otherwise specified. This allows other devices that connected processor still have power applied without drawing unwanted current.
dynamic power management feature processor allows both processor's input voltage (VDDINT) clock frequency (fCCLK) dynamically controlled. power dissipated processor largely function clock frequency square operating voltage. example, reducing clock frequency results reduction dynamic power dissipation, while reducing voltage reduces dynamic power dissipation more than 40%. Further, these power savings additive, that clock frequency supply voltage both reduced, power savings dramatic, shown following equations.
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Power Savings Factor CCLKRED DDINTRED DDINTNOM CCLKNOM Power Savings Power Savings Factor) 100% where variables equations are: fCCLKNOM nominal core clock frequency fCCLKRED reduced core clock frequency VDDINTNOM nominal internal supply voltage VDDINTRED reduced internal supply voltage TNOM duration running fCCLKNOM TRED duration running fCCLKRED operation. voltage regulator activated from this power-down state either through wakeup, wakeup, ethernet wake-up, asserting RESET pin, each which then initiates boot sequence. regulator also disabled bypassed user's discretion. voltage regulator modes VRSEL pin-the normal pulse width control external external supply mode which signal power down during hibernate external regulator. VRSEL VDDEXT external regulator VRSEL internal regulator. external mode VROUT becomes EXT_WAKE1. internal regulator used, EXT_WAKE0 control other power sources system during hibernate state. Both signals high-true power-up connected directly low-true shutdown input many common regulators. mode SS/PG (Soft Start/Power Good) signal also changes according state VRSEL. When using internal regulator, SS/PG Soft Start, when using external regulator, Power Good. Soft Start feature recommended reduce inrush currents reduce VDDINT voltage overshoot when coming hibernate changing voltage levels. Power Good (PG) input signal allows processor start only after internal voltage reached chosen level. this way, startup time external regulator detected after hibernation. complete description Soft Start Power Good functionality, refer ADSP-BF52x Blackfin Processor Hardware Reference.
VOLTAGE REGULATION
provides onchip voltage regulator that generate processor core voltage levels from external supply. Figure shows typical external components required complete power management system.
DECOUPLING CAPACITORS
2.25V 3.6V INPUT VOLTAGE RANGE
VDDEXT (LOW-INDUCTANCE)
VOLTAGE REGULATION
VDDEXT
100F 100F FDS9431A ZHCS1000 100F 100nF
VDDINT
SS/PG
SHORT LOWINDUCTANCE WIRE REFERENCE, SYSTEM DESIGN CHAPTER, DETERMINE VALUE NOTE: DESIGNER SHOULD MINIMIZE TRACE LENGTH FDS9431A.
VROUT EXT_WAKE1 VRSEL
Figure Voltage Regulator Circuit
regulator controls internal logic voltage levels programmable with voltage regulator control register (VR_CTL) increments This register accessed using bfrom_SysControl() function on-chip ROM. reduce standby power consumption, internal voltage regulator programmed remove power processor core while keeping power supplied. While hibernate state, external supplies (VDDEXT, VDDMEM, VDDUSB, VDDOTP) still applied, eliminating need external buffers. VDDRTC must applied times correct hibernate
processor requires external voltage regulator power VDDINT domain. reduce standby power consumption, external voltage regulator signaled through EXT_WAKE0 EXT_WAKE1 remove power from processor core. These identical signals high-true power-up connected directly low-true shut down input many common regulators. While hibernate state, external supplies (VDDEXT, VDDMEM, VDDUSB, VDDOTP) still applied, eliminating need external buffers. VDDRTC must applied times correct hibernate operation. external voltage regulator activated from this power down state either through wakeup, wakeup, ethernet wakeup, asserting RESET pin, each which then initiates boot sequence. EXT_WAKE0 EXT_WAKE1 indicate wakeup external voltage regulator. Power Good (PG) input signal allows processor start only after internal voltage reached chosen level. this way, startup time external regulator detected after hibernation. complete description Power Good functionality, refer ADSP-BF52x Blackfin Processor Hardware Reference.
CLOCK SIGNALS
processor clocked external crystal, sine wave input, buffered, shaped clock derived from external clock oscillator.
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external clock used, should compatible signal must halted, changed, operated below specified frequency during normal operation. This signal connected processor's CLKIN pin. When external clock used, XTAL must left unconnected. Alternatively, because processor includes on-chip oscillator circuit, external crystal used. fundamental frequency operation, circuit shown Figure parallel-resonant, fundamental frequency, microprocessorgrade crystal connected across CLKIN XTAL pins. on-chip resistance between CLKIN XTAL range. Further parallel resistors typically recommended. capacitors series resistor shown Figure fine tune phase amplitude sine frequency. capacitor resistor values shown Figure typical values only. capacitor values dependent upon crystal manufacturers' load capacitance recommendations physical layout. resistor value depends drive level specified crystal manufacturer. user should verify customized values based careful investigations multiple devices over temperature range.
BLACKFIN CLKOUT CIRCUITRY CLKBUF CLKIN XTAL OVERTONE OPERATION ONLY:
external oscillator used CLKIN, CLKBUF will have 40/60 duty cycle required some devices. CLKBUF output active default disabled power savings reasons using VR_CTL register. Blackfin core runs different clock rate than on-chip peripherals. shown Figure core clock (CCLK) system peripheral clock (SCLK) derived from input clock (CLKIN) signal. on-chip capable multiplying CLKIN signal programmable multiplication factor (bounded specified minimum maximum frequencies). default multiplier modified software instruction sequence. This sequence managed bfrom_SysControl() function on-chip ROM. On-the-fly CCLK SCLK frequency changes applied using bfrom_SysControl() function on-chip ROM. maximum allowed CCLK SCLK rates depend applied voltages VDDINT, VDDEXT, VDDMEM; always permitted frequency specified part's maximum instruction rate. CLKOUT reflects SCLK frequency off-chip world. part SDRAM interface, functions reference signal other timing specifications well. While active default, disabled using EBIU_SDGCTL EBIU_AMGCTL registers.
"FINE" ADJUSTMENT REQUIRES SEQUENCING "COARSE" ADJUSTMENT ON-THE-FLY
CLKIN
CCLK
SCLK
SCLK CCLK SCLK
NOTE: VALUES MARKED WITH MUST CUSTOMIZED, DEPENDING CRYSTAL LAYOUT. PLEASE ANALYZE CAREFULLY. FREQUENCIES ABOVE MHz, SUGGESTED CAPACITOR VALUE SHOULD TREATED MAXIMUM, SUGGESTED RESISTOR VALUE SHOULD REDUCED
Figure Frequency Modification Methods
Figure External Crystal Connections
third-overtone crystal used frequencies above MHz. circuit then modified ensure crystal operation only third overtone adding tuned inductor circuit shown Figure design procedure third-overtone operation discussed detail application note (EE-168) Using Third Overtone Crystals with ADSP-218x Analog Devices website (www.analog.com)-use site search "EE-168." CLKBUF output pin, which buffered version input clock. This particularly useful Ethernet applications limit number required clock sources system. this type application, single crystal applied directly processor. output CLKBUF then connected external Ethernet RMII device. instead crystal,
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on-chip peripherals clocked system clock (SCLK). system clock frequency programmable means SSEL3-0 bits PLL_DIV register. values programmed into SSEL fields define divide ratio between output (VCO) system clock. SCLK divider values through Table illustrates typical system clock ratios.
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Note that divisor ratio must chosen limit system clock frequency maximum fSCLK. SSEL value dynamically changed without lock latencies writing appropriate values divisor register (PLL_DIV) using bfrom_SysControl() function on-chip ROM. Table Example System Clock Ratios
Example Frequency Ratios (MHz) SCLK
Table Booting Modes
BMODE3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Idle boot Boot from 16-bit external flash memory Boot from 16-bit asynchronous FIFO Boot from serial memory (EEPROM flash) Boot from host device Boot from serial memory (EEPROM/flash) Boot from host Boot from UART0 Host Boot from UART1 Host Reserved Boot from SDRAM Boot from memory Boot from 8-bit NAND flash using PORTF data pins Boot from 8-bit NAND flash using PORTH data pins Boot from 16-Bit Host Boot from 8-Bit Host
Signal Name SSEL3-0 0001 0110 1010
Divider Ratio VCO/SCLK 10:1
core clock (CCLK) frequency also dynamically changed means CSEL1-0 bits PLL_DIV register. Supported CCLK divider ratios shown Table This programmable core clock capability useful fast core frequency modifications. Table Core Clock Ratios
Example Frequency Ratios (MHz) CCLK
Signal Name Divider Ratio CSEL1-0 VCO/CCLK
Idle/no boot mode (BMODE 0x0) this mode, processor goes into idle. idle boot mode helps recover from illegal operating modes, such when memory been misconfigured. Boot from 8-bit 16-bit external flash memory (BMODE 0x1) this mode, boot kernel loads first block header from address 0x2000 0000, (depending instructions contained header) boot kernel performs 16-bit boot starts program execution address provided header. default, configuration settings slowest device possible (3-cycle hold time, 15-cycle access times, 4-cycle setup). ARDY enabled default, enabled through programming. Similarly, interface behavior timings customized through programming. This includes activation burst-mode page-mode operation. this mode, asynchronous interface signals enabled port muxing level. Boot from 16-bit asynchronous FIFO (BMODE 0x2) this mode, boot kernel starts booting from address 0x2030 0000. Every 16-bit word that boot kernel read from FIFO must requested placing pulse DMAR1 pin. Boot from serial memory, EEPROM flash (BMODE 0x3) 16-, 24-, 32-bit addressable devices supported. processor uses GPIO select single EEPROM/flash device submits read command successive address bytes (0x00) until valid 16-, 24-, 32-bit addressable device
maximum CCLK frequency only depends part's maximum instruction rate (see Page 80). This frequency also depends applied VDDINT voltage. Table Table details. maximal system clock rate (SCLK) depends chip package applied VDDINT, VDDEXT, VDDMEM voltages (see Table Table 17).
BOOTING MODES
processor several mechanisms (listed Table automatically loading internal external memory after reset. boot mode defined four BMODE input pins dedicated this purpose. There categories boot modes. master boot modes processor actively loads data from parallel serial memories. slave boot modes processor receives data from external host devices. boot modes listed Table provide number mechanisms automatically loading processor's internal external memories after reset. default, boot modes slowest meaningful configuration settings. Default settings altered initialization code feature boot time proper programming pre-boot time. BMODE pins reset configuration register, sampled during poweron resets software-initiated resets, implement modes shown Table
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detected. Pull-up resistors required SPISEL1 MISO pins. default, value 0x85 written SPI_BAUD register. Boot from host device (BMODE 0x4) processor operates slave mode configured receive bytes file from host (master) agent. HWAIT signal must interrogated host before every transmitted byte. pull-up resistor required SPISS input. pull-down serial clock (SCK) improve signal quality booting robustness. Boot from serial memory, EEPROM/flash (BMODE 0x5) processor operates master mode selects slave connected with unique 0xA0. processor submits successive read commands memory device starting internal address 0x0000 begins clocking data into processor. memory device should comply with Philips I2C® Specification version should able auto-increment internal address counter such that contents memory device read sequentially. default, PRESCALE value TWI_CLKDIV value 0x0811 used. Unless altered settings, memory that takes address bytes assumed. development tools ensure that data booted memories that cannot accessed Blackfin core written intermediate storage location then copied final destination memory DMA. Boot from host (BMODE 0x6) host selects slave with unique 0x5F. processor replies with acknowledgement host then downloads boot stream. host agent should comply with Philips Specification version 2.1. multiplexer used select processor time when booting multiple processors from single TWI. Boot from UART0 host Port (BMODE 0x7) Using autobaud handshake sequence, boot-stream formatted program downloaded host. host selects rate within UART clocking capabilities. When performing autobaud, UART expects (0x40) character (eight bits data, start bit, stop bit, parity bit) UART0RX determine rate. UART then replies with acknowledgement composed bytes (0xBF, value UART0_DLL, value UART0_DLH, then 0x00). host then download boot stream. hold host Blackfin processor signals host with boot host wait (HWAIT) signal. Therefore, host must monitor HWAIT before every transmitted byte. Boot from UART1 host Port (BMODE 0x8). Same BMODE except that UART1 port used. Boot from SDRAM (BMODE 0xA) This warm boot scenario, where boot kernel starts booting from address 0x0000 0010. SDRAM expected contain valid boot stream SDRAM controller must configured settings. Boot from memory (BMODE 0xB) This provides stand-alone booting method. boot stream loaded from on-chip memory. default, boot stream expected start from page 0x40 occupy public memory page 0xDF. This 2560 bytes. Since start page programmable, maximum size boot stream extended 3072 bytes. Table Fourth Byte Large Page Devices
Parameter Value Meaning byte byte byte byte byte/512 byte byte/512 byte byte 128K byte 256K byte 512K byte supported
D1:D0 Page Size (excluding spare area)
Spare Area Size
D5:D4 Block Size (excluding spare area)
width
Used configuration
Boot from 8-bit external NAND flash memory (BMODE BMODE 0xD) this mode, auto detection NAND flash device performed. BMODE 0xC, processor configures PORTF GPIO pins PF7:0 NAND data pins PORTH pins PH15:10 NAND control signals. BMODE 0xD, processor configures PORTH GPIO pins PH7:0 NAND data pins PORTH pins PH15:10 NAND control signals. correct device operation pull-up resistors required both ND_CE (PH10) ND_BUSY (PH13) signals. default, value 0x0033 written NFC_CTL register. booting procedure always starts booting from byte block NAND flash device.
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NAND flash boot supports following features: -Device Auto Detection -Error Detection Correction maximum reliability boot stream size limitation -Peripheral providing efficient transfer data (excluding parity data) -Software-configurable boot mode booting from boot streams spanning multiple blocks, including blocks -Software-configurable boot mode booting from multiple copies boot stream, allowing handling blocks uncorrectable errors -Configurable timing memory Small page NAND flash devices must have 512-byte page size, pages block, 16-byte spare area size, configuration bits. default, read requests from NAND flash followed four address cycles. NAND flash device requires only three address cycles, device must capable ignoring additional address cycles. small page NAND flash device must comply with following command set: -Reset: 0xFF -Read lower half page: 0x00 -Read upper half page: 0x01 -Read spare area: 0x50 large-page NAND-flash devices, four-byte electronic signature read order configure kernel booting, which allows support multiple large-page devices. fourth byte electronic signature must comply with specification Table NAND flash array configuration from Table excluding 16-bit devices, that also complies with command listed below directly supported boot kernel. There restrictions page size block size imposed small-page boot kernel. devices consisting five-byte signature, only four read. fourth must comply outlined above. Large page devices must support following command set: -Reset: 0xFF -Read Electronic Signature: 0x90 -Read: 0x00, 0x30 (confirm command) Large-page devices must support react NAND flash command 0x50. This small-page NAND flash command used device auto detection. default, boot kernel will always issue five address cycles; therefore, large page device requires only four cycles, device must capable ignoring additional address cycles. Boot from 16-Bit Host (BMODE 0xE) this mode, host port configured 16-bit Acknowledge mode, with little endian data formatting. Unlike other modes, host responsible interpreting boot stream. writes data blocks individually into Host port. Before configuring settings each block, host either poll ALLOW_CONFIG HOST_STATUS wait interrupted HWAIT signal. When using HWAIT, host must still check ALLOW_CONFIG least once before beginning configure Host Port. After completing configuration, host required poll READY HOST_STATUS before beginning transfer data. When host sends HIRQ control command, boot kernel issues CALL instruction address 0xFFA0 0000. host's responsibility ensure that valid code been placed this address. routine 0xFFA0 0000 simple initialization routine configure internal resources, such SDRAM controller, which then returns using instruction. routine also final application, which will never return boot kernel. Boot from 8-Bit Host (BMODE 0xF) this mode, Host port configured 8-bit interrupt mode, with little endian data formatting. Unlike other modes, host responsible interpreting boot stream. writes data blocks individually into Host port. Before configuring settings each block, host either poll ALLOW_CONFIG HOST_STATUS wait interrupted HWAIT signal. When using HWAIT, host must still check ALLOW_CONFIG least once before beginning configure Host Port. host will receive interrupt from HOST_ACK signal every time allowed send next FIFO depths worth (sixteen 32-bit words) information. When host sends HIRQ control command, boot kernel issues CALL instruction address 0xFFA0 0000. host's responsibility ensure valid code been placed this address. routine 0xFFA0 0000 simple initialization routine configure internal resources, such SDRAM controller, which then returns using instruction. routine also final application, which will never return boot kernel. each boot modes, 16-byte header first read from external memory device. header specifies number bytes transferred memory destination address. Multiple memory blocks loaded boot sequence. Once blocks loaded, program execution commences from address stored EVT1 register. Prior booting, pre-boot routine interrogates memory. Individual boot modes customized even disabled based programming. External hardware, especially booting hosts, watch HWAIT signal determine when pre-boot finished boot kernel starts boot process. programming memory, user also instruct pre-boot routine customize PLL, Internal
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Voltage Regulator only), SDRAM Controller, Asynchronous Memory Controller. boot kernel differentiates between regular hardware reset wakeup-from-hibernate event speed booting later case. Bits system reset configuration (SYSCR) register used bypass pre-boot routine and/or boot kernel case software reset. They also used simulate wakeup-from-hibernate boot software reset case. boot process further customized "initialization code." This piece code that loaded executed prior regular application boot. Typically, this used configure SDRAM controller speed booting managing PLL, clock frequencies, wait states, serial rates. boot also features C-callable function that called user application time. This enables secondstage boot boot management schemes implemented with ease.
DEVELOPMENT TOOLS
processor supported with complete CROSSCORE® software hardware development tools, including Analog Devices emulators VisualDSP++® development environment. same emulator hardware that supports other Blackfin processors also fully emulates ADSP-BF52x processors.
EZ-KIT Lite Evaluation Board
evaluation ADSP-BF52x processors, EZ-KIT Lite® boards available from Analog Devices. Order using part numbers ADZS-BF526-EZLITE ADZS-BF527-EZLITE. boards come with on-chip emulation capabilities equipped enable software development. Multiple daughter cards available.
DESIGNING EMULATOR-COMPATIBLE PROCESSOR BOARD (TARGET)
Analog Devices family emulators tools that every system developer needs order test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG processor. emulator uses access internal features processor, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. processor must halted send data commands, once operation been completed emulator, processor system running full speed with impact system timing. these emulators, target board must include header that connects processor's JTAG port emulator. details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, (EE-68) Analog Devices JTAG Emulation Technical Reference Analog Devices website (www.analog.com)- site search "EE-68." This document updated regularly keep pace with improvements emulator support.
INSTRUCTION DESCRIPTION
Blackfin processor family assembly language instruction employs algebraic syntax designed ease coding readability. instructions have been specifically tuned provide flexible, densely encoded instruction that compiles very small final memory size. instruction also provides fully featured multifunction instructions that allow programmer many processor core resources single instruction. Coupled with many features more often seen microcontrollers, this instruction very efficient when compiling source code. addition, architecture supports both user (algorithm/application code) supervisor (O/S kernel, device drivers, debuggers, ISRs) modes operation, allowing multiple levels access core processor resources. assembly language, which takes advantage processor's unique architecture, offers following advantages: Seamlessly integrated DSP/MCU features optimized both 8-bit 16-bit operations. multi-issue load/store modified-Harvard architecture, which supports 16-bit four 8-bit load/store pointer updates cycle. registers, I/O, memory mapped into unified byte memory space, providing simplified programming model. Microcontroller features, such arbitrary bit-field manipulation, insertion, extraction; integer operations 16-, 32-bit data-types; separate user supervisor stack pointers. Code density enhancements, which include intermixing 16-bit 32-bit instructions mode switching, code segregation). Frequently used instructions encoded bits.
RELATED DOCUMENTS
following publications that describe ADSP-BF52x processors (and related processors) ordered from Analog Devices sales office accessed electronically website: Getting Started With Blackfin Processors ADSP-BF52x Blackfin Processor Hardware Reference (volumes Blackfin Processor Programming Reference Blackfin Processor Anomaly List Blackfin Processor Anomaly List
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LOCKBOX SECURE TECHNOLOGY DISCLAIMER
Analog Devices products containing Lockbox Secure Technology warranted Analog Devices detailed Analog Devices Standard Terms Conditions Sale. knowledge, Lockbox Secure Technology, when used accordance with data sheet hardware reference manual specifications, provides secure method implementing code data safeguards. However, Analog Devices does guarantee that this technology provides absolute security. ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS EXPRESS IMPLIED WARRANTIES THAT LOCKBOX SECURE TECHNOLOGY CANNOT BREACHED, COMPROMISED OTHERWISE CIRCUMVENTED EVENT SHALL ANALOG DEVICES LIABLE LOSS, DAMAGE, DESTRUCTION RELEASE DATA, INFORMATION, PHYSICAL PROPERTY INTELLECTUAL PROPERTY.
SIGNAL DESCRIPTIONS
Signal definitions ADSP-BF52x processors listed Table order maintain maximum function reduce package size ball count, some balls have dual, multiplexed functions. cases where ball function reconfigurable, default state shown plain text, while alternate function shown italics. pins three-stated during immediately after reset, with exception external memory interface, asynchronous synchronous memory control, buffered XTAL output (CLKBUF). external memory interface, control address lines driven high, with exception CLKOUT, which toggles system clock rate. pins have their input buffers disabled with exception pins that need pull-ups pull-downs, noted Table Table Signal Descriptions
Signal Name EBIU ADDR19-1 DATA15-0 ABE1-0/SDQM1-0 AMS3-0 ARDY SRAS SCAS SCKE CLKOUT SA10 Address Data Byte Enables/Data Mask Bank Select Hardware Ready Control Output Enable Read Enable Write Enable SDRAM Address Strobe SDRAM Column Address Strobe SDRAM Write Enable SDRAM Clock Enable SDRAM Clock Output SDRAM Signal SDRAM Bank Select Type Function Driver Type1
strongly advised available IBIS models ensure that given board design meets overshoot/undershoot signal integrity requirements. IBIS simulation performed, strongly recommended series resistor terminations Driver Types termination resistors should placed near processor reduce transients improve signal integrity. resistance value, typically should chosen match average board trace impedance. Additionally, adding parallel termination CLKOUT prove useful further enhancing signal integrity. sure verify overshoot/undershoot signal integrity specifications actual hardware.
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Table Signal Descriptions (Continued)
Signal Name USB_DP USB_DM USB_XI USB_XO USB_ID USB_VREF USB_RSET USB_VBUS Data (This ball should pulled when unused present.) Data (This ball should pulled when unused present.) Crystal Input (This ball should pulled when unused present.) Crystal Output (This ball should left unconnected when unused present.) mode (This ball should pulled when unused present.) voltage reference (Connect through capacitor, leave unconnected unused present.) resistance set. (This ball should left unconnected when unused present.) Type Function Driver Type1
VBUS (USB_VBUS output only during initialization session request pulses. Host mode type mode require that external voltage source more-per specification- applied VBUS. Other modes require that this external voltage disabled. This ball should pulled when unused present.) GPIO/PPI Data 0/SPORT0 Primary Receive Data /NAND Alternate Data GPIO/PPI Data 1/SPORT0 Receive Frame Sync /NAND Alternate Data GPIO/PPI Data 2/SPORT0 Receive Serial Clock /NAND Alternate Data 2/Alternate Capture Input GPIO/PPI Data 3/SPORT0 Transmit Primary Data /NAND Alternate Data GPIO/PPI Data 4/SPORT0 Transmit Frame Sync /NAND Alternate Data 4/Alternate Timer Clock GPIO/PPI Data 5/SPORT0 Transmit Serial Clock /NAND Alternate Data 5/Alternate Timer Clock GPIO/PPI Data 6/SPORT0 Transmit Secondary Data /NAND Alternate Data 6/Alternate Capture Input GPIO/PPI Data 7/SPORT0 Receive Secondary Data /NAND Alternate Data 7/Alternate Capture Input GPIO/PPI Data 8/SPORT1 Primary Receive Data GPIO/PPI Data 9/SPORT1 Receive Serial Clock/SPI Slave Select GPIO/PPI Data 10/SPORT1 Receive Frame Sync/SPI Slave Select GPIO/PPI Data 11/SPORT1 Transmit Frame Sync/Counter Zero Marker GPIO/PPI Data 12/SPORT1 Transmit Primary Data/SPI Slave Select 2/Counter Down Gate
Port GPIO Multiplexed Peripherals PF0/PPI D0/DR0PRI /ND_D0A PF1/PPI D1/RFS0/ND_D1A PF2/PPI D2/RSCLK0/ND_D2A PF3/PPI D3/DT0PRI/ND_D3A PF4/PPI D4/TFS0/ND_D4A/TACLK0 PF5/PPI D5/TSCLK0/ND_D5A/TACLK1 PF6/PPI D6/DT0SEC/ND_D6A/TACI0 PF7/PPI D7/DR0SEC/ND_D7A/TACI1 PF8/PPI D8/DR1PRI PF9/PPI D9/RSCLK1/SPISEL6 PF10/PPI D10/RFS1/SPISEL7 PF11/PPI D11/TFS1/CZM PF12/PPI D12/DT1PRI/SPISEL2/CDG PF13/PPI D13/TSCLK1/SPISEL3/CUD PF14/PPI D14/DT1SEC/UART1TX PF15/PPI D15/DR1SEC/UART1RX/TACI3
GPIO/PPI Data 13/SPORT1 Transmit Serial Clock/SPI Slave Select 3/Counter Direction GPIO/PPI Data 14/SPORT1 Transmit Secondary Data/UART1 Transmit GPIO/PPI Data 15/SPORT1 Receive Secondary Data /UART1 Receive /Alternate Capture Input
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Table Signal Descriptions (Continued)
Signal Name Port GPIO Multiplexed Peripherals PG0/HWAIT PG1/SPISS/SPISEL1 PG2/SCK PG3/MISO/DR0SECA PG4/MOSI/DT0SECA PG5/TMR1/PPI_FS2 PG6/DT0PRIA/TMR2/PPI_FS3 PG7/TMR3/DR0PRIA/UART0TX PG8/TMR4/RFS0A/UART0RX/TACI4 PG9/TMR5/RSCLK0A/TACI5 PG10/TMR6/TSCLK0A/TACI6 PG11/TMR7/HOST_WR PG12/DMAR1/UART1TXA/HOST_ACK PG14/TSCLK0A1/MDC/HOST_RD GPIO/Boot Host Wait2 GPIO/SPI Slave Select Input/SPI Slave Select GPIO/SPI Clock GPIO/SPI Master Slave Out/Sport Alternate Receive Data Secondary GPIO/SPI Master Slave In/Sport Alternate Transmit Data Secondary GPIO/Timer1/PPI Frame Sync2 GPIO/SPORT0 Alternate Primary Transmit Data Timer2 Frame Sync3 GPIO/Timer3/Sport Alternate Receive Data Primary/UART0 Transmit GPIO/Timer 4/Sport Alternate Receive Clock/Frame Sync /UART0 Receive/Alternate Capture Input GPIO/Timer5/Sport Alternate Receive Clock /Alternate Capture Input GPIO/Timer /Sport Alternate Transmit /Alternate Capture Input GPIO/Timer7/Host Write Enable GPIO/DMA Request 1/Alternate UART1 Transmit/Host Acknowledge GPIO/DMA Request 0/Alternate UART1 Receive/Host Address/Alternate Capture Input GPIO/SPORT0 Alternate Transmit/Ethernet Management Channel Clock /Host Read Enable Type Function Driver Type1
PG153/TFS0A/MII PHYINT/RMII MDINT/HOST_CE Port GPIO Multiplexed Peripherals PH1/ND_D1/ERxER/HOST_D1 PH2/ND_D2/MDIO/HOST_D2 PH3/ND_D3/ETxEN/HOST_D3 PH5/ND_D5/ETxD0/HOST_D5 PH6/ND_D6/ERxD0/HOST_D6 PH7/ND_D7/ETxD1/HOST_D7 PH10/ND_CE/ERxD2/HOST_D10 PH11/ND_WE/ETxD3/HOST_D11 PH12/ND_RE/ERxD3/HOST_D12 PH13/ND_BUSY/ERxCLK/HOST_D13 PH14/ND_CLE/ERxDV/HOST_D14 PH15/ND_ALE/COL/HOST_D15
GPIO/SPORT0 Alternate Transmit Frame Sync/Ethernet/MII Interrupt/RMII Management Channel Data Interrupt/Host Chip Enable GPIO/NAND D0/Ethernet RMII Carrier Sense/Host GPIO/NAND D1/Ethernet RMII Receive Error/Host GPIO/NAND D2/Ethernet Management Channel Serial Data/Host GPIO/NAND D3/Ethernet Transmit Enable/Host GPIO/NAND D4/Ethernet RMII Reference Clock/Host GPIO/NAND D5/Ethernet RMII Transmit D0/Host GPIO/NAND D6/Ethernet RMII Receive D0/Host GPIO/NAND D7/Ethernet RMII Transmit D1/Host
GPIO/Alternate Capture Input 2/Ethernet RMII Receive D1/Host /SPI Slave Select GPIO/SPI Slave Select 5/Ethernet Transmit D2/Host /Alternate Timer Clock GPIO/NAND Chip Enable/Ethernet Receive D2/Host GPIO/NAND Write Enable/Ethernet Transmit D3/Host GPIO/NAND Read Enable/Ethernet Receive D3/Host GPIO/NAND Busy/Ethernet Receive Clock/Host
GPIO/NAND Command Latch Enable/Ethernet RMII Receive Data Valid/ Host GPIO/NAND Address Latch Enable/Ethernet Collision/Host Data
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Table Signal Descriptions (Continued)
Signal Name Port Multiplexed Peripherals PJ0: PPI_FS1/TMR0 PJ1: PPI_CLK/TMRCLK PJ2: PJ3: Real Time Clock RTXI RTXO JTAG Port TRST Clock CLKIN XTAL CLKBUF Mode Controls RESET BMODE3-0 Voltage Regulation VRSEL VROUT/EXT_WAKE1 EXT_WAKE0 SS/PG Voltage Regulation EXT_WAKE1 EXT_WAKE0 Wake Indication Wake Indication Power Good Internal/External Voltage Regulator Select External Drive/Wake Indication Wake Indication Soft Start/Power Good Reset Nonmaskable Interrupt (This ball should pulled high when used.) Boot Mode Strap Clock/Crystal Input Crystal Output Buffered XTAL Output JTAG Clock JTAG Serial Data JTAG Serial Data JTAG Mode Select JTAG Reset (This ball should pulled JTAG port used.) Emulation Output Crystal Input (This ball should pulled when used.) Crystal Output Frame Sync1/Timer0 Clock/Timer Clock Type Function Driver Type1
Serial Clock (This open-drain output requires pull-up resistor.4) Serial Data (This open-drain output requires pull-up resistor.4)
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Table Signal Descriptions (Continued)
Signal Name Power Supplies Type Function SUPPLIES MUST POWERED Operating Conditions Page Preliminary Operating Conditions ADSP-BF522/ADSP-BF524/ ADSP-BF526 Page Power Supply Internal Power Supply Real Time Clock Power Supply Power Supply Power Supply Power Supply Programming Voltage Ground Supplies Driver Type1
VDDEXT VDDINT VDDRTC VDDUSB VDDMEM VDDOTP VPPOTP
Output Drive Currents Page more information about each driver type. HWAIT must pulled high configure polarity. driven output toggle during processor boot. Booting Modes Page When driven low, this ball used wake processor from hibernate state, either normal GPIO mode Ethernet mode PHYINT. ball used wake enable feature with PHYWE VR_CTL register, pull-up ball with resistor. Consult version specification proper resistor value.
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SPECIFICATIONS
Specifications subject change without notice.
PRELIMINARY OPERATING CONDITIONS
specifications references ADSP-BF522/ADSP-BF524/ ADSP-BF526 Blackfin processors preliminary subject change.
Parameter VDDINT VDDEXT VDDRTC VDDMEM VDDOTP VPPOTP Conditions Internal Supply Voltage External Supply Voltage1 Power Supply Voltage2 Supply Voltage3 Supply Voltage1 Programming Voltage Reads Writes4 Supply Voltage5 High Level Input Voltage6, High Level Input Voltage6, High Level Input Voltage6, High Level Input Voltage Level Input Voltage6, Level Input Voltage6, Level Input Voltage6, Level Input Voltage Junction Temperature Junction Temperature Junction Temperature 1.70 2.25 1.70 2.25 Nominal 1.8, 1.8, 2.75 2.75 VBUSTWI8 VBUSTWI9 +105 +105 +105 Unit
VDDUSB VIHTWI VILTWI
2.25 VDDEXT/VDDMEM 1.90 VDDEXT/VDDMEM 2.75 VDDEXT/VDDMEM VDDEXT 1.90 V/2.75 V/3.6 VBUSTWI VDDEXT/VDDMEM -0.3 VDDEXT/VDDMEM 2.25 -0.3 VDDEXT/VDDMEM -0.3 VDDEXT minimum -0.3 289-Ball CSP_BGA TAMBIENT +70°C 208-Ball CSP_BGA TAMBIENT +70°C 208-Ball CSP_BGA TAMBIENT -40°C +85°C
Must remain powered (even associated function used). used, power with VDDEXT. Balls that VDDMEM DATA15-0, ADDR19-1, ABE1-0, ARE, AWE, AOE, AMS3-0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls tolerant voltages higher than VDDMEM. VPPOTP voltage writes must only applied when programming memory. There finite amount cumulative time that this voltage applied (dependent voltage junction temperature) over lifetime part. Please Table Page details. When using peripheral ADSP-BF524/ADSP-BF526 terminating VDDUSB ADSP-BF522, VDDUSB must powered VDDEXT. Bidirectional balls (PF15-0, PG15-0, PH15-0) input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, BMODE3-0) ADSP-BF52x processors tolerant (always accept maximum VIH). Voltage compliance outputs, VOH) limited VDDEXT supply voltage. Parameter value applies input bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, SCL. VIHTWI value vary with selection TWI_DT field NONGPIO_DRIVE register. VBUSTWI values Table pulled VBUSTWI. Table
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Table shows settings TWI_DT NONGPIO_DRIVE register. this register prior using port. Table TWI_DT Field Selections VDDEXT/VBUSTWI
TWI_DT (default)1 (reserved)
VDDEXT Nominal
VBUSTWI Minimum 2.97 2.97 2.97 2.25 2.25
VBUSTWI Nominal
VBUSTWI Maximum 3.63 1.98 3.63 3.63 2.75 2.75
Unit
Designs must comply with VDDEXT VBUSTWI voltages specified default TWI_DT setting correct JTAG boundary scan operation during reset.
Clock Related Operating Conditions
Table describes core clock timing requirements processors. Take care selecting MSEL, SSEL, CSEL ratios exceed maximum core clock system clock (see Table 14). Table describes phase-locked loop operating conditions. Table Core Clock (CCLK) Processors-All Instruction Rates1,2
Parameter fCCLK fCCLK fCCLK fCCLK fCCLK
Core Clock Frequency (VDDINT =TBD3 minimum) Core Clock Frequency (VDDINT =TBD5 minimum) Core Clock Frequency (VDDINT TBD6 minimum) Core Clock Frequency (VDDINT minimum) Core Clock Frequency (VDDINT minimum)
Maximum 4004
Unit
specifications references Blackfin processors perliminary subect change. Ordering Guide Page Preliminary data indicates value 1.33 Applies only instruction rate only. Ordering Guide Page Preliminary data indicates value 1.235 Preliminary data indicates value 1.14
Table Phase-Locked Loop Operating Conditions
Parameter fVCO
Voltage Controlled Oscillator (VCO) Frequency
Minimum
Maximum Instruction Rate1
Unit
Ordering Guide Page
Table Processors Maximum SCLK Conditions1
Parameter fSCLK fSCLK
CLKOUT/SCLK Frequency (VDDINT CLKOUT/SCLK Frequency (VDDINT
VDDEXT/VDDMEM V/2.5 V/3.3 Nominal
Unit
specifications references Blackfin processors perliminary subect change. fSCLK must less than equal fCCLK subject additional restrictions SDRAM interface operation. Table Page
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OPERATING CONDITIONS
Parameter VDDINT VDDINT VDDINT VDDEXT Conditions Nonautomotive models2 Automotive models3 Automotive models3 Nonautomotive models, Internal Voltage Regulator Disabled Nonautomotive models, Internal Voltage Regulator Enabled Automotive models Nonautomotive models Automotive models Nonautomotive models Automotive models 0.95 1.093 1.045 1.70 Nominal 1.15 1.10 1.8, 1.26 1.26 1.20 Unit
Internal Supply Voltage Internal Supply Voltage1 Internal Supply Voltage1 External Supply Voltage4,
VDDEXT
External Supply Voltage4,
2.25
VDDEXT VDDRTC VDDRTC VDDMEM VDDMEM VDDOTP VPPOTP VDDUSB VIHTWI VILTWI
External Supply Voltage4, Power Supply Voltage6 Power Supply Voltage6 Supply Voltage4, Supply Voltage4, Supply Voltage4 Programming Voltage4 Supply Voltage8 High Level Input Voltage9, High Level Input Voltage9, High Level Input Voltage9, High Level Input Voltage Level Input Voltage9, Level Input Voltage9, Level Input Voltage9, Level Input Voltage Junction Temperature Junction Temperature Junction Temperature
VDDEXT/VDDMEM 1.90 VDDEXT/VDDMEM 2.75 VDDEXT/VDDMEM VDDEXT 1.90 V/2.75 V/3.6 VDDEXT/VDDMEM VDDEXT/VDDMEM 2.25 VDDEXT/VDDMEM VDDEXT minimum 289-Ball CSP_BGA TAMBIENT +70°C 208-Ball CSP_BGA TAMBIENT +70°C 208-Ball CSP_BGA TAMBIENT -40°C +85°C
2.25 1.70 2.25 2.25 VBUSTWI -0.3 -0.3 -0.3 -0.3
1.8,
2.75 2.75 VBUSTWI11 VBUSTWI12 +105 +105 +105
voltage regulator generate VDDINT levels 1.00 1.20 with tolerance when VRCTL programmed with bfrom_SysControl() API. This specification only guaranteed when used. Ordering Guide Page Automotive Products Page Must remain powered (even associated function used). VDDEXT supply voltage regulator GPIO. used, power with VDDEXT. Balls that VDDMEM DATA15-0, ADDR19-1, ABE1-0, ARE, AWE, AOE, AMS3-0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls tolerant voltages higher than VDDMEM. When using peripheral ADSP-BF525/ADSP-BF527 terminating VDDUSB ADSP-BF523, VDDUSB must powered VDDEXT. Bidirectional balls (PF15-0, PG15-0, PH15-0) input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, BMODE3-0) ADSP-BF52x processors tolerant (always accept maximum VIH). Voltage compliance outputs, VOH) limited VDDEXT supply voltage. Parameter value applies input bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, SCL. VIHTWI value vary with selection TWI_DT field NONGPIO_DRIVE register. VBUSTWI values Table Page pulled VBUSTWI. Table Page
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Clock Related Operating Conditions
Table describes core clock timing requirements processors. Take care selecting MSEL, SSEL, CSEL ratios exceed maximum core clock system clock (see Table 17). Table describes phase-locked loop operating conditions. nominal voltage setting (Table internal external regulators.
Table Core Clock (CCLK) Processors-All Instruction Rates1
Parameter fCCLK fCCLK fCCLK
Core Clock Frequency (VDDINT =1.14 minimum)2 Core Clock Frequency (VDDINT =1.093 minimum)3 Core Clock Frequency (VDDINT 0.95 minimum)
Nominal Voltage Setting 1.20 1.15
Unit
Ordering Guide Page Applies only instruction rates. Ordering Guide Page Applies only instruction rates. Ordering Guide Page
Table Phase-Locked Loop Operating Conditions
Parameter fVCO
Voltage Controlled Oscillator (VCO) Frequency
Minimum
Maximum Instruction Rate1
Unit
Ordering Guide Page
Table Processors Maximum SCLK Conditions
Parameter fSCLK fSCLK
CLKOUT/SCLK Frequency (VDDINT 1.14 CLKOUT/SCLK Frequency (VDDINT 1.14
VDDEXT/VDDMEM Nominal1
VDDEXT/VDDMEM V/3.3 Nominal Unit
either VDDEXT VDDMEM operating 1.8V nominal, fSCLK constrained 100MHz. fSCLK must less than equal fCCLK subject additional restrictions SDRAM interface operation. Table Page Rounded number. Actual test specification SCLK period Table Page
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ELECTRICAL CHARACTERISTICS
Table Common Electrical Characteristics ADSP-BF52x Processors
Parameter IIHP IOZH IOZHTWI IOZL CINTWI
Test Conditions High Level Output Voltage High Level Output Voltage High Level Output Voltage Level Output Voltage High Level Input Current1 Level Input Current1 VDDEXT /VDDMEM -0.5 VDDEXT /VDDMEM 2.25 -0.5 VDDEXT /VDDMEM -0.5 VDDEXT /VDDMEM 1.7/2.25/3.0 VDDEXT /VDDMEM =3.6 VDDEXT /VDDMEM =3.6
1.35
Typical
Unit
10.0 10.0 75.0 10.0 10.0 10.0
High Level Input Current JTAG2 VDDEXT Three-State Leakage Current3 VDDEXT /VDDMEM= Three-State Leakage Current4 VDDEXT =3.0 Three-State Leakage Current VDDEXT /VDDMEM= Input Capacitance
MHz, TAMBIENT 25°C, MHz, TAMBIENT 25°C,
Input Capacitance4,6
Applies input balls. Applies JTAG input balls (TCK, TDI, TMS, TRST). Applies three-statable balls. Applies bidirectional balls SDA. Applies signal balls, except SDA. Guaranteed, tested.
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Table Preliminary Electrical Characteristics Processors1
Parameter IDDDEEPSLEEP
Test Conditions VDDINT Current Deep Sleep Mode VDDINT fCCLK MHz, fSCLK MHz, 25°C, 0.00
Typical
Unit
IDDSLEEP IDD-IDLE IDD-TYP IDD-TYP IDD-TYP IDDHIBERNATE2,
VDDINT Current Sleep Mode VDDINT fSCLK MHz, 25°C VDDINT Current Idle VDDINT Current VDDINT Current VDDINT Current Hibernate State Current VDDINT fCCLK MHz, 25°C, 0.44 VDDINT fCCLK MHz, 25°C, 1.00 VDDINT 1.15 fCCLK MHz, 25°C, 1.00 VDDINT fCCLK MHz, 25°C, 1.00 VDDEXT =VDDMEM =VDDRTC VDDUSB 3.30 VDDOTP =VPPOTP =2.5 25°C, CLKIN with voltage regulator (VDDINT VDDRTC 25°C VDDUSB 25°C, Full Speed Transmit
IDDRTC IDDUSB-FS IDDUSB-HS IDDSLEEP2,
VDDRTC Current VDDUSB Current Full/Low Speed Mode
Table (TBD VDDINT fSCLK)5 Table
VDDUSB Current High Speed VDDUSB 25°C, High Mode Speed Transmit VDDINIT Current Sleep Mode fCCLK MHz, fSCLK
IDDDEEPSLEEP2, IDDINT4,
VDDINT Current Deep Sleep Mode VDDINT Current
fCCLK MHz, fSCLK fCCLK MHz, fSCLK
Table (Table ASF) (TBD VDDINT fSCLK)
IDDOTP IDDOTP IPPOTP IPPOTP
VDDOTP Current VDDOTP Current VPPOTP Current VPPOTP Current
VDDOTP 25°C, Memory Read VDDOTP 25°C, Memory Write VPPOTP 25°C, Memory Read VPPOTP Table 25°C, Memory Write
specifications references Blackfin processors preliminary subject change. ADSP-BF52x Blackfin Processor Hardware Reference Manual definition sleep, deep sleep, hibernate operating modes. Includes current VDDEXT, VDDUSB, VDDMEM, VDDOTP, VPPOTP supplies. Clock inputs tied high low. Guaranteed maximum specifications. Unit VDDINT (Volts). Unit fSCLK MHz. Example: would adder. Table list IDDINT power vectors covered.
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Table Electrical Characteristics Processors
Parameter IDDDEEPSLEEP
Test Conditions VDDINT Current Deep Sleep Mode VDDINT fCCLK MHz, fSCLK MHz, 25°C, 0.00
Typical
Unit
IDDSLEEP IDD-IDLE IDD-TYP IDD-TYP
VDDINT Current Sleep Mode VDDINT fSCLK MHz, 25°C VDDINT Current Idle VDDINT Current VDDINT Current VDDINT fCCLK MHz, 25°C, 0.44 VDDINT fCCLK MHz, 25°C, 1.00 VDDINT 1.15 fCCLK MHz, 25°C, 1.00 VDDINT fCCLK MHz, 25°C, 1.00 VDDEXT =VDDMEM =VDDRTC VDDUSB 3.30 VDDOTP =VPPOTP =2.5 25°C, CLKIN with voltage regulator (VDDINT VDDRTC 25°C VDDUSB 25°C, Full Speed Transmit
IDD-TYP IDDHIBERNATE2,
VDDINT Current Hibernate State Current
IDDRTC IDDUSB-FS IDDUSB-HS IDDSLEEP2,
VDDRTC Current VDDUSB Current Full/Low Speed Mode
Table (0.61 VDDINT fSCLK)5 Table
VDDUSB Current High Speed VDDUSB 25°C, Mode High Speed Transmit VDDINT Current Sleep Mode fCCLK MHz, fSCLK
IDDDEEPSLEEP2, IDDINT4,
VDDINT Current Deep Sleep Mode VDDINT Current
fCCLK MHz, fSCLK fCCLK MHz, fSCLK
Table (Table ASF) (0.61 VDDINT fSCLK)
IDDOTP IDDOTP IPPOTP IPPOTP
VDDOTP Current VDDOTP Current VPPOTP Current VPPOTP Current
VDDOTP 25°C, Memory Read VDDOTP 25°C, Memory Write VPPOTP 25°C, Memory Read VPPOTP 25°C, Memory Write
ADSP-BF52x Blackfin Processor Hardware Reference Manual definition sleep, deep sleep, hibernate operating modes. Includes current VDDEXT, VDDUSB, VDDMEM, VDDOTP, VPPOTP supplies. Clock inputs tied high low. Guaranteed maximum specifications. Unit VDDINT (Volts). Unit fSCLK MHz. Example: would 0.61 54.9 adder. Table list IDDINT power vectors covered.
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Total Power Dissipation
Total power dissipation components: Static, including leakage current Dynamic, transistor switching characteristics Many operating conditions also affect power dissipation, including temperature, voltage, operating frequency, processor activity. Electrical Characteristics Page shows current dissipation internal circuitry (VDDINT). IDDDEEPSLEEP specifies static power dissipation function voltage (VDDINT) temperature (see Table Table 24), IDDINT specifies total power specification listed test conditions, including dynamic component function voltage (VDDINT) frequency (Table Table 25). There parts dynamic component. first part transistor switching core clock (CCLK) domain. This part subject Activity Scaling Factor (ASF) which represents application code running processor core memories (Table 21). combined with CCLK Frequency VDDINT dependent data Table Table calculate this part. second part transistor switching system clock (SCLK) domain, which included IDDINT specification equation. Table Activity Scaling Factors (ASF)1
IDDINT Power Vector IDD-PEAK IDD-HIGH IDD-TYP IDD-APP IDD-NOP IDD-IDLE
Activity Scaling Factor (ASF) 1.29 1.26 1.00 0.88 0.72 0.44
Estimating Power ASDP-BF534/BF536/BF537 Blackfin Processors (EE-297). power vector information also applies ADSP-BF52x processors.
Table Preliminary Static Current IDD-DEEPSLEEP (mA)1
(°C)
Voltage (VDDINT)2
specifications references Blackfin processors preliminary subject change. Valid temperature voltage ranges model-specific. Preliminary Operating Conditions Page
Table Preliminary Dynamic Current CCLK Domain (mA, with 1.0)1,2
fCCLK (MHz)3
Voltage (VDDINT)3
specifications references Blackfin processors preliminary subject change. values guaranteed standalone maximum specifications. They must combined with static current equations Electrical Characteristics Page Valid frequency voltage ranges model-specific. Preliminary Operating Conditions Page
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Table Static Current IDD-DEEPSLEEP (mA)
(°C)
0.95 13.2 22.3 30.8 42.9 59.1 80.4 109.3 120.8 144.4 173.9
1.00 10.6 15.2 25.4 34.8 47.9 65.6 88.6 118.7 132.1 157.5 189.1
1.05 12.4 17.7 28.9 39.2 53.6 72.9 97.9 130.5 144.7 172.3 206.4
Voltage (VDDINT)1 1.10 1.15 11.1 13.1 14.6 17.0 20.4 23.5 32.8 37.2 44.1 49.6 59.9 66.9 80.8 89.7 107.8 119.2 143.2 157.4 158.8 174.2 188.4 206.0 224.9 245.4
1.20 15.4 19.8 27.0 42.1 55.7 74.6 99.4 131.5 172.8 190.9 225.3 267.8
1.25 18.0 22.9 30.9 47.6 62.5 83.2 110.2 145.1 189.7 209.3 246.4 292.2
1.30 21.0 26.4 35.3 53.7 70.0 92.6 122.0 159.8 208.1 229.2 269.2 318.7
Valid temperature voltage ranges model-specific. Operating Conditions Page
Table Dynamic Current CCLK Domain (mA, with 1.0)1
fCCLK (MHz)2
0.95 69.8 53.4 36.9 20.5
1.00 74.3 56.9 39.4 22.0
1.05 97.3 78.9 60.4 41.9 23.6
Voltage (VDDINT)2 1.10 1.15 130.4 110.3 116.7 103.1 109.1 83.6 88.5 64.1 68.0 44.6 47.4 25.3 27.0
1.20 137.6 123.3 115.0 93.5 71.8 50.1 28.8
1.25 145.1 129.8 121.3 98.6 75.8 53.0 30.6
1.30 152.5 136.4 127.7 103.9 80.0 56.0 32.5
values guaranteed standalone maximum specifications. They must combined with static current equations Electrical Characteristics Page Valid frequency voltage ranges model-specific. Operating Conditions Page
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ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed table cause permanent damage device. These stress ratings only. Functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Parameter Rating
Page There finite amount cumulative time that write voltage applied (dependent voltage junction temperature) VPPOTP over lifetime part. Therefore, maximum memory programming time processors shown Table processors have similar restriction. Table Preliminary Maximum Memory Programming Time Processors1
Temperature (TJ) VPPOTP Voltage
-0.3 +1.26 Internal Supply Voltage (VDDINT) processors Preliminary Internal Supply Voltage (VDDINT) processors1 External (I/O) Supply Voltage (VDDEXT/VDDMEM) -0.3 +3.8 Input Voltage2, Input Voltage2, Input Voltage
25°C 2400 1000
85°C
110°C
125°C
-0.5 +3.6 -0.5 +5.5 -0.5 +5.25 -0.5 VDDEXT /VDDMEM+0.5 (max) -65°C +150°C +110°C
specifications references Blackfin processors preliminary subject change.
Output Voltage Swing Load Capacitance6 IOH/IOL Current Group7 Storage Temperature Range Junction Temperature Underbias
specifications references Blackfin processors preliminary subject change. Applies 100% transient duty cycle. other duty cycles Table Applies only when VDDEXT within specifications. When VDDEXT outside specifications, range VDDEXT ±0.2 Applies balls SDA. Applies balls USB_DP, USB_DM, USB_VBUS. proper SDRAM controller operation, maximum load capacitance ADDR19-1, DATA15-0, ABE1-0/SDQM1-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, SMS. more information, description preceding Table
Absolute Maximum Ratings table specifies maximum total source/sink (IOH/IOL) current group pins. Permanent damage occur this value exceeded. understand this specification, pins PH4, PH3, PH2, PH1, from group Total Current Groups table, each were sourcing sinking each, total current those pins would This would allow total that could sourced sunk remaining pins group without damaging device. list groups their pins, Total Current Groups table. Note that specifications have separate per-pin maximum current requirements, Preliminary Electrical Characteristics Processors Electrical Characteristics ADSP-BF523/ADSP-BF525/ ADSP-BF527 Processors tables. Table Total Current Groups
Group Pins Group PH4, PH3, PH2, PH1, PH0, PF15, PF14, PF13 PF12, SDA, SCL, PF11, PF10, PF9, PF8, PF6, PF5, PF4, PF3, PF2, PF1, PF0, PPI_FS1 PPI_CLK, PG15, PG14, PG13, PG12, PG11, PG10, PG8, PG7, PG6, PG5, PG4, BMODE3, BMODE2, BMODE1 BMODE0, PG3, PG2, PG1, PG0, TDI, TDO, EMU, TCK, TRST, TMS, DATA15, DATA14, DATA13, DATA12, DATA11, DATA10 DATA9, DATA8, DATA7, DATA6, DATA5, DATA4 DATA3, DATA2, DATA1, DATA0, ADDR19, ADDR18 ADDR17, ADDR16, ADDR15, ADDR14, ADDR13 ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, ADDR7 ADDR6, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1
Table Maximum Duty Cycle Input Transient Voltage1
-0.50 -0.70 -0.80 -0.90 -1.00
(V)2 +3.80 +4.00 +4.10 +4.20 +4.30
Maximum Duty Cycle
Applies signal balls with exception CLKIN, XTAL, VROUT/ EXT_WAKE1. Only listed options apply particular design.
When programming memory ADSP-BF522/ ADSP-BF524/ADSP-BF526 processors, VPPOTP ball must write value specified Preliminary Operating Conditions
Rev.
Page
April 2009
Table Total Current Groups
Group Pins Group ABE1, ABE0, SA10, SWE, SCAS, SRAS SMS, SCKE, ARDY, AWE, ARE, AMS3, AMS2, AMS1, AMS0, CLKOUT
SENSITIVITY
(electrostatic discharge) sensitive device. Charged devices circuit boards discharge without detection. Although this product features patented proprietary protection circuitry, damage occur devices subjected high energy ESD. Therefore, proper precautions should taken avoid performance degradation loss functionality.
PACKAGE INFORMATION
information presented Figure Table provides details about package branding ADSP-BF52x processors. complete listing product availability, Ordering Guide Page
ADSP-BF52x tppZccc vvvvvv.x yyww country_of_origin
Figure Product Information Package
Table Package Brand Information
Brand ADSP-BF52x vvvvvv.x yyww
Field Description Product Name1 Temperature Range Package Type RoHS Compliant Designation Ordering Guide Assembly Code Silicon Revision Date Code
product names Ordering Guide Page
Rev.
Page
April 2009
TIMING SPECIFICATIONS
direct implied specifications references Blackfin processors preliminary subject change.
Clock Reset Timing
Table Figure describe clock reset operations. CCLK SCLK timing specifications Table Table combinations CLKIN clock multipliers must select core/peripheral clocks excess processor's maximum instruction rate. Table Clock Reset Timing
Parameter Timing Requirements tCKIN CLKIN Period tCKINL CLKIN Pulse1 tCKINH CLKIN High Pulse1 tWRST RESET Asserted Pulse Width Low2 Switching Characteristic tBUFDLAY CLKIN CLKBUF Delay
20.0 10.0 10.0 tCKIN
100.0
Unit
Applies bypass mode non-bypass mode. Applies after power-up sequence complete. power-up, processor's internal phase-locked loop requires more than 2000 CLKIN cycles, while RESET asserted, assuming stable power supplies CLKIN (not including start-up time external clock oscillator).
tCKIN
CLKIN
tCKINL
tCKINH tBUFDLAY tBUFDLAY
CLKBUF
tWRST
RESET
Figure Clock Reset Timing
Rev.
Page
April 2009
Asynchronous Memory Read Cycle Timing
Table Asynchronous Memory Read Cycle Timing
VDDMEM VDDMEM 2.5/3.3
Parameter Timing Requirements tSDAT DATA15-0 Setup Before CLKOUT tHDAT DATA15-0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics Output Delay After CLKOUT1 Output Hold After CLKOUT
Unit
Output balls include AMS3-0, ABE1-0, ADDR19-1, AOE, ARE.
SETUP CYCLES
PROGRAMMED READ ACCESS CYCLES
ACCESS EXTENDED CYCLES
HOLD CYCLE
CLKOUT
AMSx
ABE1-0
ADDR19-1
ABE, ADDRESS
tSARDY
ARDY
tHARDY tHARDY
tSARDY
tSDAT tHDAT
DATA15-0
READ
Figure Asynchronous Memory Read Cycle Timing
Rev.
Page
April 2009
Asynchronous Memory Write Cycle Timing
Table Asynchronous Memory Write Cycle Timing
VDDMEM VDDMEM 2.5/3.3
Parameter Timing Requirements tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDDAT DATA15-0 Disable After CLKOUT tENDAT DATA15-0 Enable After CLKOUT Output Delay After CLKOUT1 Output Hold After CLKOUT
Unit
Output balls include AMS3-0, ABE1-0, ADDR19-1, DATA15-0, AOE, AWE.
SETUP CYCLES
PROGRAMMED WRITE ACCESS CYCLES
ACCESS EXTENDED CYCLE
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ABE, ADDRESS
SARDY
ARDY
HARDY
tSARDY ENDAT
DATA15-0 WRITE DATA
DDAT
Figure Asynchronous Memory Write Cycle Timing
Rev.
Page
April 2009
NAND Flash Controller Interface Timing
Table Figure Page through Figure Page describe NAND Flash Controller Interface operations. Table NAND Flash Controller Interface Timing
Parameter Write Cycle Switching Characteristics tCWL ND_CE Setup Time ND_CE Hold Time From High tCLEWL ND_CLE Setup Time tCLH ND_CLE Hold Time From high tALEWL ND_ALE Setup Time tALH ND_ALE Hold Time From High tWP1 high tWHWL High tWC1 tDWS1 Data Setup Time Write Access tDWH Data Hold Time Write Access Read Cycle Switching Characteristics tCRL ND_CE Setup Time tCRH ND_CE Hold Time From High High tRHRL High tRC1 Timing Requirements tDRS Data Setup Time Read Transaction tDRH Data Hold Time Read Transaction Write Followed Read Switching Characteristics tWHRL High
Unit
tSCLK tSCLK tSCLK tSCLK (WR_DLY +1.0) tSCLK tSCLK (WR_DLY +5.0) tSCLK (WR_DLY +1.5) tSCLK tSCLK
tSCLK tSCLK (RD_DLY +1.0) tSCLK tSCLK (RD_DLY +5.0) tSCLK 8.02
tSCLK
WR_DLY RD_DLY defined NFC_CTL register. only parameter that differs from 1.8V 2.5/3.3V operation tDRS, which 8.0ns 2.5/3.3V 11ns 1.8V.
tCWL ND_CE
ND_CLE tCLEWL tALEWL ND_ALE
tCLH tALH
tDWS ND_D0-D7
tDWH
Figure NAND Flash Controller Interface Timing Command Write Cycle
Rev.
Page
April 2009
tCWL ND_CE tCLEWL ND_CLE
ND_ALE tALEWL tDWS tDWH tDWS tDWH tALH tWHWL tALEWL tALH
ND_D0-D7
Figure NAND Flash Controller Interface Timing Address Write Cycle
tCWL
ND_CE tCLEWL ND_CLE tALEWL ND_ALE
tWHWL
tDWS tDWH
tDWS
tDWH
ND_D0-D7
Figure NAND Flash Controller Interface Timing Data Write Operation
Rev.
Page
April 2009
tCRL
tCRH
ND_CE
ND_CLE
ND_ALE
tRHRL
tDRS ND_D0-D7
tDRH
tDRS
tDRH
Figure NAND Flash Co
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