+3.3V, Low-Jitter Crystal LVPECL Clock Generator Crystal Oscillat

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+3.3V, Low-Jitter Crystal LVPECL Clock Generator Crystal Oscillat

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19-4858; 8/09
+3.3V, Low-Jitter Crystal LVPECL Clock Generator
Crystal Oscillator Interface: 25MHz CMOS Input: 25MHz Output Frequencies Ethernet 62.5MHz, 125MHz, 156.25MHz, 312.5MHz Jitter 0.14psRMS (1.875MHz 20MHz) 0.36psRMS (12kHz 20MHz) Excellent Power-Supply Noise Rejection External Loop Filter Capacitor Required
MAX3679A
MAX3679A low-jitter precision clock generator with integration three LVPECL LVCMOS outputs optimized Ethernet applications. device integrates crystal oscillator phase-locked loop (PLL) clock multiplier generate high-frequency clock outputs Ethernet applications. Maxim's proprietary design features ultra-low jitter (0.36psRMS) excellent power-supply noise rejection, minimizing design risk network equipment.
Applications
Ethernet Networking Equipment
Ordering Information
PART MAX3679AETJ+ TEMP RANGE -40°C +85°C PIN-PACKAGE TQFN-EP*
Configuration appears data sheet.
+Denotes lead(Pb)-free/RoHS-compliant package. Exposed pad.
Typical Application Circuit
+3.3V 10.5 0.1F 0.1F 0.1F 0.01F 0.1F
VCCA 0.1F REF_IN IN_SEL QAC_OE QA_OE QB0_OE QB1_OE BYPASS SELA1 SELA0 SELB1 SELB0 RES1 RES0 X_OUT
VCCO_A
VCCO_B
VDDO_A QA_C 125MHz 125MHz
ASIC
ASIC
(VCC
MAX3679A
312.5MHz
ASIC
(VCC X_IN GNDO_A 312.5MHz (VCC ASIC
25MHz 18pF) 33pF 27pF
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim Direct 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
+3.3V, Low-Jitter Crystal LVPECL Clock Generator MAX3679A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range VCC, VCCA, VDDO_A, VCCO_A, VCCO_B .-0.3V +4.0V Voltage Range REF_IN, IN_SEL, SELA[1:0], SELB[1:0], RES[1:0], QAC_OE, QA_OE, QB0_OE, QB1_OE, BYPASS .-0.3V (VCC 0.3V) Voltage Range X_IN .-0.3V +1.2V Voltage Range GNDO_A.-0.3V +0.3V Voltage Range X_OUT .-0.3V (VCC 0.6V) Current into QA_C .±50mA Current into QB0, QB0, QB1, .-56mA Continuous Power Dissipation +70°C) 32-Pin TQFN (derate 34.5mW/°C above +70°C) .2759mW Operating Junction Temperature Range .-55°C +150°C Storage Temperature Range .-65°C +160°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC +3.0V +3.6V, -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C, unless otherwise noted.) (Notes
PARAMETER Power-Supply Current SYMBOL (Note CONDITIONS UNITS
CONTROL INPUT CHARACTERISTICS (SELA[1:0], SELB[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, BYPASS Pins) Input Capacitance Input Pulldown Resistor Input Logic Bias Resistor Input Pullup Resistor RPULLDOWN RBIAS RPULLUP Pins SELA[1:0], SELB[1:0], QB0_OE Pins QAC_OE, QA_OE, QB1_OE, IN_SEL, BYPASS 1.13 1.18 1.85 1.90 0.72
LVPECL OUTPUT SPECIFICATIONS (QA, QB0, QB0, QB1, Pins) +85°C Output High Voltage -40°C +85°C Output Voltage -40°C Peak-to-Peak Output-Voltage Swing (Single-Ended) Clock Output Rise/Fall Time Output Duty-Cycle Distortion (Note (Note enabled bypassed (Note 0.98 0.83 0.83 1.55 1.55 VP-P
LVCMOS/LVTTL INPUT SPECIFICATIONS (SELA[1:0], SELB[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, BYPASS Pins) Input-Voltage High Input-Voltage
+3.3V, Low-Jitter Crystal LVPECL Clock Generator
ELECTRICAL CHARACTERISTICS (continued)
(VCC +3.0V +3.6V, -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C, unless otherwise noted.) (Notes
PARAMETER Input High Current Input Current SYMBOL enabled bypassed enabled -240 QA_C sourcing 12mA QA_C sinking 12mA (Notes enabled bypassed (Note RJRMS 12kHz 20MHz 1.875MHz 20MHz LVPECL output (Notes LVPECL output LVCMOS output 0.36 0.14 Between Output Skew Between QB1, PECL outputs 1kHz 10kHz Clock Output Phase Noise 125MHz (Note 100kHz 1MHz 10MHz -124 -125 -130 -145 -153 dBc/Hz psRMS psP-P 1000 CONDITIONS UNITS
MAX3679A
REF_IN SPECIFICATIONS (Input AC-Coupled) Reference Clock Frequency Input-Voltage High Input-Voltage Input High Current Input Current Reference Clock Duty Cycle Input Capacitance QA_C SPECIFICATIONS Output High Voltage Output Voltage Output Rise/Fall Time Output Duty-Cycle Distortion Output Impedance CLOCK OUTPUT SPECIFICATIONS Frequency Range Random Jitter (Note Deterministic Jitter Supply Noise Spurs Induced Power-Supply Noise (Notes Nonharmonic Subharmonic Spurs
Note
series resistor 10.5 allowed between VCCA filtering supply noise when system power-supply tolerance 3.3V ±5%. Figure
+3.3V, Low-Jitter Crystal LVPECL Clock Generator MAX3679A
ELECTRICAL CHARACTERISTICS (continued)
(VCC +3.0V +3.6V, -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C, unless otherwise noted.) (Notes Guaranteed 320MHz LVPECL output. Guaranteed 160MHz LVCMOS output. outputs enabled unloaded. IN_SEL high. Measured with crystal AC-coupled, duty-cycle signal REF_IN. Measured using setup shown Figure with 3.3V ±5%. Measured with crystal source. Total including random deterministic jitter. Measured with Agilent DSO81304A 40GS/s real-time oscilloscope using sample record length. Note Measured with 40mVP-P, 100kHz sinusoidal signal supply. Note Measured 156.25MHz output. Note Measured with 25MHz crystal 25MHz reference clock LVCMOS input with slew rate 0.5V/ns greater. Note Note Note Note Note Note Note
MAX3679A
QA_C
4.7pF
0.1F
OSCILLOSCOPE
Figure LVCMOS Output Measurement Setup
+3.3V, Low-Jitter Crystal LVPECL Clock Generator
Typical Operating Characteristics
(Typical values +3.3V, +25°C, crystal frequency 25MHz.)
MAX3679A
SUPPLY CURRENT TEMPERATURE
MAX3679A toc01
DIFFERENTIAL OUTPUT WAVEFORM 156.25MHz (LVPECL OUTPUT)
MAX3679A toc02
OUTPUT WAVEFORM 125MHz (LVCMOS OUTPUT)
MAX3679A toc03
SUPPLY CURRENT (mA) OUTPUTS ACTIVE UNTERMINATED OUTPUTS ACTIVE TERMINATED
MEASURED USING OSCILLOSCOPE INPUT THROUGH NETWORK SHOWN FIGURE AMPLITUDE (200mV/div) AMPLITUDE (50mV/div)
1ns/div
1ns/div
AMBIENT TEMPERATURE (°C)
PHASE NOISE 312.5MHz CLOCK FREQUENCY
MAX3679A toc04
PHASE NOISE 125MHz CLOCK FREQUENCY
-100 -110 -120 -130 -140 -150 -160
MAX3679A toc05
NOISE POWER DENSITY (dBc/Hz) -100 -110 -120 -130 -140 -150 -160
NOISE POWER DENSITY (dBc/Hz)
1000 10,000 100,000
1000 10,000 100,000
OFFSET FREQUENCY (kHz)
OFFSET FREQUENCY (kHz)
JITTER HISTOGRAM (312.5MHz OUTPUT, 40mVP-P SUPPLY NOISE 100kHz)
MAX3679A toc06
NOISE SPUR AMPLITUDE NOISE FREQUENCY
SPUR AMPLITUDE (dBc) 1000 10,000 156.25MHz NOISE AMPLITUDE 40mVP-P
MAX3679A toc07
5.0psP-P
5ps/div
NOISE FREQUENCY (kHz)
+3.3V, Low-Jitter Crystal LVPECL Clock Generator MAX3679A
Description
NAME VCCO_B QB0_OE SELB1, SELB0 QAC_OE GNDO_A QA_C VDDO_A VCCO_A BYPASS RES1 RES0 VCCA QA_OE SELA0, SELA1 QB1_OE X_OUT X_IN REF_IN IN_SEL Supply Ground LVCMOS/LVTTL Input. Enables/disables clock output. Connect high enable LVPECL clock output QB0. Connect logic internal input impedance. LVCMOS/LVTTL Input. Controls divider setting. more information. input impedance. Table FUNCTION Power Supply Clock Outputs. Connect +3.3V.
LVCMOS/LVTTL Input. Enables/disables QA_C clock output. Connect high enable QA_C. Connect QA_C high-impedance state. internal pullup VCC. LVCMOS/LVTTL Input. Master reset input. Pulse high reset dividers. internal pulldown GND. required normal operation. Ground QA_C Output. Connect supply ground. LVCMOS Clock Output Power Supply QA_C Clock Output. Connect +3.3V. Power Supply Clock Output. Connect +3.3V. Noninverting Clock Output, LVPECL Inverting Clock Output, LVPECL LVCMOS/LVTTL Input (Active Low). Connect bypass internal PLL. Connect high normal operation. When bypass mode output dividers divide internal pullup VCC. Internally Connected. Connect GND, VCC, leave open normal operation. Reserved Test. Connect normal operation. Analog Power Supply VCO. Connect +3.3V. additional power-supply noise filtering, this connect through 10.5 shown Figure (requires +3.3V ±5%). Core Power Supply. Connect +3.3V. LVCMOS/LVTTL Input. Enables/disables clock output. Connect this high enable LVPECL clock output Connect logic internal pullup VCC. LVCMOS/LVTTL Input. Controls divider setting. Table more information. input impedance. LVCMOS/LVTTL Input. Enables/disables clock output. Connect high enable LVPECL clock output QB1. Connect logic internal input impedance. Crystal Oscillator Output Crystal Oscillator Input LVCMOS Reference Clock Input. Self-biased allow DC-coupling. LVCMOS/LVTTL Input. Connect high leave open crystal. Connect REF_IN. internal pullup VCC. LVPECL, Inverting Clock Output LVPECL, Noninverting Clock Output LVPECL, Inverting Clock Output LVPECL, Noninverting Clock Output Exposed Pad. Connect supply ground proper electrical thermal performance.
+3.3V, Low-Jitter Crystal LVPECL Clock Generator
Detailed Description
MAX3679A low-jitter clock generator designed operate Ethernet frequencies. consists onchip crystal oscillator, PLL, programmable dividers, LVCMOS output buffer, LVPECL output buffers. Using low-frequency clock (crystal CMOS input) reference, internal generates high-frequency output clock with excellent jitter performance.
LVCMOS Driver
QA_C, LVCMOS output, designed drive single-ended high-impedance load. maximum operating frequency specified 160MHz. This output disabled QAC_OE used goes high impedance when disabled.
MAX3679A
Reset Logic/POR
During power-on, power-on reset (POR) signal generated synchronize dividers. external master reset (MR) signal required.
Crystal Oscillator
integrated oscillator provides low-frequency reference clock PLL. This oscillator requires external crystal connected between X_IN X_OUT. Crystal frequency 25MHz.
Applications Information
Power-Supply Filtering
MAX3679A mixed analog/digital contains analog circuitry susceptible random noise. addition excellent on-chip power-supply noise rejection, MAX3679A provides separate powersupply pin, VCCA, circuitry. Figure illustrates recommended power-supply filter network purpose this design technique ensure clean input power supply circuitry improve overall immunity power-supply noise. This network requires that power supply +3.3V ±5%. Decoupling capacitors should used other supply pins best performance.
REF_IN Buffer
LVCMOS-compatible clock source connected REF_IN serve reference clock. LVCMOS REF_IN buffer internally biased allow DC-coupling. designed operate 320MHz.
takes signal from crystal oscillator reference clock input synthesizes low-jitter, highfrequency clock. contains phase-frequency detector (PFD), lowpass filter, 625MHz voltagecontrolled oscillator (VCO). output connected input through feedback divider. compares reference frequency divideddown output (fVCO/25) generates control signal that keeps locked reference clock. high-frequency output clock sent output dividers. minimize noise-induced jitter, supply (VCCA) isolated from core logic output buffer supplies.
Output Divider Configuration
Table shows input settings required output dividers. Leakage OPEN case must less than 1µA. Note that when MAX3679A bypass mode (BYPASS low), output dividers automatically divide
Output Dividers
output divider programmable allow range output frequencies. Table divider input settings. output dividers automatically divide when MAX3679A bypass mode (BYPASS
+3.3V
0.1F 10.5 VCCA
LVPECL Drivers
high-frequency outputs-QA, QB0, QB1-are differential PECL buffers designed drive transmission lines terminated with 2.0V. maximum operating frequency specified 320MHz. Each output individually disabled, used. outputs logic when disabled.
0.1F
Figure Analog Supply Filtering
+3.3V, Low-Jitter Crystal LVPECL Clock Generator MAX3679A
Table Output Frequency Determination
CMOS INPUT FREQUENCY (MHz) FEEDBACK DIVIDER, FREQUENCY (MHz) OUTPUT DIVIDER, OUTPUT FREQUENCY (MHz) 312.5 156.25 62.5 Ethernet APPLICATIONS
Table Output Divider Configuration
INPUT SELA1/SELB1 SELA0/SELB0 OPEN NA/NB DIVIDER
Table Crystal Selection Parameters
PARAMETER Crystal Oscillation Frequency Shunt Capacitance Load Capacitance Equivalent Series Resistance (ESR) Maximum Crystal Drive Level SYMBOL UNITS
*Maximum guaranteed output frequency 160MHz CMOS 320MHz LVPECL output.
27pF X_IN 25MHz CRYSTAL 18pF) X_OUT 33pF
Figure Crystal, Capacitors Connection
Crystal Input Layout Frequency Stability
crystal, trace, external capacitors should placed board close possible MAX3679A's X_IN X_OUT pins reduce crosstalk active signals into oscillator. layout shown Figure gives approximately trace plus footprint capacitors side crystal (Y1). dielectric material dielectric thickness reference board mils. Using 25MHz crystal capacitor values 27pF 33pF, measured output frequency accuracy -14ppm +25°C ambient temperature.
Figure Crystal Layout
Crystal Selection
crystal oscillator designed drive fundamental mode, AT-cut crystal resonator. Table recommended crystal specifications. Figure external capacitance connection.
+3.3V, Low-Jitter Crystal LVPECL Clock Generator
Interfacing with LVPECL Outputs
equivalent LVPECL output circuit given Figure These outputs designed drive pair transmission lines terminated with separate termination voltage (VTT) available, other termination methods used such shown Figures Unused outputs should disabled left open. more information LVPECL terminations interface with other logic families, refer Application Note 291: HFAN-01.0: Introduction LVDS, PECL, CML.
MAX3679A
+3.3V
Interface Models
Figures show examples interface models.
HIGH IMPEDANCE
MAX3679A
Figure Thevenin Equivalent Standard PECL Termination
0.1F HIGH IMPEDANCE STRUCTURES
0.1F
MAX3679A
Figure Simplified LVPECL Output Circuit Schematic
NOTE: AC-COUPLING OPTIONAL.
Figure AC-Coupled PECL Termination
VDDO_A
DISABLE
1.4V 14.5k REF_IN QA_C
STRUCTURES STRUCTURES
Figure Simplified REF_IN Circuit Schematic
Figure Simplified LVCMOS Output Circuit Schematic
+3.3V, Low-Jitter Crystal LVPECL Clock Generator MAX3679A
Layout Considerations
inputs outputs critical paths MAX3679A, care should taken minimize discontinuities these transmission line. Here some suggestions maximizing MAX3679A's performance: uninterrupted ground plane should positioned beneath clock I/Os. Ground vias should placed close input/output interfaces allow return current path MAX3679A receive devices. Supply decoupling capacitors should placed close MAX3679A supply pins. Maintain differential single-ended) transmission line impedance MAX3679A. good high-frequency layout techniques multilayer board with uninterrupted ground plane minimize crosstalk. Refer MAX3679A Evaluation more information.
VIEW
Configuration
REF_IN IN_SEL X_IN X_OUT QB1_OE SELA1 SELA0 QA_OE VCCA QA_C VDDO_A VCCO_A BYPASS RES1 RES0
VCCO_B QB0_OE SELB1 SELB0 QAC_OE GNDO_A
MAX3679A
Exposed-Pad Package
exposed 32-pin TQFN package provides very inductance path return current traveling ground plane. also electrical ground MAX3679A must soldered circuit board ground proper electrical performance.
THIN (5mm 5mm)
*EXPOSED CONNECTED GROUND.
Chip Information
TRANSISTOR COUNT: 10,780 PROCESS: BiCMOS
+3.3V, Low-Jitter Crystal LVPECL Clock Generator
Block Diagram
IN_SEL BYPASS SELA[1:0]
MAX3679A
QAC_OE LVCMOS BUFFER DIVIDER LVPECL BUFFER LVCMOS REF_IN 27pF X_IN 25MHz X_OUT 33pF DIVIDERS: LVPECL BUFFER CRYSTAL OSCILLATOR DIVIDER FILTER 625MHz LVPECL BUFFER QB1_OE QB0_OE
QA_C
QA_OE
MAX3679A
SELB[1:0]
Package Information
latest package outline information land patterns, www.maxim-ic.com/packages. PACKAGE TYPE TQFN-EP PACKAGE CODE T3255+3 DOCUMENT 21-0140
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2009 Maxim Integrated Products Maxim registered trademark Maxim Integrated Products, Inc.

+3.3V, Low-Jitter Crystal LVPECL Clock Generator Crystal Oscillat

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