dual UART, Mbit/s (max.), with 16-byte FIFOs mode interface Rev.
|
|
|
Top Searches for this datasheet
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs mode interface
Rev. October 2009 Product data sheet
SC68C2550B channel Universal Asynchronous Receiver Transmitter (UART) used serial data communications. principal function convert parallel data into serial data vice versa. UART handle serial data rates Mbit/s. SC68C2550B provides enhanced UART functions with 16-byte FIFOs, modem control interface, mode data transfer. mode data transfer controlled FIFO trigger levels TXRDYn RXRDYn signals. On-board status registers provide user with error indications operational status. System interrupts modem control features tailored software meet specific user requirements. internal loopback capability allows on-board diagnostics. Independent programmable baud rate generators provided select transmit receive baud rates. SC68C2550B operates industrial temperature range, available plastic LQFP48 package.
Features
channel UART with mode (Motorola) interface operation tolerant input only pins1 Industrial temperature range Mbit/s data rate Mbit/s 16-byte transmit FIFO reduce bandwidth requirement external 16-byte receive FIFO with error flags reduce bandwidth requirement external Independent transmit receive UART control Four selectable Receive FIFO interrupt trigger levels Software selectable baud rate generator Standard asynchronous error framing bits (Start, Stop, Parity Overrun Break) Transmit, Receive, Line Status, Data interrupts independently controlled Fully programmable character formatting: 8-bit characters Even, odd, no-parity formats 11/2, 2-stop Baud generation Mbit/s) False start-bit detection
data pins Table "Limiting values".
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Complete status reporting capabilities 3-state output drive capabilities bidirectional data control Line break generation detection Internal diagnostic capabilities: Loopback controls communications link fault isolation Prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR,
Ordering information
Table Ordering information Package Name SC68C2550BIB48 LQFP48 Description plastic profile quad flat package; leads; body Version SOT313-2 Type number
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Block diagram
SC68C2550B
TRANSMIT FIFO REGISTER RESET DATA CONTROL LOGIC TRANSMIT SHIFT REGISTER
TXA,
INTERCONNECT LINES CONTROL SIGNALS
RECEIVE FIFO REGISTER
RECEIVE SHIFT REGISTER
RXA,
REGISTER SELECT LOGIC
DTRA, DTRB RTSA, RTSB OP2A, OP2B MODEM CONTROL LOGIC
TXRDYA, TXRDYB RXRDYA, RXRDYB
INTERRUPT CONTROL LOGIC
CLOCK BAUD RATE GENERATOR
CTSA, CTSB RIA, CDA, DSRA, DSRB
002aab334
XTAL1
XTAL2
Block diagram SC68C2550B
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Pinning information
Pinning
TXRDYA
DSRA
CTSA
TXRDYB OP2B
n.c. RESET DTRB DTRA RTSA OP2A RXRDYA n.c. n.c.
002aab335
SC68C2550BIB48
n.c. XTAL1 XTAL2 RXRDYB DSRB RTSB CTSB
configuration LQFP48
description
Table Symbol description Type Description Address select bit. Internal register address selection. Address select bit. Internal register address selection. Address select bit. Internal register address selection. Address used select Channel Channel logic selects Channel logic HIGH selects Channel (See Table Carrier Detect (active LOW). These inputs associated with individual UART channels through logic this indicates that carrier been detected modem that channel. Chip Select (active LOW). This enables data transfers between user SC68C2550B channel(s) addressed. Individual UART sections addressed Table Clear Send (active LOW). These inputs associated with individual UART channels, through logic CTSn indicates modem data ready accept transmit data from SC68C2550B. Status tested reading MSR[4]. This effect UART's transmit receive operation.
CTSA CTSB
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Table Symbol DSRA DSRB
description .continued Type Data Ready (active LOW). These inputs associated with individual UART channels, through logic this indicates modem data powered-on ready data exchange with UART. This effect UART's transmit receive operation. Data Terminal Ready (active LOW). These outputs associated with individual UART channels, through logic this indicates that SC68C2550B powered-on ready. This controlled modem control register. Writing logic MCR[0] will DTRn output logic enabling modem. This will logic after writing logic MCR[0], after reset. This effect UART's transmit receive operation. Signal power ground. Interrupt Request. Interrupts from UART channels wire-ORed internally function single interrupt. This transitions logic enabled interrupt enable register) whenever UART channel(s) requires service. Individual channel interrupt status determined addressing each channel through associated internal register, using external pull-up resistor must connected between this VCC. Output (user-defined). This function associated with individual channels state these pins defined user through software settings MCR[3]. OP2A/OP2B logic when MCR[3] logic OP2A/OP2B logic when MCR[3] logic output these pins HIGH after reset. logic this will transfer contents data (D[7:0]) from external internal register that defined address bits A[2:0]. logic HIGH this will load contents internal register defined address bits A[2:0] SC68C2550B data (D[7:0]) access external CPU. Reset (active LOW). logic this will reset internal registers outputs. UART transmitter output receiver input will disabled during reset time. (See Section 7.10 "SC68C2550B external reset condition" initialization details.) Ring Indicator (active LOW). These inputs associated with individual UART channels, through logic this indicates modem received ringing signal from telephone line. logic transition this input will generate interrupt. Request Send (active LOW). These outputs associated with individual UART channels, through logic RTSn indicates transmitter data ready waiting send. Writing logic modem control register MCR[1] will this logic indicating data available. After reset this will logic This effect UART's transmit receive operation. Receive data These inputs associated with individual serial channel data SC68C2550B receive input circuits, A-B. signal will logic during reset, idle data), when transmitter disabled. During local Loopback mode, input disabled transmit data connected UART receive input, internally. Description Data (bidirectional). These pins 8-bit, 3-state data transferring information from controlling CPU. least significant first data transmit receive serial data stream.
DTRA DTRB
OP2A OP2B
RESET
RTSA RTSB
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Table Symbol RXRDYA RXRDYB
description .continued Type Description Receive Ready (active LOW). These outputs provide receive FIFO/RHR status individual receive channels (A-B). RXRDYn primarily intended monitoring mode transfers receive data FIFOs. logic indicates there receive data read/upload, that receive ready status with more receive characters available FIFO/RHR. This logic when FIFO/RHR empty when programmed trigger level been reached. This signal also used single mode transfers (DMA mode Transmit data These outputs associated with individual serial transmit channel data from SC68C2550B. will logic during reset, idle data), when transmitter disabled. During local Loopback mode, output disabled transmit data internally connected UART receive input. Transmit Ready (active LOW). These outputs provide FIFO/THR status individual transmit channels (A-B). TXRDYn primarily intended monitoring mode transfers transmit data FIFOs. individual channel's TXRDYA, TXRDYB buffer ready status indicated logic that lease location empty available FIFO THR. This goes logic (DMA mode when there more empty locations FIFO THR. This signal also used single mode transfers (DMA mode Power supply input Crystal external clock input. Functions crystal input external clock input. crystal connected between this XTAL2 form internal oscillator circuit. Alternatively, external clock connected this provide custom data rates. (See Section "Programmable baud rate generator".) Figure Output crystal oscillator buffered clock. (See also XTAL1.) Crystal oscillator output buffered clock output. Should left open external clock connected XTAL1. extended frequency operation, this should tied resistor. connected
TXRDYA TXRDYB
XTAL1
XTAL2
n.c.
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Functional description
SC68C2550B provides serial asynchronous receive data synchronization, parallel-to-serial serial-to-parallel data conversions both transmitter receiver sections. These functions necessary converting serial data stream into parallel data that required with digital data systems. Synchronization serial data stream accomplished adding start stop bits transmit data form data character (character orientated protocol). Data integrity insured attaching parity data character. parity checked receiver transmission errors. electronic circuitry provide these functions fairly complex, especially when manufactured single integrated silicon chip. SC68C2550B represents such integration with greatly enhanced features. SC68C2550B fabricated with advanced CMOS process. SC68C2550B upward solution that provides dual UART capability with bytes transmit receive FIFO memory. SC68C2550B designed work with high speed modems shared network environments that require fast data processing time. Increased performance realized SC68C2550B transmit receive FIFOs. This allows external processor handle more networking tasks within given time. example, ST16C2450 without receive FIFO, will require unloading microseconds (this example uses character length bits, including start/stop bits 115.2 kbit/s). This means external will have service receive FIFO less than every microseconds. However, with 16-byte FIFO SC68C2550B, data buffer will require unloading/loading 1.53 This increases service interval, giving external additional time other applications reducing overall UART interrupt servicing time. addition, four selectable receive FIFO trigger interrupt levels uniquely provided maximum data throughput performance especially when operating multi-channel environment. FIFO memory greatly reduces bandwidth requirement external controlling CPU, increases performance, reduces power consumption. SC68C2550B capable operation Mbit/s with clock. With crystal external clock input 7.3728 MHz, user select data rates 460.8 kbit/s. rich feature SC68C2550B available through internal registers. Selectable receive FIFO trigger levels, selectable transmit receive baud rates, modem interface controls standard features.
UART functions
UART provides user with capability bidirectionally transfer information between external CPU, SC68C2550B package, external serial device. logic chip select (LOW HIGH) allows user configure, send data, and/or receive data UART channels Individual channel select functions shown Table
Table
SC68C2550B_3
Channel selection using UART select none channel channel
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Internal registers
SC68C2550B provides sets internal registers consisting registers each monitoring controlling functions each channel UART. These registers shown Table UART registers function data holding registers (THR/RHR), interrupt status control registers (IER/ISR), FIFO control register (FCR), line status control registers (LCR/LSR), modem status control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), user accessible scratchpad register (SPR).
Table
Internal registers decoding Read mode Receive Holding Register Interrupt Enable Register Interrupt Status Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register (DLL/DLM)[2] Divisor Latch Divisor Latch Divisor Latch Divisor Latch Write mode Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register Scratchpad Register
General register (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)[1]
Baud rate register
These registers accessible only when LCR[7] logic These registers accessible only when LCR[7] logic
FIFO operation
byte transmit receive data FIFOs enabled FIFO Control Register (FCR) user receive trigger level FCR[7:6], transmit trigger level. receiver FIFO section includes time-out function ensure data delivered external CPU. interrupt generated whenever Receive Holding Register (RHR) been read following loading character receive trigger level been reached.
Table Flow control mechanism activation
Selected trigger level (characters)
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Hardware/software time-out interrupts
interrupts enabled IER[3:0]. Care must taken when handling these interrupts. Following reset, Interrupt Enable Register (IER) SC68C2550B will issue Transmit Holding Register interrupt. This interrupt must serviced prior continuing operations. register provides current singular highest priority interrupt only. condition exist where higher priority interrupt mask lower priority interrupt(s). Only after servicing higher pending interrupt will lower priority interrupt(s) reflected status register. Servicing interrupt without investigating further interrupt conditions result data errors. When interrupt conditions have same priority, important service these interrupts correctly. Receive Data Ready Receive Time-Out have same interrupt priority (when enabled IER[0]). receiver issues interrupt after number characters have reached programmed trigger level. this case, SC68C2550B FIFO hold more characters than programmed trigger level. Following removal data byte, user should re-check LSR[0] additional characters. Receive Time-Out will occur receive FIFO empty. time-out counter reset center each stop received each time receive holding register (RHR) read. actual time-out value character time, including data information length, start bit, parity bit, size stop bit, that times.
Programmable baud rate generator
SC68C2550B supports high speed modem technologies that have increased input data rates employing data compression schemes. example, 33.6 kbit/s modem that employs data compression require 115.2 kbit/s input data rate. 128.0 kbit/s ISDN modem that supports data compression need input data rate 460.8 kbit/s. SC68C2550B support standard data rate 921.6 kbit/s. single baud rate generator provided transmitter receiver, allowing independent transmit/receive channel control. programmable Baud Rate Generator (BRG) capable operating with frequency MHz. obtain maximum data rate, necessary full rail swing clock input. SC68C2550B configured internal external clock operation. internal clock oscillator operation, industry standard microprocessor crystal connected externally between XTAL1 XTAL2 pins. Alternatively, external clock connected XTAL1 clock internal baud rate generator standard custom rates (see Table generator divides input clock divisor from (216 SC68C2550B divides basic external clock basic clock provides table rates support standard custom applications using same system design. rate table configured internal register functions. Customized baud rates achieved selecting proper divisor values sections baud rate generator. Programming baud rate generator registers (MSB) (LSB) provides user capability selecting desired final baud rate. example Table shows selectable baud rate table available when using 1.8432 external clock input.
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
XTAL1
XTAL2
1.8432
002aab325
Table
Crystal oscillator connection Baud rate generator programming table using 1.8432 clock Output clock divisor (decimal) 2304 1536 1047 Output clock divisor (HEX) program value (HEX) program value (HEX)
Output baud rate 1200 2400 3600 4800 7200 9600 19.2 38.4 57.6 115.2
operation
SC68C2550B FIFO trigger level provides additional flexibility user block mode operation. LSR[6:5] provide indication when transmitter empty empty location(s). user optionally operate transmit receive FIFOs mode (FCR[3]). When transmit receive FIFOs enabled mode de-activated (DMA Mode SC68C2550B activates interrupt output each data transmit receive operation. When mode activated (DMA Mode user takes advantage block mode operation loading unloading FIFO block sequence determined receive trigger level transmit FIFO. this mode, SC68C2550B sets TXRDYn RXRDYn) output when characters transmit FIFO below characters receive FIFOs above receive trigger level.
SC68C2550B_3 B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Loopback mode
internal loopback capability allows on-board diagnostics. Loopback mode, normal modem interface pins disconnected reconfigured loopback internally (see Figure MCR[3:0] register bits used controlling loopback diagnostic testing. Loopback mode, transmitter output (TXn) receiver input (RXn) disconnected from their associated interface pins, instead connected together internally. CTSn, DSRn, CDn, pins disconnected from their normal modem control inputs pins, instead connected internally MCR[1] RTS, MCR[0] DTR, MCR[3] (OP2) MCR[2] (OP1). Loopback test data entered into transmit holding register user data interface, transmit UART serializes data passes serial data receive UART internal loopback connection. receive UART converts serial data back into parallel data that then made available user data interface user optionally compares received data initial transmitted data verifying error-free operation UART transmit/receive circuits. this mode, receiver transmitter interrupts fully operational. Modem Control Interrupts also operational.
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
SC68C2550B
TRANSMIT FIFO REGISTERS RESET DATA CONTROL LOGIC MCR[4] TRANSMIT SHIFT REGISTER
TXA,
INTERCONNECT LINES CONTROL SIGNALS
RECEIVE FIFO REGISTERS
RECEIVE SHIFT REGISTER
RXA,
REGISTER SELECT LOGIC
RTSA, RTSB
CTSA, CTSB DTRA, DTRB MODEM CONTROL LOGIC TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK BAUD RATE GENERATOR
DSRA, DSRB (OP1A, OP1B)
RIA, (OP2A, OP2B)
CDA,
002aab336
XTAL1 XTAL2
Internal Loopback mode diagram
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Register descriptions
Table details assigned functions SC68C2550B internal registers. assigned functions more fully defined Section through Section 7.10.
Table SC68C2550B internal registers Register Default[1] set[2] transmit holding register interrupt RCVR FIFO reset priority receive holding register FIFOs enable status word length receive data ready
General register
modem receive status line interrupt status interrupt mode select priority parity enable XMIT FIFO reset priority
RCVR trigger (MSB) FIFOs enabled divisor latch enable FIFO data error
RCVR trigger (LSB) FIFOs enabled
reserved
reserved
break parity even parity
stop bits word length (OP1) parity error overrun error
loop back control break interrupt framing error
empty empty
Special register set[3]
value shown represents register's initialized hexadecimal value; n/a. Accessible only when LCR[7] logic Baud rate registers accessible only when LCR[7] logic
Transmit Holding Register (THR) Receive Holding Register (RHR)
serial transmitter section consists 8-bit Transmit Hold Register (THR) Transmit Shift Register (TSR). status provided Line Status Register (LSR). Writing transfers contents data UART THR, providing that empty. empty flag register will logic when transmitter empty when data transferred TSR. Note that write operation performed when empty flag (logic least byte FIFO/THR, logic FIFO/THR empty). serial receive section also contains 8-bit Receive Holding Register (RHR) Receive Serial Shift Register (RSR). Receive data removed from SC68C2550B receive FIFO reading register. receive section provides mechanism
SC68C2550B_3 B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
prevent false starts. falling edge start false start bit, internal receiver counter starts counting clocks clock rate. After 71/2 clocks, start time should shifted center start bit. this time start sampled, still logic validated. Evaluating start this manner prevents receiver from assembling false character. Receiver status codes will posted LSR.
Interrupt Enable Register (IER)
Interrupt Enable Register (IER) masks interrupts from receiver ready, transmitter empty, line status modem status registers. These interrupts would normally seen output pin.
Table Interrupt Enable Register bits description Symbol IER[7:4] IER[3] Description used Modem Status Interrupt. This interrupt will issued whenever there modem status change reflected MSR[3:0]. logic disable modem status register interrupt (normal default condition) logic enable modem status register interrupt IER[2] Receive Line Status interrupt. This interrupt will issued whenever receive data error condition exists reflected LSR[4:1]. logic disable receiver line status interrupt (normal default condition) logic enable receiver line status interrupt IER[1] Transmit Holding Register interrupt. 16C450 mode, this interrupt will issued whenever empty, associated with LSR[5]. FIFO modes, this interrupt will issued whenever FIFO empty. logic disable Transmit Holding Register Empty (TXRDY) interrupt (normal default condition) logic enable TXRDY (ISR level interrupt IER[0] Receive Holding Register. 68C450 mode, this interrupt will issued when data, cleared when empty. FIFO mode, this interrupt will issued when FIFO reached programmed trigger level cleared when FIFO drops below trigger level. logic disable receiver ready (ISR level RXRDY) interrupt (normal default condition) logic enable RXRDY (ISR level interrupt
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
7.2.1 versus Transmit/Receive FIFO interrupt mode operation
When receive FIFO (FCR[0] logic receive interrupts (IER[0] logic enabled, receive interrupts register status will reflect following:
receive RXRDY interrupt (Level interrupt) issued external
when receive FIFO reached programmed trigger level. will cleared when receive FIFO drops below programmed trigger level.
Receive FIFO status will also reflected user accessible register when
receive FIFO trigger level reached. Both register receive status interrupt will cleared when FIFO drops below trigger level.
receive data ready (LSR[0]) soon character transferred from
shift register (RSR) receive FIFO. reset when FIFO empty.
When Transmit FIFO interrupts enabled, interrupt generated when
transmit FIFO empty unloading data UART transmission transmission media. interrupt cleared either reading register, loading with data characters.
7.2.2 versus Receive/Transmit FIFO polled mode operation
When FCR[0] logic resetting IER[3:0] enables SC68C2550B FIFO polled mode operation. this mode, interrupts generated user must poll register transmit and/or receive data status. Since receiver transmitter have separate bits either both used polled mode selecting respective transmit receive control bit(s).
LSR[0] will logic long there byte receive FIFO. LSR[4:1] will provide type receive errors, receive break, encountered. LSR[5] will indicate when transmit FIFO empty. LSR[6] will indicate when both transmit FIFO transmit shift register empty. LSR[7] will show FIFO data errors occurred.
FIFO Control Register (FCR)
This register used enable FIFOs, clear FIFOs, receive FIFO trigger levels, select mode.
7.3.1 mode
7.3.1.1 Mode (FCR enable interrupt each single transmit receive operation, similar 68C450 mode. Transmit Ready (TXRDYn) will logic whenever FIFO (THR, FIFO enabled) empty. Receive Ready (RXRDYn) will logic whenever Receive Holding Register (RHR) loaded with character. 7.3.1.2 Mode (FCR enable interrupt block mode operation. transmit interrupt when transmit FIFO empty. TXRDYn remains logic long empty FIFO location available. receive interrupt when receive FIFO fills
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
programmed trigger level. However, FIFO continues fill regardless programmed level until FIFO full. RXRDYn packages transitions when FIFO reaches trigger level, transitions HIGH when FIFO empties.
7.3.2 FIFO mode
Table FIFO Control Register bits description Description Symbol
FCR[7:6] RCVR trigger. These bits used trigger level receive FIFO interrupt. logic cleared) normal default condition logic receive trigger level interrupt generated when number characters FIFO equals programmed trigger level. However, FIFO will continue loaded until full. Refer Table
FCR[5:4] used; initialized logic FCR[3] mode select logic mode logic mode Transmit operation mode `0': When SC68C2550B 68C450 mode (FIFOs disabled; FCR[0] logic FIFO mode (FIFOs enabled; FCR[0] logic FCR[3] logic when there characters transmit FIFO transmit holding register, TXRDYn will logic Once active, TXRDYn will logic after first character loaded into transmit holding register. Receive operation mode `0': When SC68C2550B mode (FCR[0] logic FIFO mode (FCR[3] logic there least character receive FIFO, RXRDYn will logic Once active, RXRDYn will logic when there more characters receiver. Transmit operation mode `1': When SC68C2550B FIFO mode (FCR[0] logic FCR[3] logic TXRDYn will logic when transmit FIFO completely full. will logic more FIFO locations empty. Receive operation mode `1': When SC68C2550B FIFO mode (FCR[0] logic FCR[3] logic trigger level been reached, Receive Time-Out occurred, RXRDYn will logic Once activated, will logic after there more characters FIFO.
FCR[2]
XMIT FIFO reset logic transmit FIFO reset (normal default condition) logic clears contents transmit FIFO resets FIFO counter logic (the transmit shift register cleared altered). This will return logic after clearing FIFO.
FCR[1]
RCVR FIFO reset logic receive FIFO reset (normal default condition) logic clears contents receive FIFO resets FIFO counter logic (the receive shift register cleared altered). This will return logic after clearing FIFO.
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
FIFO Control Register bits description .continued Description FIFOs enabled logic disable transmit receive FIFO (normal default condition). logic enable transmit receive FIFO. This must when other bits written they will programmed.
Table
Symbol FCR[0]
Table FCR[7]
RCVR trigger levels FCR[6] Receive FIFO trigger level
Interrupt Status Register (ISR)
SC68C2550B provides four levels prioritized interrupts minimize external software interaction. Interrupt Status Register (ISR) provides user with four interrupt status bits. Performing read cycle will provide user with highest pending interrupt level serviced. other interrupts acknowledged until pending interrupt serviced. lower level interrupt seen after servicing higher level interrupt re-reading interrupt status bits. Table shows data values (bit four prioritized interrupt levels interrupt sources associated with each these interrupt levels.
Table Priority level Table Interrupt source ISR[3] ISR[2] ISR[1] ISR[0] Source interrupt (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data Time-out) TXRDY (Transmitter Holding Register Empty) (Modem Status Register)
Interrupt Status Register bits description Symbol ISR[7:6] Description FIFOs enabled. These bits logic when FIFOs being used 68C450 mode. They logic when FIFOs enabled SC68C2550B mode. logic cleared default condition used priority bits These bits indicate source pending interrupt interrupt priority levels (see Table 11). logic cleared default condition status logic interrupt pending contents used pointer appropriate interrupt service routine logic interrupt pending (normal default condition)
ISR[5:4] ISR[3:1]
ISR[0]
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Line Control Register (LCR)
Line Control Register used specify asynchronous data communication format. word length, number stop bits, parity selected writing appropriate bits this register.
Table Line Control Register bits description Symbol LCR[7] Description Divisor Latch enable. internal baud rate counter latch Enhanced Feature mode enable. logic Divisor Latch disabled (normal default condition). Logic Divisor Latch enabled. LCR[6] break. When enabled, Break control causes break condition transmitted (the output forced logic state). This condition exists until disabled setting LCR[6] logic logic break condition (normal default condition) logic forces transmitter output (TXn) logic alerting remote receiver line break condition LCR[5:3] LCR[2] programs parity conditions (see Table Stop bits. length stop specified this conjunction with programmed word length (see Table 15). logic cleared default condition LCR[1:0] Word length bits These bits specify word length transmitted received (see Table 16). logic cleared default condition Table LCR[5] Table LCR[2] Table LCR[1] LCR[5:3] parity selection LCR[4] LCR[3] Parity selection parity parity even parity forced parity forced parity
LCR[2] stop length Word length Stop length (bit times) 11/2
LCR[1:0] word length LCR[0] Word length
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Modem Control Register (MCR)
This register controls interface with modem peripheral device.
Table Modem Control Register bits description Symbol MCR[7:5] MCR[4] Description reserved; Loopback. Enable local Loopback mode (diagnostics). this mode transmitter output (TXn) receiver input (RXn), CTSn, DSRn, CDn, pins disconnected from SC68C2550B pins. Internally modem data control pins connected into loopback data configuration (see Figure this mode, receiver transmitter interrupts remain fully operational. Modem Control Interrupts also operational, interrupts' sources switched lower four bits Modem Control. Interrupts continue controlled register. logic disable Loopback mode (normal default condition) logic enable local Loopback mode (diagnostics) MCR[3] control logic forces OP2n output HIGH state logic forces OP2n output state. Loopback mode, controls MSR[7]. MCR[2] (OP1). OP1A/OP1B available external signal SC68C2550B. This instead used Loopback mode only. Loopback mode, this used write state modem interface signal. logic force RTSn output logic (normal default condition) logic force RTSn output logic MCR[0] logic force DTRn output logic (normal default condition) logic force DTRn output logic
MCR[1]
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Line Status Register (LSR)
This register provides status data transfers between SC68C2550B CPU.
Table Line Status Register bits description Description FIFO data error logic error (normal default condition) logic least parity error, framing error break indication current FIFO data. This cleared when there remaining error flags associated with remaining data FIFO. LSR[6] empty. This Transmit Empty indicator. This logic whenever Transmit Holding Register Transmit Shift Register both empty. reset logic whenever either contains data character. FIFO mode, this whenever transmit FIFO transmit shift register both empty. empty. This Transmit Holding Register Empty indicator. This indicates that UART ready accept character transmission. addition, this causes UART issue interrupt when interrupt enable set. logic when character transferred from Transmit Holding Register into Transmit Shift Register. reset logic concurrently with loading Transmit Holding Register CPU. FIFO mode, this when transmit FIFO empty; cleared when least byte written transmit FIFO. Break interrupt logic break condition (normal default condition) logic receiver received break signal (RXn logic character frame time). FIFO mode, only break character loaded into FIFO. LSR[3] Framing error logic framing error (normal default condition) logic framing error. receive character have valid stop bit(s). FIFO mode, this error associated with character FIFO. LSR[2] Parity error logic parity error (normal default condition) logic parity error. receive character does have correct parity information suspect. FIFO mode, this error associated with character FIFO. LSR[1] Overrun error logic overrun error (normal default condition) logic overrun error. data overrun error occurred receive shift register. This happens when additional data arrives while FIFO full. this case, previous data shift register overwritten. Note that under this condition, data byte Receive Shift Register transferred into FIFO, therefore data FIFO corrupted error. LSR[0] Receive data ready logic data Receive Holding Register FIFO (normal default condition) logic data been received saved Receive Holding Register FIFO
SC68C2550B_3 B.V. 2009. rights reserved.
Symbol LSR[7]
LSR[5]
LSR[4]
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Modem Status Register (MSR)
This register provides current state control interface signals from modem, other peripheral device which SC68C2550B connected. Four bits this register used indicate changed information. These bits logic whenever control input from modem changes state. These bits logic whenever reads this register.
Table Modem Status Register bits description Symbol MSR[7] MSR[6] MSR[5] MSR[4] MSR[3] Description During normal operation, this complement input pin. Reading this Loopback mode produces state MCR[3] (OP2). During normal operation, this complement input pin. Reading this Loopback mode produces state MCR[2] (OP1). DSR. During normal operation, this complement DSRn input pin. During Loopback mode, this equivalent state MCR[0]. CTS. During normal operation, this complement CTSn input pin. During Loopback mode, this equivalent state MCR[1]. logic change state (normal default condition) logic input SC68C2550B changed state since last time read. Modem Status Interrupt will generated. MSR[2] logic change state (normal default condition) logic input SC68C2550B changed from logic logic Modem Status Interrupt will generated. MSR[1] logic change state DSRn (normal default condition) logic DSRn input SC68C2550B changed state since last time read. Modem Status Interrupt will generated. MSR[0] logic change state CTSn (normal default condition) logic CTSn input SC68C2550B changed state since last time read. Modem Status Interrupt will generated.
Whenever logic Modem Status Interrupt will generated.
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Scratchpad Register (SPR)
SC68C2550B provides temporary data register store bits user information.
7.10 SC68C2550B external reset condition
Table Register Table Output TXA, OP2A, OP2B RTSA, RTSB DTRA, DTRB Reset state registers Reset state IER[7:0] FCR[7:0] ISR[7:1] ISR[0] LCR[7:0] MCR[7:0] LSR[7] LSR[6:5] LSR[4:0] MSR[7:4] input signals; MSR[3:0] SFR[7:0] DLL[7:0] DLM[7:0] Reset state outputs Reset state logic logic logic logic 3-state condition
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Symbol Tamb Tstg Ptot/pack Parameter supply voltage voltage other ambient temperature storage temperature total power dissipation package input only operating Conditions +150 Unit
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Static characteristics
Table Static characteristics Tamb tolerance unless otherwise specified. Symbol VIL(clk) VIH(clk) Parameter clock LOW-level input voltage clock HIGH-level input voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage except clock except clock outputs (data bus) (other outputs) (data bus) (other outputs) HIGH-level output voltage (data bus) (other outputs) -800 (data bus) -400 (other outputs) ILIL IL(clk)
Conditions
-0.3 -0.3 1.85 1.85 0.45 0.65
-0.3 -0.3
-0.5 -0.5
Unit
LOW-level input leakage current clock leakage current supply current input capacitance
Except XTAL2, typical.
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Dynamic characteristics
Table Dynamic characteristics Tamb tolerance unless specified otherwise. Symbol td10 td11 td12 td13 td14 td15 td16 td17 td18 fXTAL t(RESET) tsu1 tsu2 tw(CS)
Parameter chip select read cycle delay delay from data data disable time write cycle delay delay from write output delay interrupt from modem input delay reset interrupt from read delay from stop interrupt delay from read reset interrupt delay from start interrupt delay from write transmit start delay from write reset interrupt delay from stop RXRDY delay from read reset RXRDY delay from write TXRDY delay from start reset TXRDY hold time from data hold time address hold time pulse width HIGH pulse width clock speed RESET pulse width address set-up time data set-up time pulse width
Conditions
1TRCLK[1] 24TRCLK[1] 1TRCLK[1] 16TRCLK[1]
8TRCLK[1] 1TRCLK[1] 24TRCLK[1] 1TRCLK[1]
Unit
load load load load load load load
8TRCLK[1]
[2][3]
16TRCLK[1]
RCLK internal signal derived from Divisor Latch (DLL) Divisor Latch (DLM) divisor latches. Applies external clock; crystal oscillator maximum MHz.
XTAL
Reset pulse must happen when inactive.
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
10.1 Timing diagrams
tsu1
valid address tw(CS)
valid address
valid data
valid data
002aae395
General read timing
tsu1
valid address
valid address
tw(CS)
tsu2
valid data
valid data
002aae396
General write timing
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
(write)(1)
active
RTSA, RTSB DTRA, DTRB
change state
change state
CDA, CTSA, CTSB DSRA, DSRB
change state
change state
active
active
active
(read)(2)
active
active
active
RIA,
change state
002aab089
timing during write cycle. Figure timing during read cycle. Figure
Modem input/output timing
external clock
tw(clk)
002aac357
XTAL External clock timing
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Start
data bits data bits data bits data bits
parity
Stop
next data Start
RXA,
td10 active td11
(read)
active
baud rate clock
002aab090
Receive timing
Start
data bits
parity
Stop
next data Start
RXA,
td15 RXRDYA, RXRDYB active data ready td16 (read)
active
002aab091
Receive ready timing non-FIFO mode
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Start
data bits
parity
Stop
RXA,
first byte that reaches trigger level
td15 RXRDYA, RXRDYB active data ready td16 (read)
active
002aab092
Receive ready timing FIFO mode
Start
data bits data bits data bits data bits active transmitter ready
parity
Stop
next data Start
TXA,
td12 td13
td14 active
(write)
active
baud rate clock
002aab093
Transmit timing
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Start TXA,
data bits
parity
Stop
next data Start
(write)
active
byte
td18
td17 TXRDYA, TXRDYB active transmitter ready transmitter ready
002aab094
Transmit ready timing non-FIFO mode
start
data bits
parity
stop
TXA,
data bits data bits data bits (write) active td18 byte
td17 TXRDYA, TXRDYB trigger lead
002aab337
Transmit ready timing FIFO mode
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Package outline
LQFP48: plastic profile quad flat package; leads; body SOT313-2
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 9.15 8.85 9.15 8.85 0.75 0.45 0.12 0.95 0.55 0.95 0.55
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT313-2 REFERENCES 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Package outline SOT313-2 (LQFP48)
SC68C2550B_3 B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Soldering packages
This text provides very brief insight into complex technology. more in-depth account soldering found Application Note AN10365 "Surface mount reflow soldering description".
12.1 Introduction soldering
Soldering most common methods through which packages attached Printed Circuit Boards (PCBs), form electrical circuits. soldered joint provides both mechanical electrical connection. There single soldering method that ideal packages. Wave soldering often preferred when through-hole Surface Mount Devices (SMDs) mixed printed wiring board; however, suitable fine pitch SMDs. Reflow soldering ideal small pitches high densities that come with increased miniaturization.
12.2 Wave reflow soldering
Wave soldering joining technology which joints made solder coming from standing wave liquid solder. wave soldering process suitable following:
Through-hole components Leaded leadless SMDs, which glued surface printed circuit board
SMDs wave soldered. Packages with solder balls, some leadless packages which have solder lands underneath body, cannot wave soldered. Also, leaded SMDs with leads having pitch smaller than ~0.6 cannot wave soldered, increased probability bridging. reflow soldering process involves applying solder paste board, followed component placement exposure temperature profile. Leaded packages, packages with solder balls, leadless packages reflow solderable. characteristics both wave reflow soldering are:
Board specifications, including board finish, solder masks vias Package footprints, including solder thieves orientation moisture sensitivity level packages Package placement Inspection repair Lead-free soldering versus SnPb soldering
12.3 Wave soldering
characteristics wave soldering are:
Process issues, such application adhesive flux, clinching leads, board
transport, solder wave parameters, time during which components exposed wave
Solder bath specifications, including temperature impurities
SC68C2550B_3 B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
12.4 Reflow soldering
characteristics reflow soldering are:
Lead-free versus SnPb soldering; note that lead-free reflow process usually leads
higher minimum peak temperatures (see Figure than SnPb process, thus reducing process window
Solder paste printing issues including smearing, release, adjusting process
window large small components board
Reflow temperature profile; this profile includes preheat, reflow which board
heated peak temperature) cooling down. imperative that peak temperature high enough solder make reliable solder joints solder paste characteristic). addition, peak temperature must enough that packages and/or boards damaged. peak temperature package depends package thickness volume classified accordance with Table
Table SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) Table Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) 2000 2000
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, indicated packing, must respected times. Studies have shown that small packages reach higher temperatures during reflow soldering, Figure
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
temperature
maximum peak temperature limit, damage level
minimum peak temperature minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Temperature profiles large small components
further information temperature profiles, refer Application Note AN10365 "Surface mount reflow soldering description".
Abbreviations
Table Acronym FIFO ISDN UART Abbreviations Description Central Processing Unit Direct Memory Access First In/First Integrated Service Digital Network Least Significant Most Significant Transistor-Transistor Logic Universal Asynchronous Receiver Transmitter
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Revision history
Table Revision history Release date 20091009 Data sheet status Product data sheet Change notice Supersedes SC68C2550B_2 Document SC68C2550B_3 Modifications:
format this data sheet been redesigned comply with identity guidelines Semiconductors. Legal texts have been adapted company name where appropriate. Data sheet descriptive title changed from Motorola interface" mode interface" Section "Features": added (new) bullet item Footnote Table "Pin description": Description RXRDYA, RXRDYB: deleted "This function associated with PLCC44 LQFP48 packages only." Description TXRDYA, TXRDYB: deleted "This function associated with PLCC44 LQFP48 packages only."
Table "Limiting values": parameter description symbol changed from "voltage pin" "voltage other pin"; added separate conditions input only pin" parameter description symbol Tamb changed from "operating temperature" "ambient temperature" (moved "operating" Conditions column) symbol `total power dissipation package" changed from "Ptot(pack)" "Ptot/pack"
Table "Static characteristics": descriptive line below table title changed from "VCC "tolerance symbol/parameter changed from "VIL(CK), LOW-level clock input voltage" "VIL(clk), clock LOW-level input voltage" symbol/parameter changed from "VIH(CK), HIGH-level clock input voltage" "VIH(clk), clock HIGH-level input voltage" symbol/parameter changed from "ICL, clock leakage" "IL(clk), clock leakage current"
Table "Dynamic characteristics": descriptive line below table title changed from "VCC "tolerance symbol "t1w, t2w" (clock cycle period) separated into symbols "tWH, pulse width HIGH" "tWL, pulse width LOW" symbol "tw1, strobe width" changed "tw(CS), pulse width" Table note [3]: changed denominator from "t3w" "tw(clk)" added Table note reference t(RESET)
Figure "General read timing": changed symbol from "tw1" "tw(CS)" Figure "General write timing": changed symbol from "tw1" "tw(CS)" Figure "External clock timing": symbol changed from "t1w" "tWH" symbol changed from "t2w" "tWL" symbol changed from "t3w" "tw(clk)"
SC68C2550B_2 (9397 14941) SC68C2550B_1 (9397 14698)
SC68C2550B_3
updated soldering information Product data sheet Product data sheet SC68C2550B_1
20050428 20050329
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
15.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights. Export control This document well item(s) described herein subject export control regulations. Export might require prior authorization from national authorities.
15.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental
15.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
SC68C2550B_3
B.V. 2009. rights reserved.
Product data sheet
Rev. October 2009
Semiconductors
SC68C2550B
dual UART, Mbit/s (max.), with 16-byte FIFOs
Contents
General description Features Ordering information Block diagram Pinning information Pinning description Functional description UART functions Internal registers. FIFO operation Hardware/software time-out interrupts. Programmable baud rate generator operation Loopback mode Register descriptions Transmit Holding Register (THR) Receive Holding Register (RHR) Interrupt Enable Register (IER) 7.2.1 versus Transmit/Receive FIFO interrupt mode operation. 7.2.2 versus Receive/Transmit FIFO polled mode operation. FIFO Control Register (FCR) 7.3.1 mode 7.3.1.1 Mode (FCR 7.3.1.2 Mode (FCR 7.3.2 FIFO mode Interrupt Status Register (ISR) Line Control Register (LCR) Modem Control Register (MCR) Line Status Register (LSR) Modem Status Register (MSR). Scratchpad Register (SPR) 7.10 SC68C2550B external reset condition Limiting values. Static characteristics. Dynamic characteristics 10.1 Timing diagrams Package outline Soldering packages 12.1 Introduction soldering 12.2 Wave reflow soldering 12.3 Wave soldering 12.4 Reflow soldering 15.1 15.2 15.3 15.4 Abbreviations Revision history Legal information Data sheet status Definitions Disclaimers. Trademarks Contact information Contents.
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2009.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: October 2009 Document identifier: SC68C2550B_3
Other recent searches
TC7MET138AFK - TC7MET138AFK TC7MET138AFK Datasheet
HY57V28820B - HY57V28820B HY57V28820B Datasheet
HG4518 - HG4518 HG4518 Datasheet
CLC016 - CLC016 CLC016 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
