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CMOS ADCV08832 2001 CMOS V08832 20001001 33080 24000 11800 ds2000


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CMOS ADCV08832
2001 CMOS V08832 20001001 33080 24000 11800 ds200084
Converted nat2000 Edits before phase
ADCV08832
ADCV08832
CMOS
ADCV08832 MICROWIRE ADCV08832 TTL/CMOS TLV0832 ADC0832
3.3V (fCLK kHz) (max)
2.7V
ADCV08832 SOIC-8 Package
Industrial ADCV08832CIM ADCV08832CIMX Package M08A M08A Package Marking ADC08832I ADC08832I Transport Media Units Rail 2500 Units Tape Reel
20010112
COPSMICROWIRE
National Semiconductor Corporation
Printed Japan 5/2001
ADCV08832
(Notes
(Note
(VCC) (Note (Note (Note (Note
6.5V 0.3V 0.3V
2.7V 5.5V fCLK 1000
2500V 250V
3.3VDCfCLK 500kHz50 TMIN TMAX Symbol Parameter Conditions Typical (Note CONVERTER MULTIPLEXED CHARACTERISTICS VOFF Total Unadjusted Error Offset Error Differential Nonlinearity Integral Nonlinearity Full Scale Error Analog Input Voltage Common Mode Error Analog Input Leakage Current (Note CHARACTERISTICS VIN(1) VIN(0) VOUT(1) VOUT(0) IOUT ISOURCE ISINK Logical "1"Input Voltage Logical "0"Input Voltage Digital Input Current Logical "1"Output Voltage Logical "0"Output Voltage TRI-STATE Output Current Digital Output Short Circuit Current Digital Output Sink Circuit Supply Current (Note 2.7V IOUT 2.7V IOUT VOUT VOUT 3.3V VOUT VOUT Low, (min) (max) (max) (min) (max) (max) Channel Channel (Note 0.02 11.0 (Note 0.03 0.06 (VCC 0.05) (GND 0.05) (max) (max) (min) (max) Limits (Note Units
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ADCV08832
3.3V50 20ns TMIN TMAX Symbol fCLK Parameter Clock Frequency Clock Duty Cycle (Note tCONV tSET-UP Conversion Time (Not Including Addressing Time) Acquisition Time Time Required from Falling Rising Clock Edge Data Input Valid after Rising Edge Falling Edge Output Data Valid (Note TRI-STATE Delay from Rising Edge Data Output SARS Hi-Z Input Capacitance CH0, (Note Input Capacitance CLK, Output Capacitance Logic Outputs TRI-STATE) Data First Data First (see TRI-STATE Test Circuit) fCLK Conditions Typical 1000 Limits Units (min) (max) 1/fCLK 1/fCLK (max) (min) (min)
tHOLD tpd1, tpd0
(max) (max)
t1H, COUT
3.3VfCLK 500kHzTA RSOURCE 25fIN 9.6kHzVIN 3.3VP-P 2048 Symbol SINAD ENOB SFDR
Note Note
Parameter Sampling Rate Signal-to-Noise Ratio (Note Total Harmonic Distortion (Note Signal-to-Noise Distortion Effective Number Bits (Note Spurious Free Dynamic Range
Conditions
Typical fCLK/13 49.5 49.4 67.6
Limits
Units ksps Bits
0VDC (VIN) (GND) (20mA) TJmax( (TJmax TA)/ 100pF 1.5k 200pF (Typical) AOQL(Average Outgoing Quality Level)
Note Note Note
Note Note Note Note
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ADCV08832
Note VIN( VIN( 0000 0000 2.7V) 3.3V) 50mV 50mV 0VDC 3.30VDC 3.25VDC Note "High" (3.3VDC) "Low" (0VDC) "Low" "High" Note Note Data first Note 300( 13pF Note (ENOB) (SINAD) ENOB (SINAD 1.76)/6.02 Note Note
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ADCV08832
ADCV08832
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ADCV08832
3.3V
Clock Frequency Output Codes
Output Codes
(operating)
Typical Digital Output Current Temperature
(operating) Temperature
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ADCV08832
3.3V
Spectral Response with Sine Wave Input, fCLK Spectral Response with Sine Wave Input, fCLK
Spectral Response with 18.8 Sine Wave Input, fCLK
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ADCV08832
TRI-STATE
Data Input Timing
Data Output Timing
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ADCV08832
ADCV08832 Timing
ADCV08832 Differential Mode Address Start SGL/ ODD/ SIGN Channel
50mV 50mV
(DI)
Addressing: ADCV08832
Single-Ended Mode Address Start SGL/ ODD/ SIGN Channel
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ADCV08832
(DO) TRI-STATE (High) (Low) High 500kHz 60Hz 1/4LSB (5mV) 0.328V
ADCV08832
(100) LM6142
3.3V ADCV08832 High TRI-STATE CLKCSDI CMOS High(2.4V) High CMOS
ADCV08832 (RON) 13pF (CIN)
ADCV08832
VIN(MIN) VIN(MIN) (0000 0000) VIN( VIN( 0000 0000 0000 0001 1/2LSB (1/2LSB 6.4mV)
ADCV08832 ADCV08832 (tca) Verror(MAX) VPEAK CM)(tconv) PEAK tconv (tconv 13/fCLK)
102420484096) (FFT)
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ADCV08832
1/2)
(SINAD)
(SINAD) RMS( 1/2( SINAD SINAD SINAD (6.02 1.76) SINAD 49.92dB
(SNR) RMS( 1/2(
(ENOB) ENOB ENOB [(SINAD 1.76) 6.02] SINAD
(THD)
[(V22 V62) 1/2/V1] V2V3V4V5
(SFDR)
(SFDR)
Protecting Input
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ADCV08832
Isolated Data Converter
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ADCV08832
A"Stand-Alone"Hook-Up ADCV08832 Evaluation
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ADCV08832 CMOS
inches (millimeters)
Order Number ADCV08832CIM Package Number M08A
135-0042 2-17-16 TEL.(03)5639-7300
http://www.national.com/JPN/
0120-666-116

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