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SMJ320C6701-SP
www.ti.com SGUS030E APRIL 2000 REVISED JULY 2009
RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR
FEATURES
Rad-Tolerant: 100-kRad (Si) Immune 89MeV-cm2/mg Ions QML-V Qualified, 5962-98661 Highest-Performance Floating-Point Digital Signal Processor (DSP) SMJ320C6701 7-ns Instruction Cycle Time 140-MHz Clock Rate Eight 32-Bit Instructions/Cycle GFLOPS Performance Compatible With 'C6201 Fixed-Point SMJ: Processing MIL-PRF-38535 Standard Processing Operating Temperature Ranges -55°C 115°C -55°C 125°C VelociTIAdvanced Very Long Instruction Word (VLIW) 'C67x Core Eight Highly Independent Functional Units: Four ALUs (Floating Fixed Point) ALUs (Fixed Point) Multipliers (Floating Fixed Point) Load-Store Architecture With 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size Instructions Conditional Instruction Features Hardware Support IEEE Single-Precision Instructions Hardware Support IEEE Double-Precision Instructions Byte Addressable (8-/16-/32-Bit Data) 32-Bit Address Range 8-Bit Overflow Protection Saturation Bit-Field Extract, Set, Clear
23456
Counting Normalization 1M-Bit On-Chip SRAM 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) 512K-Bit Dual-Access Internal Data (64K Bytes) 32-Bit External Memory Interface (EMIF) Glueless Interface Synchronous Memories: SDRAM SBSRAM Glueless Interface Asynchronous Memories: SRAM EPROM Four-Channel Bootloading Direct Memory Access (DMA) Controller With Auxiliary Channel 16-Bit Host-Port Interface (HPI) Access Entire Memory Multichannel Buffered Serial Ports (McBSPs) Direct Interface T1/E1, MVIP, SCSA Framers Switching Compatible Channels Each AC97 Compatible Serial Peripheral Interface (SPI) Compatible (MotorolaTM) 32-Bit General-Purpose Timers Flexible Phase-Locked Loop (PLL) Clock Generator IEEE 1149.1 (JTAG Boundary Scan Compatible 429-Pin Ceramic Ball Grid Array (CBGA/GLP) Ceramic Land Grid Array (CLGA/ZMB) Package Types 0.18-µm/5-Level Metal Process CMOS Technology 3.3-V I/Os, Internal
IEEE 1149.1-1990 Test Access Port Boundary Scan Architecture
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. VelociTI, XDS, XDS510, XDS510WS trademarks Texas Instruments. Windows, Win32, trademarks Microsoft Corporation. Motorola trademark Motorola, Inc. SPARC trademark SPARC International. Solaris trademark Microsystems, Inc.
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PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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PACKAGES BOTTOM VIEW
DESCRIPTION
SMJ320C67x DSPs floating-point family SMJ320C6000 platform. SMJ320C6701 ('C6701) device based high-performance, advanced (VLIW) architecture developed Texas Instruments (TI), making this excellent choice multichannel multifunction applications. With performance giga floating-point operations second (GFLOPS) clock rate MHz, 'C6701 offers cost-effective solutions high-performance programming challenges. 'C6701 possesses operational flexibility high-speed controllers numerical capability array processors. This processor general-purpose registers 32-bit word length eight highly independent functional units. eight functional units provide four floating-/fixed-point ALUs, fixed-point ALUs, floating-/fixed-point multipliers. 'C6701 produce multiply-accumulates (MACs) cycle total million MACs second (MMACS). 'C6701 also application-specific hardware logic, on-chip memory, additional on-chip peripherals. 'C6701 includes large bank on-chip memory powerful diverse peripherals. Program memory consists 64K-byte block that user-configurable cache memory-mapped program space. Data memory consists 32K-byte blocks RAM. peripheral includes multichannel buffered serial ports (McBSPs), general-purpose timers, host-port interface (HPI), glueless external memory interface (EMIF) capable interfacing SDRAM SBSRAM asynchronous peripherals. 'C6701 complete development tools that includes compiler, assembly optimizer simplify programming scheduling, Windowsdebugger interface visibility into source code execution.
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Device Characteristics
Table provides overview 'C6701 DSP. table shows significant features each device, including capacity on-chip RAM, peripherals, execution time, package type with count. Table Characteristics 'C6701 Processors
CHARACTERISTICS Device Number On-Chip Memory SMJ320C6701 512K-bit Program Memory 512K-bit Data Memory (organized blocks) Mutichannel Buffered Serial Ports (McBSP) General-Purpose Timers Host-Port Interface (HPI) External Memory Interface (EMIF) 429-Pin (GLP) 429-Pin (ZMB) Core DESCRIPTION
Peripherals Cycle Time Package Type Nominal Voltage
Functional Block Diagram
SDRAM SBSRAM
Program
'C6701 Digital Signal Processor
Program Access/Cache Controller Internal Program Memory Block Program/Cache (64K Bytes)
SRAM ROM/FLASH Devices
External Memory Interface (EMIF)
'C67x Timer Timer Multichannel Buffered Serial Port Multichannel Buffered Serial Port Instruction Fetch Instruction Dispatch Instruction Decode Data Path Register File
Buses
Control Registers Control Logic Test In-Circuit Emulation Interrupt Control
HOST CONNECTION MC68360 Glueless MPC860 Glueless PCI9050 Bridge Inverter MC68302 MPC750 MPC960 (Jx/Rx)
Host Port Interface (HPI)
Direct Memory Access Controller (DMA) Channels) (x1,
Data
Framing Chips: H.100, MVIP, SCSA, AC97 Devices, Devices, Codecs
Data Path Register File
.L1(1) .S1(1) .M1(1)
.M2(1) .S2(1) .L2(1)
PowerDown Logic
Data Access Controller
Internal Data Memory (64K Bytes) Blocks Banks Each
These functional units execute floating-point instructions.
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Description
fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) supply eight 32-bit instructions eight functional units during every clock cycle. VelociTI VLIW architecture features controls which eight units have supplied with instructions they ready execute. first every 32-bit instruction determines next instruction belongs same execute packet previous instruction, whether should executed following clock part next execute packet. Fetch packets always bits wide; however, execute packets vary size. variable-length execute packets memory-saving feature, distinguishing 'C67x from other VLIW architectures. features sets functional units. Each contains four units register file. contains functional units .L1, .S1, .M1, .D1; other contains units .D2, .M2, .S2, .L2. register files contain 32-bit registers each total general-purpose registers. sets functional units, along with register files, compose sides (see functional block diagram Figure four functional units each side freely share registers belonging that side. Additionally, each side features single data connected registers other side, which sets functional units access data from register files opposite sides. While register access functional units same side register file service units single clock cycle, register access using register file across supports read write cycle. 'C67x executes 'C62x instructions. addition 'C62x fixed-point instructions, eight functional units (.L1, .M1, .D1, .D2, .M2, .L2) also execute floating-point instructions. remaining functional units (.S1 .S2) also execute LDDW instruction which loads bits side total bits cycle. Another feature 'C67x load/store architecture, where instructions operate registers opposed data memory). sets data-addressing units (.D1 .D2) responsible data transfers between register files memory. data address driven units allows data addresses generated from register file used load store data from other register file. 'C67x supports variety indirect-addressing modes using either linear- circular-addressing modes with 15-bit offsets. instructions conditional, most access registers. Some registers, however, singled support specific addressing hold condition conditional instructions condition automatically "true"). functional units dedicated multiplies. functional units perform general arithmetic, logical, branch functions with results available every clock cycle. processing flow begins when 256-bit-wide instruction fetch packet fetched from program memory. 32-bit instructions destined individual functional units "linked" together bits least significant (LSB) position instructions. instructions that "chained" together simultaneous execution eight total) compose execute packet. instruction breaks chain, effectively placing instructions that follow next execute packet. execute packet crosses fetch-packet boundary (256 bits wide), assembler places next fetch packet, while remainder current fetch packet padded with instructions. number execute packets within fetch packet vary from eight. Execute packets dispatched their respective functional units rate clock cycle next 256-bit fetch packet fetched until execute packets from current fetch packet have been dispatched. After decoding, instructions simultaneously drive active functional units maximum execution rate eight instructions every clock cycle. While most results stored 32-bit registers, they subsequently moved memory bytes half-words well. load store instructions byte, half-word, word addressable.
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.L1(1)
src2
long long
Data Path
src2
.M1(1) src1 src2
src1 src2
src2
.M2(1) src1 src2
Data Path
src1 .S2(1) long long
long long
.L2(1) src2
These functional units execute floating-point instructions.
Figure SMJ320C67x Data Paths
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src2 src1
long long .S1(1)
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Register File (A0-A15) Register File (B0-B15) Control Register File
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Signal Groups Description
CLKIN CLKOUT2 CLKOUT1 CLKMODE1 CLKMODE0 CLOCK/PLL PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV PLLG PLLF
Boot Mode
BOOTMODE4 BOOTMODE3 BOOTMODE2 BOOTMODE1 BOOTMODE0
Reset Interrupts TRST EMU1 EMU0
IEEE Standard 1149.1 (JTAG) Emulation Little ENDIAN ENDIAN
RESET EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0
LENDIAN
RSV9 RSV8 RSV7 RSV6 RSV5 RSV4 RSV3 RSV2 RSV1 RSV0
Status Reserved Power-Down Status
DMAC3 DMAC2 DMAC1 DMAC0
Control/Status
HD[15:0]
Data
(Host-Port Interface)
HCNTL0 HCNTL
Register Select Control
HHWIL HBE1 HBE0
Half-Word/Byte Select
HR/W HDS1 HDS2 HRDY HINT
Figure Peripheral Signals
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ED[31:0] EA[21:2] Data Asynchronous Memory Control ARDY
Memory Space Select SBSRAM Control SSADS SSOE SSWE SSCLK
Word Address
Byte Enables SDRAM Control HOLD/ HOLDA EMIF (External Memory Interface)
HOLD HOLDA
SDA10 SDRAS SDCAS SDWE SDCLK
TOUT1 TINP
Timer
Timer
TOUT0 TINP0
Timers
McBSP
McBSP0
CLKX1 FSX1
Receive
Receive
CLKX0 FSX0
CLKR1 FSR1
Transmit
Transmit
CLKR0 FSR0
CLKS
Clock
Clock
CLKS0
McBSPs (Multichannel Buffered Serial Ports)
Figure Peripheral Signals
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Signal Descriptions
SIGNAL NAME CLKIN CLKOUT1 CLKOUT2 CLKMODE1 CLKMODE0 PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV PLLF TRST EMU1 EMU0 RESET EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0
TYPE CLOCK/PLL Clock Input Clock output full device speed
DESCRIPTION
Clock output half device speed Clock mode select Selects whether output clock frequency input clock freq frequency range target range CLKOUT1 frequency determined 3-bit value PLLFREQ pins. analog connection low-pass filter analog connection low-pass filter low-pass filter connection external components bypass capacitor JTAG EMULATION JTAG test port mode select (features internal pull-up) JTAG test port data JTAG test port data (features internal pull-up) JTAG test port clock JTAG test port reset (features internal pull-down) Emulation pullup with dedicated 20-k resistor Emulation pullup with dedicated 20-k resistor RESET INTERRUPTS Device reset Nonmaskable interrupt Edge driven (rising edge) External interrupts Edge driven (rising edge) Interrupt acknowledge active interrupts serviced Active interrupt identification number Valid during IACK active interrupts (not just external) Encoding order follows interrupt service fetch packet ordering. LITTLE ENDIAN/BIG ENDIAN
I/O/Z I/O/Z
PLLG
LENDIAN
high, selects little-endian byte/half-word addressing order within word. low, selects big-endian addressing. POWER-DOWN STATUS Power-down mode (active high)
Input, Output, High impedance, Supply voltage, Ground PLLV PLLG signals part external voltage supply ground. CLOCK/PLL documentation information connect those pins. Analog signal (PLL filter) emulation normal operation, pull EMU1 EMU0 with dedicated 20-k resistor. boundary scan, pull down EMU1 EMU0 with dedicated 20-k resistor.
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Signal Descriptions (continued)
SIGNAL NAME HINT HCNTL1 HCNTL0 HHWIL HBE1 HBE0 HR/W HD15 HD14 HD13 HD12 HD11 HD10 HDS1 HDS2 HRDY BOOTMODE4 BOOTMODE3 BOOTMODE2 BOOTMODE1 BOOTMODE0 Boot mode Host address strobe Host chip select Host data strobe Host data strobe Host ready (from host) BOOT MODE I/O/Z Host-port data (used transfer data, address control) TYPE HOST-PORT INTERFACE (HPI) Host interrupt (from host) Host control selects between control, address data registers Host control selects between control, address data registers Host halfword select first second halfword (not necessarily high order) Host byte select within word half-word Host byte select within word half-word Host read write select DESCRIPTION
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Signal Descriptions (continued)
SIGNAL NAME EA21 EA20 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 External address (word address) TYPE DESCRIPTION
EMIF CONTROL SIGNALS COMMON TYPES MEMORY Byte enable control Decoded from lowest bits internal address Byte write enables most types memory directly connected SDRAM read write mask signal (SDQM) EMIF ADDRESS Memory space enables Enabled bits word address Only asserted during external data access
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Signal Descriptions (continued)
SIGNAL NAME ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 ED15 ED14 ED13 ED12 ED11 ED10 ARDY AA13 AA10 EMIF ASYNCHRONOUS MEMORY CONTROL Asynchronous memory read enable Asynchronous memory output enable Asynchronous memory write enable Asynchronous memory ready input I/O/Z External data TYPE EMIF DATA DESCRIPTION
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Signal Descriptions (continued)
SIGNAL NAME SSADS SSOE SSWE SSCLK SDA10 SDRAS SDCAS SDWE SDCLK HOLD HOLDA TOUT1 TINP1 TOUT0 TINP0 DMAC3 DMAC2 DMAC1 DMAC0 CLKS1 CLKR1 CLKX1 FSR1 FSX1 MULTICHANNEL BUFFERED SERIAL PORT (McBSP1) I/O/Z I/O/Z I/O/Z I/O/Z External clock source opposed internal) Receive clock Transmit clock Receive data Transmit data Receive frame sync Transmit frame sync action complete TYPE DESCRIPTION
EMIF SYNCHRONOUS BURST SRAM CONTROL SBSRAM address strobe SBSRAM output enable SBSRAM write enable SBSRAM clock EMIF SYNCHRONOUS DRAM CONTROL SDRAM address (separate deactivate command) SDRAM address strobe SDRAM column address strobe SDRAM write enable SDRAM clock EMIF ARBITRATION Hold request from host Hold request acknowledge host TIMERS Timer general-purpose output Timer general-purpose input Timer general-purpose output Timer general-purpose input ACTION COMPLETE
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Signal Descriptions (continued)
SIGNAL NAME CLKS0 CLKR0 CLKX0 FSR0 FSX0 RSV0 RSV1 RSV2 RSV3 RSV4 RSV5 RSV6 RSV7 RSV8 RSV9 DVDD 3.3-V supply voltage TYPE DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT (McBSP0) I/O/Z I/O/Z I/O/Z I/O/Z Extended clock source opposed internal) Receive clock Transmit clock Receive data Transmit data Receive frame sync Transmit frame sync RESERVED TEST Reserved testing, pullup with dedicated 20-k resistor Reserved testing, pullup with dedicated 20-k resistor Reserved testing, pullup with dedicated 20-k resistor Reserved testing, pullup with dedicated 20-k resistor Reserved testing, pulldown with dedicated 20-k resistor Reserved (leave unconnected, connect power ground) Reserved testing, pullup with dedicated 20-k resistor Reserved testing, pullup with dedicated 20-k resistor Reserved testing, pullup with dedicated 20-k resistor Reserved (leave unconnected, connect power ground)
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Signal Descriptions (continued)
SIGNAL NAME DVDD CVDD 1.9-V supply voltage 3.3-V supply voltage TYPE DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
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Signal Descriptions (continued)
SIGNAL NAME AA15 AA17 AA19 CVDD 1.9-V supply voltage TYPE DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
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Signal Descriptions (continued)
SIGNAL NAME CVDD AA11 AA12 1.9-V supply voltage TYPE DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
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Signal Descriptions (continued)
SIGNAL NAME AA14 AA16 AA18 Ground TYPE GROUND PINS DESCRIPTION
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Signal Descriptions (continued)
SIGNAL NAME Ground pins TYPE GROUND PINS (CONTINUED) DESCRIPTION
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Signal Descriptions (continued)
SIGNAL NAME Ground pins TYPE GROUND PINS (CONTINUED) DESCRIPTION
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Signal Descriptions (continued)
SIGNAL NAME Unconnected pins TYPE REMAINING UNCONNECTED PINS DESCRIPTION
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Development Support
Texas Instruments (TI) offers extensive line development tools 'C6x generation DSPs, including tools evaluate performance processors, generate code, develop algorithm implementations, fully integrate debug software hardware modules. following products support development 'C6x-based applications: Software-development tools Assembly optimizer Assembler/Linker Simulator Optimizing ANSI compiler Application algorithms C/Assembly debugger code profiler Hardware-development tools Extended development system (XDSTM) emulator (supports 'C6x multiprocessor system debug) (Evaluation Module) TMS320 Development Support Reference Guide (SPRU011) contains information about development-support products TMS320 family member devices, including documentation. this document further information TMS320 documentation TMS320 support products from Texas Instruments. additional document, TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320-related products from other companies industry. receive TMS320 literature, contact Literature Response Center 800/477-8924. Table complete listing development-support tools 'C6x. information pricing availability, contact nearest field sales office authorized distributor. Table SMJ320C6x Development-Support Tools
DEVELOPMENT TOOL PLATFORM Software Compiler
PART NUMBER AD0345AS8500RF Single user AD0345BS8500RF Multi user TMDX3246855-07 TMDX3246555-07 TMDS3246851-07 TMDS3246551-07 TMDX324016X-07 TMDS00510 TMDS00510WS TMDX3260A6201 TMDX32600620
Solaris 2.3(2) Win32SPARCSolarisWin32 SPARC Solaris Win32, Windows NTHardware SCSI Software/Hardware PC/Win95/Windows PC/Win95/Windows
Optimizer Optimizer Simulator Simulator XDS510Debugger/Emulation Software XDS510 Emulator XDS510WSEmulator Evaluation Evaluation (including TMDX3246855-07)
Contact IRVINE Compiler Corporation (949) 250-1366 order support estimated availability 1Q00 Includes XDS510 board JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software included. Includes XDS510WS box, SCSI cable, power supply, JTAG emulation cable.
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Device Development-Support Tool Nomenclature designate stages product-development cycle, assigns prefixes part numbers SMJ320 devices support tools. Each SMJ320 member three prefixes: SMX, SMJ. Texas Instruments recommends three possible prefix designators support tools: TMDX TMDS. These prefixes represent evolutionary stages product development from engineering prototypes (SMX/TMDX) through fully qualified production devices/tools (SMJ/TMDS). Device development evolutionary flow: Experimental device that necessarily representative final device's electrical specifications Final silicon that conforms device's electrical specifications completed quality reliability verification Fully qualified production device processed MIL-PRF-38535
Support tool development evolutionary flow: TMDX TMDS Development-support product that completed Texas Instruments internal qualification testing. Fully qualified development-support product
devices TMDX development-support tools shipped against following disclaimer: "Developmental product intended internal evaluation purposes." devices TMDS development-support tools have been characterized fully, quality reliability device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (SMX have greater failure rate than standard production devices. Texas Instruments recommends that these devices used production system because their expected end-use failure rate still undefined. Only qualified production devices used. device nomenclature also includes suffix with device family name. This suffix indicates package type (for example, GLP), temperature range, device speed range megahertz (for example, MHz). Figure provides legend reading complete device name SMJ320 family member.
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PREFIX SMX= Experimental device MIL-PRF-38535, Commercial processing
RAD-TOLERANT CLASS DEVICE SPEED RANGE
DEVICE FAMILY SMJ320 family
TEMPERATURE RANGE (DEFAULT: 90°C) 115°C, extended temperature
TECHNOLOGY CMOS
PACKAGE TYPE 429-pin ceramic 429-pin ceramic
DEVICE DSP: 6201B 6203
Ball grid array
Figure SMJ320 Device Nomenclature (Including SMJ320C6701-SP)
Documentation Support
Extensive documentation supports SMJ320 family generations devices from product announcement through applications development. types documentation available include: data sheets, such this document, with design specifications; complete user's reference guides devices; technical briefs; development-support tools; hardware software applications. following brief, descriptive list support documentation specific 'C6x devices: TMS320C6000 Instruction Reference Guide (literature number SPRU189) describes 'C6000 architecture, instruction set, pipeline, associated interrupts. TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes functionality peripherals available 'C6x devices, such external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion (XB), clocking phase-locked loop (PLL); power-down modes. This guide also includes information internal data program memories. TMS320C6000 Programmer's Guide (literature number SPRU198) describes ways optimize assembly code 'C6x devices includes application program examples. TMS320C6x Source Debugger User's Guide (literature number SPRU188) describes invoke 'C6x simulator emulator versions source debugger interface discusses various aspects debugger, including: command entry, code execution, data management, breakpoints, profiling, analysis. TMS320C6x Peripheral Support Library Programmer's Reference (literature number SPRU273) describes contents 'C6x peripheral support library functions macros. lists functions macros both header file alphabetically, provides complete description each, gives code examples show they used. TMS320C6000 Assembly Language Tools User's Guide (literature number SPRU186) describes assembly language tools (assembler, linker, other tools used develop assembly language code), assembler directives, macros, common object file format, symbolic debugging directives 'C6000 generation devices.
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TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions installing operating 'C6x evaluation module. also includes support software documentation, application programming interfaces, technical reference material. TMS320C6000 DSP/BIOS User's Guide (literature number SPRU303) describes DSP/BIOS tools APIs analyze embedded real-time applications. Code Composer User's Guide (literature number SPRU296) explains Code Composer development environment build debug embedded real-time applications. Code Composer Studio Tutorial (literature number SPRU301) introduces Code Composer Studio integrated development environment software tools. TMS320C6000 Technical Brief (literature number SPRU197) gives introduction 'C62x/C67x devices, associated development tools, third-party support. series textbooks published Prentice-Hall John Wiley Sons support research education. TMS320 newsletter, Details Signal Processing, published quarterly distributed update SMJ320 customers product information. TMS320 bulletin board service (BBS) provides access information pertaining SMJ320 family, including documentation, source code, object code many algorithms utilities. reached 281/274-2323. Information regarding products also available Worldwide http://www.ti.com uniform resource locator (URL).
Clock
internal 'C67x clocks generated from single source through CLKIN pin. This source clock either drives PLL, which multiplies source clock frequency generate internal clock, bypasses become internal clock. generate clock, external filter circuit must properly designed. Table Table Figure show external circuitry either (PLL bypass) multiply modes. Table Figure show external circuitry system with ONLY (PLL bypass) mode. minimize clock jitter, single clean power supply should power both 'C67x device external clock oscillator circuit. Noise coupling into PLLF will directly impact clock jitter. minimum CLKIN rise fall times should also observed. input clock timing requirements, input output clocks electricals section. Guidelines filter selection follows: maximum attenuation frequency 20-30 MHz, maximum attenuation 45-50 minimum attenuation above Table CLKOUT1 Frequency Ranges
PLLFREQ3 (C13) PLLFREQ2 (G11) PLLFREQ1 (F11) CLKOUT1 FREQUENCY RANGE (MHz) 50-140
overlap frequency ranges when choosing PLLFREQ, more than frequency range contain CLKOUT1 frequency. Choose lowest frequency range that includes desired frequency. example, CLKOUT1 MHz, choose PLLFREQ value 000b. PLLFREQ values other than 000b, 001b, 010b reserved.
Table 'C6701 Component Selection Table
CLKMODE CLKIN RANGE (MHz) 12.5 41.7 CLOCK FREQUENCY (CLKOUT1) RANGE (MHz) 50-140 CLKOUT2 RANGE (MHz) 83.5 60.4 (nF) (pF) TYPICAL LOCK TIME (µs)
Under some operating conditions, maximum lock time vary much 150% from specified typical value. example, typical lock time specified maximum value long
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AVAILABLE MULTIPLY FACTORS CLKMODE1 CLKMODE0 MULTIPLY FACTORS x1(BYPASS) Reserved Reserved
PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV Filter CLKMODE0 CLKMODE
CLOCK FREQUENCY F(CPUCLOCK) f(CLKIN) Reserved Reserved f(CLKIN)
Table
3.3V
PLLMULT PLLCLK
Internal 'C670
CLKIN
CLKIN LOOP FILTER
CLOCK
Keep lead length number vias between PLLF pin, PLLG pin, minimum. addition, place external components (R1, filter) close 'C6000 device possible. best performance, recommends that external components single side board without jumpers, switches, components other than ones shown. reduced jitter, maximize spacing between switching signals external components (R1, filter). 3.3-V supply filter must from same 3.3-V power plane supplying voltage, DVDD.
Figure External Circuitry Either Mode (Bypass) Mode
PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV CLKMODE0 CLKMODE1 Internal 'C6701 PLLMULT
PLLG
PLLF
3.3V
Table
PLLCLK
CLKIN
CLKIN LOOP FILTER
CLOCK
system with ONLY (bypass) mode, short PLLF terminal PLLG terminal. 3.3-V supply filter must from same 3.3-V power plane supplying voltage, DVDD.
Figure External Circuitry (Bypass) Mode Only
PLLG
PLLF
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Power-Supply Sequencing
DSPs require specific power sequencing between core supply supply. However, systems should designed ensure that neither supply powered extended periods time other supply below proper operating voltage.
System-Level Design Considerations
System-level design considerations, such contention, require supply sequencing implemented. this case, core supply should powered same time prior (and powered down after), buffers. This ensure that buffers receive valid inputs from core before output buffers powered thus, preventing contention with other chips board.
Power-Supply Design Considerations
systems using C6000DSP platform devices, core supply required provide excess until supply powered This extra current condition result uninitialized logic within DSP(s) corrected once sees internal clock pulse. With enabled, supply powered clock pulse produced stopping extra current draw from supply. With disabled, external clock pulse required stop this extra current draw. normal current state returns once power supply turned sees clock pulse. Decreasing amount time between core supply power supply power minimize effects this current draw. dual-power supply with simultaneous sequencing, such available with TPS563xx controllers PT69xx plug-in power modules, used eliminate delay between core power [see Using TPS56300 Power DSPs application report (literature number SLVA088)]. Schottky diode also used core rail rail, effectively pulling power supply level that help initialize logic within DSP. Core supply voltage regulators should located close array) minimize inductance resistance power delivery path. Additionally, when designing high-performance applications utilizing C6000platform DSPs, board should include separate power planes core, I/O, ground, bypassed with high-quality low-ESL/ESR capacitors.
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Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
CVDD DVDD Supply voltage range Supply voltage range Input voltage range Output voltage range Tstg Operating case temperature range Storage temperature range S-suffix device W-suffix device -0.3 -0.3 -0.3 -0.3 UNIT
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. voltage values with respect VSS.
Recommended Operating Conditions
CVDD DVDD Supply voltage Supply voltage Supply ground High-level input voltage Low-level input voltage High-level output current Low-level output current Case temperature S-suffix device W-suffix device 1.81 3.14 1.99 3.46 UNIT
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Electrical Characteristics
over recommended ranges supply voltage operating case temperature (unless otherwise noted) (unchanged after kRad)
PARAMETER IDD2V IDD2V IDD3V High-level output voltage Low-level output voltage Input current Off-state output current Supply current, memory access Supply current, peripherals Supply current, pins Input capacitance Output capacitance included internal pullups. TRST included internal pulldown. Measured with average activity: time: instructions cycle, 32-bit DMEM access cycle time: instructions cycle, 16-bit DMEM access cycle Measured with average peripheral activity: time: Timers rate, McBSPs rate, burst transfer between DMEM SDRAM time: Timers rate, McBSPs rate, servicing McBSPs Measured with average activity (30-pF load, SDCLK on): time: Reads from external SDRAM time: Writes external SDRAM time: activity This parameter tested. TEST CONDITIONS DVDD MIN, DVDD MIN, DVDD DVDD CVDD NOM, clock CVDD NOM, clock DVDD NOM, clock
UNIT
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PARAMETER MEASUREMENT INFORMATION
Tester Electronics Output Under Test
Vref
pF(1)
Typical distributed load circuit capacitance.
Signal-Transition Levels
input output timing parameters referenced both logic levels.
Vref
Figure Input Output Voltage Reference Levels Timing Measurements
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INPUT OUTPUT CLOCKS Timing Requirements CLKIN
(see Figure
tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN Transition time, CLKIN CLKMODE 28.4 0.4C 0.4C CLKMODE 0.45C 0.45C UNIT
reference points rise fall transitions measured 80%, respectively, VIH. This parameter tested. CLKIN cycle time example, when CLKIN frequency MHz,
CLKIN
Figure CLKIN Timing
Switching Characteristics CLKOUT1
(see Figure
tc(CKO1) tw(CKO1H) tw(CKO1L) tt(CKO1) PARAMETER Cycle time, CLKOUT1 Pulse duration, CLKOUT1 high Pulse duration, CLKOUT1 Transition time, CLKOUT1 CLKMODE (P/2)
CLKMODE
UNIT
(P/2)
(P/2)
(P/2)
1/CPU clock frequency nanoseconds (ns). high period CLKIN period CLKIN This parameter tested.
CLKOUT1
Figure CLKOUT1 Timing
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Switching Characteristics CLKOUT2
(see Figure
tc(CKO2) tw(CKO2H) tw(CKO2L) tt(CKO2) PARAMETER Cycle time, CLKOUT2 Pulse duration, CLKOUT2 high Pulse duration, CLKOUT2 Transition time, CLKOUT2
UNIT
1/CPU clock frequency This parameter tested.
CLKOUT2
Figure CLKOUT2 Timing
SDCLK, SSCLK Timing Parameter
SDCLK timing parameters same CLKOUT2 parameters. SSCLK timing parameters same CLKOUT1 CLKOUT2 parameters, depending SSCLK configuration.
Switching Characteristics Relation SSCLK, SDCLK, CLKOUT2 CLKOUT(see Figure
td(CKO1-SSCLK) td(CKO1-SSCLK1/2) td(CKO1-CKO2) td(CKO1-SDCLK) PARAMETER Delay time, CLKOUT1 edge SSCLK edge Delay time, CLKOUT1 edge SSCLK edge (1/2 clock rate) Delay time, CLKOUT1 edge CLKOUT2 edge Delay time, CLKOUT1 edge SDCLK edge -0.8 -1.5 -1.5 UNIT
CLKOUT1 SSCLK SSCLK (1/2rate) CLKOUT2 SDCLK
Figure Relation CLKOUT2, SDCLK, SSCLK CLKOUT
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ASYNCHRONOUS MEMORY TIMING Timing Requirements Asynchronous Memory Cycles
(see Figure Figure
tsu(EDV-CKO1H) th(CKO1H-EDV) tsu(ARDY-CKO1H) th(CKO1H-ARDY) Setup time, read valid before CLKOUT1 high Hold time, read valid after CLKOUT1 high Setup time, ARDY valid before CLKOUT1 high Hold time, ARDY valid after CLKOUT1 high UNIT
ensure data setup time, simply program strobe width wide enough. ARDY internally synchronized. ARDY does meet setup hold time, recognized current cycle next cycle. Thus, ARDY asynchronous input.
Switching Characteristics Asynchronous Memory Cycles
(see Figure Figure
td(CKO1H-CEV) td(CKO1H-BEV) td(CKO1H-BEIV) td(CKO1H-EAV) td(CKO1H-EAIV) td(CKO1H-AOEV) td(CKO1H-AREV) td(CKO1H-EDV) td(CKO1H-EDIV) td(CKO1H-AWEV) PARAMETER Delay time, CLKOUT1 high valid Delay time, CLKOUT1 high valid Delay time, CLKOUT1 high invalid Delay time, CLKOUT1 high valid Delay time, CLKOUT1 high invalid Delay time, CLKOUT1 high valid Delay time, CLKOUT1 high valid Delay time, CLKOUT1 high valid Delay time, CLKOUT1 high invalid Delay time, CLKOUT1 high valid UNIT
minimum delay also minimum output hold after CLKOUT1 high.
Setup CLKOUT1 BE[3:0] EA[21:2] ED[31:0] ARDY Strobe ready
HOLD
Figure Asynchronous Memory Read Timing
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Setup CLKOUT1 BE[3:0] EA[21:2]
Strobe
ready HOLD
ED[31:0] ARDY
Figure Aysnchronous Memory Write Timing
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SYNCHRONOUS-BURST MEMORY TIMING Timing Requirements Synchronous-Burst SRAM Cycles (Full-Rate SSCLK)
(see Figure
tsu(EDV-SSCLKH) th(SSCLKH-EDV) Setup time, read valid before SSCLK high Hold time, read valid after SSCLK high UNIT
Switching Characteristics Synchronous-burst SRAM Cycles (Full-Rate SSCLK)
(see Figure Figure
tosu(CEV-SSCLKH) toh(SSCLKH-CEV) tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) tosu(ADSV-SSCLKH) toh(SSCLKH-ADSV) tosu(OEV-SSCLKH) toh(SSCLKH-OEV) tosu(EDV-SSCLKH) toh(SSCLKH-EDIV) tosu(WEV-SSCLKH) toh(SSCLKH-WEV) PARAMETER Output setup time, valid before SSCLK high Output hold time, valid after SSCLK high Output setup time, valid before SSCLK high Output hold time, invalid after SSCLK high Output setup time, valid before SSCLK high Output hold time, invalid after SSCLK high Output setup time, SSADS valid before SSCLK high Output hold time, SSADS valid after SSCLK high Output setup time, SSOE valid before SSCLK high Output hold time, SSOE valid after SSCLK high Output setup time, valid before SSCLK high Output hold time, invalid after SSCLK high Output setup time, SSWE valid before SSCLK high Output hold time, SSWE valid after SSCLK high 0.5P 0.5P 0.5P 0.5P 0.5P 0.5P 0.5P 0.5P 0.5P 0.5P 0.5P 0.5P 0.5P 0.5P UNIT
effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. When used (CLKMODE x4), 1/CPU clock frequency example, when running parts MHz, CLKMODE 0.5P defined (pulse duration CLKIN high) output setup times; 0.5P defined (pulse duration CLKIN low) output hold times.
SSCLK BE[3:0] EA[21:2] ED[31:0] SSADS SSOE SSWE
Figure SBSRAM Read Timing (Full-Rate SSCLK)
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SSCLK BE[3:0] EA[21:2] ED[31:0] SSADS SSOE SSWE
Figure SBSRAM Write Timing (Full-Rate SSCLK)
Timing Requirements Synchronous-Burst SRAM Cycles (Half-Rate SSCLK)
(seeFigure
tsu(EDV-SSCLKH) th(SSCLKH-EDV) Setup time, read valid before SSCLK high Hold time, read valid after SSCLK high UNIT
Switching Characteristics Synchronous-Burst SRAM Cycles (Half-Rate SSCLK)
(see Figure Figure
tosu(CEV-SSCLKH) toh(SSCLKH-CEV) tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) tosu(ADSV-SSCLKH) toh(SSCLKH-ADSV) tosu(OEV-SSCLKH) toh(SSCLKH-OEV) tosu(EDV-SSCLKH) toh(SSCLKH-EDIV) tosu(WEV-SSCLKH) toh(SSCLKH-WEV) PARAMETER Output setup time, valid before SSCLK high Output hold time, valid after SSCLK high Output setup time, valid before SSCLK high Output hold time, invalid after SSCLK high Output setup time, valid before SSCLK high Output hold time, invalid after SSCLK high Output setup time, SSADS valid before SSCLK high Output hold time, SSADS valid after SSCLK high Output setup time, SSOE valid before SSCLK high Output hold time, SSOE valid after SSCLK high Output setup time, valid before SSCLK high Output hold time, invalid after SSCLK high Output setup time, SSWE valid before SSCLK high Output hold time, SSWE valid after SSCLK high 1.5P 0.5P 1.5P 0.5P 1.5P 0.5P 1.5P 0.5P 1.5P 0.5P 1.5P 0.5P 1.5P 0.5P UNIT
effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. When used (CLKMODE x4), 1/CPU clock frequency example, when running parts MHz, CLKMODE 1.5P where 1/CPU clock frequency, pulse duration CLKIN high. 0.5P where pulse duration CLKIN low.
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SSCLK BE[3:0] ED[31:0] SSADS SSOE SDWE
EA[21:2]
Figure SBSRAM Read Timing (Half-Rate SSCLK)
SSCLK BE[3:0] ED[31:0] SSADS SSOE SSWE
EA[21:2]
Figure SBSRAM Write Timing (Half-Rate SSCLK)
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SYNCHRONOUS DRAM TIMING Timing Requirements Synchronous DRAM Cycles
(see Figure
tsu(EDV-SDCLKH) th(SDCLKH-EDV) Setup time, read valid before SDCLK high Hold time, read valid after SDCLK high UNIT
Switching Characteristics Synchronous DRAM Cycles
(see Figure Figure
tosu(CEV-SDCLKH) toh(SDCLKH-CEV) tosu(BEV-SDCLKH) toh(SDCLKH-BEIV) tosu(EAV-SDCLKH) toh(SDCLKH-EAIV) tosu(SDCAS-SDCLKH) toh(SDCLKH-SDCAS) tosu(EDV-SDCLKH) toh(SDCLKH-EDIV) tosu(SDWE-SDCLKH) toh(SDCLKH-SDWE) tosu(SDA10V-SDCLKH) toh(SDCLKH-SDA10IV) tosu(SDRAS-SDCLKH) toh(SDCLKH-SDRAS) PARAMETER Output setup time, valid before SDCLK high Output hold time, valid after SDCLK high Output setup time, valid before SDCLK high Output hold time, invalid after SDCLK high Output setup time, valid before SDCLK high Output hold time, invalid after SDCLK high Output setup time, SDCAS valid before SDCLK high Output hold time, SDCAS valid after SDCLK high Output setup time, valid before SDCLK high Output hold time, invalid after SDCLK high Output setup time, SDWE valid before SDCLK high Output hold time, SDWE valid after SDCLK high Output setup time, SDA10 valid before SDCLK high Output hold time, SDA10 invalid after SDCLK high Output setup time, SDRAS valid before SDCLK high Output hold time, SDRAS valid after SDCLK high 1.5P 0.5P 1.5P 0.5P 1.5P 0.5P 1.5P 0.5P 1.5P 0.5P 1.5P 0.5P 1.5P 0.5P 1.5P 0.5P UNIT
effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. When used (CLKMODE x4), 1/CPU clock frequency example, when running parts MHz, CLKMODE 1.5P where 1/CPU clock frequency, pulse duration CLKIN high. 0.5P where pulse duration CLKIN low.
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READ SDCLK BE[3:0] EA[15:2]
READ
READ
ED[31:0] SDA10 SDRAS SDCAS SDWE
Figure Three SDRAM Read Commands
WRITE SDCLK BE[3:0] EA[15:2] SDA10 SDRAS SDCAS SDWE WRITE WRITE
ED[31:0]
Figure Three SDRAM Write Commands
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ACTV SDCLK BE[3:0] Bank Activate/Row Address
EA[15:2] ED[31:0]
SDA10 SDRAS SDCAS SDWE Address
Figure SDRAM ACTV Command
DCAB SDCLK BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS SDWE
Figure SDRAM DCAB Command
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REFR SDCLK BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS SDWE
Figure SDRAM REFR Command
SDCLK BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS SDWE Value
Figure SDRAM Command
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HOLD/HOLDA TIMING Timing Requirements Hold/Hold Acknowledge Cycles
(see Figure
tsu(HOLDH-CKO1H) th(CKO1H-HOLDL) Setup time, HOLD high before CLKOUT1 high Hold time, HOLD after CLKOUT1 high UNIT
HOLD synchronized internally. Therefore, setup hold times met, will either recognized current cycle next cycle. Thus, HOLD asynchronous input.
Switching Characteristics Hold/Hold Acknowledge Cycles
(seeFigure
tR(HOLDL-EMHZ) tR(EMHZ-HOLDAL) tR(HOLDH-HOLDAH) td(CKO1H-HOLDAL) td(CKO1H-BHZ) td(CKO1H-BLZ) tR(HOLDH-BLZ) PARAMETER Response time, HOLD EMIF high impedance Response time, EMIF high impedance HOLDA Response time, HOLD high HOLDA high Delay time, CLKOUT1 high HOLDA valid Delay time, CLKOUT1 high EMIF high impedance Delay time, CLKOUT1 high EMIF impedance Response time, HOLD high EMIF impedance
UNIT
1/CPU clock frequency example, when running parts MHz, pending EMIF transactions allowed complete before HOLDA asserted. worst cases this asynchronous read write with external ARDY used minimum eight consecutive SDRAM reads writes when RBTR8 transactions occurring, then minimum delay time achieved. Also, hold indefinitely delayed setting NOHOLD EMIF consists CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE. This parameter tested.
Owns
External Requester
Owns
CLKOUT1 HOLD HOLDA EMIF Bus(1) 'C6701 'C6701
EMIF consists CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE.
Figure HOLD/HOLDA Timing
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RESET TIMING Timing Requirements Reset
(see Figure
Width RESET pulse (PLL stable) Width RESET pulse (PLL needs sync UNIT CLKOUT cycles
tw(RESET)
This parameter applies CLKMODE when CLKIN stable applies CLKMODE when CLKIN stable. This parameter tested. This parameter only applies CLKMODE RESET signal connected internally clock circuit. PLL, however, need stabilize following device powerup after configuration been changed. During that time, RESET must asserted ensure proper device operation. clock section lock times.
Switching Characteristics During Reset
(see Figure
tR(RESET) td(CKO1H-CKO2IV) td(CKO1H-CKO2V) td(CKO1H-SDCLKIV) td(CKO1H-SDCLKV) td(CKO1H-SSCKIV) td(CKO1H-SSCKV) td(CKO1H-LOWIV) td(CKO1H-LOWV) td(CKO1H-HIGHIV) td(CKO1H-HIGHV) td(CKO1H-ZHZ) td(CKO1H-ZV) PARAMETER Response time change value RESET signal Delay time, CLKOUT1 high CLKOUT2 invalid Delay time, CLKOUT1 high CLKOUT2 valid Delay time, CLKOUT1 high SDCLK invalid Delay time, CLKOUT1 high SDCLK valid Delay time, CLKOUT1 high SSCLK invalid Delay time, CLKOUT1 high SSCLK valid Delay time, CLKOUT1 high group invalid Delay time, CLKOUT1 high group valid Delay time, CLKOUT1 high high group invalid Delay time, CLKOUT1 high high group valid Delay time, CLKOUT1 high group high impedance Delay time, CLKOUT1 high group valid -(2)
UNIT CLKOUT1 cycles
group consists IACK, INUM[3:0], DMAC[3:0], TOUT0, TOUT1. High group consists HRDY HINT. group consists EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1. This parameter tested
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CLKOUT1 RESET CLKOUT2 SDCLK SSCLK GROUP(1) HIGH GROUP(1) GROUP(1)
group consists IACK, INUM[3:0], DMAC[3:0], TOUT0, TOUT1. High group consists HRDY HINT. group consists EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1.
Figure Reset Timing
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EXTERNAL INTERRUPT/RESET TIMING Timing Requirements Interrupt Response Cycles
(see Figure
tw(ILOW) tw(IHIGH) Width interrupt pulse Width interrupt pulse high UNIT
Interrupt signals synchronized internally potentially recognized cycle later setup hold times violated. Thus, they connected asynchronous inputs. 1/CPU clock frequency example, when running parts MHz, This parameter tested.
Switching Characteristics During Interrupt Response Cycles
(see Figure
tR(EINTH-IACKH) td(CKO2L-IACKV) td(CKO2L-INUMV) td(CKO2L-INUMIV) PARAMETER Response time, EXT_INTx high IACK high Delay time, CLKOUT2 IACK valid Delay time, CLKOUT2 INUMx valid Delay time, CLKOUT2 INUMx invalid -0.5P -0.5P 0.5P 0.5P UNIT
1/CPU clock frequency example, when running parts MHz, When used (CLKMODE x4), 0.5P 1/(2 clock frequency). CLKMODE 0.5P where high period CLKIN.
CLKOUT2 EXT_INTx, Intr Flag IACK INUMx Interrupt Number
Figure Interrupt Timing
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HOST-PORT INTERFACE TIMING Timing Requirements Host-Port Interface Cycles
(see Figure Figure Figure Figure
tsu(SEL-HSTBL) th(HSTBL-SEL) tw(HSTBL) tw(HSTBH) tsu(SEL-HASL) th(HASL-SEL) tsu(HDV-HSTBH) th(HSTBH-HDV) th(HRDYL-HSTBL) tsu(HASL-HSTBL) th(HSTBL-HASL) Setup time, select signals valid before HSTROBE Hold time, select signals valid after HSTROBE Pulse duration, HSTROBE Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals valid before Hold time, select signals valid after Setup time, host data valid before HSTROBE high Hold time, host data valid after HSTROBE high Hold time, HSTROBE after HRDY low. HSTROBE should inactivated until HRDY active (low); otherwise, writes will complete properly. Setup time, before HSTROBE Hold time, after HSTROBE
UNIT
HSTROBE refers following logical operation HCS, HDS1, HDS2: [NOT(HDS1 HDS2)] HCS. effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. 1/CPU clock frequency example, when running parts MHz, Select signals include: HCNTRL[1:0], HR/W, HHWIL. This parameter tested.
Switching Characteristics During Host-Port Interface Cycles
(see Figure Figure Figure Figure
td(HCS-HRDY) td(HSTBL-HRDYH) toh(HSTBL-HDLZ) td(HDV-HRDYL) toh(HSTBH-HDV) td(HSTBH-HDHZ) td(HSTBL-HDV) td(HSTBH-HRDYH) PARAMETER Delay time, HRDY Delay time, HSTROBE HRDY high Output hold time, impedance after HSTROBE read Delay time, valid HRDY Output hold time, valid after HSTROBE high Delay time, HSTROBE high high impedance Delay time, HSTROBE valid Delay time, HSTROBE high HRDY high
UNIT
HSTROBE refers following logical operation HCS, HDS1, HDS2: [NOT(HDS1 HDS2)] HCS. effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. 1/CPU clock frequency example, when running parts MHz, enables HRDY, HRDY always when high. case where HRDY goes high when falls indicates that busy completing previous HPID write READ with autoincrement. This parameter used during HPID read. beginning first half-word transfer falling edge HSTROBE, sends request auxiliary channel, HRDY remains high until auxiliary channel loads requested data into HPID. This parameter tested. This parameter used after second half-word HPID write autoincrement read. HRDY remains access HPID write autoincrement read. Reading writing HPIC HPIA does affect HRDY signal.
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HCNTL[1:0] HR/W HHWIL HSTROBE(1) HD[15:0] (output) HRDY (case HRDY (case half-word half-word
HSTROBE refers following logical operation HCS, HDS1, HDS2: [NOT(HDS1 HDS2)] HCS.
Figure Read Timing (HAS Used, Tied High)
HCNTL[1:0] HR/W HHWIL HSTROBE(1) HD[15:0] (output) HRDY (case HRDY (case half-word half-word
HSTROBE refers following logical operation HCS, HDS1, HDS2: [NOT(HDS1 HDS2)] HCS.
Figure Read Timing (HAS Used)
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HCNTL[1:0] HBE[1:0] HR/W HHWIL HSTROBE(1) HD[15:0] (input) HRDY half-word half-word
HSTROBE refers following logical operation HCS, HDS1, HDS2: [NOT(HDS1 HDS2)] HCS.
Figure Write Timing (HAS Used, Tied High)
HBE[1:0] HCNTL[1:0] HR/W HHWIL HSTROBE(1) HD[15:0] (input) HRDY half-word half-word
HSTROBE refers following logical operation HCS, HDS1, HDS2: [NOT(HDS1 HDS2)] HCS.
Figure Write Timing (HAS Used)
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MULTICHANNEL BUFFERED SERIAL PORT TIMING Timing Requirements McBSP
(see Figure
tc(CKRX) tw(CKRX) tsu(FRH-CKRL) th(CKRL-FRH) tsu(DRV-CKRL) th(CKRL-DRV) tsu(FXH-CKXL) th(CKXL-FXH) Cycle time, CLKR/X Pulse duration, CLKR/X high CLKR/X Setup time, external high before CLKR Hold time, external high after CLKR Setup time, valid before CLKR Hold time, valid after CLKR Setup time, external high before CLKX Hold time, external high after CLKX CLKR/X CLKR/X CLKR CLKR CLKR CLKR CLKR CLKR CLKR CLKR CLKX CLKX CLKX CLKX UNIT
1/CPU clock frequency example, when running parts MHz, CLKRP CLKXP FSRP FSXP control register (PCR). polarity signals inverted, then timing references that signal also inverted. This parameter tested.
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Switching Characteristics McBSP
(see Figure
td(CKSH-CKRXH) tc(CKRX) tw(CKRX) td(CKRH-FRV) td(CKXH-FXV) tdis(CKXH-DXHZ) td(CKXH-DXV) PARAMETER Delay time, CLKS high CLKR/X high internal CLKR/X generated from CLKS input Cycle time, CLKR/X Pulse duration, CLKR/X high CLKR/X Delay time, CLKR high internal valid Delay time, CLKX high internal valid Disable time, high impedance following last data from CLKX high Delay time, CLKX high valid. Delay time, high valid. ONLY applies when data delay (XDATDLY 00b) mode. CLKR/X CLKR/X CLKR CLKX CLKX CLKX CLKX CLKX CLKX
UNIT
td(FXH-DXV)
CLKRP CLKXP FSRP FSXP control register (PCR). polarity signals inverted, then timing references that signal also inverted. Minimum delay times also represent minimum output hold times. 1/CPU clock frequency example, when running parts MHz, sample rate generator input clock CLKSM 1/CPU clock frequency) sample rate generator input clock P_clks CLKSM (P_clks CLKS period) CLKX high pulse width (CLKGDV/2 CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKX pulse width (CLKGDV/2) CLKGDV even (CLKGDV 1)/2 CLKGDV zero This parameter tested.
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CLKS CLKR (int) (ext) CLKX (int) (ext) (XDATDLY=00b) Bit(n-1) (n-2) (n-3) Bit(n-1) (n-2) (n-3)
Figure McBSP Timing
Timing Requirements When GSYNC (see Figure
tsu(FRH-CKSH) th(CKSH-FRH) Setup time, high before CLKS high Hold time, high after CLKS high
UNIT
This parameter tested.
CLKS external CLKR/X need resync) CLKR/X(needs resync)
Figure Timing When GSYNC
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Timing Requirements McBSP Master Slave: CLKSTP 10b, CLKXP
(seeFigure
tsu(DRV-CKXL) th(CKXL-DRV) Setup time, valid before CLKX Hold time, valid after CLKX MASTER SLAVE UNIT
effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV
Switching Characteristics McBSP Master Slave: CLKSTP 10b, CLKXP=0
(see Figure
th(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) tdis(CKXL-DXHZ) tdis(FXH-DXHZ) td(FXL-DXV) PARAMETER Hold time, after CLKX Delay time, CLKX high Delay time, CLKX high valid Disable time, high impedance following last databit from CLKX Disable time, high impedance following last databit from high Delay time, valid MASTER
SLAVE
UNIT
effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV sample rate generator input clock CLKSM 1/CPU clock frequency) sample rate generator input clock P_clks CLKSM (P_clks CLKS period) CLKX period CLKGDV) CLKX high pulse width (CLKGDV/2 CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKX pulse width (CLKGDV/2) CLKGDV even (CLKGDV 1)/2 CLKGDV zero FSRP FSXP master, inverted provide active-low slave-enable output. slave, active-low signal input inverted before being used internally. CLKXM FSXM CLKRM FSRM master McBSP CLKXM CLKRM FSXM FSRM slave McBSP should before rising edge clock enable slave devices then begin transfer rising edge master clock (CLKX). This parameter tested.
CLKX Bit(n-1) Bit(n-1) (n-2) (n-3) (n-4) (n-2) (n-3) (n-4)
Figure McBSP Timing Master Slave: CLKSTP 10b, CLKXP
Timing Requirements Master Slave: CLKSTP 11b, CLKXP
(see Figure
effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. 1/CPU clock frequency example, when running parts MHz, Submit Documentation Feedback
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Timing Requirements Master Slave: CLKSTP 11b, CLKXP (continued)
(see Figure
tsu(DRV-CKXH) th(CKXH-DRV) Setup time, valid before CLKX high Hold time, valid after CLKX high MASTER SLAVE UNIT
Switching Characteristics McBSP Master Slave: CLKSTP 11b, CLKXP
(see Figure
th(CKXL-FXL) td(FXL-CKXH) td(CKXL-DXV) tdis(CKXL-DXHZ) td(FXL-DXV) PARAMETER Hold time, after CLKX Delay time, CLKX high Delay time, CLKX valid Disable time, high impedance following last data from CLKX Delay time, valid
MASTER
SLAVE
UNIT
effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV sample rate generator input clock CLKSM 1/CPU clock frequency) sample rate generator input clock P_clks CLKSM (P_clks CLKS period) CLKX period CLKGDV) CLKX high pulse width (CLKGDV/2 CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKX pulse width (CLKGDV/2) CLKGDV even (CLKGDV 1)/2 CLKGDV zero FSRP FSXP master, inverted provide active-low slave-enable output. slave, active-low signal input inverted before being used internally. CLKXM FSXM CLKRM FSRM master McBSP CLKXM CLKRM FSXM FSRM slave McBSP should before rising edge clock enable slave devices then begin transfer rising edge master clock (CLKX). This parameter tested.
CLKX Bit(n-1) Bit(n-1) (n-2) (n-2) (n-3) (n-4) (n-3) (n-4)
Figure McBSP Timing Master Slave: CLKSTP 11b, CLKXP
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Timing Requirements MCBSP Master Slave: CLKSTOP 10b, CLKXP
(see Figure
tsu(DRV-CKXH) th(CKXH-DRV) Setup time, valid before CLKX high Hold time, valid after CLKX high MASTER SLAVE UNIT
effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV
Switching Characteristics McBSP Master Slave: CLKSTP 10b, CLKXP
(see Figure
th(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) tdis(CKXH-DXHZ) tdis(FXH-DXHZ) td(FXL-DXV) PARAMETER Hold time, after CLKX high Delay time, CLKX Delay time, CLKX valid Disable time, high impedance following last data from CLKX high Disable time, high impedance following last data from high Delay time, valid MASTER
SLAVE
UNIT
effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV sample rate generator input clock CLKSM 1/CPU clock frequency) sample rate generator input clock P_clks CLKSM (P_clks CLKS period) CLKX period CLKGDV) CLKX high pulse width (CLKGDV/2 CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKX pulse width (CLKGDV/2) CLKGDV even (CLKGDV 1)/2 CLKGDV zero FSRP FSXP master, inverted provide active-low slave-enable output. slave, active-low signal input inverted before being used internally. CLKXM FSXM CLKRM FSRM master McBSP CLKXM CLKRM FSXM FSRM slave McBSP should before rising edge clock enable slave devices then begin transfer rising edge master clock (CLKX). This parameter tested.
CLKX Bit(n-1) Bit(n-1) (n-2) (n-3) (n-4) (n-2) (n-3) (n-4)
Figure McBSP Timing Master Slave: CLKSTP 10b, CLKXP
Timing Requirements McBSP Master Slave: CLKSTOP 11b, CLKXP
(see Figure
effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV Submit Documentation Feedback
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Timing Requirements McBSP Master Slave: CLKSTOP 11b, CLKXP (continued)
(see Figure
tsu(DRV-CKXL) th(CKXL-DRV) Setup time, valid before CLKX Hold time, valid after CLKX MASTER SLAVE UNIT
Switching Characteristics McBSP Master Slave: CLKSTP 11b, CLKXP
(see Figure
th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ) td(FXL-DXV) PARAMETER Hold time, after CLKX high Delay time, CLKX Delay time, CLKX high valid Disable time, high impedance following last data from CLKX high Delay time, valid MASTER
SLAVE
UNIT
effects internal clock jitter included test. There need adjust timing numbers internal clock jitter. 1/CPU clock frequency example, when running parts MHz, slave modes, CLKG programmed clock setting CLKSM CLKGDV sample rate generator input clock CLKSM 1/CPU clock frequency) sample rate generator input clock P_clks CLKSM (P_clks CLKS period) CLKX period CLKGDV) CLKX high pulse width (CLKGDV/2 CLKGDV even (CLKGDV 1)/2 CLKGDV zero CLKX pulse width (CLKGDV/2) CLKGDV even (CLKGDV 1)/2 CLKGDV zero FSRP FSXP master, inverted provide active-low slave-enable output. slave, active-low signal input inverted before being used internally. CLKXM FSXM CLKRM FSRM master McBSP CLKXM CLKRM FSXM FSRM slave McBSP should before rising edge clock enable slave devices then begin transfer rising edge master clock (CLKX). This parameter tested.
CLKX Bit(n-1) Bit(n-1) (n-2) (n-2) (n-3) (n-4) (n-3) (n-4)
Figure McBSP Timing Master Slave: CLKSTP 11b, CLKXP
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DMAC, TIMER, POWER-DOWN TIMING Switching Characteristics DMAC Outputs
(see Figure
td(CKO1H-DMACV) PARAMETER Delay time, CLKOUT1 high DMAC valid UNIT
CLKOUT1 DMAC[0:3]
Figure DMAC Timing
Timing Requirements Timer Inputs
(see Figure
tw(TINPH) Pulse duration, TINP high UNIT
1/CPU clock frequency example, when running parts MHz,
Switching Characteristics Timer Outputs
(see Figure
td(CKO1H-TOUTV) PARAMETER Delay time, CLKOUT1 high TOUT valid UNIT
CLKOUT1 TINP TOUT
Figure Timer Timing
Switching Characteristics Power-Down Outputs
(seeFigure
td(CKO1H-PDV) PARAMETER Delay time, CLKOUT1 high valid UNIT
CLKOUT1
Figure Power-Down Timing
JTAG TEST-PORT TIMING Timing Requirements JTAG Test Port
(see Figure
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Timing Requirements JTAG Test Port (continued)
(see Figure
tc(TCK) tsu(TDIV-TCKH) th(TCKH-TDIV) Cycle time, Setup time, TDI/TMS/TRST valid before high Hold time, TDI/TMS/TRST valid after high UNIT
Switching Characteristics JTAG Test Port
(see Figure
td(TCKL-TDOV) PARAMETER Delay time, valid UNIT
This parameter tested.
TDI/TMS/TRST
Figure JTAG Test-Port Timing
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device 5962-9866101VXA 5962-9866102VXA 5962-9866102VYC
Status ACTIVE ACTIVE ACTIVE
Package Type CFCBGA CFCBGA FCLGA
Package Drawing
Pins Package Plan
Lead/Ball Finish Call Call Call
Peak Temp Type Type Type
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis. OTHER QUALIFIED VERSIONS SMJ320C6701-SP Catalog: SMJ320C6701 NOTE: Qualified Version Definitions: Catalog TI's standard catalog product
Addendum-Page
MECHANICAL DATA
MCBG004A SEPTEMBER 1998 REVISED JANUARY 2002
(S-CBGA-N429)
27,20 26,80
CERAMIC BALL GRID ARRAY
25,40 1,27 Corner 3,30 Bottom View
1,22 1,00
Seating Plane 0,90 0,60 0,10 0,15 4164732/B 11/0
0,70 0,50
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MO-156 Flip chip application only
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