Integrated Powerline Communication Analog Front-End Transceiver Line D
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Integrated Powerline Communication Analog Front-End Transceiver Line Driver
MAX2981 powerline communication analog frontend (AFE) line-driver state-of-the-art CMOS device that delivers high performance cost. This highly integrated design combines analog-to-digital converter (ADC), digital-to-analog converter (DAC), adaptive gain control (AGC), filters, line driver single chip. MAX2981 substantially reduces previously required system components complies with HomePlug® standard. Combined with Maxim's integrated PHY/MAC digital baseband, device delivers most flexible cost-effective solution. advanced design MAX2981 allows operation without external control, enabling simplified connection variety HomePlug digital ICs. MAX2981 specified over -40°C +105°C automotive temperature range offered 64-pin lead-free LQFP package. device qualified AEC-Q100 automotive standard. HomePlug Compliant Fully Integrated Line Driver Fully Compatible with MAX2982/MAX2986 Pin-to-Pin Compatible with MAX2980 Seamless Interface Third-Party Fully Integrated, 10-Bit, 50Msps 56dB Adaptive Gain Control Line Impedance Drive Capability Line-Driver Bypass Mode 220mA Mode 150mA Mode 3.3V -40°C +105°C Operating Temperature Range AEC-Q100 (Automotive) Qualified 64-Pin LQFP Package
Features
MAX2981
Ordering Information
PART MAX2981GCB/V+ TEMP RANGE -40°C +105°C PIN-PACKAGE LQFP
Applications
Local Area Networking (LAN) Broadband-over-Powerline (BPL) Remote Monitoring Control Energy Management Industrial Automation
denotes automotive qualified part. +Denotes lead(Pb)-free/RoHS-compliant part.
Configuration
FREEZE RESET DGND AGND AGND AGND AGND DVDD AVDD AVDD AVDD STBY ENTX I.C. I.C.
Building Automation IPTV Distribution
AGND AVDD PLIP PLIN AGND AVDD CEXT
DAD0 DGND DAD1 DAD2 DVDD3 DAD3 DAD4 DVDD3 DGND DAD5 DAD6 DVDD3 DAD7 DAD8 DGND DAD9
Typical Operating Circuit appears data sheet.
REXT AGND AGND PLOP
MAX2981
HomePlug registered trademark HomePlug Powerline Alliance, Inc.
AVDD AGND PLON AVDD AVDD
AGND
REGOUT
DVDD
DGND
SDIO
SCLK
SHRCV
ENREAD
DVDD
DGND
AGND
AVDD
DVDD3
AGND
LQFP
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim Direct 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Integrated Powerline Communication Analog Front-End Transceiver Line Driver MAX2981
ABSOLUTE MAXIMUM RATINGS
AVDD AGND .-0.3V +3.9V DVDD3 DGND .-0.3V +3.9V DVDD DGND .-0.3V +2.8V AGND DGND.-0.3V +0.3V Other Pins.-0.3V (VDD 0.3V) Current into Pin.±100mA Short-Circuit Duration (VREGOUT AGND) .10ms Continuous Power Dissipation +70°C) 64-Pin LQFP (derate 25mW/°C above +70°C).2000mW Operating Temperature Range .-40°C +105°C Junction Temperature .+150°C Storage Temperature Range .-40°C +150°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION! SENSITIVE DEVICE
ELECTRICAL CHARACTERISTICS
(VAVDD VDVDD3 +3.3V, DVDD REGOUT, VAGND VDGND VSHRCV -40°C +105°C, unless otherwise noted. Typical values +25°C.) (Note
PARAMETER Analog Supply Voltage Digital Supply Voltage Digital Supply Voltage SYMBOL VAVDD VDVDD3 VDVDD (Note Receive mode, transmitter disabled, signal applied Quiescent Supply Current IAVDD Transmit mode, receiver disabled, signal load applied clock VREGOUT tones 17MHz 18MHz input 1VP-P differential voltage (Note VDVDD (Note -51.5 ISOURCE ISINK CONDITIONS UNITS
Standby Supply Current Regulator Output Output-Voltage High Output-Voltage LOGIC INPUT Input High Voltage Input Voltage Input Leakage Current
ANALOG-TO-DIGITAL CONVERTER (ADC) Resolution Integral Nonlinearity Differential Nonlinearity Two-Tone 3rd-Order Distortion Bits
DIGITAL-TO-ANALOG CONVERTER (DAC) Resolution Integral Nonlinearity Differential Nonlinearity Two-Tone 3rd-Order Distortion tones 17MHz 18MHz output 1VP-P differential voltage Bits
Integrated Powerline Communication Analog Front-End Transceiver Line Driver
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD VDVDD3 +3.3V, DVDD REGOUT, VAGND VDGND VSHRCV -40°C +105°C, unless otherwise noted. Typical values +25°C.) (Note
PARAMETER RECEIVER Common-Mode Voltage Input Impedance Two-Tone 3rd-Order Distortion Receiver Gain Range Lowpass Filter -3dB Corner Frequency Lowpass Filter Ripple Highpass Filter -3dB Corner Frequency TRANSMITTER Common-Mode Voltage Output Impedance ZOUT Between PLOP/PLON 12.5MHz (Note Predriver gain -6dB 12.5MHz, VP-P single-ended output load Output Voltage Swing Predriver gain 12.5MHz, VP-P single-ended output load Predriver Output Voltage Swing Two-Tone 3rd-Order Distortion Lowpass Filter -3dB Corner Frequency Lowpass Filter Ripple Minimum Line Impedance Drive Capability Predriver Line Impedance Capability TIMING CHARACTERISTICS Frequency Fall Data Output Fall Data Latch Time tADCO tDACI Line driver bypass mode, predriver gain 3dB; single-ended output load tones 17MHz 18MHz (Note (Note Single-ended output Line driver bypass mode, single-ended output VP-P VP-P (Note (Note (Note Between PLIP PLIN 12MHz (Note tones 17MHz 18MHz input 1VP-P differential voltage SYMBOL CONDITIONS UNITS
MAX2981
Note values guaranteed design characterization -40°C production tested +25°C +105°C. Typical values tested functionally +25°C. Note Bypass internal 2.4V regulator with 0.1µF capacitor DGND. Note Typical values guaranteed design +25°C.
Integrated Powerline Communication Analog Front-End Transceiver Line Driver MAX2981
Description
NAME AGND Analog Ground Analog Power-Supply Voltage. AVDD supply range 3.0V 3.6V. Bypass AVDD with 0.1µF capacitor AGND. Powerline Positive Input Powerline Negative Input External Capacitor Connection. Connect 10nF capacitor from CEXT AGND. External Resistor Connection. Connect resistor from REXT AGND. Powerline Positive Output Powerline Negative Output Voltage Regulator Output. Connect REGOUT DVDD normal operation. Digital 2.4V Voltage Input. Connect DVDD REGOUT normal operation. Digital Ground Serial Data Input/Output Serial Clock Input Receiver Shutdown Control. Drive SHRCV high power down receiver. Drive normal operation. Read-Mode Enable Control. Drive ENREAD high place DAD[9:0] bidirectional buffers read mode. Data transferred from digital DAC. ENREAD signal frames transmission. Active-High Carrier-Select Input. Drive high initiate internal timer. Digital Power-Supply Voltage. DVDD3 supply range 3.0V 3.6V. Bypass DVDD3 DGND with 0.1µF capacitor close possible pin. 50MHz System Clock Input DAC/ADC Input/Output Data Bit. Input/output 10-bit, 50MHz bidirectional digital-to-analog analog-to-digital converter. Data binary format. DAC/ADC Input/Output Data Input/output 10-bit, 50MHz bidirectional digital-to-analog analog-to-digital converter. Data binary format. FUNCTION
AVDD PLIP PLIN CEXT REXT PLOP PLON REGOUT DVDD DGND SDIO SCLK SHRCV
ENREAD DVDD3 DAD9 DAD8
Integrated Powerline Communication Analog Front-End Transceiver Line Driver
Description (continued)
NAME DAD7 DAD6 DAD5 DAD4 DAD3 DAD2 DAD1 DAD0 FREEZE I.C. ENTX RESET STBY FUNCTION DAC/ADC Input/Output Data Input/output 10-bit, 50MHz bidirectional digital-to-analog analog-to-digital converter. Data binary format. DAC/ADC Input/Output Data Input/output 10-bit, 50MHz bidirectional digital-to-analog analog-to-digital converter. Data binary format. DAC/ADC Input/Output Data Input/output 10-bit, 50MHz bidirectional digital-to-analog analog-to-digital converter. Data binary format. DAC/ADC Input/Output Data Input/output 10-bit, 50MHz bidirectional digital-to-analog analog-to-digital converter. Data binary format. DAC/ADC Input/Output Data Input/output 10-bit, 50MHz bidirectional digital-to-analog analog-to-digital converter. Data binary format. DAC/ADC Input/Output Data Input/output 10-bit, 50MHz bidirectional digital-to-analog analog-to-digital converter. Data binary format. DAC/ADC Input/Output Data Input/output 10-bit, 50MHz bidirectional digital-to-analog analog-to-digital converter. Data binary format. DAC/ADC Input/Output Data Bit. Input/output 10-bit, 50MHz bidirectional digital-to-analog analog-to-digital converter. Data binary format. Active-High Freeze-Mode Enable. Drive FREEZE high place adaptive gain control (AGC) freeze mode. Drive FREEZE signal available companion baseband chip. Internally Connected. Leave these pins unconnected. Active-High Transmit Enable. Drive ENTX high enable transmitter. Drive ENTX place transmitter three-state. Active-High Register Write Enable. Drive high place registers write mode. Active-Low Reset Input. Drive RESET place MAX2981 reset mode. freerunning mode during reset. minimum reset pulse width 100ns. Active-High Standby Input. Drive STBY high place MAX2981 standby mode. Drive normal operation.
MAX2981
Integrated Powerline Communication Analog Front-End Transceiver Line Driver MAX2981
Functional Diagram
MAX2981
PLIP PLIN PLOP PLON DAD[9:0]
Detailed Description
MAX2981 powerline communication linedriver state-of-the-art CMOS device that delivers high performance cost. This highly integrated design combines ADC, DAC, AGC, filters, line driver single chip shown Functional Diagram. MAX2981 substantially reduces previously required system components complies with HomePlug standard. Combined with Maxim's integrated PHY/MAC digital baseband, device delivers most flexible cost-effective solution. advanced design MAX2981 allows operation without external control, enabling simplified connection variety HomePlug digital ICs.
integrates reference voltages biasing input differential signal.
Transmit Channel
transmit channel consists 10-bit DAC, LPF, adjustable-gain transmitter buffer line driver. receives data stream from digital through block. 50MHz, 10-bit provides complementary function receive channel. converts 10bit digital stream analog voltage 50MHz rate. removes spurs harmonics adjacent desired passband help reduce out-of-band transmitted frequencies energy from output. transmit buffer line-driver blocks allow output level obtain level necessary connect directly powerline medium, without external amplifiers buffers. output level adjustable from 1.4VP-P 4.0VP-P differential. line driver drive resistive loads singleended.
Receive Channel
receiver analog front-end consists variablegain amplifier (VGA), lowpass filter (LPF), highpass filter (HPF), circuit. block samples output. communicates digital chip through block. reduces receive channel input-referred noise providing some signal gain input. filter blocks remove unwanted noise, provide anti-aliasing required accurate sampling. scales signal conversion from analog digital. scaling maintains optimum signal level input keeps amplifiers saturation. 10-bit samples analog signal 50Msps converts 10-bit digital stream. block fully
Line Driver Bypass
register R6B[2:1] bypass line driver. With line driver bypassed, output drive singleended external load.
Digital Interface
digital interface composed control signals 10-bit bidirectional data ADC. control signals include reset line, transmit request, direction request, receiver shutdown control.
Integrated Powerline Communication Analog Front-End Transceiver Line Driver
Control Signals
Transmit Enable (ENTX) ENTX line enables transmitter MAX2981 circuit. With ENTX ENREAD driven high, data sent through DAD[9:0] conditioned delivered onto power line. Read Enable (ENREAD) ENREAD line sets direction data DAD[9:0]. With ENREAD high, data sent from digital MAX2981 AFE. ENREAD sends data from digital PHY. Receiver Power-Down (SHRCV) SHRCV line provides receiver shutdown control. logic-high SHRCV powers down receiver section MAX2981 whenever device transmitting. MAX2981 also features transmit power-saving mode, which reduces supply current from 350mA 150mA. enter transmit power-saving mode, drive SHRCV high 0.1µs prior transmission. Connect SHRCV ENTX ENREAD normal operation. Digital-to-Analog Analog-to-Digital Converter Input/Output (DAD[9:0]) DAD[9:0] 10-bit bidirectional connecting digital MAX2981 ADC. direction controlled ENREAD, described Read Enable (ENREAD) section. Control Signal (CS) signal controls circuit receive path MAX2981. logic-low sets gain circuit input signal continuously adapt maximum sensitivity. valid preamble detected digital raises high. While high, continues adapt additional 8µs; then locks currently adapted level incoming signal. digital holds high while receiving transmission, then lowers continuous adaptation maximum sensitivity other incoming signals. Freeze Mode (FREEZE) FREEZE signal instantly lock gain. Clock (CLK) signal provides timing MAX2981. Apply 50MHz clock this input. timing diagram (Figure more information. Reset Input (RESET) RESET signal provides reset control MAX2981. perform reset, free-running
tCLK 50MHz tADCO DATA tDACI DATA INPUT
MAX2981
Figure Timing Diagram
mode drive RESET minimum 100ns. Always perform reset power-up.
Standby Control (STBY) MAX2981 features low-power, shutdown mode that activated STBY. Drive STBY high place MAX2981 standby mode. standby, MAX2981 consumes only 20mA with clock without clock.
MAX2981 Control Registers
MAX2981 Serial Interface 3-wire serial interface controls MAX2981 operation mode. SCLK serial clock line register programming. SDIO serial data input output register writing reading. signal controls write/read mode serial interface.
high, serial interface write mode value written into MAX2981 registers. Following low-to-high transitions, data shifted synchronously (LSB first) registers falling edge serial clock (SCLK) illustrated Figure Note that extra clock (WR_CLK) required write content holding buffer appropriate register bank. low, serial interface read mode value current register read. read operation specific register must followed immediately after writing same register. Following high-to-low transitions, data shifted synchronously (LSB first) registers falling edge serial clock (SCLK) illustrated Figure MAX2981 read/write registers; bits register address bits.
Integrated Powerline Communication Analog Front-End Transceiver Line Driver MAX2981
SDAT
WR_CLK
SDAT
SCLK
SCLK
Figure Writing Mode Register Timing Diagram
Figure Reading Mode Register Timing Diagram
Table Register Addresses
REGISTER (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
MAX2981 Register Maps
Table Register
REGISTER R1B0 R1B1 R1B2 R1B3 R1B4 R1B5 R1B6 R1B7 R1B8 R1B9 R1B10 R1B11 R1B12 R1B13 R1B14 R1B15 DEFAULT High High COMMENT Active high, powers down receiver when transmit mode. Active high, powers down transmitter when receive mode. Active high, powers down when receive mode. Active high, powers down entire device. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved.
Integrated Powerline Communication Analog Front-End Transceiver Line Driver MAX2981
Table Register
REGISTER R2B0 R2B1 R2B2 R2B3 R2B4 R2B5 R2B6 R2B7 R2B8 R2B9 R2B10 R2B11 R2B12 R2B13 R2B14 R2B15 DEFAULT High Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Active high, bypass receive LPF. COMMENT
Table Register
REGISTER R3B0 R3B1 R3B2 R3B3 R3B4 R3B5 R3B6 R3B7 R3B8 R3B9 R3B10 R3B11 R3B[15:12] DEFAULT High 0111 Active high, place process tune continuous mode. Otherwise active only during reset. Reserved. Reserved. Reserved. These predriver gain follows setting 111: 3dB, 2dB, 1dB, 0dB, -1dB, -2dB, -3dB, -6dB R3B2 LSB. COMMENT
Integrated Powerline Communication Analog Front-End Transceiver Line Driver MAX2981
Table Register
REGISTER R4B0 R4B1 R4B2 R4B3 R4B4 R4B5 R4B[10:6] R4B11 R4B12 R4B13 R4B14 R4B15 DEFAULT High High High 01011 High High High High Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. COMMENT
Table Register
REGISTER R5B[6:0] R5B[12:7] R5B13 R5B14 R5B15 DEFAULT Reserved. Reserved. Reserved. Reserved. Reserved. COMMENT
Table Register
REGISTER R6B0 R6B[2:1] R6B3 R6B4 R6B[6:5] R6B7 R6B8 R6B9 R6B[11:10] R6B[13:12] R6B14 R6B15 DEFAULT High High Disable receiver highpass filter. Reserved. Reserved. Reserved. internal active; internal bypassed external load predriver current consumption 21mA; internal bypassed external load predriver current consumption 42mA. Reserved. Active high, allow bypass transmit LPF. COMMENT
Integrated Powerline Communication Analog Front-End Transceiver Line Driver
Applications Information
Interfacing Digital Circuit
MAX2981 interfaces MAX2982/MAX2986 digital baseband using bidirectional pass digital data from ADC. Handshake lines help accomplish data transfer operation MAX2981. application circuit diagram Figure shows connection MAX2981 MAX2982/MAX2986 digital baseband chip.
Layout Considerations
properly designed essential part high-speed circuit. controlled-impedance lines frequency inputs outputs. low-inductance connections ground ground pins wherever components connected ground. Place decoupling capacitors close connections. proper operation, connect metal exposed paddle back ground plane with multiple vias.
MAX2981
DAD[9:0]
MAX2981
ENREAD* ENTX*
MAX2982/MAX2986
PLIP SHRCV POWERLINE POWERLINE INTERFACE NEUTRAL PLOP PLIN SCLK SDI0 50MHz RESET STBY *SIGNALS CONNECTED CONTROL LINE. HOST INTERFACES
PLON
CLOCK
Figure Interfacing MAX2981 MAX2982/MAX2986
Integrated Powerline Communication Analog Front-End Transceiver Line Driver MAX2981
Typical Operating Circuit
RECEIVER 10nF DRIVER 10nF 100nF 560pF 220pF 270pF *10nF CAPACITOR NEUTRAL OPTIONAL 22nF 10nF* SPARK 22nF 10nF
POWERLINE
MAX2981
560pF
6.8µH
5.6µH
220pF
270pF
Chip Information
PROCESS: CMOS
Package Information
latest package outline information land patterns, www.maxim-ic.com/packages. PACKAGE TYPE LQFP PACKAGE CODE C64+1 DOCUMENT 21-0083
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2009 Maxim Integrated Products Maxim registered trademark Maxim Integrated Products, Inc.
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