6ED003L06-F Integrated Phase Gate Driver Power Management Dr

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6ED003L06-F Integrated Phase Gate Driver Power Management Dr

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Data sheet, Rev. 2.1, 2008
6ED003L06-F
Integrated Phase Gate Driver
Power Management Drives
6ED003L06-F Integrated Phase Gate Driver
6ED003L06-F Revision History: Previous Version: Page 2009-07 Subjects (major changes since last revision) changed Corrected RthJA Fig3 Fig13 Rev.
Edition 2006-01 Published Infineon Technologies 81726 Germany Infineon Technologies 7/28/09. Rights Reserved. Attention please! information given this data sheet shall event regarded guarantee conditions characteristics ("Beschaffenheitsgarantie"). With respect examples hints given herein, typical values stated herein and/or information regarding application device, Infineon Technologies hereby disclaims warranties liabilities kind, including without limitation warranties non-infringement intellectual property rights third party. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
Datasheet
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
Table Contents:
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7
Overview Features Description Configuration Description.5 Description /HIN1,2,3 /LIN1,2,3 (Low side high side control pins, (Gate driver enable, 10). /FAULT (Fault feedback, ITRIP RCIN (Over-current detection function, VCC, (Low side supply, 12,13) VB1,2,3 VS1,2,3 (High side supplies, 28). LO1,2,3 HO1,2,3 (Low High side outputs, 27). Electrical parameters.9 Absolute Maximum Ratings Required Operation Conditions. Operating Range Static Logic function Table Static Parameters. Dynamic Parameters. Timing Diagrams Package.17 Package Drawing Reference thermal resistance
Datasheet
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
Overview
Features Thin-film-SOI-technology Insensitivity bridge output negative transient voltages -50V given SOI-technology Maximum blocking voltage +600V Power supply high side drivers boot strap Separate control circuits drivers CMOS LSTTL compatible input (negative logic) Signal interlocking every phase prevent cross-conduction Detection over-current under-voltage supply 'shut down' switches during error conditions externally programmable delay fault clear after over current detection Description device 6ED003L06-F full bridge driver control power devices like MOS-transistors IGBTs 3phase systems with maximum blocking voltage +600V. Based used SOI-technology there excellent ruggedness transient voltages. parasitic thyristor structures present device. Hence, parasitic latch occur temperature voltage conditions. Figure Typical Application independent drivers controlled low-side using CMOS resp. LSTTL compatible signals, down 3.3V logic. device includes under-voltage detection unit with hysterese characteristic over-current detection. over-current level adjusted choosing resistor value threshold
3.3V HIN1,2,3 LIN1,2,3 FAULT RRCIN CRCIN RCIN ITRIP LO1,2,3 HIN1,2,3 LIN1,2,3 FAULT VB1,2,3 HO1,2,3 Load VS1,2,3 DC-Bus
PG-DSO28-17
RNTC
level ITRIP. Both error conditions (under-voltage over-current) lead definite shut-down switches. error signal provided FAULT open drain output pin. blocking time after overcurrent adjusted with RC-network RCIN. input RCIN owns internal current source Therefore, resistor RRCIN optional. minimum output current given with 120mA pull-up 250mA pull down. Because system safety reasons 380ns interlocking time been realised. function input optionally extended with over-temperature detection, using external NTC-resistor (see Fig.1). There parasitic diode structures between pins monolithic setup external bootstrap diodes still mandatory.
Datasheet
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
Configuration Description
Figure Configuration 6ED003L06-F
Table Description Symbol /HIN1,2,3 /LIN1,2,3 /FAULT ITRIP RCIN VB1,2,3 HO1,2,3 VS1,2,3 LO1,2,3 Description side power supply Logic ground High side logic input (negative logic) side logic input (negative logic) Indicates over-current under-voltage (negative logic, open-drain output) Enable functionality (positive logic) Analog input over-current shutdown, activates FAULT RCIN external RC-network define FAULT clear delay after FAULT-Signal (TFLTCLR) side gate driver reference High side positive power supply High side gate driver output High side negative power supply side gate driver output Connected 2.1.1 /HIN1,2,3 /LIN1,2,3 (Low side high side control pins, These pins active they responsible HO1,2,3 LO1,2,3 out-of-phase Rev. 2008
Description
Datasheet
6ED003L06-F Integrated Phase Gate Driver
commutation. schmitt-trigger input threshold them such guarantee LSTTL CMOS compatibility down 3.3V controller outputs. Under-voltage condition supply: this case fault condition released soon supply voltage condition returns normal operation range (please refer description more details). Over-current detection (ITRIP): fault condition latched until current trip condition finished RCIN input released (please refer ITRIP pin).
Figure Input structure internal pull-up resistor about prebiases input during supply start-up zener clamp provided protection purposes. Input schmitt-trigger noise filter provide beneficial noise rejection short input pulses according Figure Figure
Figure /Fault structure 2.1.4 ITRIP RCIN (Over-current detection function, 6ED003L06-F provides over-current detection function connecting ITRIP input with motor current feedback. ITRIP comparator threshold (typ 0.46V) referenced ground. input noise filter (typ: tITRIPMIN prevents driver detect false over-current events. Over-current detection generates hard shut down outputs gate driver provides latched fault feedback /FAULT pin. RCIN input/output used determine reset time fault condition. soon ITRIP threshold exceeded external capacitor connected RCIN fully discharged. capacitor then recharged RCIN current generator when over-current condition finished. soon RCIN voltage exceeds rising threshold VRCIN,TH 6.0V, fault condition releases driver returns operational following /HIN /LIN inputs. Please refer AN-GateDriver-6ED003L06-1 details setting RCIN time constant. 2.1.5 VCC, (Low side supply, 12,13) side supply provides power both input logic side output power stage. Input logic referenced ground well under-voltage detection circuit. Output power stage referenced ground.COM ground floating respect ground with recommended range operation +/-2.5V. back-to-back zener structure protects grounds from noise spikes. under-voltage circuit enables device operate power when typical supply voltage VCCUV+ present. Rev. 2008
Figure Input filter timing diagram anyway recommended proper work driver provide input pulse-width lower than 1us. 6ED003L06-F provides additionally antishoot through prevention capability which avoids simultaneous on-state gate drivers same (i.e. LO1, LO2, LO3). When inputs same activated, only output activated, that kept steadily safe state. Please refer application note AN-Gatedrive6ED003L06-1 detailed description. minimum deadtime insertion 380ns also provided, order reduce cross-conduction external power switches. 2.1.2 (Gate driver enable, signal applied controls directly output stages. outputs LOW, logic level. internal structure same Figure made exception switching levels Schmitt-Trigger, which here VEN,TH+ VEN,TH- typical propagation delay time 2.1.3 /FAULT (Fault feedback, /Fault active open-drain output indicating status gate driver (see Figure active (i.e. forces voltage level) when following conditions occur: Datasheet
6ED003L06-F Integrated Phase Gate Driver
shuts down gate drivers power outputs, when supply voltage below VCCUV- 10.4 This prevents external power switches from critically gate voltage levels during on-state therefore from excessive power dissipation. 2.1.6 VB1,2,3 VS1,2,3 (High side supplies, high side supply voltage. high side circuit float with respect following external high side power device emitter/source voltage. power consumption, floating driver stage supplied bootstrap topology connected VCC. Under-voltage detection operates with rising supply threshold typical VBSUV+ falling threshold VCCUV- 10.4 Please refer Figure datasheet device operating area function supply voltage. Details bootstrap supply section transient immunity found application note ANGateDriver-6ED003L06-1. 2.1.7 LO1,2,3 HO1,2,3 (Low High side outputs, side high side power outputs specifically designed pulse operation such gate drive IGBT MOSFET devices. side outputs (i.e. LO1,2,3) state triggered respective inputs (/LIN1,2,3), while high side outputs (i.e. HO1,2,3) edge triggered respective inputs (/HIN1,2,3). particular, after under-voltage condition supply, falling /HIN edge necessary turn-on respective high side output, while after undervoltage condition supply, side outputs switch state their respective inputs.
Datasheet
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
BIAS NETWORK VDD2 HIN1 INPUT NOISE FILTER DEADTIME SHOOT-THROUGH PREVENTION BIAS NETWORK LATCH LEVEL-SHIFTER REVERSE-DIODE COMPA RATOR UVDETECT GateDrive
LIN1
INPUT NOISE FILTER
HIN2
INPUT NOISE FILTER
DEADTIME SHOOT-THROUGH PREVENTION
BIAS NETWORK LATCH LEVEL-SHIFTER REVERSE-DIODE COMPA RATOR UVDETECT GateDrive
LIN2
INPUT NOISE FILTER
HIN3
INPUT NOISE FILTER
DEADTIME SHOOT-THROUGH PREVENTION
BIAS NETWORK LATCH LEVEL-SHIFTER REVERSE-DIODE COMPA RATOR UVDETECT GateDrive
LIN3
INPUT NOISE FILTER
INPUT NOISE FILTER
UVDETECT DELAY LEVELSHIFTER LEVELSHIFTER LEVELSHIFTER GateDrive
ITRIP
INPUT NOISE FILTER DELAY
VDD2 IRCIN
GateDrive
RCIN
DOMINANT LATCH
DELAY
GateDrive
FAULT
Figure Block diagram
Datasheet
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
Electrical parameters
Absolute Maximum Ratings voltages absolute voltages referenced -potential unless otherwise specified. (TA=25°C) Symbol Definition High side offset voltage(Note High side offset voltage (tp<500ns, Note High side offset voltage(Note High side offset voltage (tp<500ns, Note VCCOM VCOM VFLT VRCIN RthJA dVs/dt High side floating supply voltage High side output voltage (VHO side supply voltage (internally clamped) side supply voltage (VCC VCOM) Gate driver ground side output voltage (VLO VCOM) Input voltage LIN,HIN,EN,ITRIP <10µs FAULT output voltage RCIN output voltage Power dissipation package) Note Thermal resistance (junction ambient, device mounted Fig.13) Junction temperature Storage temperature offset voltage slew rate Min. VCC-VBS6 -VBS -0.5 -0.5 -5.7 -0.5 -1.0 -0.5 -0.5 Max. VCCOM +0.5 V/ns Unit
Note :The minimal value immunity 1.0kV (Human Body Model). immunity inside pins connected side (VCC, HINx, LINx, FAULT, RCIN, ITRIP, VSS, COM, LOx) pins connected inside each high side itself (VBx, HOx, VSx) guaranteed 1.5kV (Human Body Model). Note Insensitivity bridge output negative transient voltage -50V subject production test verified design characterization. External bootstrap diode mandatory. Refer application note. Note Consistent power dissipation outputs
Datasheet
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
Required Operation Conditions voltages absolute voltages referenced -potential unless otherwise specified. (TA=25°C) Symbol VCCOM Definition High side offset voltage (Note side supply voltage (VCC VCOM) Min. 11.1 Max. Unit
Note Logic operational VSS) 11,1V
Operating Range voltages absolute voltages referenced -potential unless otherwise specified. (TA=25°C) Symbol VBCC VCOM VFLT VRCIN Definition High side floating supply offset voltage High side floating supply offset voltage VCC, statically, Note Note High side floating supply voltage High side output voltage (VHO side output voltage (VLO VCOM) side supply voltage side ground voltage Logic input voltages LIN,HIN,EN,ITRIP FAULT output voltage RCIN input voltage Pulse width (Note Ambient temperature Min. -VBS0.5 -0.5 -2.5 Max. 17.5 17.5 Unit
Note input pins (/HINx, /LINx) ITRIP internally clamped with 10.5V zener diode. Note case input pulse width /LINx /HINx below input pulse transmitted properly
Datasheet
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
Static Logic function Table <VCCUV15V <VBSUV15V RCIN 3.3V 5.8V 5.8V ITRIP VIT,TH+ ENABLE FAULT High High High LO1,2,3 /LIN1,2,3 /LIN1,2,3 HO1,2,3 /HIN1,2,3
Static Parameters unless otherwise specified. (TA=25°C) Symbol VEN,TH+ VEN,THVIT,TH+ VIT,HYS VRCIN,TH VRCIN,HYS VCCUV+ VBSUV+ VCCUVVBSUVVCCUVH VBSUVH ILVS+ ILVS+1 ILVS-1 Definition Logic input voltage (LIN,HIN) Logic input voltage (LIN,HIN) positive going threshold negative going threshold ITRIP positive going threshold ITRIP input hysteresis RCIN positive going threshold RCIN input hysteresis Output voltage (high level, VCC-VO VBSVO) Output voltage (low level, VO-VCOM VO-VS) supply undervoltage positive going threshold supply undervoltage negative going threshold supply undervoltage lockout hysteresis High side leakage current betw. High side leakage current betw. High side leakage current between (x=1,2,3 y=1,2,3) Min. 11.0 Typ. 10.4 12.8 11.0 600V Tj=125°C, 600V Tj=125°C =600V 20mA -20mA Max. Unit Test Conditions
subject production test, verified characterisation Rev. 2008
Datasheet
6ED003L06-F Integrated Phase Gate Driver
Symbol IQBS1 IQBS2 IQCC1 IQCC2 IQCC3 VIN,CLAMP ILIN+ ILINIHIN+ IHINIITRIP+ IEN+ IRCIN IODefinition Quiescent supply current only) Quiescent supply current only) Quiescent supply current (VCC only) Quiescent supply current (VCC only) Quiescent supply current (VCC only) Input clamp voltage (/HIN, /LIN, ITRIP) (Note Input bias current Input bias current Input bias current Input bias current Input bias current (ITRIP=high) Input bias current (EN=high) Input bias current RCIN (internal current source) Mean output current load capacity charging range from 3V(20%) 6V(40%) Mean output current load capacity discharging range from 12V(80%) 9V(60%) RCIN resistance pull down transistors FAULT resistance pull down transistors Min. Typ. 10.6 Max. Unit Test Conditions HO=low HO=high VLIN=float. VLIN=0V, VHIN=5V, VLIN=5V, VHIN=0V IIN=4mA VLIN=5V VLIN=0V VHIN=5V VHIN=0V VITRIP=5V VENABLE=5V VRCIN CL=10nF CL=10nF
RON,RCIN RON,FLT
VRCIN=0.5V VFAULT=0.5V
Note There additional power dissipation input voltages above clamping voltage. series clamping diode there limiting resistor (see also Fig.3)
Datasheet
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
Dynamic Parameters =15V, VCOM, unless otherwise specified. (TA=25°C) Symbol toff tITRIP tITRIPMIN tFLT tFILIN Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time (CL=1nF) Turn-off fall time (CL=1nF) Shutdown propagation delay ENABLE Shutdown propagation delay ITRIP Input filter time ITRIP Propagation delay ITRIP FAULT Input filter time turn input filter time turn only Input filter time turn (Note Input filter time turn (Note Input filter time Fault clear time RCIN after ITRIPfault, (CRCin=1nF) Dead time Matching delay max(ton)-min(ton), applicable driver outputs Matching delay OFF, max(toff)min(toff), toff applicable driver outputs Output pulse width matching. PwinPWout Min. Typ. Max. 1000 1000 VLIN/HIN=0V& VHIN VHIN VITRIP=1V Unit Test Condition VLIN/HIN=0V VLIN/HIN=5V VLIN/HIN=0V VLIN/HIN=5V VEN=0
tFILIN1 tFILIN2 tFILEN tFLTCLR MTON
VLIN/HIN VITRIP=0V VLIN/HIN external dead time>500ns external dead time>500ns PWin>1µs
MTOFF
Note Because internal signal processing safety aspects output short turn pulses shows behaviour according figure proper work driver input pulses must fall below recommended input width 1µs. short signal range subject production test guaranteed.
Datasheet
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
Timing Diagrams
tFILIN
tFILIN
high
tFILIN1 toff,HINx toff,HINx tFILIN1 high toff,HINx toFILIN1 toff,HINx tFILIN2 toff,HINx toff,HINx tFILIN2 tFILIN2
Figure Timing short pulse suppression
Figure Timing internal deadtime
Datasheet
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
Figure Enable delay time definition
Figure Input output propagation delay times switching times definition
Figure Operating Areas
Datasheet
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
Figure ITRIP-timing
Datasheet
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
Package
Package Drawing
-0.1
2.65 MAX.
0.35
2.45 -0.2
1.27 0.35 +0.15
+0.8 10.3 ±0.3
Index Marking
18.1 -0.4
Does include plastic metal protrusion 0.15 max. side Does include dambar protrusion 0.05 max. side
Footprint Reflow soldering
1.27 9.73 1.67 0.65
HLG05506
Datasheet
MAX.
-0.2
0.23 +0.09
Rev. 2008
6ED003L06-F Integrated Phase Gate Driver
Reference thermal resistance
Figure Reference layout
Dimensions Material Metal (Copper)
80.0 80.0 70µm
therm [W/mK]
Datasheet
Rev. 2008

6ED003L06-F Integrated Phase Gate Driver Power Management Dr

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