8203E Mirror Power Automotive Power 8203E Table Co

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8203E Mirror Power Automotive Power 8203E Table Co

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Final Data Sheet, Rev. 1.0, February 2009
8203E
Mirror Power
Automotive Power
8203E
Table Contents
Table Contents
10.1 10.2 11.1 12.1 Overview Block Diagram Configuration Assignment Definitions Functions General Product Characteristics Absolute Maximum Ratings Operating Range Thermal Resistance
Monitoring Functions Power Supply Monitoring Temperature Monitoring Current Sense Power Supply General Sleep-Mode Reverse Polarity Electrical Characteristics General Register Address Definitions Status Register Address Selection Reset Electrical Characteristics Inputs
Power-Outputs (Bridge Outputs) Protection Diagnosis Electrical Characteristics Power-Output (Mirror Heater Driver) Protection Diagnosis Electrical Characteristics Power-Outputs (Lamp drivers) Protection Diagnosis Electrical Characteristics Logic Outputs Electrical Characteristics Application Information Application Diagram Package Outlines Revision History
Final Data Sheet
Rev. 1.0, 2009-02-04
Mirror Power 8203E
8203E
Features
Overview
Three half-bridges RDSON(MAX) TJ=150°C mirror position High-side switch 0.17 RDSON(MAX) TJ=150°C mirror defrost high-side switches RDSON(MAX) TJ=150°C lamps Current sense analog output with multiplexer outputs with short circuit protection diagnosis Over-temperature protection with warning Open load diagnosis outputs Charge pump-Output n-channel MOSFET reverse-polarity protection Very current consumption sleep mode Standard 16-bit control diagnosis Over- Under-voltage Lockout package with exposed thermal resistance Part scalable door family products Green Product (RoHS compliant) Qualified
PG-DSO-36-50
Functional Description 8203E Application Specific Standard Product automotive mirror control applications. includes power stages necessary drive mirror loads such mirror position, mirror defrost lamp, i.e. turn signal. monolithic based Infineon's smart mixed technology which combines bipolar CMOS control circuitry with DMOS power devices. short circuit over-temperature protection detailed diagnosis offered meet automotive application safety requirements. current sense output mprove system reliability performance. standard interface saves microcontroller lines while still providing flexible control power stages detailed diagnosis.
Type 8203E Final Data Sheet
Package PG-DSO-36-50
Marking TLE8203E Rev. 0.9, 2009-01-23
8203E
Block Diagram
Block Diagram
Chargepump RevPol driver FaultDetect
PWM1 PWM2
Biasing
OUT4
OUT5
OUT6 Logic current sense Logic Latch OUT7
OUT8 OUT10
Figure Block Diagram
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Configuration
Configuration
Assignment
Figure
Configuration PG-DSO-36-50
Definitions Functions
Symbol Function Cooling Tab; internally connected GND; reduce thermal resistance, place cooling areas thermal vias PCB. Ground; internally connected cooling (exposed pad). Power-Output Half-Bridge output DMOS half-bridge (mirror position). Power-Output Half-Bridge output DMOS half-bridge (mirror position). Power Supply; needs decoupling capacitors GND. electrolytic parallel with ceramic recommended. pins must connected externally. Inhibit; active low. Sets device sleep mode with current consumption when left open pulled LOW. internal pull-down current source. Logic Input Direct Power Stage Control; direct input control high-side switches selected xsel1 bits control register CtrlReg01. Logic Input Direct Power Stage Control; direct input control switches selected xsel2 bits control register CtrlReg11. Rev. 1.0, 2009-02-04
cooling OUT5 OUT6
PWM1 PWM2
Final Data Sheet
8203E
Configuration Symbol Function Current Sense Output; Mirrors current high-side switch selected current sense multiplexer control bits ISx. Logic Supply Voltage; needs decoupling capacitors (pin electrolytic parallel with ceramic recommended. Serial Data Output; Transfers data master when chip selected LOW. Data transmission synchronized CLK, state changed rising edge CLK. most significant (MSB) transferred first. tristated long HIGH. Serial Data Clock Input; Receives clock signal from master clocks shift register. internal pull-down current source. Serial Port Chip Select Input; communication enabled pulling LOW. must during transition CSN. CSN-pin internal pull-up current source. Serial Data Input; Receives serial data from master when chip selected LOW. Data transmission synchronized CLK. Data accepted falling edge CLK. transferred first. DI-pin internal pull-down current source. Gate Out; Charge pump output drive gate external n-channel MOSFET reverse polarity protection. Connected Connected Connected Connected Power-Output High-Side Switch output DMOS high-side switch (lamp driver Charge Pump; optional external charge-pump reservoir capacitor. recommended. Connected Power-Output High-Side Switch output DMOS high-side switch (lamp driver) Power Output High-Side Switch output DMOS high-side switch (mirror heat) Power-Output Half-Bridge output DMOS half-bridge (sum mirror position). Connected
OUT10 OUT8 OUT7 OUT4 N.C.
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
General Product Characteristics
General Product Characteristics Absolute Maximum Ratings
Absolute Maximum Ratings +150 voltages with respect ground, positive current flowing into (unless otherwise specified) Pos. Voltages 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 Supply voltage Logic supply voltage Logic input- output voltages Voltage GO-pin Junction Temperature Storage Temperature capability power stage output pins vers. Parameter Symbol Limit Values Min. Max.
Unit
Conditions
Tstg VESD
-0.3 -0.3 -0.3
Temperatures
Susceptibility
capability logic pins VESD vers.
subject production test, specified design. Human Body Model according JEDEC EIA/JESD22-A114-B (1.5k,
Note: Stresses above ones listed here cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect device reliability. Note: Integrated protection functions designed prevent destruction under fault conditions described data sheet. Fault conditions considered "outside" normal operating range. Protection functions designed continuous repetitive operation.
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
General Product Characteristics
Pos. 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6
Operating Range
Parameter Supply voltage range normal operation Extended supply voltage range operation Logic supply voltage range normal operation Extended logic supply voltage range operation clock frequency Junction temperature Symbol Limit Values Min. Max. 5.25 (Limit Values Deviations possible) (Limit Values Deviations possible) 4.75 4.75 Unit Conditions
VS(ext) VDD(ext) fCLK
Note: Within functional range operates described circuit description. electrical characteristics specified within conditions given related electrical characteristics table.
Pos. 4.3.1 4.3.2
Thermal Resistance
Parameter Junction Case Junction Ambient Symbol Min. Limit Values Typ. Max.
Unit
Conditions
RthjC RthjA
subject production test, specified design. Specified RthJA value according Jedec JESD51-2,-5,-7 natural convection 2s2p board; Product (Chip+Package) simulated 76.2 114.3 board with inner copper layers 70µm 35µm Cu). Where applicable thermal array under exposed contacted first inner copper layer
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Monitoring Functions
Monitoring Functions
Power Supply Monitoring
power supply Voltage monitored over- under-voltage. Under Voltage supply voltage drops below switch voltage OFF, output transistors switched power supply fail set. error latched, i.e. rises again reaches switch voltage power stages restarted error reset. Over Voltage supply voltage rises above switch voltage OFF, output transistors switched power supply fail (bit diagnosis word) set. error latched, i.e. falls again reaches switch voltage power stages restarted error reset.
5.1.1
Characteristics Power Supply Monitoring
Electrical Characteristics: Power Supply Monitoring
+150 High; outputs open, voltages with respect ground, positive current flowing into (unless otherwise specified)
Pos. 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 Parameter UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis OV-Switch-OFF voltage OV-Switch-ON voltage OV-ON/OFF-Hysteresis Symbol Min. Limit Values Typ. 0.25 Max. Unit Conditions
VUVON VUVOFF VUVHY VOVOFF VOVON VOVHY
increasing decreasing VUVON VUVOFF increasing decreasing VOVOFF VOVON
Temperature Monitoring
Temperature sensors integrated power stages. temperature monitoring circuit compares measured temperature warning shutdown thresholds. more temperature sensors reach warning temperature, temperature warning HIGH. This latched (i.e. temperature falls below warning threshold (with hysteresis), reset again). more temperature sensors reach shut-down temperature, outputs shut down described next paragraph temperature shut-down HIGH. shutdown latched (i.e. output stages remain high until command sent power-on reset performed). more temperature sensors reaches shutdown threshold, outputs switched off.
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Monitoring Functions
5.2.1
Characteristics Temperature Monitoring
Electrical Characteristics: Temperature Monitoring
4.75 5.25 High; outputs open, voltages with respect ground, positive
current flowing into (unless otherwise specified) Pos. 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 Parameter Thermal warning junction temperature1) Temperature warning hysteresis Thermal shutdown junction temperature1) Temperature shutdown hysteresis Ratio temperature
Symbol Min.
Limit Values Typ. 1.20 Max. 1.05
Unit
Conditions
TjSD
Thermal switch-on junction temperature1) TjSO TjSD
TjSD/TjW
subject production test, specified design.
Current Sense
current proportional output current that flows from selected power output provided sense out) pin. output selection done SPI. sense current transformed into voltage external sense resistor provided converter input (see Chapter 12).
5.3.1
Characteristics Current Sense
Electrical Characteristics: Current Sense
4.75 5.25 +150 High; outputs open, voltages with
respect ground, positive current flowing into (unless otherwise specified) Pos. Parameter Symbol Min. (Register 011) 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 Output voltage range Current sense ratio Current sense accuracy Output voltage range Current Sense Ratio Current Sense accuracy Limit Values Typ. 1000 2000 Max. Unit Conditions
VISO4 kILIS4 kILISacc4 VISO7 kILIS7 kILISacc7
kILIS IOUT/IISO; IOUT kILIS IOUT/IISO; IOUT
(Register 100)
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Power Supply
Power Supply
General
8203E power domains: power drivers connected supply voltage which connected automotive board-net. internal logic part supplied separate Voltage advantage this system that information stored logic remains intact event short-term failures supply voltage system therefore continue operate after recovered, without having reprogrammed. rising edge triggers internal Power-On Reset (POR) initialize power-on. data stored internally deleted, outputs switched high-impedance status (tristate).
Sleep-Mode
8203E current-consumption mode setting input LOW. internal pull-down current source. sleep-mode, output transistors turned operating. When enabling setting from Power-On Reset performed described above.
Reverse Polarity
8203E requires external reverse polarity protection. gate-driver (charge-pump output) external n-channel logic-level MOSFET integrated. gate voltage provided which should connected shown application diagram.
Electrical Characteristics
Electrical Characteristics: Power Supply
4.75 5.25 +150 High; outputs open, voltages with
respect ground, positive current flowing into (unless otherwise specified) Pos. Parameter Symbol Min. Current Consumption 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 Supply current Logic supply current Supply quiescent current Logic quiescent current Total quiescent current Limit Values Typ. Max. active Unit Conditions
IS_Q IDD_Q IS_Q IDD_Q IlkGO
VOUTX
Charge Pump-output Reverse-Polarity Protection (GO) 6.4.6 6.4.7 6.4.8 Gate-Voltage Setup-time Reverse leakage current
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
General
used bidirectional communication with control unit. 8203E acts SPI-slave control unit acts SPI-master. 16-bit control word read serial data input. status word appears synchronously serial data output. communication synchronized serial clock input CLK. Standard data transfer timing shown Figure clock polarity data valid falling edge. must during transition. transfer first. transmission cycle begins when chip selected with chip-select-not (CSN) input Then data clocked through shift register. transmission ends when input changes from word which been read into shift register becomes control word. output switches then tristate status, thereby releasing circuit other uses. allows parallel multiple devices using multiple lines. also used with other SPI-devices daisy-chain configuration.
High rising edge SCLK: enabled. Status information transfered Output Shift Register High: Data from Shift-Register transfered Output Driver Logic
time
actual Data
Data
SDI: Data will accepted falling edge CLK-Signal previous Status actual Status
SDO: State will change rising edge CLK-Signal
Figure
Standard Data Transfer Timing
Register Address
16-bit frame composed addressable block, address-independent block 2-bit address shown Figure control word transmitted from master 8203E executed transmission (CSN remains valid until different control word transmitted power reset occurs. beginning transmission (CSN diagnostic data currently valid latched into transferred master. Status Register address handling, please refer Section 7.4.
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
time
Input data Data selected register address output data Data from selected register address
generic data
Register Address
generic data
Figure
Structure
7.3.1
Table
Definitions Control Word
Input (Control) Data Register CtrlReg PWM1 Input Select HS7sel1 HS8sel1 HS10sel1 OpL7ON Testmode IS_2 IS_1 IS_0 RA_1 RA_0 CtrlReg CtrlReg Mirror Lamp-driver PWM2 Input Select Control LS4ON HS4ON LS5ON HS5ON LS6ON HS6ON HS8ON HS10ON IS_2 IS_1 IS_0 RA_1 RA_0 HS7sel2 HS8sel2 HS10sel2 OpL8ON OpL10ON IS_2 IS_1 IS_0 RA_1 RA_0
CtrlReg Mirror Heat Control HS7ON Testmode Testmode Testmode IS_2 IS_1 IS_0 RA_1 RA_0
Address Independent Data
Address Bits
Note: Testmode entered when Testmode bits High. Otherwise normal operation.
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Table Control LSxON HSxON xsel1 xsel2 OpLxON IS_x
Control Definitions Definition Low-side switch turned (OFF) this HIGH (LOW). High-side switch turned (OFF) this HIGH (LOW). Power switch selected switched PWM1 input. Power switch selected switched PWM2 input pull-up current open-load detection output switched (off) this HIGH (LOW). output current sense multiplexer selected these bits: IS_2 others IS_1 IS_0 Power stage selected current sense output selected (IISO
RA_x
Status Register Reset. high, error bits selected status register reset after transmission data next frame (see Chapter 7.4). Register Address, selects control-register address current transmission status-register address next transmission.
7.3.2
Table
Diagnosis
Output (Status) Data Register StatReg Lock Mirror Heat Open Load valid input data HS7OpL StatReg StatReg Mirror Lamp-driver Mirror Lamp-driver Overload Open Load valid input data LS4OvL HS4OvL LS5OvL HS5OvL LS6OvL HS6OvL HS8OvL HS10OvL valid input data LS4OpL LS5OpL LS6OpL HS8OpL HS10OpL
StatReg Lock Mirror Heat Overload valid input data
HS7OvL
Address Independent Data
Error Flags Final Data Sheet Rev. 1.0, 2009-02-04
8203E
Table Output (Status) Data Register (cont'd) StatReg Lock Mirror Heat Open Load EF_11 EF_10 EF_00 StatReg StatReg Mirror Lamp-driver Mirror Lamp-driver Open Load Overload EF_11 EF_01 EF_00 EF_10 EF_01 EF_00
StatReg Lock Mirror Heat Overload EF_11 EF_10 EF_01
Note: x-bits Table Status LSxOvL HSxOvL LSxOpL HSxOpL EF_xy N.C. Status Definitions Definition Low-Side switch Over Load. HIGH low-side switch shut down overcurrent overtemperature crosscurrent. High-Side switch Over Load. HIGH high-side switch shut down overcurrent overtemperature crosscurrent. Low-Side switch open load. HIGH open load (undercurrent) detected low-side switch High-Side switch Open Load. HIGH open load detected high-side switch Power Supply Fail. HIGH Voltage below undervoltage threshold above overvoltage threshold. powerstages shut down overtemperature. more powerstages have reached warning temperature. Error Flag StatReg HIGH HIGH StatReg connected. These bits used test-mode purposes. They fixed normal operation.
Status Register Address Selection Reset
using standard shift-register concept with daisy-chain capability. data transmitted will available internal logic part transmission (CSN read specific register, address register sent master first frame. data that corresponds this address transmitted during following (second) frame master. default address Status Register transmission after Power-ON Reset Status-Register-Reset command-bit executed after next transmission. three bits RA_0, RA_1 command read reset reset) addressed Status-Register. This also explained Figure status part addressable data address independent data. When status registers reset, reset, too.
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Ctrl-Reg Data Ctrl-Reg Data Ctrl-Reg Data
RA_0 RA_1
RA_1
RA_0
RA_0 RA_1
xxxxx Stat-Reg Data
xxxxx Stat-Reg Data
xxxxx Stat-Reg Data
EF_2
EF_0 EF_1
EF_1 EF_2
EF_0
EF_2
EF_0 EF_1
xxxxx
xxxxx
xxxxx
StatReg10 reset after L->H
Comment
After Power-ON Reset, Status Register sent default
Status Register transferred master, reset after transmission
Status Register transferred master, reset after transmission
Figure
Status Register Addressing Reset
7.4.1
Error-Flag
addition bits transferred from 8203E master, additional Error Flag (EF) transmitted pin. status shown after before first rising edge CLK, shown Figure Error flag Status Registers contains error message (i.e. EF_00 EF_01 EF_10 EF_11).
bit15 bit14 bit13 bit12
Figure
Error Flag Transmission during Standard Transmission (top), without Additional Transmission, (bottom) Rev. 1.0, 2009-02-04
Final Data Sheet
8203E
Electrical Characteristics
Electrical Characteristics: SPI-Timing
4.75 5.25 +150 High; outputs open, voltages with
respect ground, positive current flowing into (unless otherwise specified) Pos. 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.5.11 7.5.12 Parameter lead time time Fall time CSN, CLK, Rise time CSN, CLK, data setup time data hold time data valid time data setup time data hold time No-data-time between commands Clock frequency Symbol Min. Limit Values Typ. Max.
Unit
Conditions
tlead tlag tDOsetup tDOhold tnodata
Duty cycle incoming clock
Timing subject production test specified design. functional test performed frequency. Timing specified with external load [DO].
Figure
Timing Diagram
Inputs
inputs PWM1 PWM2 direct power stage control inputs that used switch more power transistors with signal supplied this pin. setting Registers CtrlReg_01 CtrlReg_11 defines which power stages will controlled inputs. selection-bits power Stage xsel1 xsel2 LOW, power stage controlled only control xON. selection xsel1 HIGH control also high, power stage controlled PWM1 (xsel2 PWM2, respectively). behavior shown principal schematic Table below. terms power dissipation switching loss, frequency below recommended. Final Data Sheet Rev. 1.0, 2009-02-04
8203E
xsel1 xsel2
{HS7, HS8, HS10}
PWM1
Gate driver
PWM2
control logic power transistor
power transistor
Figure Table
Input Control Registers Truth Table Inputs xsel1 xsel2 PWM1 PWM2 Power Stage
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Power-Outputs (Bridge Outputs)
8.1.1
Power-Outputs (Bridge Outputs)
Protection Diagnosis Short Circuit Output Ground
low-side switches protected against short circuit supply high-side switches against short GND. switch turned current rises above shutdown threshold longer than shutdown delay time tdSD, output transistor turned corresponding diagnosis set. During delay time, current limited shown Figure
OUTx short IOUT tdSD
short
Figure
Short Circuit Protection
delay time relatively short (typ. limit energy that dissipated device during short circuit. This scheme allows high peak-currents required motor-applications. output stage stays error until status register reset sent power-on reset performed.
8.1.2
Cross-Current
instance OFF, turn turn with same command. ensure that there overlap switching slopes that would lead cross current, dead-time specified. control registers, also possible turn high- low-side switches same half-bridge (e.g. LS4ON HS4ON prevent cross-current through bridge, such command executed. Instead, both switches turned Over-Load High both switches (e.g. LS4OvL HS4OvL
8.1.3
Open Load
Open-load detection ON-state implemented low-side switches bridge outputs: When current through side transistor lower than reference current IOCD ON-state longer than open-load detection delay time tdOC, according open-load diagnosis set. output transistor, however, remains open load error latched reset status register reset power-on reset. example, motor connected between outputs with broken wire shown Figure resulting diagnostic information shown Table
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Power-Outputs (Bridge Outputs)
Open Load
Motor
Figure Table
Open Load Example Open Load Diagnosis Example Control Motor Connected Diagnostic Information Motor Remark Open Load Disconnected Detection detectable detected detected detectable detectable
Motor Rotation motor clock-wise counter clockwise brake high brake
Electrical Characteristics
Electrical Characteristics: OUT4 (Driver mirror halfbridge fold)
4.75 5.25 +150 High; outputs open, voltages with
respect ground, positive current flowing into (unless otherwise specified) Pos. Parameter Symbol Min. Static Drain-Source ON-Resistance 8.2.1 High- low-side switch Limit Values Typ. Max. Unit Conditions
RDSON4
IOUT IOUT
resistive load Figure Figure
Switching Times 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 High-side delay-time High-side delay time Low-side delay-time Low-side delay time Dead-time
tdONH4 tdOFFH4 tdONL4 tdOFFL4 tDHL4
tdONL4 tdOFFH4
Rev. 1.0, 2009-02-04
Final Data Sheet
8203E
Power-Outputs (Bridge Outputs) Electrical Characteristics: OUT4 (Driver mirror halfbridge fold) (cont'd)
4.75 5.25 +150 High; outputs open, voltages with
respect ground, positive current flowing into (unless otherwise specified) Pos. 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12 8.2.13 Parameter Dead-time Over-current shutdown threshold Shutdown delay time Short Circuit current Detection current Delay time OFF-state output current
Symbol Min.
Limit Values Typ. Max.
Unit
Conditions
tDLH4 ISD4 tdSD4 ISC4 IOCD4 tdOC4
tdONH4 tdOFFL4
high- lowside
Short Circuit Protection
Open Load Detection low-side
Leakage Current
IOUT4_leakage
VOUT
subject production test specified design.
Electrical Characteristics: (driver mirror position)
4.75 5.25 +150 High; outputs open, voltages with
respect ground, positive current flowing into (unless otherwise specified) Pos. Parameter Symbol Min. Static Drain-Source ON-Resistance 8.2.14 High- low-side switch Limit Values Typ. Max. Conditions
RDSON56
IOUT ±0.5 IOUT ±0.5
resistive load Figure Figure
Switching Times 8.2.15 8.2.16 8.2.17 8.2.18 8.2.19 8.2.20 8.2.21 8.2.22 8.2.23 8.2.24 8.2.25 High-side delay time High-side delay time Low-side delay time Low-side delay time Dead-time Dead-time Over-current shutdown threshold Shutdown delay time Short Circuit current Detection current Delay time
tdONH56 tdOFFH56 tdONL56 tdOFFL56 tDHL56 tDLH56 ISD56 tdSD56 ISC56 IOCD56 tdOC56
1.25
tdONL56 tdOFFH56 tdONH56 tdOFFL56
low-side high- low-side
Short Circuit Protection
Open Load Detection
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Power-Outputs (Bridge Outputs) Electrical Characteristics: (driver mirror position) (cont'd)
4.75 5.25 +150 High; outputs open, voltages with
respect ground, positive current flowing into (unless otherwise specified) Pos. Parameter Symbol Min. Leakage Current 8.2.26 OFF-state output current Limit Values Typ. Max. Conditions VOUT
IOUT56_leakage
subject production test specified design.
OUTx high-side delay time tdOFFH
tDHL OUTx tdONL
low-side delay time
Figure
Timing Bridge Outputs High
OUTx
low-side delay time tdOFFL
tDLH OUTx high-side delay time tdONH
Figure
Timing Bridge Outputs High
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Power-Output (Mirror Heater Driver)
9.1.1
Power-Output (Mirror Heater Driver)
Protection Diagnosis Short Circuit Output Ground
Output high-side switch intended drive ohmic loads like heater exterior mirror.
high-side switch turned current rises above shutdown threshold longer than shutdown delay time tdSD, output transistor turned corresponding diagnosis set. During delay time, current limited shown Figure
short
Figure
Short Circuit Protection
output stage stays error until status register reset sent power-on reset performed.
9.1.2
Open Load
high-side switches, open-load OFF-state scheme used shown Figure output pulled current source IOpL. OFF-state, output voltage monitored compared threshold VOpL. voltage rises above this threshold, open-load signal high. This equivalent comparing load resistance value VOpL IOpL. open load error latched reset status register reset power-on reset. pull-up current switched OpLxON bits. This should (i.e. pull-up current switched off) output used drive LEDs because they emit light biased with pull-up current.
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Power-Output (Mirror Heater Driver)
OpL7ON
IOpL
switch
Gate driver high-side switch VOpL
HS7OpL Filter
RLoad
Figure
Open Load OFF-state Scheme
Electrical Characteristics
Electrical Characteristics: 7(mirror heater driver)
4.75 5.25 +150 High; outputs open, voltages with
respect ground, positive current flowing into (unless otherwise specified) Pos. Parameter Symbol Min. Static Drain-source ON-Resistance 9.2.1 High-side switch Limit Values Typ. 0.07 Max. 0.17 Unit Conditions
RDSON7
IOUT IOUT
resistive load Figure
Switching Times 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.2.7 9.2.8 9.2.9 Turn-ON delay time Output rise-time Turn-OFF delay time Output fall-time Over-current shutdown threshold Shutdown delay time Short Circuit current Pull-up current
tdONH7 trise7 tdOFFH7 tfall7 ISD7 tdSD7 ISC7 IOpL7
6.25
Short Circuit Protection
Open Load Detection
VOUT
Rev. 1.0, 2009-02-04
Final Data Sheet
8203E
Power-Output (Mirror Heater Driver) Electrical Characteristics: 7(mirror heater driver) (cont'd)
4.75 5.25 +150 High; outputs open, voltages with
respect ground, positive current flowing into (unless otherwise specified) Pos. 9.2.10 9.2.11 9.2.12 Parameter Detection Threshold Delay time OFF-state output current Symbol Min. Limit Values Typ. Max. Unit Conditions
VOpL7 tdOC7
Leakage Current
IOUT7_leakage
VOUT
subject production test specified design.
tRISE
FALL
OUT7
dOFF
Figure
Timing
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Power-Outputs (Lamp drivers)
10.1 10.1.1
Power-Outputs (Lamp drivers)
Protection Diagnosis Short Circuit Output Ground
Outputs high-side switches intended drive ohmic loads lamp (bulb) loads.
high-side switches protected against short GND. Short Circuit during Switch-on During switch-on output current voltage level used check short circuit. switch turned short circuit condition valid after tdSDon8 output transistor turned corresponding diagnosis set. short circuit condition valid current rises above shutdown threshold ISD8 voltage output stays below VSD8. During delay time, current limited ISC8 shown Figure
IOUT short VOUT IOUT
ISC8 ISD8 tdSDon8
VSD8 VOUT
Figure
Short Circuit Protection during Switch-on
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Power-Outputs (Lamp drivers) Short Circuit On-state switch already current rises above shutdown threshold longer than shutdown delay time tdSD output transistor turned corresponding diagnosis set. This independent voltage Vout. Figure
IOUT short IOUT
ISC8 ISD8 tdSD8
Figure
Short Circuit Protection On-state
10.1.2
Open Load
high-side switches, open-load OFF-state scheme used shown Figure output pulled current source IOpL. OFF-state, output voltage monitored compared threshold VOpL. voltage rises above this threshold, open-load signal high. This equivalent comparing load resistance value VOpL IOpL. open load error latched reset status register reset power-on reset. pull-up current switched OpLxON bits. This should (i.e. pull-up current switched off) output used drive LEDs because they emit light biased with pull-up current.
OpLxON
IOpL
switch
Gate driver high-side switch
HSxOpL
Filter
Load
Figure
Open Load OFF-state Scheme Rev. 1.0, 2009-02-04
Final Data Sheet
8203E
Power-Outputs (Lamp drivers)
10.2
Electrical Characteristics
Electrical Characteristics: (Lamp drivers)
4.75 5.25 +150 High; outputs open, voltages with
respect ground, positive current flowing into (unless otherwise specified) Pos. Parameter Symbol Min. Static Drain-Source ON-Resistance 10.2.1 High-side switch Limit Values Typ. Max. Unit Conditions
RDSON8,10
IOUT +0.5 IOUT +0.5
resistive load Figure
Switching Times 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 10.2.8 10.2.9 Turn-ON delay time Output rise-time Turn-OFF delay time Output fall-time Over-current shutdown threshold Over-current shutdown threshold voltage Short circuit current1) Shutdown delay time
tdONH8,10 trise8,10 tdOFFH8,10 tfall8,10 ISD8,10 VSD8,10 ISC8,10 tdSDon8,10 tdSD8,10 IOpL8,10 VOpL8,10 tdOC8,10
Short Circuit Protection switching-on on-state
10.2.10 Shutdown delay time Open Load Detection 10.2.11 Pull-up current 10.2.12 Detection Threshold 10.2.13 Delay time Leakage Current 10.2.14 OFF-state output current
VOUT
IOUT810_leakage
VOUT
subject production test specified design.
tRISE
FALL
dOFF
Figure
Timing Rev. 1.0, 2009-02-04
Final Data Sheet
8203E
Logic Outputs
Logic Outputs
threshold specifications logic inputs compatible both standard CMOS micro controller outputs. logic output CMOS output.
11.1
Electrical Characteristics
Electrical Characteristics: Diagnostics
4.75 5.25 +150 High; outputs open, voltages with
respect ground, positive current flowing into (unless otherwise specified) Pos. Parameter Symbol Min. Inhibit Input 11.1.1 11.1.2 11.1.3 11.1.4 11.1.5 11.1.6 11.1.7 11.1.8 11.1.9 H-input voltage threshold L-input voltage threshold Hysteresis input voltage Pull-down current H-input voltage threshold L-input voltage threshold Hysteresis input voltage Pull-up current Pull-down current pins PWM1, PWM2, Limit Values Typ. Max. Unit Conditions
VIHY IIINH VIHY IICSN IInput
rising falling
VIINH rising falling
Logic Inputs CLK, CSN, PWM1 PWM2
VCSN VInput
5.25
11.1.10 Input capacitance CSN, CLK, PWM1, PWM21) Logic Output 11.1.11 H-output voltage level 11.1.12 L-output voltage level 11.1.13 Tri-state leakage current 11.1.14 Tri-state input capacitance1)
VDOH VDOL IDOLK
ISDOH ISDOL -1.6 VCSN VDD; VSDO VCSN VDD; 5.25
subject production test, specified design.
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Application Information
Application Information
Note: following information given hint implementation device only shall regarded description warranty certain functionality, condition quality device.
12.1
Application Diagram
VBATT_1
8458
VBATT_2
100k
30N03S2L-07
47uF
3.3nF
GPIO
XC866
PWM1 PWM2 Rsense
8203
GPIO GPIO SCLK TIMER TIMER mirror-x mirror-y
mirror-heat
DIG_GND
POWER_GND
Figure
Application Example Mirror Control
Final Data Sheet
Rev. 1.0, 2009-02-04
8203E
Package Outlines
Package Outlines
0.0.10 STAND 2.45 -0.2
2.55 MAX.
0.35
0.65 0.65 11.05 0.33 ±0.08 0.17
±0.2 SEATING PLANE 10.3 ±0.3
Bottom View
Ejector Mark
Exposed Diepad
12.8 -0.21) Index Marking
Index Marking
Exposed Diepad Dimensions Leadframe Package PG-DSO-36-24, -41, A6901-C001 A6901-C003 PG-DSO-36-38 A6901-C007 PG-DSO-36-38 PG-DSO-36-50 A6901-C008
Does include plastic metal protrusion 0.15 max. side Does include dambar protrusion 0.05 max. side Distance from leads bottom seating plane) exposed diepad
PG-DSO-36-24, -38, -41, -42, -50-PO
Figure
PG-DSO-36-50 (Plastic Dual Small Outline Package)
Green Product RoHS compliant meet world-wide customer requirements environmentally friendly products compliant with government regulations device available green product. Green products RoHS-Compliant (i.e Pb-free finish leads suitable Pb-free soldering according IPC/JEDEC J-STD-020).
find packages, sorts packing others Infineon Internet Page "Products": Final Data Sheet
Dimensions Rev. 1.0, 2009-02-04
MAX.
-0.2
0.23 +0.09
8203E
Revision History
Revision History
Date 03.02.09 Changes Final Data Sheet Release
Version
Final Data Sheet
Rev. 1.0, 2009-02-04
Edition 2009-02-04 Published Infineon Technologies 81726 Munich, Germany 2009 Infineon Technologies Rights Reserved. Legal Disclaimer information given this document shall event regarded guarantee conditions characteristics. With respect examples hints given herein, typical values stated herein and/or information regarding application device, Infineon Technologies hereby disclaims warranties liabilities kind, including without limitation, warranties non-infringement intellectual property rights third party. Information further information technology, delivery terms conditions prices, please contact nearest Infineon Technologies Office (www.infineon.com). Warnings technical requirements, components contain dangerous substances. information types question, please contact nearest Infineon Technologies Office. Infineon Technologies components used life-support devices systems only with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system affect safety effectiveness that device system. Life support devices systems intended implanted human body support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.

8203E Mirror Power Automotive Power 8203E Table Co

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