Circuits Fall, 2004 Williams Introduction Occasionally, tasked with de

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Application Note November 2004 Signal Sources, Conditioners Power Circuitry
Circuits Fall, 2004 Williams Introduction Occasionally, tasked with designing circuitry specific purpose. request have customer origins in-house requirement. Alternately, circuit developed because possibility simply attractive ignore1. Over time, these circuits accumulate, encompassing wide useful body proven capabilities. They also represent substantial effort. These considerations make publication almost obligatory proposition and, such, group circuits presented here. This first time have displayed such wares and, given encouraging reader response, will last2. Eighteen circuits included this latest effort, roughly arranged categories given this publication's title. They appear next paragraph. Voltage Controlled Current Source-Ground Referred Input Output voltage controlled current source with ground referred input output difficult achieve. Executions exist, often cumbersome, involving numerous components. Figure conceptual design utilizes differential amplifier featuring differential, uncommitted feedback inputs. independent feedback inputs permit differential signal inputs operate anywhere inside their common mode range, unencumbered feedback interaction. Similarly, differential feedback ports sense referred point within their common mode range. both cases, common mode range extends from within positive rail. Output swing extends both rails. freedoms described above invite Figure configuration. amplifier biased control voltage input, which feedback action impresses across resistor. Scaling equation given, which will recognized dressed version Ohm's Law. Note that this
VCONTROL
LT6552
IOUT CONTROL
Figure Conceptual Ground Referred Voltage Controlled Bipolar Current Source Utilizes Differential Amplifier's Separate Feedback Inputs. Compliance Limits Imposed Supply Voltage, Output Current Capacity Input Common Mode Range
circuit will produce current outputs either polarity, dictated control input. Compliance limits imposed power supply voltage, output current capacity input common mode range. Figure puts Figure thesis work. test circuit (figure left) produces control signals exercise current source (figure right), which drives capacitive load. Figure waveforms describe circuit activity. Trace clock, trace A1's control input trace capacitor voltage. test circuit presents alternating polarity control inputs (trace after each directed capacitor reset zero (trace result, alternating, equal amplitude, opposed polarity linear capacitor ramps, clearly demonstrates current sources capabilities.
registered trademarks Linear Technology Corporation. other trademarks property their respective owners.
Note "When something technically sweet, (Robert Oppenheimer). Note Previous efforts this include AN45, AN52, AN61, AN66, AN67 AN75. References
an98f
AN98-1
Application Note
CLOCK 74C74 7.5k CURRENT CONTROL INPUT LT6552 ZTX-849 TEST CIRCUIT CURRENT SOURCE 0.01µF
AN98
OPERATES INVERTED MODE DURING NEGATIVE COLLECTOR EXCURSIONS. SUBSITUTE OTHER DEVICES
Figure Practical Version Figure Sources Bipolar Current Capacitive Load. Test Circuit Provides Bipolar Control Input Resets Capacitor. Result Alternating, Opposed Polarity Ramps Across Capacitor
20V/DIV 1V/DIV 5V/DIV
10µs/DIV
AN98
Figure Voltage Controlled Current Source Test Circuit Waveforms Include Clock (Trace Control Input (Trace Capacitor Voltage (Trace Bipolar Control Input Voltage Results Complementary Capacitor Ramps
Stabilized Oscillator Network Telephone Identification Some telephone networks require amplitude frequency stabilized 100Hz carrier indicate status phone network. Figure operating from single supply, provides this function using only dual amps attendant discrete components. conventional multivibrator, operates 100Hz. square triangle outputs appear Figure traces respectively. 100Hz triangle, heavily filtered A2's 16Hz input pair, appears sine wave A2's
amplified output (trace A2's output, turn, applied configured half wave rectifier. A3's input attenuation keeps sine wave's negative excursions within amplifier's input range (VCM(LIMIT) 0.3V). Single rail powered A3's output can't track sine wave's negative portion; simply saturates within millivolts ground, producing trace half-wave rectified output. This output, representing A2's amplitude, compared reference band-limited A4-Q1. Q1's collector biases A1's power pin, closing amplitude stabilization loop which regulates circuit's sine wave output. Sine wave distortion, appearing trace only despite
an98f
AN98-2
Application Note
0.1µF RECTIFIER SERVO LT1013 LT1013
2N3906
5.36k* 402k* 15k*
100k* 100k*
LT1004-1.2 7.15k* 0.01µF REFERENCE 0.1µF 402k* 100Hz SINE OUTPUT. 2VP-P, AMPLITUDE STABLE
LT1366
OSCILLATOR
FILTER
LT1366
0.1µF
AN98
OUTPUT
FILM RESISTOR
Figure Amplitude/Frequency Stabilized Sine Wave Oscillator, Developed Network Telephone Identification, Suits General Purpose Use. A1's Filtered Triangle Output Produces 2VP-P Sinewave A3's Rectified Output Balanced Against Reference Closes Regulation Loop Modulating A1's Power
Micro-Mirror Display Pulse Generator
5V/DIV 1V/DIV 2V/DIV
1V/DIV
DISTORTION
Some "micro-mirror" displays require high voltage pulses biasing. Pulse amplitude must adjustable anywhere within -50V window, with pulse bottom amplitude independently settable. Additionally, rise fall times must within 150ns into 1500pF micromirror load, with absolutely overshoot permissible. input pulse supplied from powered positive going logic. These requirements dictate very carefully considered level shifter.
2ms/DIV
AN98
Figure Figure Waveforms Include A1's Square (Trace Triangle (Trace Outputs, A2's Sinewave (Trace A3's Rectified Output (Trace Distortion Residue (Trace 1M-0.01µF Filter Permits Distortion, Despite Triangle Wave Infidelity
originating triangle waves infidelity. Other specifications include less than 0.15% amplitude variation supply shifts 3.4V 36V, frequency stability inside 0.01% over same supply range initial frequency accuracy
Figure circuit meets display requirements. input pulse applied both sections ®1693 noninverting driver. LTC1693 output reproduces input pulse much lower source impedance. LTC1693 output, referenced negative rail RCdiode combination, drives level shifter utilizing Baker clamping base speed-up capacitance, provides wideband voltage gain with pulse amplitude collector emitter supply potentials. Q1's collector capacitance isolated Q2-Q3. These transistors, turn, drive output stage Q4-Q5 resistor. This resistor combines with Q4-Q5 input capacitance control edge
an98f
AN98-3
Application Note
LT1635 0.2V PULSE AMPLITUDE ADJUST -40V FZT951 NOTE: MINIMIZE INDUCTANCE FROM OUTPUT LOAD. 10µF CAPACITORS INTIMATE WITH Q4-Q5 COLLECTORS. LOAD, Q4-Q5 RESISTOR INTIMATE. TRANSITION PURITY DEFAULT VALUE 200. SUPPLY CURRENT LIMIT 25mA. METAL FILM RESISTOR.
LT1635
0.01µF 100k -50V 1000pF LTC1693 10µF TANT
100kHz WIDE
1N5711
1.5k
1N4148
Figure High Voltage, Wideband Level Shift Micro-Mirror Biasing Precludes Overshoot. Input Pulse Switches Voltage Gain Stage LTC1693 Driver. Q2-Q3 Isolate Q1's Collector, Bias Q4-Q5 Output. A1-Q6 Regulate Pulse Amplitude; Potential Sets Pulse Bottom Voltage. Output Pulse Amplitude, Settable Anywhere Within These Limits, Overshoot
times overshoot. value, nominally 200, will vary somewhat with layout should selected best output waveform purity. high current types, drive capacitive load. 5-transistor stage swings potentials established Q1's emitter collector rails3. Emitter rail voltage, hence "pulse bottom" amplitude, potential power supply, variable between -50V. collector rail controlled operating configuration4. containing amplifier 0.2V reference, drives regulate collector rail anywhere between zero accordance with potentiometer's setting. settability both power rails, combined with transistor stages wide operating region, permits pulse amplitude control over desired range. Figure shows level shift output (trace responding input pulse (trace with amplitude limits adjusted zero -50V. high voltage output transitions, occurring within 100ns, exceptionally pure.
AN98-4
1N5711 2N3904 TRANSITION 2N3906 PURITY (SELECTED TYPICAL 200) FZT851 FZT951 10µF TANT MICRO-MIRROR LOAD 1500pF MPS2222A
AN98
-50V PULSE BOTTOM AMPLITUDE ADJUST
5V/DIV
10V/DIV
100ns/DIV
AN98
Figure Level Shift Responds (Trace Input Pulse (Trace with Amplitude Limits Adjusted Zero -50V. Fast, High Voltage Transitions Exceptionally Pure
Note Transistor data sheet aficionados notice that -50V potential exceeds VCEO specifications. transistors operate under VCER conditions, where breakdown considerably higher. Note collector rail regulation scheme suggested Albert Linear Technology Corporation.
an98f
Application Note
Simple Rise Time Frequency Reference frequent requirement wideband circuit work rise time/frequency reference. LTC6905 oscillator provides simple realize this. This device, programmable strapping single resistor, achieves outputs over continuous 17MHz 170MHz range with accuracy inside Additionally, output stage transitions typically within 500ps. Figure circuit delightfully simple. LTC6905 100MHz output strapping resistor value shown. resistor isolates IC's output from
CONNECT RESISTOR DIRECTLY LTC6905 OUTPUT LTC6905 17.2k*
AN98
oscilloscope input parasitic capacitance, promoting fastest possible transitions. Figure shows circuit output 1GHz real-time bandwidth (tRISE 350ps). 100MHz square wave displays sub-nanosecond transitions. Determining transition rise fall times requires faster oscilloscope5. Figures measured 3.9GHz sampled bandpass, record 400ps rise time (Figure 320ps fall time (Figure 11).
Note Appendix "How Much Bandwidth Enough?" Appendix "Connections, Cables, Adapters, Attenuators, Probes Picoseconds."
953*
100MHz OUTPUT. CONNECT DIRECTLY INPUT OSCILLOSCOPE. CABLE
100mV/DIV
METAL FILM RESISTOR
Figure LTC6905 Oscillator Configured Sub-Nanosecond Transitions 100MHz Output Rise Time/Frequency Reference
2ns/DIV
AN98
Figure 100MHz Output Viewed 1GHz Real-Time Bandwidth Displays Sub-Nanosecond Transitions
50mV/DIV
50mV/DIV
100ps/DIV
AN98
100ps/DIV
AN98
Figure Transition Rise Time Measures 400ps 3.9GHz (tRISE 90ps) Sampled Bandpass. Trace Granularity Derives from Sampling Oscilloscope Operation
Figure Transition Fall Time Measures 320ps 3.9GHz (tRISE 90ps) Sampled Bandpass. Trace Granularity Derives from Sampling Oscilloscope Operation
an98f
AN98-5
Application Note
Picosecond Rise Time Pulse Generator with Pulse Aberrations Impulse response rise time testing often require fast rise time source with high degree pulse purity. These parameters difficult simultaneously achieve, particularly sub-nanosecond speeds. Figure 12's circuit, derived from oscilloscope calibrators, meets these criteria, delivering 850ps output with less than pulse aberrations. Oscillator delivers 10MHz square wave current mode switch Q2-Q3. Note that powered between ground meet transistor biasing requirements. provides current drive Q2-Q3. When biases goes off. Q3's collector rises rapidly potential determined Q1's collector current, resistors circuits output termination. When goes low, turns off, comes output settles zero. prevents from saturating. circuit's positive output transition extremely fast singularly clean. Figure viewed 1GHz real-time bandwidth, shows 850ps rise time with exceptionally pure pre- post-transition characteristics6. Figure details pulse settling. photo shows pulse-top region immediately following positive 500mV transition.
Note measured 850ps rise time, influenced monitoring 1GHz oscilloscopes 350ps rise time, almost certainly pessimistic. root-sum-square correction applied measurement indicates 775ps rise time. Appendix detailed discussion.
0.5V AMPLITUDE OUTPUT TRIM FRONT CORNER PEAKING 1.2k 5.1k COAX OUTPUT 1MHz/850 PICOSECOND RISE TIME BASELINE TRIM
AN98
0.1V/DIV
500ps/DIV
AN98
Figure Figure 12's Displayed 850ps Transition Time Free Discontinuities when Viewed Real-Time 1GHz (tRISE 350ps) Bandwidth. Root-Sum-Square Correction Applied Measurement Indicates 775ps Rise Time
5mV/DIV 500mV PULSE
500ps/DIV
AN98
Figure Pulse Aberrations Remain Inside Within 400ps Transition Completion. 1GHz Ring-Off Probably Breadboard Limitations. Trace Granularity Derives from Sampling Oscilloscope Operation
4.7µF
10k* LTC1799 RSET
10MHz
METAL FILM RESISTOR 2N5771 2N6304 HP5082-2810
Figure Oscillator Drives Q2-Q3 Current Mode Switch, Producing 850ps Rise Time Output. Trims Facilitate Clean Transition with Pulse Aberrations
an98f
AN98-6
Application Note
Settling occurs within 400ps edge's completion, with undesired activity within ±4mV. 1mV, 1GHz ring-off probably breadboard construction limitations, could eliminated with stripline layout techniques. This level performance requires trimming. oscilloscope used should have least 1GHz bandwidth. adjusted best pulse presentation while sets 500mV output amplitude across termination. trims somewhat interactive, although unduly converging quickly give results noted. Picosecond Rise Time Pulse Generator Figure another fast rise time pulse generator, switches high grade, commercially produced tunnel diode mount produce 20ps rise time pulse. 01's clocking (trace Figure causes Q1's collector (trace switch capacitively loaded Q2-Q3 current source. resultant repetitive ramp Q3's collector (trace buffered biases tunnel diode mount output resistors. tunnel diode driven output (trace follows ramp until abruptly rising (trace just prior vertical division). This departure caused tunnel diode triggering. edge associated with this triggering extremely steep, with specified rise time 20ps clean settling. Figure examines this edge within limitations 3.9GHz (tRISE 90ps) sampling oscilloscope. trace shows tunnel diode's switching, driving oscilloscope
10V/DIV 5V/DIV
2V/DIV
0.5V/DIV 1µs/DIV
AN98
Figure (Trace Clocks Q1's Collector (Trace Switching Capacitively Loaded Q2-Q3 Current Source. Resultant Repetitive Ramp Q3's Collector (Trace Buffered Biases Tunnel Diode Output Resistors. Tunnel Diode Output (Trace Follows Ramp Until Abruptly Triggering
50mV/DIV
20ps/DIV
AN98
Figure Figure 15's 20ps Edge Drives 3.9GHz Sampling `Scope 90ps Rise Time Limit. Trace Granularity Characteristic Sampling Oscilloscope Display
100k* RSET LTC1799 10µF 2N3906 BAT85 100kHz 4.7k
10µF RAMP BIAS GENERATOR OUTPUT COAX BIAS TRIM
AN95
2N3906 ZTX849
HEWLETT-PACKARD HP1106A TUNNEL DIODE MOUNT PICOSECOND OUTPUT RISE TIME
2N2369
1000pF 1N4148
FERRITE BEAD, FERRONICS 21-110J *0.1% METAL FILM RESISTOR "BIAS TRIM" FAST RISE OUTPUT PULSE
Figure Current Ramps Into Tunnel Diode Until Switching Occurs, Producing 20ps Edge. Squarewave Clocked from Switches Q2-Q3 Capacitively Loaded Current Source, Producing Repetitive Ramps Ascending Current Through Output Resistors Triggers Tunnel Diode
an98f
AN98-7
Application Note
90ps rise time limit7. Figure slowing sweep speed 100ps/divison, shows pulse settling 3.9GHz bandwidth) within inside 100ps8.
5V/DIV
5V/DIV
5V/DIV
50mV/DIV
5V/DIV
10ns/DIV
100ps/DIV
AN98
AN98
Figure Reducing Sweep Speed Shows Pulse Flatness Within Oscilloscope's 3.9GHz (tRISE 90ps) Bandwidth
Figure Pulse Generator Waveforms, Viewed 400MHz Real-Time Bandwidth, Include Input (Trace (Trace Fixed (Trace Variable Outputs. Circuit Output Pulse Trace Network's Differential Delay Manifests C2-C3 Positive Overlap. Extracts This Interval, Presents Output
Nanosecond Pulse Width Generator previous three circuits were optimized fast rise time. sometimes desirable produce extremely short width pulses response input trigger. Such predictable, programmable short time interval generator broad fast pulse circuitry, particularly sampling applications9. Figure built around quad high speed comparator fast gate, settable 10ns output width with 520ps, transitions. Pulse width varies less than 100ps with supply variations ±5%. Minimum input trigger width 30ns input-output delay 18ns10. input pulse (Figure trace inverted which also isolates termination. C1's output drives
fixed variable networks. networks charge time difference, hence delay, primarily determined programming resistor scale factor 80/ns. arranged complementary output level detecNote Sorry, 3.9GHz fastest `scope house. Appendix relevant comment. Note HP1106 longer produced, although available secondary market. TD1107, currently manufactured Picosecond Pulse Labs, equivalent unit, although have experience with Note Pedestrian laboratory argot interval generator "one-shot." Note This circuit considerably improved extension earlier work. References
INPUT
LT1721
80/ns VARIABLE DELAY 0.1µF
LT1721
2.5V 2.5V NOTE: GROUND UNUSED GATE INPUTS. CONNECT UNUSED LT1721 +INPUT 2.5V, GROUND -INPUT DIFFERENTIAL DELAY GENERATOR FIXED DELAY
Figure Pulse Generator 10ns Width, 520ps Transitions. Unloads Termination, Drives Differential Delay Network. C2-C3 Complementary Outputs Represent Delay Difference Edge Timing Skew. High During C2-C3 Positive Overlap, Presents Circuit Output
an98f
AN98-8
74AHC08 OUTPUT GATE
LT1721
Application Note
tors, represent network's delay difference edge time skew. Trace C3's ("fixed") output trace C2's ("variable") output. Gate G1's output (trace high during C2-C3 positive overlap, presents circuit's output pulse. Figure shows width (measured amplitude) output pulse with 390. pulse clean, with well defined transitions. Post-transition aberrations, within derive from G1's bond wire inductance imperfect coaxial probing path. Figure shows narrowest full amplitude (5V) pulse obtainable. Width measures amplitude point 1.7ns base 3.9GHz bandwidth. Shorter widths obtainable partial amplitude pulses acceptable. Figure shows 3.3V, 700ps width (50%) with 1.25ns base. G1's rise time limits minimum achievable pulse width. Figure taken 3.9GHz sampled bandpass, measures 520ps rise time. Fall time similar. Single Rail Powered Amplifier with True Zero Volt Output Swing Many single supply powered applications require amplifier output swings within millivolt even sub-millivolt levels ground. Amplifier output saturation limitations normally preclude such operation. Figure 25's power supply bootstrapping scheme achieves desired characteristics with minimal component addition11. chopper stabilized amplifier, clock output. This output switches providing drive diode-capacitor charge pump. charge pump output feeds A1's terminal, pulling below zero, permitting output swing (and below) ground. desired, negative output excursion limited either clamp option shown.
Note Reference Appendix
1V/DIV
1V/DIV
2ns/DIV
AN98
500ps/DIV
AN98
Figure Wide Output with Clean, with Well Defined Transitions. Post-Transition Aberrations, Within Derive from Bond Wire Inductance Imperfect Coaxial Probe
Figure Narrowest Full Amplitude Pulse Width 1ns; Base Width Measures 1.7ns. Measurement Bandwidth 3.9GHz
1V/DIV
1V/DIV
500ps/DIV
AN98
200ps/DIV
AN98
Figure Partial Amplitude Pulse, 3.3V High, Measures 700ps Width with 1.25ns Base. Trace Granularity Artifact 3.9GHz Sampling Oscilloscope Operation
Figure Transition Detail 3.9GHz Bandpass (tRISE 90ps) Shows 520ps Rise Time. Fall Time Similar. Trace Granularity Derives from Sampling Oscilloscope Operation
an98f
AN98-9
Application Note
Reliable start-up this bootstrapped power supply scheme valid concern, warranting investigation. Figure amplifier's (trace initially rises supply turnon (trace heads negative when amplifier clocking (trace commences about midscreen. circuit provides simple obtain output swing zero volts, permitting true "live zero" output.
resolution down produces output resistance 4-terminal Kelvin sensed input with 0.1% accuracy over 5.25V 9.5V power supply range. carrier modulation scheme employed reject noise error inducing offsets parasitic thermocouples (Seebeck effect)12. associated components form 10mA current source that alternately steered between unknown resistance, ground LTC6943 switch pins LTC6943's control (Pin clocked 45Hz from CD4024 divider output. This action causes carrier modulated 10mA current flow through Rx's value determines resultant voltage across This signal capacitively coupled LTC6943 switch pins driven synchronously with current source modulation. These pins switching forms synchronous rectifier, demodulating signal back across A2's input capacitor. amplifies this potential gain milliohm, full scale. Note that single-rail powered A2's output swing true "zero" because utilizes variant supply boostrapping scheme presented back Figure A2's clock output drives which pulses CD4024 divider. divider output switches LTC6943 modulatordemodulator while another output drives bootstrapped charge pump supply A2's with about -7V. Diode clamps prevent accidental overvoltage probe inputs without introducing loading error 10mV maximum carrier waveform. Circuit calibration involves placing 0.1% resistor adjusting trimmer 1.000VOUT. synchronously demodulated carrier technique displays inherent narrow band noise rejection characteristics "lock-in" type measurements. Figure shows normal waveform across 10mV signal clean, circuit output reads 1.000V. Figure noise deliberately injected into probes, burying carrier noise-to-signal ratio. Despite this, circuit output remains 1.000V.
Note This circuit's operation derived from Hewlett-Packard HP-4328A. Reference
LTC1150
10µF CLKOUT 100k DASHED LINE CIRCUITRY CLAMP OPTIONS. TEXT BAT85
AN98
-3.5V HERE
Figure Single Rail Powered Amplifier True Zero Volt Output Swing. A1's Clock Output Switches Driving DiodeCapacitor Charge Pump. A1's Assumes Negative Voltage, Permitting Zero (and Below) Volt Output Swing
5V/DIV
5V/DIV
0.2V/DIV
5ms/DIV
AN98
Figure Amplifier Bootstrapped Supply Start-Up. Amplifier (Trace Initially Rises Positive Supply (Trace Turn-On. When Amplifier Internal Clock Starts (Trace Vertical Division), Charge Pump Activates, Pulling Negative
Milliohmmeter Resistance measurement contacts, traces vias requires resistance ohmmeter. Figure 27's battery-powered design full-scale range, with
AN98-10
2N3904
10µF
an98f
Application Note
CURRENT SOURCE LT1004 2.5V 249*
3kHz CLOCK SWITCH CONTROL
2N3906
FREQUENCY DIVIDER CD4024 OUTPUT 10µF
MODULATOR FORCE SENSE
AMPLIFIER
931*
FULL-SCALE TRIM
FORCE
SENSE
AN98
Figure Full-Scale Ohmmeter Accurately Resolves 0.001 Board Trace/Via Resistance Measurement. Carrier Modulation Unknown Resistance Permits Narrowband Synchronous Demodulation, Rejecting Noise Parasitic Offsets. Kelvin Sensing Prevents Test Lead Induced Errors
0.01V/DIV
0.01V/DIV
5ms/DIV
AN98
5ms/DIV
Figure Normal Waveform with 1.000. Circuit Output Correctly Reads 1.000V
Figure Waveform with 1.000 Noise Added. Circuit Output Remains 1.000V Despite Noise-to-Signal Ratio
0.02% Accurate Instrumentation Amplifier with 125VCM 120dB CMRR Figure 30's circuit used when high accuracy differential input measurement required13. particularly suited transducer signal conditioning where high common mode voltage occur. circuit offset drift chopper stabilized also incorporates novel optically coupled, switched capacitor input stage achieve specifications unavailable conventional designs. common mode rejection exceeds 120dB over ±125V input range gain accuracy stability
Error from sources inside 0.02%. design's high common mode voltage capability allows reliably extract small signals while withstanding transient fault conditions often encountered industrial environments. This scheme measures input difference voltage switching (S1A, S1B) capacitor across input ("ACQUIRE"). After time capacitor charges voltage across
Note Sharp-eyed devotees publications will recognize this mildly modified variant Reference (pp. 10-11) Reference (pp. 1-2).
an98f
0.01µF
LT1784 TP0610L LTC6943
LTC1150 100k* 10µF CHARGE PUMP
SYNCHRONOUS DEMODULATOR
METAL FILM RESISTOR 1N4148 BAT85 LTC6943 NUMBER
AN98-11
AN98
Application Note
INPUT ±2.5V ±125V 750k "ACQUIRE" "READ" 10µF BAT85s 150pF -3.5V HERE 10µF 2N3906
100k
CLKOUT OUTPUT ±2.5V
LTC1150
TP0610L "ACQUIRE" (S1) 130k TP0610L "READ" (S2) 0.02µF 130k 0.02µF
74C74
140Hz
74C90
74C74
PANASONIC ECP-U1C105MA5 OPTICALLY DRIVEN MOSFETS. AROMAT AQW227NA (DUAL) VOLTAGES <80V, AQS225SX (QUAD, SO-16 PACKAGE) 74C02
1N4148 IN4689, 5.1V
Figure 0.02% Accurate, 125V Common Mode Range Instrumentation Amplifier Utilizes Optically Driven FETs Flying Capacitor. Logic Driven Q1-Q2 Provides Nonoverlapping Clocking S1-S2 LEDs. Clock Derives from A1's Internal Oscillator
input. open close ("READ"). This grounds capacitor plate capacitor discharges into grounded unit S2B. This switching cycle continuously repeated, resulting A1's ground referred positive input assuming input difference voltage. common mode voltage rejected optical switching ungrounded capacitor. driven MOSFET switches specified have junction potentials optical drive contributes charge injection error. nonoverlapping clock prevents simultaneous conduction which would result charge loss, causing errors possible circuit damage. 5.1V zener prevents switched capacitor failure inputs subjected differential overvoltage. chopper stabilized amplifier, clock output. This clock, level shifted buffered drives logic divider chain. first flip-flop activates charge pump, pulling A1's negative, permitting amplifier swing (and below) zero volts14. divider chain terminates into logic network. This network provides phase opposed
5V/DIV
5V/DIV
5mA/DIV 5mA/DIV 2ms/DIV
AN98
Figure Clocked, Cross Coupled Capacitors (Traces 74C02 Based Network Result Nonoverlapping Drive (Traces S1-S2 Actuation LEDs
charging 0.02µF capacitors (Traces Figure 31). gating associated with these capacitors arranged logic provides nonoverlapping, complementary biasing These transistors supply this nonoverlapping drive actuating LEDs (Traces
Note This arrangement will recognized from Figures also Reference Appendix
an98f
AN98-12
AN98
Application Note
extremely small parasitic error terms driven MOSFET switches results nearly theoretical circuit performance. However, residual error (0.1%) caused S1A's high voltage switching pumping S2B's junction capacitance. This results slight quantity unwanted charge being transferred capacitor S2B. amount charge transferred varies with input common mode voltage and, lesser extent, varactor-like response S2B's off-state capacitance. These terms partially cancelled feedforward A1's negative input feedforward from Q1's gate S2B. corrections compensate error factor five, resulting 0.02% accuracy. Optical switch failure could expose high voltage, destroying possibly presenting destructive voltages rail. This most unwelcome state affairs prevented resistors A1's positive input. Wideband, Feedthrough, Level Switch Rapid switching wideband, level signals complicated switch control artifacts corrupting signal channel. FET-based designs suffer large charge injectionbased errors, often orders magnitude larger than signal interest. classic diode bridge switch much lower error, requires substantial support circuitry careful trimming15. Figure 32's circuit takes different approach synthesize switch with minimal control channel feedthrough. This design switches signals over ±30mV range with peak control channel feedthrough
SWITCH CONTROL INPUT 1N4148 SIGNAL INPUT ±30mV
millivolts settling times inside 40ns. This capability, developed amplifier data converter settling time measurement, broad implication instrumentation sampling circuitry. circuit approximates switch action varying transconductance amplifier, maximum gain which unity. transconductance, amplifier gain nearly zero, essentially signal passed. maximum transconductance, signal passes unity gain. amplifier transconductance control channel very wideband, permitting them faithfully track rapid variations transconductance setting. This characteristic means amplifier never control, affording clean response rapid settling "switched" input's value. A1A, section LT®1228, wideband transconductance amplifier. voltage gain determined output resistor load current magnitude into "ISET" terminal. A1B, second LT1228 section, unloads A1A's output. shown provides gain two, when driving back-terminated cable, effective gain unity cable's receiving end. Current source controlled "switch control input," sets A1A's transconductance, hence gain. With gated (control input zero), resistor supplies about 1.5µA into A1A's ISET pin, resulting voltage gain nearly zero, blocking input signal. When switch control input goes high, turns
Note References practical examples diode bridge switches.
1.8k
7.5k
10k** 0.02µF
OUTPUT ±30mV
LT1228
2N3906 3.57* 7.5k -15V ZERO
GAIN 50pF SWITCHING ABERRATIONS (OPTIONAL, TEXT) LT1228
ISET
-15V
METAL FILM **3300ppm/°C, BREL COMPONENTS #TRS
AN98
OPTIONAL BUFFERED/GAIN OUTPUT ±60mV (0mV ±30mV WHEN DRIVING BACKTERMINATED CABLE)
Figure Transconductance Amplifier Based 100MHz Level Switch Minimal Control Channel Feedthrough. A1A's Unity-Gain Output Cleanly Switched Logic Controlled Q1's Transconductance Bias. Optional Provides Buffering Signal Path Gain
an98f
AN98-13
Application Note
sourcing 1.5mA into ISET pin. This 1000:1 current change forces maximum transconductance, causing amplifier assume unity gain pass input signal. Trims zero gain ensure accurate input signal replication circuit's output. optional 50pF variable capacitor used damp residual settling transients. specified resistor 3300ppm/°C temperature coefficient, compensating A1A's complementary transconductance tempco minimize gain drift. Figure shows circuit response switched 10mV input CABERRATION 35pF. When control input (trace low, output (trace occurs. When control input goes high, output reproduces input with "switch" feedthrough settling about 20ns. Note that turn-off feedthrough undetectable, transconductance reduction attendant bandwidth drop. Figure speeds sweep 10ns/ division examine settling detail. output (trace settles inside 40ns after switch control (trace goes high. Peak feedthrough excursion, damped CABERRATION, only 5mV. Figure taken under identical conditions, except that CABERRATION 0pF. Feedthrough increases 20mV, although settling time remains 40ns. Figure using double exposure technique, compares signal channel rise times
5V/DIV
5V/DIV
0.01V/DIV
0.005V/DIV
100ns/DIV
AN98
10ns/DIV
AN98
Figure Control Input (Trace Dictates Switch Output's (Trace Representation 0.01V Input. Control Channel Feedthrough, Evident Switch Turn-On, Settles 20ns. Turn-Off Feedthrough Undetectable Decreased Signal Channel Transconductance Bandwidth. CABERRATION 35pF This Test
Figure High Speed Delay Feedthrough Signal Input. Output (Trace Peaks Only 0.005V Before Settling Inside 0.001V 40ns After Switch Control Command (Trace CABERRATION 35pF This Test
5V/DIV
0.005V/DIV
0.005V/DIV
10ns/DIV
AN98
10ns/DIV
AN98
Figure Identical Conditions Figure Except CABERRATION 0pF. Feedthrough Related Peaking Increases 0.02V; 0.001V Settling Time Remains 40ns
Figure Signal Channel Rise Time CABERRATION (Leftmost Trace) 35pF (Rightmost Trace) Record 3.5ns 25ns, Respectively. Switch Control Input High this Measurement. Photograph Utilizes Double Exposure Technique
an98f
AN98-14
Application Note
CABERRATION (leftmost trace) 35pF (rightmost trace) with control channel tied high. larger CABERRATION value, while minimizing feedthrough amplitude (see Figure 34), increases rise time versus CABERRATION 0pF. calibrate this circuit, ground signal input control input "zero" trim zero volt output within 500µV. Next, 30mV into signal input adjust gain trim exactly 60mV A1B's unterminated output. Finally, CABERRATION used, adjust minimum feedthrough amplitude with signal input grounded control input with 1MHz square wave. Powered, 0.0015% Linearity, Quartz-Stabilized Converter Almost precision voltage-to-frequency converters (VF) utilize charge pump based feedback stability. These schemes rely capacitor stability. great deal effort towards this approach resulted high performance converters (see Reference 31). Obtaining temperature coefficients below 100ppm/°C requires
ERROR AMPLIFIER- INTEGRATOR 0.1µF FULL INPUT SCALE 31.6k*
careful attention compensating capacitor's drift with temperature. Although this done, complicates design. Similarly, capacitor dielectric absorption causes errors, limiting linearity typically 0.01%. Figure 37's powered design, derived from Reference 31's ±15V circuit, reduces gain 8ppm/°C achieves 15ppm linearity replacing capacitor with quartz-stabilized clock. charge pump feedback-based circuits, feedback based quartz-stabilized circuit, feedback based where stable current source interval time derived from clock. capacitor involved. Figure details Figure 37's waveforms operation. positive input voltage causes integrate negative direction (trace Figure 38). flip-flop's output (trace changes state first positive-going clock edge (trace after A1's output crossed input's switching threshold. provides quartz-stabilized clock. flip-flop's output controls gating
32.768kHz 100k
LT1671 100k
10pF
CLK1 CLK2 QUARTZ CLOCK 1000pF 120k
LTC1043
SWITCHED CURRENT FEEDBACK SWITCHED CURRENT SINK VN2222L
Figure Powered, Quartz-Stabilized 10kHz Converter 0.0015% Linearity 8ppm/°C Temperature Coefficient. Servo Controls Switched Current Sink Clock Synchronized Flip-Flop Maintain Zero Volt Summing Junction Loop Repetition Frequency Directly Conforms Input Voltage
an98f
LT1884
LT1884 4.99k*
74HC74
CHARGE PUMP OUTPUT -VGENERATOR 0kHz 10kHz
SYNCHRONIZING/CHARGE PUMP DRIVE FLIP-FLOPS HERE LT1461 2.5V
EPSON C-001R BAT85 *ALPHA ELEC. CORP, FLA-Y, 0.1%
AN98
AN98-15
Application Note
20mV/DIV COUPLED 5V/DIV 10mV/DIV COUPLED 5V/DIV 5V/DIV 500µA/DIV 500µA/DIV 20µs/DIV (UNCALIBRATED)
AN98
5V/DIV
200µs/DIV
AN98
Figure Quartz-Stabilized Converter Waveforms Include Output (Trace Flip-Flop Output (Trace Clock (Trace Switched Current Feedback (Trace Current Removal (Trace from Summing Junction Commenses When Clock Goes High with
Figure Same Trace Assignments Figure Reduced Oscilloscope Sweep Speed Shows Effect Timing Uncertainty Between Loop Clock. Loop Pulse Position Occasionally Irregular, Frequency Constant Over Practical Measurement Intervals
precision current sink composed LT1461 voltage reference, LTC1043 switch. negative bias supply, derived from flip-flop's output driving charge pump, furnishes sink current. When integrating negatively, Q1's output high LTC1043 directs current sink's output ground Pins When A1's output crosses input's switching threshold, goes first positive clock edge. LTC1043 Pins close precise, quickly rising current flows A1's summing point (trace This current, scaled greater than maximum signal-derived input current, causes A1's output reverse direction. first positive clock pulse after A1's output crosses input's trip point, switching again occurs entire process repeats. repetition frequency depends input-derived current, hence frequency oscillation directly related input voltage. circuit's output taken from flip-flop's output. Because this circuit replaces capacitor with quartz-locked clock, temperature drift low, typically inside 8ppm/°C. quartz crystal contributes about 0.5ppm/°C, with most drift contributed current source components, input resistor switching time variations. Short term frequency jitter occurs because uncertain timing relationship between loop frequency clock phase. This normally problem because circuit's output usually read over many cycles, e.g., second. Figure shows effects timing
uncertainty. Reduced sweep speed allows viewing phase uncertainty induced modulation A1's output ramp (trace Note pulse position (traces irregularity during A1's major excursions. This behavior causes short term pulse displacement, output frequency constant over practical measurement intervals. Circuit linearity inside 0.0015% (0.15Hz), gain temperature coefficient 8ppm/°C (0.08Hz/°C) power supply rejection better than 100ppm (1Hz) over range. LT1884's input bias drift reduce zero point originated errors insignificant levels. trim this circuit, apply 5.0000V adjust potentiometer 10.000kHz output. Basic Flashlamp Illumination Circuit Cellular Telephones/Cameras BEFORE PROCEEDING FURTHER, READER WARNED THAT CAUTION MUST USED CONSTRUCTION, TESTING THIS CIRCUIT. HIGH VOLTAGE, LETHAL POTENTIALS PRESENT THIS CIRCUIT. EXTREME CAUTION MUST USED WORKING WITH, MAKING CONNECTIONS THIS CIRCUIT. REPEAT: THIS CIRCUIT CONTAINS DANGEROUS, HIGH VOLTAGE POTENTIALS. CAUTION. Next generation cellular telephones will include high quality photographic capability. Flashlamp-based lighting crucial good photographic performance. previous full-length Linear Technology publication detailed flash illumination issues presented flash circuitry equipped
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AN98-16
Application Note
with "red-eye" reduction capability.16,17 Some applications require this feature; deleting results extremely simple compact flashlamp solution. Figure 40's circuit consists power converter, flashlamp, storage capacitor SCR-based trigger. operation LT3468-1 charges regulated 300V about efficiency. "trigger" input turns depositing C2's charge into producing high voltage trigger event flashlamp. This causes lamp conduct high current from resulting intense flash light. LT3468-1 associated waveforms, appearing Figure include trace "charge input," going high. This initiates switching, causing ramp (trace When arrives regulation point, switching ceases resistively pulled-up "DONE" line drops (trace indicating C1's charged state. "TRIGGER" command (trace resulting C1's discharge lamp, occur time this case 600ms) after "DONE" goes low. Normally, regulation feedback would provided resistively dividing down output voltage. This approach acceptable because would require excessive switch cycling offset feedback resistor's constant power drain. While this action would maintain regulation, would also drain excessive power from
DANGER! Lethal Potentials Present Caution FLASH STORAGE CAPACITOR 4.7µF
primary source, presumably battery. Regulation instead obtained monitoring T1's flyback pulse characteristic, which reflects T1's secondary amplitude. output voltage T1's turns ratio. This feature permits tight capacitor voltage regulation, necessary ensure consistent flash intensity without exceeding lamp energy capacitor voltage ratings. Also, flashlamp energy conveniently determined capacitor value without other circuit dependencies. Figure shows high speed detail high voltage trigger pulse (trace flashlamp current (trace light output (trace Some amount time required lamp ionize begin conduction after triggering. Here, after 4kVP-P trigger pulse, flashlamp
Note References Note "Red-eye" photograph caused human retina reflecting light flash with distinct color. eliminated causing eye's iris constrict response intensity flash immediately preceding main flash.
5V/DIV 200V/DIV
5V/DIV
5V/DIV
AN98
+VIN
400ms/DIV
13µF 330V TRIGGER
0.047µF 400V
FLASHLAMP
Figure Capacitor Charging Waveforms Include Charge Input (Trace (Trace DONE Output (Trace TRIGGER Input (Trace C1's Charge Time depends Upon Value Charge Circuit Output Impedance. TRIGGER Input, Widened Figure Clarity, Occur Time After DONE Goes
LT3468-1 CHARGE CHARGE DONE TRIGGER DONE CAPACITOR CHARGER
2000V/DIV
50A/DIV
AN98
RUBYCON 330FW13AK6325 TOSHIBA DUAL DIODE 1SS306, CONNECT DIODES SERIES PANASONIC MA2Z720
SCR: TOSHIBA S6A37 LDT565630T-002 TOKYO COIL-BO-02 FLASHLAMP: PERKIN ELMER BGDC0007PKI5700
RELATIVE LIGHT/DIV
5µs/DIV
AN98
Figure Complete Flashlamp Circuit Includes Capacitor Charging Components, Flash Capacitor Trigger (R1, SCR) Flashlamp. TRIGGER Command Biases SCR, Ionizing Lamp Resultant Discharge Through Lamp Produces Light
Figure High Speed Detail Trigger Pulse (Trace Resultant Flashlamp Current (Trace Relative Light Output (Trace Current Exceeds 100A After Trigger Pulse Ionizes Lamp
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AN98-17
Application Note
current begins ascent over 100A. current rises smoothly 3.5µs well defined peak before beginning descent. resultant light produced rises more slowly, peaking about before decaying. Slowing oscilloscope sweep permits capturing entire current light events. Figure shows that light output (trace follows lamp current (trace profile, although current peaking more abrupt. Total event duration 200µs with most energy expended first 100µs.
DANGER! Lethal Potentials Present Text 4.7µF
13µF 330V
300VOUT MAXIMUM
LT3468
10M*
CHARGE
DONE
LT1006
RELATIVE LIGHT/DIV
33pF
50µs/DIV
AN98
Figure Photograph Captures Entire Current (Trace Light (Trace Events. Light Output Follows Current Profile Although Peaking Less Defined. Waveform Leading Edges Enhanced Figure Clarity
METAL FILM RESISTOR RUBYCON 330FW13AK6325 TOSHIBA DUAL DIODE 1SS306, CONNECT DIODES SERIES PANASONIC MA2Z720 LDT565630T-002
300V Output DC/DC Converter BEFORE PROCEEDING FURTHER, READER WARNED THAT CAUTION MUST USED CONSTRUCTION, TESTING THIS CIRCUIT. HIGH VOLTAGE, LETHAL POTENTIALS PRESENT THIS CIRCUIT. EXTREME CAUTION MUST USED WORKING WITH, MAKING CONNECTIONS THIS CIRCUIT. REPEAT: THIS CIRCUIT CONTAINS DANGEROUS, HIGH VOLTAGE POTENTIALS. CAUTION. Figure shows LT3468 photoflash capacitor charger, described previous application, used general purpose, high voltage DC/DC converter. Normally, LT3468 regulates output 300V sensing T1's flyback pulse characteristic. This circuit forces LT3468 regulate lower voltages truncating charge cycle before output reaches 300V. compares resistively divided down portion output with program input voltage. When program input voltage input) exceeded output derived potential input) A1's output goes low, shutting down LT3468. feedback capacitor provides hysteresis, sharpening A1's output prevent chattering trip point. LT3468 remains shut down until output voltage drops enough
Figure Voltage Programmable 300V Output Regulator. Controls Regulator Output Duty Cycle Modulating LT3468/T1 DC/DC Converter Power Delivery
5V/DIV 1V/DIV COUPLED 250V LEVEL
20ms/DIV
Figure Details Figure 44's Duty Cycle Modulated Operation. High Voltage Output (Trace Ramps Down Until (Trace Goes High, Enabling LT3468/T1 Restore Output. Loop Repetition Rate Varies with Input Voltage, Output Point Load
trip A1's output high, turning back this way, duty cycle modulates LT3468, causing output voltage stabilize point determined program input. Figure shows 250V output (trace decaying down about until (trace goes high, enabling LT3468 restoring loop. This simple circuit works well, regulating over programmable
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AN98-18
100k*
AN98
50A/DIV
VPROGRAM INPUT 300VOUT
AN98
Application Note
300V range, although inherent hysteretic operation mandates output ripple noted. Loop repetition rate varies with input voltage, output point load ripple always present. next circuit essentially eliminates ripple cost increased complexity. Ripple Noise 300V Output DC/DC Converter BEFORE PROCEEDING FURTHER, READER WARNED THAT CAUTION MUST USED CONSTRUCTION, TESTING THIS CIRCUIT. HIGH VOLTAGE, LETHAL POTENTIALS PRESENT THIS CIRCUIT. EXTREME CAUTION MUST USED WORKING WITH, MAKING CONNECTIONS THIS CIRCUIT. REPEAT: THIS CIRCUIT CONTAINS DANGEROUS, HIGH VOLTAGE POTENTIALS. CAUTION. Figure uses post-regulator reduce Figure 44's output ripple noise only 2mV. LT3468 identical pervious circuit, except zener diode series with 10M-100k feedback divider. This component causes C1's voltage, hence Q1's collector, regulate above VPROGRAM inputs dictated point. VPROGRAM input also routed A2-Q2-Q1 linear post-regulator. A2's 10M-100k feedback divider does include zener, post-regulator follows VPROGRAM input with offset. This arrangement forces across output voltages. This figure high enough eliminate undesirable ripple noise from output while keeping dissipation low. form current limit, protecting from overload. Excessive current through shunt turns drives shutting down LT3468. Simultaneously portion Q3's collector current turns hard, shutting This loop dominates normal regulation feedback, protecting circuit until overload removed.
DANGER! Lethal Potentials Present Text 10M* 0.68µF LT3468 CHARGE DONE 1N4702 10M* 100k 2N3904
AN98
4.7µF
0.01µF
13µF 330V
300VOUT MAXIMUM
200k
LT1013 100k**
0.1µF
LT1013 33pF
100k
Figure Post-Regulation Reduces Figure 44's Output Ripple 2mV. LT3468-Based DC/DC Converter, Similar Figure Delivers High Voltage Collector. Form Tracking, High Voltage Linear Regulator. Zener Sets 15V, Ensuring Tracking with Minimal Dissipation. Q3-Q4 Limit Short-Circuit Output Current
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100k**
METAL FILM RESISTOR **0.1% METAL FILM RESISTOR WIMA MKS-4, 400V RUBYCON 330FW13AK6325 TOSHIBA DUAL DIODE 1SS306, CONNECT DIODES SERIES PANASONIC MA2Z720 1N4148 2N6517 2N6520 LDT565630T-002
VPROGRAM INPUT 300VOUT
AN98-19
Application Note
Figure shows just effective post regulator When (trace goes high, Q1's collector (trace ramps response (note LT3468 switching artifacts ramps upward slope). When A1-LT3468 loop satisfied, goes Q1's collector ramps down. circuits output post-regulator (trace however, rejects ripple, showing only noise. Slight trace blurring derives from A1-LT3468 loop jitter. 200V Converter Bias BEFORE PROCEEDING FURTHER, READER WARNED THAT CAUTION MUST USED CONSTRUCTION, TESTING THIS CIRCUIT. HIGH VOLTAGE, LETHAL POTENTIALS PRESENT THIS CIRCUIT. EXTREME CAUTION MUST USED WORKING WITH, MAKING CONNECTIONS THIS CIRCUIT. REPEAT: THIS CIRCUIT CONTAINS DANGEROUS, HIGH VOLTAGE POTENTIALS. CAUTION. Avalanche photodiodes (APD) require high voltage bias. Figure 48's design provides 200V from input. circuit basic inductor flyback boost regulator with major important deviation. high voltage device, been interposed between LT1172 switching regulator inductor. This permits regulator control Q1's high voltage switching without undergoing high voltage stress. operating "cascode" with LT1172's internal switch, withstands L1's high voltage flyback events18. Diodes associated with Q1's source terminal
Note References (page (Appendix
5V/DIV
0.1V/DIV 5mV/DIV COUPLED 200V LEVEL 100µs/DIV
AN98
Figure Ripple Output (Trace Apparent PostRegulator's Operation. Traces Output Q1's Collector, Respectively. Trace Blurring, Right Photo Center, Derives from Loop Jitter
DANGER! Lethal Potentials Present Text
33µF BAT85 BAS521 IRF840 0.1µF 1N5256B 0.47µF 250V 1N5819 100k 10.7V BAS521 OUTPUT 200V
LT1172 200k (TRIM)
49.9k*
6.81k* *0.1% METAL FILM RESISTOR 33µH, COILTRONICS UP2B 0.47µF PANASONIC ECW-U2474KCV
AN98
Figure 200V Output Converter Bias. Cascoded Switches High Voltage, Allowing Voltage Regulator Control Output. Diode Clamps Protect Regulator from Transient Events; 100k Path Bootstraps Q1's Gate Drive from Output. Output Connected 300-Diode Combination Provides Short-Circuit Protection
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AN98-20
Application Note
clamp orginated spikes arriving Q1's junction capacitance. high voltage rectified filtered, forming circuit's output. Feedback regulator stabilizes loop provides frequency compensation. 100k path from output divider bootstraps Q1's gate drive about 10V, ensuring saturation. output connected 300-diode combination provides short-circuit protection shutting down LT1172 output accidentally grounded. 200k trim resistor sets 200V output while using standard values feedback divider. Figure shows operating waveforms. Traces LT1172 switch current voltage, respectively. Q1's drain trace Current ramp termination results high voltage flyback event Q1's drain. safety attenuated version flyback appears LT1172 switch. sinosoidal signature, inductor ring-off between conduction cycles, harmless.
0.5A/DIV
Wide Range, High Power, High Voltage Regulator BEFORE PROCEEDING FURTHER, READER WARNED THAT CAUTION MUST USED CONSTRUCTION, TESTING THIS CIRCUIT. HIGH VOLTAGE, LETHAL POTENTIALS PRESENT THIS CIRCUIT. EXTREME CAUTION MUST USED WORKING WITH, MAKING CONNECTIONS THIS CIRCUIT. REPEAT: THIS CIRCUIT CONTAINS DANGEROUS, HIGH VOLTAGE POTENTIALS. CAUTION. Figure example monolithic switching regulator making complex function practical. This regulator provides outputs from millivolts 500V 100W with efficiency19. compares variable reference voltage with resistively scaled version circuits output biases LT1074 switching regulator configuration. switcher's output drives DC/DC converter comprised receive out-of-phase square wave drive from 74C74 flip-flop stage LTC1693 drivers. flip-flop clocked from LT1074 output level shifter. LT3010 provides power 74C74 LTC1693. biases LT1074 regulator produce input DC/DC converter required balance loop. converter voltage gain about resulting high voltage output. This output resistively divided down, closing loop A1's negative input. Frequency compensation this loop must accommodate significant phase errors generated LT1074 configuration, DC/DC converter output filter. 0.47µF rolloff term 100-0.15µF lead network provide compensation, which stable loads.
Note This circuit updated version Reference
100V/DIV
20V/DIV 2µs/DIV
AN98
Figure Waveforms 200V Converter Include LT1172 Switch Current Voltage (Traces Respectively) Q1's Drain Voltage (Trace Current Ramp Termination Results High Voltage Flyback Event Drain. Safely Attenuated Version Appears LT1172 Switch. Sinosoidal Signature, Inductor Ring-Off Between Current Conduction Cycles, Harmless. Traces Intensified Near Center Screen Photographic Clarity
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AN98-21
Application Note
LT1693 0.01µF 22µF 2N2369 LT1693 LT3010 10.7k** MUR1100 DANGER! LETHAL POTENTIALS PRESENT SCREENED AREA. TEXT 500VOUT 200mA 680µH 0.1µF 1000V 1000V 74C74
100µF SOLID TANT
1.24k** 100µH 0.15µF
28VIN 100µF SOLID TANT
LT1074 MUR8100
1000µF 0.47µF 100k OUTPUT CALIB. 13.7k** LT1021-7 100k OUTPUT ADJUST
1N914
LTC1050
0.01µF WIMA, FKP-1 *VICTOREEN SLIM-MOX-108 **1% FILM RESISTOR MAGNETICS TECHNOLOGY, WINDHAM, N.H. CT5602-2 CT4667-2 CT1070-3 IRF530
Figure LT1074 Permits High Voltage Output Over 100dB Range with Power Efficiency. DANGER! Lethal Potentials Present-See Text
Figure gives circuit waveforms 500V output into 100W load. Trace LT1074 while trace current. Traces Q2's drain waveforms. disturbance leading edges cross-current conduction, which lasts about 300ns-a small percentage cycle. Transistor currents during this interval remain within reasonable values, overstress dissipation problems occur. This effect could eliminated with non-overlapping drive Q220, although there would reliability significant efficiency gain. waveforms synchronous because flip-flop drive stage clocked from LT1074 output. LT1074's maximum duty cycle means that Q1-Q2 switches never destructive drive. only condition
allowing drive occurs when LT1074 zero duty cycle. This case clearly nondestructive, because receives power. Figure shows same circuit points Figure only output. Here, loop restricts drive DC/DC converter small levels. chop just 60mV into this level L1's output diode drops look large, loop action forces desired 0.005V output. LT1074's switched mode drive maintains high efficiency high power, despite circuits wide output range21.
Note Reference example this technique. Note circuit related presented here appears Reference linear drive step-up DC/DC converter forces dissipation, limiting output power about 10W.
AN98-22
an98f
Application Note
Figure shows output noise 500V into 100W load. Q1-Q2 chopping artifacts clearly visible, although limited about 50mV. coherent noise characteristic traceable synchronous clocking LT1074. 500V step command into 100W load produces response Figure Loop response both edges clean, with falling edge slightly underdamped. This slew asymmetry typical switching configurations, because load output capacitor determine negative slew rate. wide range possible loads mandates compromise when setting frequency compensation. falling edge could made critically even over damped, response time other conditions would suffer. compensation used seems reasonable compromise.
50V/DIV
5V/DIV 50mA/DIV
5A/DIV
0.1V/DIV
50V/DIV
0.1V/DIV
50V/DIV
10µs/DIV
AN98
10µs/DIV
AN98
Figure Figure 50's Operating Waveforms 500V Output Into 100W Load
Figure Operating Waveforms 0.005V Output
0.05V/DIV COUPLED 500V LEVEL
100V/DIV
20µs/DIV
AN98
50ms/DIV
AN98
Figure Output Noise 500V into 100W Load. Residue Composed Q1-Q2 Chopping Artifacts. DANGER! Lethal Potentials Present-See Text
Figure 500V Step Response with 100W Load (Photo Retouched Clarity). DANGER! Lethal Potentials Present-See Text
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AN98-23
Application Note
3.3V, Paralleled Linear Regulator Figure another high power supply; unlike previous example, linear regulator. 7.5A regulators paralleled "master-slave" arrangement. "master" regulator wired produce 3.3V output conventional manner. feedback resistor senses 0.001 shunt located directly before circuit output. "slave" regulator, also wired nominal 3.3V output, sources circuit output identical fashion. sensing regulators difference voltage, adjusts "slave" regulator equal master's output voltage. This allows regulators equally share load current. 0.001 shunts cause negligible regulation loss, provide adequate signal
"MASTER" 7.5A LT1083 VOUT 124* 205* 5VIN
10µF
LT1218
0.001 0.001 VOUT 3.3V RLOAD
2.05k* 1.24k* "SLAVE" LT1083 VOUT 7.5A 0.003µF
10µF
AN98
METAL FILM RESISTOR HIGH QUALITY GROUND RETURN DIRECTLY LOAD GROUND 0.001 FIXED RESISTOR WIRE/TRACE LENGTH
Figure Paralleled Regulators Share Load Current. Amplifier Senses Differential Regulator Voltage; Biases "Slave" Equalize Output Currents. Remote Sensing Negates Lead Wire Voltage Drops
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AN98-24
Application Note
REFERENCES LTC6905 Data Sheet, Linear Technology Corporation. Tektronix, Inc., "Calibrator," Type Oscilloscope Service Instruction Manual, 1973, 3-15. Hewlett-Packard Company, HP1106A/1108A Tunnel Diode Mount, Hewlett-Packard Test Measurement Catalog, 1970, 513. Williams, Jim, Seven-Nanosecond Comparator Single Supply Operation," Linear Technology Corporation, Application Note 1998, Williams, Jim, "High Speed Comparator Techniques," Linear Technology Corporation, Application Note April 1985, 17-18. Balasubramaniam, "Advanced High Speed CMOS (AHC) Logic Family," "Ground Bounce Measurement," Texas Instruments, Inc., Publication SCAA034A, 1997. Hewlett-Packard Company, HP4328A Milliohmmeter Operating Service Manual, 1967. Williams, Jim, "Bias Voltage Current Sense Circuits Avalanche Photodiodes," Linear Technology Corporation, Application Note November 2002, Williams, Albert, "Simple Circuitry Cellular Telephone/Camera Flash Illumination," Linear Technology Corporation, Application Note March 2004. Williams, Jim, "Basic Flashlamp Illumination Circuitry Cellular Telephones/Cameras," Linear Technology Corporation, Design Note 345, September 2004. Williams, Jim, "Switching Regulators Poets," Appendix Linear Technology Corporation, Application Note September 1987. Williams, Jim, "Step Down Switching Regulators," Linear Technology Corporation, Application Note August 1989, 11-13. Williams, Jim, "Applications Precision Amps," Linear Technology Corporation, Application Note January 1985, 1-2, 6-7. Williams, Jim, "Measurement Control Circuit Collection," Linear Technology Corporation, Application Note June 1991. Markell, Editor, "Linear Technology Magazine Circuit Collection, Volume Linear Technology Corporation, Application Note January 1993. Williams, Jim, "Practical Circuitry Measurement Control Problems," Linear Technology Corporation, Application Note August 1994. Markell, Editor, Linear Technology Magazine Circuit Collection, Volume II," Linear Technology Corporation, Application Note August 1996. Markell, Editor, Linear Technology Magazine Circuit Collection, Volume III," Linear Technology Corporation, Application Note September 1996. Williams, Jim, "Circuitry Signal Conditioning Power Conversion," Linear Technology Corporation, Application Note March 1999. Williams, Jim, "Component Measurement Advances Ensure 16-Bit Settling Time," Linear Technology Corporation, Application Note July 1998. Williams, Jim, Nanosecond Settling Time Measurement Precision Wideband Amplifier," Linear Technology Corporation, Application Note September 1999. Hickman, Hunt, Electronic Voltage Stabilizers," "Cascode," Review Scientific Instruments, January 1939, 6-21, Seebeck, Thomas Dr., "Magnetische Polarisation Metalle Erze durch Temperatur-Differenz," Abhaandlungen Preussischen Akademic Wissenschaften, 1822-1823, 265-373. Williams, Huffman, "Some Thoughts DC-DC Converters," Linear Technology Corporation, Application Note October 1988. Meade, "Lock-In Amplifiers Applications," London, Peregrinus, Ltd. Williams, "Designs High Performance Voltageto-Frequency Converters," Linear Technology Corporation, Application Note March 1986.
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AN98-25
Application Note
APPENDIX Much Bandwidth Enough? Accurate wideband oscilloscope measurements require bandwidth. good question just much needed. classic guideline that "end-to-end" measurement system rise time equal root-sum-square system's individual component's rise times. simplest case components; signal source oscilloscope. Figure A1's plot signal2 oscilloscope2 rise time versus error illuminating. figure plots signalto-oscilloscope rise time ratio versus observed rise time (rise time bandwidth restated time domain, where: curve shows that oscilloscope times faster than input signal rise time required measurement accuracy inside about This trying measure rise time pulse with 350MHz oscilloscope (tRISE 1ns) leads erroneous conclusions. curve indicates monstrous error. Note that this curve does include effects passive probes cables connecting signal oscilloscope. Probes necessarily follow root-sum-square must carefully chosen applied given measurement. details, Appendix Figure included reference, gives cardinal points rise time/bandwidth equivalency between 1MHz 5GHz.
RISE TIME 70ps
OBSERVED RISE TIME ERROR PERCENT
RiseTime (nanoseconds)
Bandwidth (MHz)
BANDWIDTH 5GHz 1GHz 500MHz 350MHz 150MHz 100MHz 50MHz 10MHz 5MHz 1MHz
350ps 700ps
41.00%
2.33ns 3.5ns 35ns 70ns 350ns
11.70% 2.80% 1.00% 1.37% 2.00% SIGNAL-TO-OSCILLOSCOPE RISE TIME RATIO
AN98 FA01
5.40%
Figure Some Cardinal Points Rise Time/Bandwidth Equivalency. Data Based Rise Time/Bandwidth Formula Text
Figure Oscilloscope Rise Time Effect Rise Time Measurement Accuracy. Measurement Error Rises Rapidly Signal-to-Oscilloscope Rise Time Ratio Approaches Unity. Data, Based Root-Sum-Square Relationship, Does Include Probe, Which Does Follow Root-Sum-Square
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AN98-26
Application Note
APPENDIX Connections, Cables, Adapters, Attenuators, Probes Picoseconds Subnanosecond rise time signal paths must considered transmission lines. Connections, cables, adapters, attenuators probes represent discontinuities this transmission line, deleteriously effecting ability faithfully transmit desired signal. degree signal corruption contributed given element varies with deviation from transmission lines nominal impedance. practical result such introduced aberrations degradation pulse rise time, fidelity, both. Accordingly, introduction elements connections signal path should minimized necessary connections elements must high grade components. form connector, cable, attenuator probe must fully specified high frequency use. Familiar hardware becomes lossy rise times much faster than 350ps. components preferred rise times described text. Additionally, cable should "hard line" least, teflon-based coaxial cable fully specified high frequency operation. Optimal connection practice eliminates cable coupling signal output directly measurement input. Mixing signal path hardware types adapters (e.g. BNC/ SMA) should avoided. Adapters introduce significant parasitics, resulting reflections, rise time degradation, resonances other degrading behavior. Similarly, oscilloscope connections should made directly instrument's inputs, avoiding probes. probes must used, their introduction signal path mandates attention their connection mechanism high frequency compensation. Passive "Z0" types, commercially available (10x) 5k(100x) impedances, have input capacitance below 1pf. such probe must carefully frequency compensated before misrepresented measurement will result. Inserting probe into signal path necessitates some form signal pick-off which nominally does influence signal transmission. practice, some amount disturbance must tolerated effect measurement results evaluated. High quality signal pick-offs always specify insertion loss, corruption factors probe output scale factor. preceding emphasizes vigilance designing maintaining signal path. Skepticism, tempered enlightenment, useful tool when constructing signal path amount hope effective preparation directed experimentation.
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Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
AN98-27
Application Note
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AN98-28
Linear Technology Corporation
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(408) 432-1900
LT/TP 1104 PRINTED
FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2004

Circuits Fall, 2004 Williams Introduction Occasionally, tasked with de

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