Data Sheet High-Performance DrMOS 0.8mm IQFN TDA21211- Data
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Jens Ejury July 2006 Jose,
Data Sheet High-Performance DrMOS
0.8mm IQFN
TDA21211- Data Sheet August 2009
Published Infineon Technologies http://www.infineon.com/DCDC
Power Management Drive
Data Sheet
Page
TDA21211
High-Performance DrMOS Features:
Intel compliant DrMOS, Power MOSFET Driver package Synchronous Buck step down voltage applications Maximum Average Current Wide input voltage range +30V power dissipation Extremely fast switching technology improved performance high switching frequencies (>1MHz) Remote Driver Disable function Switching Modulation (SMOD#) side Includes active PMOS structure integrated bootstrap circuit reduced part count Shoot through protection High Side Driving voltage Compatible standard controller with +3.3 logic Three-State input functionality Small Package: IQFN40 mm3) RoHS Compliant TDA21211 Type Package 6x6x0.8mm3 PG-IQFN-40-1 Marking TDA21211
Applications:
Desktop Server VR11.X VR12 Vcore non-Vcore buckconverters Network Telecom processor Single Phase MultiPhase CPU/GPU Regulation Notebook, Graphics Cards, Gaming Voltage Modules requiring high power density Memory (DDR2/3)
Data Sheet
Page
TDA21211
Pinout
PHASE CGND VDRV BOOT VCIN SMOD# VSWH PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND VSWH VSWH DISB# CGND VSWH VSWH VSWH VSWH VSWH
CGND
Note: Signals marked with active signals.
VSWH
Figure Pinout, numbering name pins (Transparent View)
Description
Name
CGND SMOD# VCIN VDRV BOOT PHASE VSWH PGND DISB#
37,CGND VSWH
Description
Control signal ground side gate disable Logic supply voltage gate supply voltage Bootstrap voltage High side gate signal Switch node output connect Input Voltage Switch node output Power ground side gate signal Disable Signal (active low) drive logic input
Remarks
Should connected PGND externally when SMOD# "low" bias voltage internal logic. High Side gate drive Connect boot capacitor monitoring gate Internally connected VSWH connected potential connection drain high current output switch node these pins must connected power plane through multiple, inductance vias. monitoring gate pull disable three-state input compatible with 3.3V logic
Data Sheet
Page
TDA21211
General Description
Infineon TDA21211 multichip module that incorporates Infineon's premier MOSFET technology single high side single side MOSFET coupled with robust, high performance, high switching frequency gate driver single package. optimized gate timing allows significant light load efficiency improvements over discrete solutions. State MOSFET technology provides exceptional full load performance. Thus this device clear advantage over exisiting approaches marketplace when both full load light load efficiencies important. Driver+MOSFET TDA21211 (DrMOS) compatible compliant with Intel DrMOS specification. device package height only 0.8mm, excellent choice applications with critical height limitations.
BLOCK DIAGRAM
VCIN PHASE BOOT
VDRV
Driver UVLO Level Shifter
500k
DISB#
500k
Logic
Shoot Through Protection
CGND VCIN
VSWH
Input Logic 3-State Logic
VDRV
CGND VCIN
400k
SMOD#
600K CGND
Driver
500k
DRIVER
PGND
CGND
VDRV
Figure Simplified block diagram
Data Sheet
Page
TDA21211
Electrical Specification Table
Absolute Maximum Ratings 25°C)
Item Frequency Average output current Input voltage Supply voltage High side driver voltage Switch node voltage BOOT voltage SMOD# voltage DISB# voltage voltage
Symbol Iout (DC) VCIN (DC) VDRV (DC) VSWH (DC) VBOOT-PHASE (DC) VSMOD# (DC) VDISB Vpwm Tj-opr Tstg
Rating -0.3 -0.3 +5.5 -0.3 +5.5 +5.5 -0.3 +5.5 -0.3 +5.5 -0.3 +5.5 +150 +150
Units
Operating junction temperature Storage temperature
Note: rated voltages relative voltages CGND PGND pins unless otherwise specified.
Latch class Level (Jedec 78). Please refer Quality Report details.
Thermal Characteristics
Parameter Thermal resistance, junction-soldering point Thermal resistance, junction-top package Symbol Min. Jtop Values Typ. Max. Unit
junction-soldering point referred VSWH bottom exposed pad.
Data Sheet
Page
TDA21211
Recommended Operating Conditions Electrical Characteristics (VCIN 25°C)
Parameter
Input Voltage Driving Voltage Bias Supply Voltage UVLO Rising UVLO Falling Driver Current
Symbol
VDRV VCIN VUVLO_R VUVLO_F
Units
Test Conditions
VCIN rising VCIN falling
IVDRV_300kHz IVDRV_PWML IVCIN_PWML IVCIN_O
DISB# 300kHz DISB# DISB# SMOD# Open DISB# Open SMOD# Open DISB#
Current (Control) quiescent Logic Inputs Thresholds
DISB#
ICIN+IDRV VDISB_L VDISB_H IDISB VSMOD#_L VSMOD#_H VSMOD#_O ISMOD# VPWM_L VPWM_H RIN-PWM VPWM_O VPWM_S
Input Input high Sink Current Input Input high Open Voltage Sink Current Input Input high
VDISB falling VDISB rising VDISB VSMOD# falling VSMOD# rising VSMOD# VPWM falling VPWM rising VPWM VPWM_O
SMOD#
12.5
Input resistance Open Voltage Tri-state Shutdown Window
Dynamic Characteristic Three State GL/GH rising propagation delay GL/GH Three State Shutdown Hold-Off time, Turn-on propagation delay Turn-off propagation delay Turn-on propagation delay Turn-off propagation delay DISB#Turn-off propogation delay falling DISB#Turn-on propogation delay rising
T_pts T_tsshd T_pdhu T_pdlu T_pdhl T_pdll T_pdl_DISB T_pdh_DISB
unloaded.
Unless otherwise specified, VCIN=VDRV
Data Sheet
Page
TDA21211
Typical Application
VCIN
VIN_SEN
BOOT VCIN VDRV PHASE VSWH
Cboot Rboot
21211
CGND PGND
PX3560 PWM1
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI# OUTEN VR_READY FAULT1 FAULT2 FAULT3
SEN1N PWM1 SEN1P ISEN1N
Cboot
Rboot
ISEN1P PWM2 ISEN2N ISEN2P
PWM2 SEN2N SEN2P
BOOT VCIN VDRV PHASE VSWH
21211
CGND PGND
PWM3
ISEN3N ISEN3P PWM4 ISEN4N ISEN4P
Cboot Rboot
BOOT VCIN VDRV
PHASE VSWH
21211
CGND PGND
PWM5 PWM3 ISEN5N SEN3N
SEN3P ISEN5P
Cboot
Rboot
PWM6 ISEN6N
BOOT VCIN VDRV PHASE VSWH
SADDR_M SADDR_L
ISEN6P
PWM4
21211
CGND PGND
VD25
SEN4N
SEN4P VSENP VSENN
VOUT COUT
VSENP
VSENN
Figure Four Phases Voltage Regulator Typical Application (Simplified Schematic) Data Sheet Page TDA21211
Theory Operation
TDA21211 incorporates high performance gate driver, high side power MOSFET low-side power MOSFET single lead package. advantages this arrangement found areas increased performance, increased efficiency lower overall package layout inductance.This module ideal Synchronous Buck Regulators either stand-alone power stage that deliver with interleaved approach higher current loads. power MOSFETs tailored this device. gate driver extremely robust high-performance driver rated switching node voltages ranging from +30V. closely coupled driver MOSFETs enable efficiency improvements that hard match using discrete components. power density transmitted power this approach approximately within 36mm2 area. Driver Characteristics gate driver TDA21211 voltage inputs, VCIN VDRV. VCIN bias supply driver. VDRV also used drive High Side MOSFETs. Ceramic capacitors should placed very close these input voltage pins decouple sensitive control circuitry from noisy environment. MOSFETs selected this application optimized gate drive, thus giving user optimized high load well light load efficiency. reference power circuitry including driver output stage PGND reference gate driver control circuit (VCIN) CGND. Referring Block Diagram, Figure VCIN internally connected UVLO circuit VCIN voltages less than required proper circuit operation will provide shut-down. VDRV supplies both, floating high side drive low-side drive circuits. active boot circuit high side gate drive also included. second UVLO circuitry, sensing BOOT voltage level, implemented prevent false turn during insufficient power supply level condition (BOOT charging/discharging sequence). During undervoltage both driven actively; further passive pull down (500k Ohm) placed each gate. Note: output signal from UVLO unit.
UVLO Output Logic Level
Shutdown Enable
VUVLO_F
VUVLO_R
VCIN
Data Sheet
Page
TDA21211
Inputs internal control circuit PWM, DISB# SMOD#: control input from external controller compatible with 3.3V logic. input three-state functionality. When voltage remains specified PWM-shutdown-window least PWM-shutdown-holdoff time T_tsshd, operation will suspended keeping both MOSFET gate outputs low. Once left open, internally fixed VPWM_O level
Open
Driver Output GL=H, GL=L, GL=L,
DISB# active signal. When DISB# pulled low, power stage disabled.
DISB# Open
Driver Output Shutdown Enable Shutdown "Active"
SMOD# feature provided disable low-side MOSFET during active operation. When synchronized with signal shown Figure SMOD# intended improve light load efficiency saving gate charge loss low-side MOSFET. Once left open, internally fixed VSMOD#_O level.
SMOD# Open
Status Enable Enable "Active" "Active"
TDA21211 driver includes gate drive functionality protect against shoot through. order protect power stage from overlap, both MOSFETs being same time, adaptive control circuitry monitors voltage "VSWH" pin. When signal goes low, High-side MOSFET will begin turn off, after propagation delay (T_pdlu). Once "VSWH" falls below Low-side MOSFET gated after predefined delay time, (T_pdhl). Additionally, gate source voltage HS-MOSFET also monitored. When VGS(HS) discharged below threshold known turn off, secondary delay initiated, (T_pdhl), which results being gated "ON" irregardless state "VSWH" pin.This will ensured that converter sink current efficiently bootstrap capacitor will refreshed appropriately during each switching cycle. Figure more detail. monitoring pins check internal gate drive signals.
Data Sheet
Page
TDA21211
CBOOT
RBOOT
CGND
VCIN
CGND
SMOD BOOT VDRV
4x10u
PHASE
CGND
DISB#
CGND
CGND VSWH
VSWH PGND
VSWH
Signal
Power
VOUT
PGND
Figure interconnection outline (Transparent View) NOTE: RBOOT value related input voltage level. PHASE internally connected VSWH node.
Data Sheet
Page
VSWH
TDA21211
Gate Driver Timing Diagrams
VPWM_H VPWM_H VPWM_L
T_pdll T_tsshd T_pts T_pdhl Three State
VPWM_L
T_tsshd T_pdlu T_pts T_pdhu
VSWH
Note: VSWH during entering/exit tristate behaves accordingly inductor current.
Figure Adaptive Gate Driver Timing Diagram
Data Sheet
Page
TDA21211
DISBL#
VDISB_H
VDISB_L
T_pdl(DISB)
T_pdh(DISB)
GH/GL
Figure Disable Timing Diagram
SMOD SMOD disabled
SMOD active
T_pdlu T_pdlu T_pdlu
VSWH
Figure SMOD# Timing Diagram Page
Data Sheet
TDA21211
Test Circuit
VCIN ICIN IDRV CDRV CCIN
VDRV
VDRV
BOOT
CBOOT
PHASE
VCIN DISBL#
TDA21211
VSWH
300n
PGND
VOUT IOUT
PX3560
SMOD# CGND
ISENN ISENP VSENP VSENN
COUT
Figure Test Circuit
Efficiency
POUT
VDRV VCIN POUT VOUT PLOSS POUT
Data Sheet
Page
TDA21211
Performance Curves Typical Data
Operating conditions (unless otherwise specified): VIN= +12V, VCIN=VDRV= +5V, VOUT=1.1 F=362k 300nH inductor (VITEC59P9081N01, (typ) =0.43m TA=25° load line=0m, airflow=100 LFM, heatsink. Power Efficiency Power Loss data reported herein includes TDA21211 inductor losses other system losses (unless otherwise specified).
Efficiency Output Current
1.6V 1.5V 1.2V 1.0V 0.8V
0.8V
Power Loss
1.0V 1.2V 1.5V 1.6V
Output Current
Figure Efficiency VOUT
Figure Power Loss VOUT
Efficiency
296Khz 362Khz 407Khz 465Khz 592Khz
Power Loss
592Khz 465Khz 407Khz 362Khz 296Khz
Output Current
Output Current
Figure Efficiency Switching Frequency
Figure Power Loss Switching Frequency
Data Sheet
Page
TDA21211
Efficiency Output Current
Power Loss
Output Current
Figure Efficiency
Figure Power Loss
105C
105C
Output Current
Power Loss
Efficiency
Output Current
Figure Efficiency TCASE
Figure Power Loss TCASE
Data Sheet
Page
TDA21211
1,20
Vin=12V
Vin=12V
1,15
VCIN=VDRV=5V Vout=1.3V
VCIN=VDRV=5V Vout=1.3V
Power Loss
F=600kHz L=510nH
1,10
Iout=25A L=510nH
1,05
1,00
0,95
0,90
0,85
1000
Output Current Figure Power Loss Iout
(inductor losses included)
Switching Frequency (kHz) Figure Normalized Power Loss Iout=25
(inductor losses included)
Vin=12V
IDRV ICIN (mA)
VCIN=VDRV=5V Vout=1.3V Iout=25A L=510nH
1000
Switching Frequency (kHz) Figure Power Supply Current (IDRV ICIN)
Data Sheet
Page
TDA21211
Package Outline
PIN#1 IDENT
Data Sheet
Page
TDA21211
Figure Footprint Solder Stencil Recommendation
Data Sheet
Page
TDA21211
Layout Example.
Figure Single Phase DrMOS typical Application Circuit
Figure Single Phase DrMOS Layout Example (Top Side View) (for DrMOS Design support customer layout guide available upon request)
Data Sheet
Page
TDA21211
questions technology, delivery prices please contact Infineon Technologies Offices Germany Infineon Technologies Companies Representatives worldwide: address list last page webpage
http://www.infineon.com/DCDC
CoreControlTM, OptiMOSand OptiMOS IIare trademarks Infineon Technologies
listen Your Comments information within this document that feel wrong, unclear missing all? Your feedback will help continously improve quality this document.
Edition 2004-11-10
Published Infineon Technologies St.-Martin-Strasse D-81541
Infineon Technologies 2004. Rights Reserved.
Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
Data Sheet
Page
TDA21211
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