PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 Family Sili
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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 Family Silicon Errata Data Sheet Clarification
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 family devices that have received conform functionally current Device Data Sheet (DS70293B), except anomalies described this document. silicon issues discussed following pages silicon revisions with Device Revision listed Table silicon issues summarized Table errata described this document will addressed future revisions PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 silicon. Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated last column Table apply current silicon revision (A3). example, identify silicon revision level using MPLAB conjunction with MPLAB PICkit3: Using appropriate interface, connect device MPLAB programmer/debugger PICkit From main menu MPLAB IDE, select Configure>Select Device, then select target part number dialog box. Select MPLAB hardware tool (Debugger>Select Tool). Perform "Connect" operation device (Debugger>Connect). Depending development tool used, part number Device Revision value appear Output window. Note: unable extract silicon revision level, please contact your local Microchip sales office assistance.
Data Sheet clarifications corrections start page following discussion silicon issues. silicon revision level identified using current version MPLAB® Microchip's programmers, debuggers emulation tools, which available Microchip corporate site (www.microchip.com).
Device Revision values various PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 silicon revisions shown Table
TABLE
SILICON DEVREV VALUES
Part Number Device ID(1) 0x0645 0x0647 0x0655 0x0657 0x0675 0x0677 0x3001 0x3002 0x3002 Revision Silicon Revision(2)
PIC24HJ32GP302 PIC24HJ32GP304 PIC24HJ64GP202 PIC24HJ64GP204 PIC24HJ64GP502 PIC24HJ64GP504 Note
Device Revision (DEVID DEVREV) located last implemented addresses program memory. Refer "dsPIC33F/PIC24H Flash Programming Specification" (DS70152) detailed information Device Revision your specific device.
2009 Microchip Technology Inc.
DS80441C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
TABLE
SILICON DEVREV VALUES (CONTINUED)
Part Number Device ID(1) 0x0665 0x0667 0x067D 0x067F 0x3001 0x3002 0x3002 Revision Silicon Revision(2)
PIC24HJ128GP202 PIC24HJ128GP204 PIC24HJ128GP502 PIC24HJ128GP504 Note
Device Revision (DEVID DEVREV) located last implemented addresses program memory. Refer "dsPIC33F/PIC24H Flash Programming Specification" (DS70152) detailed information Device Revision your specific device.
TABLE
Module UART UART
SILICON ISSUE SUMMARY
Feature Mode High-Speed Mode Transmit Operation Frame Mode Writes Item Number Issue Summary baud clock signal BCLK present only when module transmitting. When UART mode (BRGH using Stop bits (STSEL sample first Stop instead second one. Transmit Buffer Full (SPITBF) flag does immediately after writing buffer. module will generate incorrect frame synchronization pulses Frame Master mode FRMDLY I2CSTAT only cleared with Word instructions, corrupted with byte instructions operations. When module configured 10-bit addressing using same address bits (A10 other devices, bits work expected. When module configured 10-bit slave with address 0x102, I2CxRCV register content lower address byte 0x01 rather than 0x02. With module enabled, PORT bits external Interrupt Input functions any) associated with pins will reflect actual digital logic levels pins. 10-bit slave does flag load I2CxRCV register, address match Least Significant bits (LSbs) address same 7-bit reserved addresses. After ACKSTAT when receiving NACK, cleared reception Start Stop bit. UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. When UART module operating 8-bit mode (PDSEL using IrDA® encoder/decoder (IREN module incorrectly transmits data payload 00h. Affected Revisions(1)
I2C
10-bit Addressing 10-bit Addressing
10-bit Addressing
UART
Interrupts
UART
Mode
Note
Only those issues indicated last column apply current silicon revision.
DS80441C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
TABLE
Module Comparator
SILICON ISSUE SUMMARY (CONTINUED)
Feature Output Item Number Issue Summary When CMCON<CxOUTEN> set, Comparator output cannot used general purpose even Comparator disabled. When VREGS (RCON<8>) logic device reset higher Sleep current observed. address error trap occurs certain addressing modes when accessing first four bytes page. WAKIF CxINTF register cannot cleared software instruction after device interrupted from Sleep activity bus. ECAN module store received data correct location. EXCH instruction does execute correctly enabled. Writing SPIxBUF register soon cleared will cause module ignore written data. UART module will generate back-to-back Break characters. Affected Revisions(1)
Internal Voltage Regulator Operations ECAN
Sleep Mode
Sleep Mode
ECAN UART
Receive Operation EXCH Instruction Transmit Operation Break Character Generation
Note
Only those issues indicated last column apply current silicon revision.
2009 Microchip Technology Inc.
DS80441C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
Silicon Errata Issues
Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated shaded column following tables apply current silicon revision (A3).
Module:
Transmit Buffer Full (SPITBF) flag does immediately after writing buffer. Work around After write buffer, poll SPITBF flag until flag gets set, indicating that transmit buffer full. Afterwards, poll SPITBF flag again until flag gets cleared, indicating that transmit started that transmit buffer empty another write occur. Affected Silicon Revisions
Module: UART
When UART configured interface operations (UxMODE<9:8> 11), baud clock signal BCLK present only when module transmitting. idle other times. Work around Configure output compare modules generate required baud clock signal when UART receiving data Idle state. Affected Silicon Revisions
Module:
module will generate incorrect frame synchronization pulses when configured Frame Master mode start data selected coincide with start frame synchronization pulse (FRMEN SPIFSD FRMDLY However, module functions correctly Frame Slave mode, also Frame Master mode FRMDLY Work around being used, manually drive high using associated PORT register, then drive after required bit-time pulse-width. This operation needs performed when transmit buffer written. being used, other peripheral modules using transfers, timer interrupt periodically generate frame synchronization pulse (using method described above) after every 16-bit periods (depending data word size, configured using MODE16 bit). FRMDLY work around needed. Affected Silicon Revisions
Module: UART
When UART mode (BRGH using Stop bits (STSEL sample first Stop instead second one. This issue does affect other UART configurations. Work around baud rate option (BRGH adjust baud rate accordingly. Affected Silicon Revisions
DS80441C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
Module:
I2CSTAT only cleared with Word instructions, corrupted with byte instructions operations. Work around Word instructions clear BCL. Affected Silicon Revisions
Module:
With module enabled, PORT bits external interrupt input functions any) associated with pins reflect actual digital logic levels pins. Work around and/or pins need polled, these pins should connected other port pins order read correctly. This issue does affect operation module. Affected Silicon Revisions
Module:
there devices bus, them acting Master receiver other Slave transmitter. both devices configured 10-bit Addressing mode, have same value bits their addresses, then when Slave select address sent from Master, both Master Slave acknowledge When Master sends read operation, both Master Slave enter into Read mode both them transmit data. resultant data will ANDing transmissions. Work around devices, addresses well bits should different. Affected Silicon Revisions
Module:
10-bit Addressing mode, some address matches don't flag load receive register I2CxRCV, lower address byte matches reserved addresses. particular, these include addresses with form XX0000XXXX XX1111XXXX, with following exceptions: 001111000X 011111001X 101111010X 111111011X
Work around Ensure that lower address byte 10-bit Addressing mode does match 7-bit reserved addresses. Affected Silicon Revisions
Module:
When module configured 10-bit slave with address 0x102, I2CxRCV register content lower address byte 0x01 rather than 0x02; however, module acknowledges both address bytes. Work around None. Affected Silicon Revisions
Module:
When module operating either Master Slave mode, after ACKSTAT when receiving NACK, cleared reception Start Stop bit. Work around Store value ACKSTAT immediately after receiving NACK. Affected Silicon Revisions
2009 Microchip Technology Inc.
DS80441C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
Module: UART
UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. Work around Read error flags UxSTA register whenever byte received verify error status. most cases, these bits will correct, even UART error interrupt fails occur. Affected Silicon Revisions
Module: Internal Voltage Regulator
When VREGS (RCON<8>) logic device reset higher Sleep current observed. Work around Ensure VREGS (RCON<8>) logic device Sleep mode operation. Affected Silicon Revisions
Module: Operations
address error trap occurs certain addressing modes when accessing first four bytes page. This only occurs when using following addressing modes: MOV.D Register Indirect Addressing (Word Byte mode) with pre/post-decrement Work around perform accesses first four bytes using above addressing modes. applications using language, MPLAB version 3.11 higher, provides following command-line switch that implements work around erratum. -merrata=psv_trap Refer readme.txt file MPLAB v3.11 tool suite further details. Affected Silicon Revisions
Module: UART
When UART operating 8-bit mode (PDSEL using IrDA encoder/decoder (IREN module incorrectly transmits data payload 00h. Work around None. Affected Silicon Revisions
Module: Comparator
CMCON<CxOUTEN> comparator module CMCON<CxEN> disabled, remappable comparator output pins, C1OUT C2OUT, cannot used general purpose pins. Work around When comparator module disabled CMCON<CxOUTEN> should reset that remappable comparator output pins C1OUT C2OUT driven onto output pad. Affected Silicon Revisions
DS80441C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
Module: ECAN
WAKIF CxINTF register cannot cleared software instruction after device interrupted from Sleep activity bus. When device wakes from Sleep activity, ECAN module placed operational mode. ECAN Event interrupt occurs WAKIF flag. Trying clear flag Interrupt Service Routine (ISR) clear flag. WAKIF being will cause repetitive Interrupt Service Routine execution. Work around Although WAKIF does clear, device Sleep ECAN Wake function continue work expected. ECAN event enabled, will enter Interrupt Service Routine WAKIF flag getting set. application maintain secondary flag, which tracks device Sleep Wake events. Affected Silicon Revisions
still clear RXFUL flags other interrupt flags. application must manage buffer memory. Affected Silicon Revisions
Module:
EXCH instruction does execute correctly enabled. Work around writing source code assembly, recommended work around replace: EXCH Wsource, Wdestination with: PUSH Wdestination Wsource, Wdestination Wsource using MPLAB compiler, specify compiler option: -merrata=exch (Project Build Options Projects MPLAB Alternate Settings). Affected Silicon Revisions
Module: ECAN
ECAN module store received data correct location. When this occurs, receive buffers will become corrupted. addition, also possible transmit buffers become corrupted. This issue more likely occur speed approaches Mbps. Work around with ECAN Peripheral Indirect mode. Register Indirect mode, Continuous mode enabled Ping Pong mode disabled. receive channel count should words. transmit channel count should actual message size (maximum words Extended messages words Standard Messages). simplify application error handling while using this mode, only buffer should used. While message filtering affected, messages will stored distinct buffers. Instead messages stored contiguously memory. start this memory pointed receive channel. application must
Module:
Writing SPIxBUF register soon cleared will cause module ignore written data applications which with will affected this erratum. Work around After cleared, wait minimum duration clock before writing SPIxBUF register. Alternatively, following: Poll wait before writing SPIxBUF register. Poll Interrupt flag wait before writing SPIxBUF register. Interrupt Service Routine. DMA.
Affected Silicon Revisions
2009 Microchip Technology Inc.
DS80441C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
Module: UART
UART module will generate consecutive break characters. Trying perform back-toback Break character transmission will cause UART module transmit dummy character used generate first Break character instead transmitting second Break character. Break characters generated correctly they followed non-Break character transmission. Work around None. Affected Silicon Revisions
DS80441C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
Data Sheet Clarifications
following typographic corrections clarifications noted latest version device data sheet (DS70293B): Note: Corrections shown bold. Where possible, original bold text formatting been removed clarity.
data sheet clarifications this time.
2009 Microchip Technology Inc.
DS80441C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
APPENDIX
REVISION HISTORY
Document (3/2009) Initial release this document; issued revision silicon. Includes silicon issues (UART), (UART), (SPI), (I2C), (UART), (UART), (Comparator), (Internal Voltage Regulator), (PSV Operations), 1617 (ECAN), (CPU) (SPI). This document replaces following errata document: DS80373, "PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/ Rev. A1/A2/A3 Silicon Errata" Document (4/2009) Corrected part numbers. Document (8/2009) Added silicon issue (UART).
DS80441C-page
2009 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
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2009 Microchip Technology Inc.
DS80441C-page
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03/26/09
DS80441C-page
2009 Microchip Technology Inc.
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