PIC32MX3XX/4XX Family Silicon Errata Data Sheet Clarification PIC

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PIC32MX3XX/4XX Family Silicon Errata Data Sheet Clarification PIC

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PIC32MX3XX/4XX
PIC32MX3XX/4XX Family Silicon Errata Data Sheet Clarification
PIC32MX3XX/4XX family devices that have received conform functionally current Device Data Sheet (DS61143E), except anomalies described this document. silicon issues discussed following pages silicon revisions with Device Revision listed Table silicon issues summarized Table errata described this document will addressed future revisions PIC32MX3XX/4XX silicon. Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated last column Table apply current silicon revision (B4). example, identify silicon revision level using MPLAB conjunction with REAL ICEin-circuit emulator: Using appropriate interface, connect device REAL ICEin-circuit emulator. From main menu MPLAB IDE, select Configure>Select Device, then select target part number dialog box. Select MPLAB hardware tool (Debugger>Select Tool). Perform "Connect" operation device (Debugger>Connect). Depending development tool used, part number Device Revision value appear Output window. Note: unable extract silicon revision level, please contact your local Microchip sales office assistance.
Data Sheet clarifications corrections start page following discussion silicon issues. silicon revision level identified using current version MPLAB® Microchip's programmers, debuggers, emulation tools, which available Microchip corporate site (www.microchip.com).
Device Revision values various PIC32MX3XX/4XX silicon revisions shown Table
TABLE
SILICON DEVREV VALUES
Part Number Device ID(1) 0x0938053 0x0934053 0x092D053 0x092A053 0x0916053 0x0912053 0x090D053 0x090A053 0x0906053 0x0902053 0x0978053 0x0974053 0x096D053 Revision Silicon Revision(1)
PIC32MX360F512L PIC32MX360F256L PIC32MX340F128L PIC32MX320F128L PIC32MX340F512H PIC32MX340F256H PIC32MX340F128H PIC32MX320F128H PIC32MX320F064H PIC32MX320F032H PIC32MX460F512L PIC32MX460F256L PIC32MX440F128L Note
Refer "PIC32MX Flash Programming Specification" (DS61145) detailed information Device Revision your specific device.
2009 Microchip Technology Inc.
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TABLE SILICON DEVREV VALUES (CONTINUED)
Part Number PIC32MX440F256H PIC32MX440F512H PIC32MX440F128H PIC32MX420F032H Note Device
Revision Silicon Revision(1)
0x0952053 0x0956053 0x094D053 0x0942053
Refer "PIC32MX Flash Programming Specification" (DS61145) detailed information Device Revision your specific device.
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PIC32MX3XX/4XX
TABLE
Module
SILICON ISSUE SUMMARY
Feature Item Number Issue Summary Affected Revisions(1)
Device Reset Device Reset
MCLR
Reset (MCLR) Pulse that shorter than SYSCLK will reset device properly. Resets, except Power-on Reset (POR), cause FailSafe Clock Monitor event enabled) when duration Reset pulse exceeds clock period internal fail-safe clock reference clock kHz). Attempting perform software device Reset with PBDIV 1:1, SYSCLK less than will reset device properly. VDDCORE voltage less than 1.75V will cause reset when using external core voltage supply. When running Analog-to-Digital Converter (ADC) module Internal Reference mode, gain error offset error across voltage speed. BMXDUDBA, BMXDUPBA, BMXPUPBA registers values that outside device's actual memory size limit. After clock failure event, write OSCCON register erroneously clears fail-safe condition attempts switch clock source that specified NOSC bits OSCCON register. Pattern Match mode, will generate three additional byte writes destination address, after Pattern Detection event occurred when performing transfers with DCHxSSIZ greater than output compare module mode outputs high period register (PRx) length when attempting values 0x00 followed 0x01. Slave Buffer mode, underflow Status (PMSTAT<6>) cleared same time read attempted, could receive incorrect data. When using hardware assisted read-modify-write registers, PORTxINV, PORTxSET, PORTxCLR, source used operation LATx register, PORTx register. TMRx register stays zero timer clock cycles when register 0x0000. timer prescaler reset correctly when used with slow external clock. Timer1 prescaler reset correctly when used with slow external clock. does deassert until least bytes free UART FIFO. incorrect time-out Reset occur.
Device Reset External Voltage Regulator
Software Reset
Gain Offset Errors Configuration
Matrix Oscillator
Clock Fail Detect
Pattern Match Mode
Output Compare
Mode
Slave Mode
PORTs
Timers Timers Timers UART
Asynchronous Mode Hardware Handshake Mode
Watchdog Timer (WDT) Note
Only those issues indicated last column apply current silicon revision.
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TABLE
Module Oscillator
SILICON ISSUE SUMMARY (CONTINUED)
Feature Channel Abort Operating Condition Item Number Issue Summary channel abort channel that currently active have unintended effects other active channels. Primary Oscillator Circuit (POSC), when using XTPLL, HSPLL modes, does operate over voltage temperature range that listed item device data sheet. WAITE field PMMODE<1:0> does Wait state master reads when programmed value `01'. Using values cause Start shortened. 16-bit transfers from ICAP module FIFO buffer advance ICAP FIFO pointer. module does correctly switch from full-speed low-speed after sending packet hub. buffer erroneously filled with last data read prior breakpoint. Events missed PMDIN register used source used trigger. When 16-bit mode, upper bits 32-bit ICxBUF register contain Timer3 values. When programming PIC32 using 2-wire pins, programming data appears output JTAG pin. BRGH mode, received data sampled middle bit. clock signal present CLKO regardless clock source setting CLOCKOUT Configuration under certain conditions. Enabling primary programming/debug port (PGC1/PGD1) lead variants disables external internal references ADC, making unusable. Firmware clock switch requests switch from mode after FSCM event fail. plus minus pins tolerant. single-ended comparator used detect transitions voltage higher than specification. Predictive Prefetch Cache Enable bits (PREFEN<1:0>) CHECON register non-zero, improper processor behavior occur during rare boundary condition. registers must written immediately after programming operation complete. When operation, current channel shorted VREF during conversion period TAD) after sampling. Affected Revisions(1)
UART Input Capture Input Capture ICSPTM
Wait States Baud Rate Generator 16-bit Mode with Speed Switch Breakpoints Read Programming
UART Oscillator
High-Speed Mode Clock
Oscillator Prefetch Cache Flash Program Memory Note
Clock Switch Tolerance Transition Detection
Programming Operation Signal Source
Only those issues indicated last column apply current silicon revision.
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2009 Microchip Technology Inc.
PIC32MX3XX/4XX
Silicon Errata Issues
Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated shaded column following tables apply current silicon revision (B4).
Module: External Voltage Regulator
VDDCORE voltage less than 1.75V will cause reset when using external core voltage supply. Work arounds Work around internal voltage regulator. Work around external 1.8V regulator, which regulation specification 2.5%. Microchip TC1055-1.8VCT713 Drop-Out (LDO) regulator, equivalent, recommended. Affected Silicon Revisions
Module: Device Reset
Reset (MCLR) Pulse that shorter than SYSCLK will reset device properly. Work around Ensure that device held Reset more than SYSCLK ensure proper device Reset operation. Affected Silicon Revisions
Module:
When running Analog-to-Digital Converter (ADC) module Internal Reference mode, gain error offset error across voltage speed. Work around in-system calibration software techniques compensate these errors. Affected Silicon Revisions
Module: Device Reset
Resets, except Power-on Reset (POR), cause Fail-Safe Clock Monitor event enabled) when duration Reset pulse exceeds clock period internal fail-safe clock reference clock kHz). Work around long Reset pulses anticipated, ignore disable Fail-Safe Clock Monitor events. Affected Silicon Revisions
Module: Matrix
BMXDUDBA, BMXDUPBA, BMXPUPBA registers values that outside device's actual memory size limit. Work around write values greater than specified memory size device Matrix registers. Ensure that upper bits registers remain clear (`0'). Affected Silicon Revisions
Module: Device Reset
Attempting perform software device Reset with PBDIV 1:1, SYSCLK less than will reset device properly. Work arounds Work around Change PBDIV before performing software Reset. Work around SYSCLK value that greater than MHz. Affected Silicon Revisions
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Module: Oscillator
After clock failure event, write OSCCON register erroneously clears fail-safe condition attempts switch clock source that specified NOSC bits OSCCON register. Work around After clock failure event, perform following steps: Write `000' NOSC bits OSCCON register select Fast oscillator. This will ensure that erroneous clock switch selects known good on-chip Fast oscillator. Modify OSCCON register with value your application requires. Affected Silicon Revisions
Module: Output Compare
Output Compare module mode outputs high period register (PRx) length when attempting values 0x00 followed 0x01. Work around value 0x01. Affected Silicon Revisions
Module:
Slave Buffer mode, underflow Status (PMSTAT<6>) cleared same time read attempted, could receive incorrect data. Work around read underflow flag OBUF set/clear external master device read. state should indicate external master device that underflow occurred additional reads should occur until underflow status been cleared CPU. Affected Silicon Revisions
Module:
Pattern Match mode, will generate three additional byte writes destination address, after Pattern Detection event occurred when performing transfers with DCHxSSIZ greater than Work arounds Work around destination buffer needs large enough accommodate extra bytes extra bytes). Work around destination size register Work around source size register Affected Silicon Revisions
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Module: PORTs
When using hardware assisted read-modifywrite registers, PORTxINV, PORTxSET, PORTxCLR, source used operation LATx register, PORTx register. This only affects users want pins bidirectional mode store sampled PORTx data LATx register. Work around software read-modify-write sequence, such //replaces PORTAINV mask; PORTA mask; LATA Work around ensure Reset prescaler, firmware must wait least input clock periods before re-enabling timer. Affected Silicon Revisions
Module: Timers
Timer1 prescaler reset correctly when used with slow external clock. This occur when timer disabled then reenabled. result could spurious count prescaler. Work around
//replaces PORTASET mask; PORTA mask; LATA
None. Affected Silicon Revisions
//replaces PORTACLR mask; PORTA ~mask; LATA Note: These sequences atomic. Affected Silicon Revisions
Module: UART
does deassert until least bytes free UART FIFO. Work around UART TXREG must read least times rearm hardware handshaking lines. Affected Silicon Revisions
Module: Timers
TMRx register stays zero timer clock cycles when register 0x0000. Work around None. Affected Silicon Revisions
Module: Watchdog Timer (WDT)
incorrect Time-out Reset occur when both these conditions present: enabled. Either MCLR (EXTR) Software Reset (SWR) occurs just before about expire. Work around detect incorrect Time-out Reset, always confirm that only WDTO RCON register. EXTR, SWR, other Reset bits set, indicates that incorrect occurred. Affected Silicon Revisions
Module: Timers
timer prescaler reset correctly when used with slow external clock. This occur when timer disabled then reenabled. result could spurious count prescaler.
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Module:
channel abort channel that currently active have unintended effects other active channels. Work around Suspend channel, rather than abort, clearing channel enable DCHxCON<CHEN>. Wait until other channels complete before issuing abort. Affected Silicon Revisions
Module:
WAITE field PMMODE<1:0> does Wait state master reads when programmed value `01'. WAITE field allows Wait states added read/write operations. This field intended following Wait clocks after read operation completes: Wait states Wait state Wait states Wait states Current behavior following: Wait states Wait states Wait states Wait states Work around This erratum only applies master read operations. writes work correctly. another Wait state control value that allowed attached device. Affected Silicon Revisions
Module: Oscillator
Primary Oscillator Circuit (POSC), when using XTPLL, HSPLL modes, does operate over voltage temperature range that listed item device data sheet. operation range without work around limited -40°C through +70°C when <3.0V. Work around Install resistor parallel with crystal. This allows operation across temperature range that listed data sheet. Affected Silicon Revisions
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Module: UART
Using values cause Start shortened. This results errors when receiving data. This issue exists BRGH values Work around values Select system peripheral clocks' frequencies such that value desired Baud Rate Generator value greater than Affected Silicon Revisions
Module:
buffer erroneously filled with last data read prior breakpoint. This buffer fill will continue until buffer full. However, buffer fills correctly those same peripherals used destinations, even when goes into Debug Exception mode. This behavior occurs when controller actively transferring data debugger hits breakpoint, causes single-step operation, halts target. Refer Table which lists peripherals input registers that could affect buffer usage.
TABLE
Module: Input Capture
16-bit transfers from ICAP module FIFO buffer advance ICAP FIFO pointer. This results entire output buffer being filled with first value from ICAP FIFO. Work around Configure perform 32-bit transfers from ICAP FIFO. Affected Silicon Revisions
REGISTERS PERIPHERALS AFFECTED BREAKPOINTS DURING TRANSFERS
Transfer from Input Register PORTx SPIxBUF PMDIN UxRXREG ICxBUF
Peripheral Source Change Notice UART Input Capture Work around
Module:
module does correctly switch from full-speed low-speed after sending packet hub. Work around Connect low-speed device directly PIC32. Affected Silicon Revisions
debugger halts during transfer from these registers, either ignore transferred data restart debug session. Affected Silicon Revisions
Module:
Events missed PMDIN register used source used trigger. Work around read operations. used write operations with PMDIN register destination. Affected Silicon Revisions
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Module: Input Capture
When 16-bit mode, upper bits 32-bit ICxBUF register contain Timer3 values. Work around Mask upper bits read value. Example: result 0xFFFF IC1BUF Affected Silicon Revisions
Module: Oscillator
clock signal present CLKO regardless clock source setting CLOCKOUT Configuration under following conditions. During Power-On-Reset (POR). During device programming. After JTAG erase. clock present CLKO until Configuration disable CLOCKOUT programmed. Work around connect CLKO device that would adversely affected rapid toggling frequency other than that defined oscillator configuration. CLKO input device connected CLKO would adversely affected driving signal out. Affected Silicon Revisions
Module: ICSPWhen programming PIC32 using 2-wire pins, programming data appears output JTAG pin. Work around connect device that would adversely affected rapid toggling during programming. Affected Silicon Revisions
Module:
Enabling primary programming/debug port (PGC1/PGD1) 64-lead variants disables external internal references ADC, making unusable. Work around secondary programming/debug port. Affected Silicon Revisions
Module: UART
BRGH mode, received data sampled middle bit. This reduces UART's baud rate mismatch tolerance. Work around BRGH mode. Affected Silicon Revisions
Module: Oscillator
After Fail-Safe Clock Monitor (FSCM) event, clock source will FRC. Firmware clock switch requests switch from mode after FSCM event fail. clock switch does fail, subsequent retries firmware will also fail clock source will FRC. Work around None. Affected Silicon Revisions
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Module:
plus minus pins tolerant. During normal operation these pins subject tolerance specification intended prevent device damage abnormal operation mode such connecting shorted cable device. Work around subject plus minus Affected Silicon Revisions
Module: Flash Program Memory
registers must written immediately after programming operation complete. When operation completes, NVMWR (NVMCON<15>) switches states from `0', indicating that another operation started. However, there period internal clocks after this transition where write NVMCON work correctly. Since internal clock MHz, system clock much faster, care must taken ensure that correct delay met. Work around Wait least after seeing NVMCON<15> before writing registers. Affected Silicon Revisions
Module:
single-ended comparator detecting transitions higher voltage than indicated specification. This compliance issue relating items Peripheral Silicon checklist, which result reduced noise immunity. Work around None. Affected Silicon Revisions
Module:
When operation, current channel shorted VREF during conversion period TAD) after sampling. impact highimpedance sources that they have time recover between conversions. impact low-impedance sources high current draw, which damage either source device. Work around Place resistor between device external capacitance board limit current draw. Affected Silicon Revisions
Module: Prefetch Cache
Predictive Prefetch Cache Enable bits (PREFEN<1:0>) CHECON register nonzero, improper processor behavior occur during rare boundary condition. This condition occurs only when predictive prefetch enabled, occur both cacheable noncacheable memory areas. prefetch buffer overwritten "next" 16-bytes instructions causing invalid instruction execution. This cause invalid instruction fault, execution wrong instruction. Work around Make sure that PREFEN field CHECON programmed `00'. cache still used, although predictive prefetching will disabled. Affected Silicon Revisions
2009 Microchip Technology Inc.
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PIC32MX3XX/4XX
Data Sheet Clarifications
following typographic corrections clarifications noted latest version device data sheet (DS61143E): Note: Corrections shown bold. Where possible, original bold text formatting been removed clarity.
Module: Inputs
Section "USB On-the-Go", Figure 11-6, Figure 11-7, Figure 11-8, incorrectly state numbering inputs Type Macro `B', `A', `AB' Connectors, respectively. input should input should three figures.
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APPENDIX REVISION HISTORY
Document (4/2009) Initial release this document; issued revision silicon. Includes silicon issues (Device Reset), (Device Reset), (Device Reset), (External Voltage Regulator), (ADC), (Bus Matrix), (Oscillator), (DMA), (Output Compare), (PMP), (I/O PORTs), (Timers), (Timers), (Timers), (UART), (Watchdog Timer (WDT)), (DMA), (Oscillator), (PMP), (UART), (Input Capture), (USB), (DMA), (PMP), (Input Capture), (ICSPTM), (UART), (Oscillator), (ADC), (Oscillator), (USB), (USB), (Prefetch Cache), (Flash Program Memory), (ADC). This document replaces these errata documents: DS80350, "PIC32MX3XX/4XX Rev. Silicon Errata" DS80367, "PIC32MX3XX/4XX Rev. Silicon Errata" DS80402, "PIC32MX3XX/4XX Rev. Silicon Errata"
2009 Microchip Technology Inc.
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NOTES:
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2009 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
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PIC32MX3XX/4XX Family Silicon Errata Data Sheet Clarification PIC

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