PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 Rev. A1/A2/
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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 Rev. A1/A2/A3 Silicon Errata
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 (Rev. A1/A2/A3) devices have received were found conform specifications functionality described following documents: DS70293 "PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/ Data Sheet" DS70157 "dsPIC30F/33F Programmer's Reference Manual" exceptions specifications documents listed above described this section. specific devices which these exceptions described listed below: PIC24HJ128GP504 PIC24HJ128GP502 PIC24HJ128GP204 PIC24HJ128GP202 PIC24HJ64GP504 PIC24HJ64GP502 PIC24HJ64GP204 PIC24HJ64GP202 PIC24HJ32GP304 PIC24HJ32GP302
Silicon Errata Summary
following list summarizes errata described further detail remainder this document: UART Module baud clock signal BCLK present only when module transmitting. UART Module When UART mode (BRGH using Stop bits (STSEL sample first Stop instead second one. Module transmit buffer full (SPITBF) flag does immediately after writing buffer. Module Frame Master Mode module will generate incorrect frame synchronization pulses Frame Master mode FRMDLY I2CModule I2CSTAT only cleared with Word instructions, corrupted with byte instructions operations. Module ACKSTAT cleared shortly after being following slave transmit. Module: 10-bit Addressing Mode When module configured 10-bit addressing using same address bits (A10 other devices, bits work expected. Module: 10-bit Addressing Mode When module configured 10-bit slave with address 0x102, I2CxRCV register content lower address byte 0x01 rather than 0x02. Module With module enabled, PORT bits external Interrupt Input functions any) associated with pins will reflect actual digital logic levels pins.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 Rev. A1/A2/A3 silicon identified performing "Reset Connect" operation device using MPLAB® with MPLAB v7.40 later. output window will show successful connection device specified Configure>Select Device. resulting DEVREV register values Rev. A1/A2/A3 silicon 0x3001, 0x3002 0x3003, respectively. errata described this document will addressed future revisions silicon.
2008 Microchip Technology Inc.
DS80373B-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
Module: 10-bit Addressing Mode 10-bit slave does flag load I2CxRCV register, address match Least Significant bits (LSbs) address same 7-bit reserved addresses. UART (UxE Interrupt) UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. UART Module When UART module operating 8-bit mode (PDSEL using IrDA® encoder/ decoder (IREN module incorrectly transmits data payload 00h. Comparator Module When CMCON<CxOUTEN> set, Comparator output cannot used General Purpose pins even Comparator disabled. Internal Voltage Regulator When VREGS (RCON<8>) logic higher sleep current observed. Product Identification Revision devices marked extended temperature range devices, support only industrial temperature range (I). Operations address error trap occurs certain addressing modes when accessing first four bytes page. ECAN Module ECAN module store received data correct location. ECAN Module ECAN module does generate event interrupt when coming Disable mode wake-up activity even WAKIE CiINTE register set. following sections describe errata work around these errata, where they apply.
Module: UART
When UART configured interface operations (UxMODE<9:8> 11), baud clock signal BCLK present only when module transmitting. idle other times. Work around Configure output compare modules generate required baud clock signal when UART receiving data Idle state.
Module: UART
When UART mode (BRGH using Stop bits (STSEL sample first Stop instead second one. This issue does affect other UART configurations. Work around baud rate option (BRGH adjust baud rate accordingly.
Module:
transmit buffer full (SPITBF) flag does immediately after writing buffer. Work around After write buffer, poll SPITBF flag until flag gets set, indicating that transmit buffer full. Afterwards, poll SPITBF flag again until flag gets cleared, indicating that transmit started that transmit buffer empty another write occur.
DS80373B-page
2008 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
Module:
module will generate incorrect frame synchronization pulses when configured Frame Master mode start data selected coincide with start frame synchronization pulse (FRMEN SPIFSD FRMDLY However, module functions correctly Frame Slave mode, also Frame Master mode FRMDLY Work around being used, manually drive high using associated PORT register, then drive after required time pulse-width. This operation needs performed when transmit buffer written. being used, other peripheral modules using transfers, timer interrupt periodically generate frame synchronization pulse (using method described above) after every 16-bit periods (depending data word size, configured using MODE16 bit). FRMDLY work around needed.
Module:
there devices bus, them acting Master receiver other Slave transmitter. both devices configured 10-bit addressing mode, have same value bits their addresses, then when Slave select address sent from Master, both Master Slave acknowledge When Master sends read operation, both Master Slave enter into Read mode both them transmit data. resultant data will ANDing transmissions. Work around devices, addresses well bits should different.
Module:
When module configured 10-bit slave with address 0x102, I2CxRCV register content lower address byte 0x01 rather than 0x02; however, module acknowledges both address bytes. Work around None.
Module:
I2CSTAT only cleared with Word instructions, corrupted with byte instructions operations. Work around Word instructions clear BCL.
Module:
With module enabled, PORT bits external interrupt input functions any) associated with pins reflect actual digital logic levels pins. Work around and/or pins need polled, these pins should connected other port pins order read correctly. This issue does affect operation module.
Module:
During communication, after device operating Slave mode transmits data master, ACKSTAT I2CxSTAT register cleared depending whether master sent NACK after byte data. ACKSTAT set, will cleared again after some delay. Work around Store value ACKSTAT immediately after interrupt occurs.
Module:
10-bit Addressing mode, some address matches don't flag load receive register I2CxRCV, lower address byte matches reserved addresses. particular, these include addresses with form XX0000XXXX XX1111XXXX, with following exceptions: 001111000X 011111001X 101111010X 111111011X
Work around Ensure that lower address byte 10-bit Addressing mode does match 7-bit reserved addresses.
2008 Microchip Technology Inc.
DS80373B-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
Module: UART (UxE Interrupt)
UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. Work around Read error flags UxSTA register whenever byte received verify error status. most cases, these bits will correct, even UART error interrupt fails occur.
Module: Operations
address error trap occurs certain addressing modes when accessing first four bytes page. This only occurs when using following addressing modes: MOV.D Register indirect addressing (word byte mode) with pre/post-decrement Work around perform accesses first four bytes using above addressing modes. applications using language, MPLAB version 3.11 higher, provides following command-line switch that implements work around erratum. -merrata=psv_trap Refer readme.txt file MPLAB v3.11 tool suite further details.
Module: UART (IrDA)
When UART operating 8-bit mode (PDSEL using IrDA encoder/decoder (IREN module incorrectly transmits data payload 00h. Work around None.
Module: Comparator
CMCON<CxOUTEN> Comparator module CMCON<CxEN> disabled, remappable comparator output pins, C1OUT C2OUT, cannot used General Purpose pins. Work around When Comparator module disabled CMCON<CxOUTEN> should reset that remappable comparator output pins C1OUT C2OUT driven onto output pad.
Module: ECAN
ECAN module store received data correct location. When this occurs, receive buffers will become corrupted. addition, also possible transmit buffers become corrupted. This issue more likely occur speed approaches Mbps. Work around None.
Module: ECAN
ECAN module does generate event interrupt when coming Disable mode wake-up activity even WAKIE CiINTE register set. WAKIF CiINTF register will reflect correct status. event interrupt occurs only device Sleep mode when wake-up activity occurred. Work around When placing ECAN module Disable mode, place device Sleep mode able generate event interrupt wake-up activity. possible place device Sleep mode, poll WAKIF CiINTF register track wake-up activity.
Module: Internal Voltage Regulator
When VREGS (RCON<8>) logic `0', higher sleep current observed. Work around Ensure VREGS (RCON<8>) logic device Sleep mode operation.
Module: Product Identification
Revision devices marked extended temperature range devices, support only industrial temperature range (I). Work around Revision devices marked extended temperature range devices.
DS80373B-page
2008 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
APPENDIX
Revision (3/2008)
REVISION HISTORY
This initial release this document. Revision (9/2008) Added reference silicon revisions Added silicon issues 8-10 (I2C), (UART (UxE Interrupt)), (UART (IrDA)), (Comparator), (Internal Voltage Regulator), (Product Identification), (PSV Operations) 17-18 (ECAN).
2008 Microchip Technology Inc.
DS80373B-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04
NOTES:
DS80373B-page
2008 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
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Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2008 Microchip Technology Inc.
DS80373B-page
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DS80373B-page
2008 Microchip Technology Inc.
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