PIC24FJ256GB110 Family Silicon Errata Data Sheet Clarification PI

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PIC24FJ256GB110 Family Silicon Errata Data Sheet Clarification PI

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PIC24FJ256GB110 FAMILY
PIC24FJ256GB110 Family Silicon Errata Data Sheet Clarification
PIC24FJ256GB110 family devices that have received conform functionally current Device Data Sheet (DS39897B), except anomalies described this document. silicon issues discussed following pages silicon revisions with Device Revision listed Table silicon issues summarized Table errata described this document will addressed future revisions PIC24FJ256GB110 family silicon. Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated last column Table apply current silicon revision (A5). example, identify silicon revision level using MPLAB conjunction with MPLAB PICkit3: Using appropriate interface, connect device MPLAB programmer/debugger PICkit From main menu MPLAB IDE, select Configure>Select Device, then select target part number dialog box. Select MPLAB hardware tool (Debugger>Select Tool). Perform "Connect" operation device (Debugger>Connect). Depending development tool used, part number Device Revision value appear Output window. Note: unable extract silicon revision level, please contact your local Microchip sales office assistance.
Data Sheet Clarifications corrections start page following discussion silicon issues. silicon revision level identified using current version MPLAB® Microchip's programmers, debuggers emulation tools, which available Microchip corporate site (www.microchip.com).
DEVREV values various PIC24FJ256GB110 family silicon revisions shown Table
TABLE
SILICON DEVREV VALUES
Revision Silicon Revision(2) PIC24FJ128GB108 PIC24FJ64GB108 PIC24FJ256GB106 PIC24FJ192GB106 PIC24FJ128GB106 PIC24FJ64GB106 100Bh 1003h 1019h 1011h 1009h 1001h Revision Silicon Revision(2)
Part Number
Device ID(1)
Part Number
Device ID(1)
PIC24FJ256GB110 PIC24FJ192GB110 PIC24FJ128GB110 PIC24FJ64GB110 PIC24FJ256GB108 PIC24FJ192GB108 Note
101Fh 1017h 100Fh 1007h 101Bh 1013h
Device (DEVID DEVREV) located last implemented addresses configuration memory space. They shown hexadecimal format, "DEVID DEVREV". Refer "PIC24FJXXXGA0XX Flash Programming Specification" (DS39768) detailed information Device Revision your specific device.
2009 Microchip Technology Inc.
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TABLE
Module Core Core JTAG UART CTMU UART UART UART UART UART I2CI2C Memory ICSPCore RTCC Core CTMU Oscillator Note
SILICON ISSUE SUMMARY
Feature Operation Device Programming PORTB Master mode VUSB Regulator UERIF Interrupt FIFO Error IrDA® IrDA IrDA Master mode Slave mode Instruction Enhanced Buffer mode Enhanced Buffer mode Code-Protect Trigger LPRC Item Number Issue Summary Repeated register operations entering Doze mode Spontaneous with analog peripherals Programming lockout during JTAG programming Framing issues when using Stop bits remains high-impedance Open-Drain mode SPIxIF SPIRBF early some instances Trigger modules work Issue with Host mode, low-speed operation Does regulate 3.3V errors while using external transceiver ACTIVIF flag functions only during Sleep Interrupt function with multiple errors PERR FERR flags incorrect certain cases Payload error 8-bit mode Framing error 9-bit mode Payload errors 8-bit mode Master module Acknowledge transmission slave Module respond correctly reserved addresses False address error traps PGEC3/PGED3 functional Issue with Read-After-Write stalls REPEAT loops Unexpected decrements Alarm Repeat Counter Issue with early full buffer interrupt Disabled voltage references during Debug mode (64-pin devices only) Issue with SRMPT becomes early certain cases disables write access interrupt vectors Automatic conversion function Failure restart following events Affected Revisions(1)
Only those issues indicated last column apply current silicon revision.
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2009 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
Silicon Errata Issues
Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated shaded column following tables apply current silicon revision (A5).
Module: JTAG (Device Programming)
JTAGEN Configuration programmed while using JTAG interface device programming. This cause situation where JTAG programming lock itself being able program device. Work around None. Affected Silicon Revisions
Module: Core (RAM Operation)
read performed instruction immediately prior enabling Doze mode, extra read event occur when Doze mode enabled. This effect most SFRs user space. However, this could cause registers which also perform some action read (such auto-incrementing pointer removing data from FIFO buffer) repeat that action, possibly resulting lost data unexpected operation. Work around Avoid reading registers which perform secondary action (e.g., UART FIFO buffers, RTCVAL registers) immediately prior entering Doze mode. this cannot avoided, execute instruction before entering Doze mode. Affected Silicon Revisions
Module: UART
When UART operating using Stop bits (STSEL sample first Stop instead second one. device being communicated with using Stop communications, this lead framing errors. Work around None. Affected Silicon Revisions
Module: (PORTB)
When configured open-drain output, remains high-impedance state. settings LATB5 TRISB5 have effect pin's state. Work around open-drain operation required, configure regular (ODCB<5> open-drain operation required, there options: Select different open-drain function Place external transistor configure regular Affected Silicon Revisions
Module: Core (BOR)
When on-chip regulator enabled (ENVREG tied VDD), event spontaneously occur under following circumstances: less than 2.5V, either: internal band reference being used reference with Converter (AD1PCFG2<1> comparators (CMxCON<1:0> 11); CTMU module enabled. Work around Limit following activities only those times when on-chip regulator Tracking mode (LVDIF (IFS4<8>) Enabling CTMU modules Selecting internal band reference Converter comparators Affected Silicon Revisions
2009 Microchip Technology Inc.
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Module: (Master Mode)
Master mode, both Interrupt Flag (SPIxIF) SPIRBF (SPIxSTAT<0>) become one-half clock cycle early, instead clock edge. This occurs only under following circumstances: Enhanced Buffer mode disabled (SPIBEN module configured serial data output changes transition from clock active clock Idle state (CKE application using interrupt flag determine when data transmitted written transmit buffer, data currently buffer overwritten. Work around Before writing buffer, check determine last clock edge passed. Example (below) demonstrates method doing this. this example, pin, RD1, functions clock, SCK, which configured Idle low. Affected Silicon Revisions
Module:
While operating Host mode attached low-speed device through full-speed hub, signal generated correctly. This will result being able communicate correctly with low-speed device. Work around Connect low-speed devices directly application through hub. Affected Silicon Revisions
Module: (VUSB Regulator)
internal voltage regulator does regulate 3.3V. internal voltage regulator optional feature required operation compliance. Work around Disable voltage regulator (DISUVREG Configuration `1') supply 3.0V 3.6V from external source VUSB pin. Affected Silicon Revisions
Module: CTMU
When CTMU module selected trigger source (SYNCSEL<4:0> 11000), output compare input capture module triggers work. Work around Manually trigger output compare and/or input capture modules after CTMU event received. certain compensate time latency required manually triggering module. Affected Silicon Revisions
Module:
When module configured external transceiver, CRC5 value some packets incorrect. Work around module's internal transceiver. Affected Silicon Revisions
EXAMPLE
CHECKING STATE SPIxIF AGAINST CLOCK
//wait transmission complete //wait last clock finish //write data buffer
while(IFS0bits.SPI1IF 0){} while(PORTDbits.RD1 1){} SPI1BUF 0xFF;
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2009 Microchip Technology Inc.
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Module:
Activity Interrupt Flag, ACTVIF, active only while device Sleep mode. will become when microcontroller mode. Work around type work around depends type application that microcontroller being used for. Self-Powered Peripherals: After receiving Suspend command from suspend disable module. addition, switch clock configuration that incompatible with operation (refer device data sheet compatible clock settings). Powered Peripherals: After receiving suspend command from (IDLEIF Interrupt Flag Suspend module (U1PWRC<1> Globally enable interrupts (IEC5<6> Specifically enable activity interrupt (U1OTGIE<4> Place microcontroller into Sleep mode soon possible Embedded Host Devices: Issue suspend command peripheral device Suspend module (U1PWRC<1> Globally enable interrupts (IEC5<6> Place microcontroller into Sleep mode soon possible alternate procedure, suspend disable module switch clock configuration that incompatible with operation. Affected Silicon Revisions
Module: UART (UERIF Interrupt)
UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. Work around Read error flags UxSTA register whenever byte received verify error status. most cases, these bits will correct, even UART error interrupt fails occur. possible exceptions, refer Errata Affected Silicon Revisions
Module: UART (FIFO Error Flags)
Under certain circumstances, PERR FERR error bits correct bytes receive FIFO. This only been observed when both following conditions met: UART receive interrupt occur when FIFO full full (UxSTA<7:6> More than bytes with error received these cases, only first bytes with parity framing error will have corresponding bits indicate correctly. error bits will after this. Work around None. Affected Silicon Revisions
Module: UART (IrDA®)
When UART operating 8-bit mode (PDSEL<1:0> using IrDA endec (IREN module incorrectly transmits data payload 00h. Work around None. Affected Silicon Revisions
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Module: UART (IrDA)
When UART operating 8-bit mode (PDSEL<1:0> using IrDA endec (IREN framing error occur when transmitting data payload 00h. Work around: None. Affected Silicon Revisions this cannot avoided: Clear A10M (I2CxCON<10> prior performing Master mode transmit. Read ADD10 (I2CxSTAT<8>) check full 10-bit match whenever slave interrupt occurs master module. Affected Silicon Revisions
Module: Module (Slave Mode) Module: UART (IrDA)
When UART operating 9-bit mode (PDSEL<1:0> using IrDA endec (IREN module will incorrectly transmit bits when transmitting data payloads 80h. Work around: None. Affected Silicon Revisions Under certain circumstances, module operating Slave mode, respond correctly some special addresses reserved protocol. This happens when following occurs: 10-Bit Addressing mode used (A10M Bits, A<7:1>, slave address (I2CADD<7:1>) fall into range reserved 7-bit address ranges: `1111xxx' `0000xxx'. these cases, Slave module Acknowledges command triggers slave interrupt; does copy data into I2CxRCV register bit. Work around bits, A<7:1>, module's slave address equal `1111xxx' `0000xxx'. Affected Silicon Revisions
Module:
I2C
Module (Master Mode)
Under certain circumstances, module operating Master mode Acknowledge command addressed slave device. This happens when following occurs: 10-Bit Addressing mode used (A10M Master same upper address bits (I2CADD<9:8>) addressed slave module these cases, Master also Acknowledges address command generates erroneous slave interrupt, well master interrupt. Work around Several options available: When using 10-Bit Addressing mode, make certain that master slave devices share same MSbs their addresses.
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Module: Memory (Program Space Visibility)
When accessing data area data RAM, possible generate false address error trap condition reading data located precisely lower address boundary (8000h). data read using instruction with auto-decrement, resulting address will below boundary (i.e., 7FFEh); this will result address error trap. This false address error also occur 32-bit instruction used read data location, 8000h. Work around first location page (address 8000h). MPLAB Compiler (v3.11 later) supports option, "-merrata=psv_trap", prevent from generating code that would cause this erratum. Affected Silicon Revisions
Module: Core (Instruction Set)
instruction producing Read-After-Write stall condition executed inside REPEAT loop, instruction will executed fewer times than intended. example, this loop: repeat #0xf [w1],[++w1] will execute less than times. Work around Avoid using REPEAT repetitively execute instructions that create stall condition. Instead, software loop using conditional branches. MPLAB Compiler will generate REPEAT loops that cause this erratum. Affected Silicon Revisions
Module: RTCC
Under certain circumstances, value Alarm Repeat Counter (ALCFGRPT<7:0>) unexpectedly decremented. This happens only when byte write upper byte ALCFGRPT performed interval between device POR/BOR, first edge from RTCC clock source. Work around perform byte writes ALCFGRPT, particularly upper byte. Alternatively, wait until period SOSC completed before performing byte writes ALCFGRPT. Affected Silicon Revisions
Module: ICSPICSP/ICD port pair, PGEC3/PGED3 (RB5/RB4), cannot used read program device. Work around either PGEC2/PGED2 PGEC1/PGED1. Affected Silicon Revisions
2009 Microchip Technology Inc.
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Module: (Enhanced Buffer Modes)
event interrupt configured occur when enhanced FIFO buffer full (SISEL<2:0> 111), interrupt actually occur when byte written buffer, instead byte. other enhanced buffer interrupts function previously described. Work around Full Buffer Interrupt mode. SPITBF (SPIxSTAT<1>) reliably indicates when enhanced FIFO buffer full polled instead using Full Buffer Interrupt mode. Affected Silicon Revisions Work around SISEL<2:0> (SPIxSTAT<4:2>) `101'. This configures module generate event interrupt whenever last shifted shift register. When SPIxIF flag becomes set, shift register empty. Affected Silicon Revisions
Module: Core (Code Protection)
When general segment code protection been enabled (GCP Configuration programmed), applications unable write first bytes program memory space (0000h through 0200h). applications that require interrupt vectors changed during time, such bootloaders, modifications Interrupt Vector Tables (IVT) will possible. Work around Create Interrupt Vector Tables, each AIVT, area program space beyond affected region. addresses vector tables tables. These tables then modified needed actual addresses ISRs. Affected Silicon Revisions
Module: Converter
When using PGEC1 PGED1 debug application 64-pin devices this family, voltage references will disabled. This includes VREF+, VREF-, AVDD AVSS. conversion will always equal 0x3FF. Note: This issue only applies 64-pin devices this family (PIC24FJ256GB106, PIC24FJ192GB106, PIC24FJ64GB106).
Work around PGEC2 PGED2 debug functionality. Affected Silicon Revisions
Module: CTMU (A/D Trigger)
CTMU trigger automatic conversion after current source turned off. This happens even when trigger control bit, CTTRIG (CTMUCON<8>), been set. Work around Perform manual conversion clearing SAMP (AD1CON1<1>) immediately after CTMU current source been stopped. Affected Silicon Revisions
Module: (Enhanced Buffer Mode)
Enhanced Master mode, SRMPT (SPIxSTAT<7>) erroneously become several clock cycles middle FIFO transfer, indicating that shift register empty when not. This happens when both clock prescalers values other than their maximum (SPIxCON<4:2> SPIxCON<1:0> 00).
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Module: Oscillator (LPRC)
LPRC automatically restart following events (i.e., when supply voltage sags between thresholds, then returns above level). When this happens, systems that LPRC clock work. This includes PLL, Two-Speed Start-up, Fail-Safe Clock Monitor WDT. Work around issues: select non-PLL Clock mode initial start-up mode, using FNOSC Configuration bits (CW2<10:8>). After application initialized, switch Clock mode software using NOSC bits (OSCCON<10:8>). Allow elapse between application start-up software clock switch. issues: disable programming FWDTEN (CW1<7>). After application initialized, enable software setting SWDTEN (RCON<5>). Allow elapse between application start-up setting SWDTEN. Affected Silicon Revisions
Data Sheet Clarifications
following typographic corrections clarifications noted latest version device data sheet (DS39897B): Note: Corrections shown bold. Where possible, original bold text formatting been removed clarity.
None.
2009 Microchip Technology Inc.
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APPENDIX DOCUMENT REVISION HISTORY
Document (2/2008) Original version this document, silicon revision Includes silicon issues (Core, Operation), (Core, BOR), (JTAG, Programming), (UART), (I/O, PORTB), (SPI, Master Mode), (Input Capture) through (USB). Document (7/2008) Revised silicon issues (UART) (SPI, Master Mode) reflect updated definition issues. Added revision silicon issues (UART, UERIF Interrupt), (UART, FIFO Error Flags), through (UART, IrDA), (I2C, Master Mode), (I2C, Slave Mode), (Memory, Program Space Visibility), (ICSP), (Core, Instruction Set), (RTCC), (SPI, Enhanced Buffer Modes) (A/D Converter). Document (10/2008) Added silicon issue (SPI Enhanced Buffer Mode) revision Document (1/2009) Added silicon issue (Core Code Protection) revision Document (5/2009) Added silicon issues (CTMU Trigger) (Oscillator LPRC) revision Ported document unified silicon errata/data sheet clarification format. Document (7/2009) Added silicon revision document. Includes existing silicon issues (Core, Operation), (JTAG, Programming), through (USB) (Core, Instruction Set). additional issues added.
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Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Hampshire, HI-TECH Linear Active Thermistor, MXDEV, MXLAB, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
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03/26/09
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PIC24FJ256GB110 Family Silicon Errata Data Sheet Clarification PI

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