SPIDER 7240SL Channel Protected Low-Side Relay Switch Driver

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SPIDER 7240SL Channel Protected Low-Side Relay Switch Driver

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Data Sheet, Rev. 1.1, April 2009
SPIDER 7240SL
Channel Protected Low-Side Relay Switch
Driver Enhanced Relay Control SPIDER 7240SL
Table Contents
Table Contents
5.1.1 5.2.1 5.2.2 8.3.1 Overview Block Diagram Configuration Assignment Definitions Functions Voltage Current naming definition
General Product Characteristics Absolute Maximum Ratings Functional Range Thermal Resistance Input Power Stages Power Supply Limp Home Mode Input Circuit Inductive Output Clamp Timing Diagrams Input Power Stages Characteristics Protection Functions Over Load Protection Over Temperature Protection Reverse Polarity Protection Protection Characteristics
Diagnosis Features Diagnosis Characteristics Serial Peripheral Interface (SPI) Signal Description Daisy Chain Capability Protocol Timing Diagrams Characteristics
Application Information Package Outlines Revision History
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER-TLE7240SL
SPIDER 7240SL
Features
Overview
input pins providing flexible configuration Limp home functionality (direct driving) provided dedicated diagnostics control Daisy chain capability also compatible with 8bit devices Very wide range digital supply voltage Green Product (RoHS compliant) Qualified PG-SSOP-24-7
Description SPIDER 7240SL eight channel low-side switch PG-SSOP-24-7 package providing embedded protective functions. especially designed relay driver automotive applications. serial peripheral interface (SPI) utilized control diagnosis device load. direct control there four input pins available. device monolithically integrated. power transistors built N-channel MOSFETs. Table Basic Electrical data
Analog supply voltage VDDA Max. State resistance 150°C each channel RDS(ON,max) Nominal load current (nom) Overload switch threshold (OVL,max) Output leakage current channel (STB,max) Drain Source clamping voltage VDS(AZ) Maximum clock frequency fSCLK,max
Digital supply voltage Diagnostic Features latched diagnostic information register Overtemperature monitoring Overload detection state Open load detection state
Type SPIDER 7240SL Data Sheet
Package PG-SSOP-24-7
Marking TLE7240SL Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Overview Protection Functions Short circuit Over load Over temperature Electrostatic discharge (ESD)
Application types resistive, inductive capacitive loads Especially designed driving relays automotive applications
Detailed Description SPIDER 7240SL eight channel low-side relay switch designed typical automotive relays providing embedded protective functions. PG-SSOP-24-7 package used footprint optimized solution. serial peripheral interface (SPI) utilized control diagnosis device loads. interface provides daisy chain capability. SPIDER 7240SL equipped with four input pins that individually routed output control their dedicated channels thus offering flexibility design layout. input multiplexer controlled SPI. There dedicated limp home which provides straightforward usage input pins dedicated driver four outputs. device provides full diagnosis load, which open load well short circuit detection. diagnosis bits indicate latched fault conditions that have occurred. Each output stage protected against short circuit. case over load, affected channel switches off. There temperature sensors available each channel protect device case over temperature. device supplied power supply lines. analog supply supports digital supply offers very wide flexibility supply voltage ranging from power transistors built N-channel vertical power MOSFETs. inputs ground referenced CMOS compatible. device monolithically integrated Smart Power Technology. terms layout improvement, output pins available side device. other side bundle signals micro-controller.
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Block Diagram
Block Diagram
VDDA OUT1 OUT2 SCLK diagnosis register input control stand-by control OUT3 OUT4 OUT5 OUT6 OUT7 control, diagnostic protective functions OUT8 temperature sensor short circuit detection gate control open load detection
Blockdiagram .emf
Figure
Block Diagram SPIDER 7240SL
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Configuration
Configuration
Assignment
(top view
OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
Figure Configuration
VDDA SCLK
Pinout.emf
Definitions Functions
Symbol VDDA
Function Digital Supply Voltage; Connected 3.3V Voltage with Reverse protection Diode Filter against Analog Supply Voltage;Connected Voltage with Reverse protection Diode Filter against Ground; common ground digital, analog power Output Channel Drain power transistor channel Output Channel Drain power transistor channel Output Channel Drain power transistor channel Output Channel Drain power transistor channel Output Channel Drain power transistor channel Output Channel Drain power transistor channel Output Channel Drain power transistor channel Output Channel Drain power transistor channel
Power Supply
1,2,11,12 Power Stages Inputs OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
Control Input; Digital input case used keep open. Control Input; Digital input case used keep open. Rev. 1.1, 2009-04-15
Data Sheet
Driver Enhanced Relay Control SPIDER 7240SL
Configuration SCLK chip select; Digital input 5V.Low active serial clock; Digital input serial data Digital input serial data out; Digital output with voltage level referring VDD. Symbol
Function
Control Input; Digital input case used keep open. Control Input; Digital input case used keep open. Limp Home; Digital input case used keep open. Reset input pin; Digital input active
Output, Input, pull-down resistor integrated, pull-up resistor integrated
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Configuration
Voltage Current naming definition
Figure shows terms used this data sheet, with associated convention positive values.
Vbat
IDDA VRST IIN1 VIN1 VIN3 IIN2 OUT8 SCLK IGND OUT6 OUT7 VDDA OUT1 OUT2 OUT3 OUT4 OUT5
VDS3 VDS4
VLHI
SCLK SCLK
Terms.emf
Figure
Terms
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
General Product Characteristics
General Product Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings Unless otherwise specified: +150 VDDA, VDDA= 4.5V 5.5V voltages with respect ground, positive current flowing into Pos. Parameter Symbol Limit Values Min. Power Supply 4.1.1 4.1.2 4.1.3 Digital supply voltage Analog supply voltage Max. Unit Conditions
VDDA
-0.3 -0.3
Output voltage short circuit protection VOUT (single pulse) Load current Voltage power transistor Maximum energy dissipation channel
Power Stages 4.1.4 4.1.5 4.1.6 -0.5 active clamped Vbat=16V, Vclamp=45V, tpulse=
Tj(0) ID(0) 0.40 Tj(0) ID(0) 0.35 ID(0) 0.35
single pulse repetitive cycles) repetitive cycles) Logic Pins 4.1.7 4.1.8 4.1.9 4.1.10 4.1.11 4.1.12 4.1.13 4.1.14 4.1.15 4.1.16
IN1,IN2,IN3,IN4;Voltage input pins RST; Voltage reset LHI; Voltage limp home input Voltage chip select SCLK; Voltage serial clock Voltage serial input Voltage serial output Junction Temperature Storage Temperature Resistivity
VRST VLHI VSCLK Tstg
VESD
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
Temperatures HBM4)
Susceptibility
subject production test, specified design. Pulse shape represents inductive switch off: ID(t) ID(0) tpulse); tpulse level must exceed VDD+0.3V susceptibility, according EIA/JESD 22-A114
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
General Product Characteristics Note: Stresses above ones listed here cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect device reliability. Note: Integrated protection functions designed prevent destruction under fault conditions described data sheet. Fault conditions considered "outside" normal operating range. Protection functions designed continuous repetitive operation.
Pos. 4.2.1 4.2.1 4.2.2
Functional Range
Parameter Digital supply voltage Analog supply voltage extended supply range Symbol Min. Limit Values Max. parameter deviations possible
Unit
Conditions
VDDA VDDA
4.2.3 4.2.4
Digital Supply current reset mode IDD(RST) Digital supply current (all channels active)
IDD(ON)
VDDA VRST VSCLK
4.2.5
Analog supply current (all channels active)
IDDA(ON)
Note: Within functional range operates described circuit description. electrical characteristics specified within conditions given related electrical characteristics table.
Thermal Resistance
Note: This thermal data generated accordance with JEDEC JESD51 standards. more information, www.jedec.org.
Pos. 4.3.6 4.3.7 4.3.8
Parameter Junction Soldering Point Junction Ambient (1s0p+600mm2Cu) Junction Ambient (2s2p)
Symbol Min.
Limit Values Typ. Max.
Unit
Conditions
RthJSP RthJA RthJA
subject production test, specified design Specified RthJSP value simulated natural convection cold plate setup (all pins fixed ambient temperature). dissipating power (0.125 each). Specified RthJA value according Jedec JESD51-2,-3 natural convection 1s0p board; product (Chip+Package) simulated 76.2 114.3 board with additional heatspreading copper area 600mm2 thickness. dissipating power (0.125 each). Specified RthJA value according Jedec JESD51-2,-7 natural convection 2s2p board; product (Chip+Package) simulated 76.2 114.3 board with inner copper layers Cu). dissipating power (0.125 each).
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Input Power Stages
Input Power Stages
SPIDER 7240SL eight channel low-side relay switch. power stages built N-channel vertical power MOSFET transistors.
Power Supply
SPIDER 7240SL supplied power supply lines VDDA. digital power supply line designed functional very wide voltage range. analog power supply VDDA supports supply. There power-on reset functions implemented both supply lines. After start-up power supply, registers reset their default values device stand-by mode. Capacitors pins -GND VDDA -GND recommended. There reset available. level this causes registers their default values quiescent supply currents minimized.
5.1.1
Limp Home Mode
SPIDER 7240SL offers capability driving dedicated channels during eventual fail-safe operation system. This limp home mode activated high signal LHI. this mode, registers reset input pins directly routed their corresponding channels OUT1 OUT4, Table details. OUT5 OUT8 turned limp home mode. Furthermore, ignored input referred VDDA order ensure defined operation mode digital supply microcontroller fail. high signal overrides Reset signal RST. case limp home during standby device will therefore wake enter limp home mode. After limp home operation registers reset device enters standby mode following logic state, returns idle (all channels OFF). Next transmission will receive Flag. Input Table Routing during limp home mode controlled Output OUT1 OUT2 OUT3 OUT4
Input Circuit
There four input pins available SPIDER 7240SL, which configured used control output stages. parameter selects input used. Figure shows input circuit SPIDER 7240SL. During Limp home mode default routing switched commands ignored.
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Input Power Stages
Channel
Channel
Channel
Channel
Channel
Channel
Channel
ILHI
Channel
InputLogic .emf
Figure
Input matrix logic
current sink ground ensures that channels switch case open input pin. zener diode protects input circuit against pulses. After power-on reset, device enters idle mode (all channel OFF).
5.2.1
Inductive Output Clamp
When switching inductive loads, potential rises VDS(CL) potential, because inductance intends continue driving current. voltage clamping necessary prevent destruction device, Figure details. Nevertheless, maximum allowed load inductance limited.
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Input Power Stages
Vbat
(CL)
OutputClamp .emf
Figure
Output Clamp Implementation
Maximum Load Inductance During demagnetization inductive loads, energy dissipated SPIDER 7240SL. This energy calculated with following equation:
DS(CL) DS(CL) DS(CL)
Following equation simplifies under assumption
DS(CL)
maximum energy, which converted into heat, limited thermal design component.
5.2.2
Timing Diagrams
power transistors switched with dedicated slope bits serial peripheral interface SPI. switching times tOFF designed equally.
SPI: SPI: tOFF
SwitchOn.emf
Figure
Switching Resistive Load
input mode, high signal input equivalent command signal command respectively. Please refer Section details operation modes. Note: listed switching times valid, when switching from stand-by mode.
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Input Power Stages
Input Power Stages Characteristics
Note: Characteristics show deviation parameter given supply voltage junction temperature. Typical values show typical parameters expected from manufacturing. Electrical Characteristics: Supply Input voltages with respect ground, positive current flowing into unless otherwise specified: VDDA, VDDA= 4.5V 5.5V, +150 Pos. Parameter Symbol Min. Power Supply 5.3.1 5.3.2 Digital supply voltage Limit Values Typ. Max. Unit Conditions
Digital supply current, channels IDD(ON)
VDDA VRST VSCLK
fSCLK VRST =VLHI
5.3.3
Digital supply stand-by current, channels stand-by mode
IDD(STB)
5.3.4
Digital supply reset current
IDD(RST)
5.3.5 5.3.6 5.3.7 5.3.8
Digital power-on reset threshold voltage Analog supply voltage Analog supply current channels Analog supply stand-by current channels stand-by mode
VDD(PO) VDDA IDDA(ON) IDDA(STB)
VSCLK
5.3.9
Analog supply reset current
IDDA(RST)
VRST =VLHI
5.3.10
Analog power-on reset threshold VDDA(PO) voltage
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Input Power Stages Electrical Characteristics: Supply Input voltages with respect ground, positive current flowing into unless otherwise specified: VDDA, VDDA= 4.5V 5.5V, +150 Pos. Parameter Symbol Min. Output characteristics 5.3.11 On-State resistance channel
RDS(ON)
Limit Values Typ. Max.
Unit
Conditions
5.3.12
Nominal load current
IL(nom)
5.3.13
Output leakage current stand-by ID(STB) mode (per channel) Output clamping voltage
level pins IN1.IN4 level pins IN1.IN4 L-input pull-down current through H-input pull-down current through level level L-input pull-down current through H-input pull-down current through
channels Tj,max based Rthja,2s2p 13.5
5.3.14 5.3.15 5.3.16 5.3.17 5.3.18
VDS(CL) VIN(L) VIN(H)
Input Characteristics
IIN(L) IIN(H)
Reset Characteristics 5.3.19 5.3.20 5.3.21 5.3.22 Timings 5.3.23 5.3.24 5.3.25 Reset wake-up time Reset signal duration Turn-on time Vbat channels 5.3.26 Turn-off time channels
subject production test level must exceed VDD+0.3V
VRST(L) VRST(H) IRST(L) IRST(H)
0.4*
0.2*
VRST
VRST
twu(RST) tRST(L)
Vbat 13.5 resistive load
tOFF
Vbat 13.5 resistive load
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Protection Functions
Protection Functions
device provides embedded protective functions. Integrated protection functions designed prevent destruction under fault conditions described this data sheet. Fault conditions considered "outside" normal operating range. Protection functions designed continuous repetitive operation.
Over Load Protection
SPIDER 7240SL protected case over load short circuit load. After time tOFF(OVL), over loaded channel switches according diagnosis flag set.The channel switched after clearing diagnosis flag. Please refer Figure details.
tOFF(OVL) IOUT1 IOUT(OVL) Program STANDBY again
OverLoad.emf
Figure
Shut down over load
current sink ground ensures that channels switch case open input pin. zener diode protects input circuit against pulses. After power-on reset, device enters idle mode.
Over Temperature Protection
temperature sensor each channel causes overheated channel switch prevent destruction according diagnosis flag set. channel switched after clearing diagnosis flag. Please refer Chapter information diagnosis features.
Reverse Polarity Protection
case reverse polarity, intrinsic body diode power transistor causes power dissipation. reverse current through intrinsic body diode power transistor limited connected load. VDDA supply pins must protected against reverse polarity externally. over temperature over load protection active during reverse polarity.
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Protection Functions
Protection Characteristics
Note: Characteristics show deviation parameter given supply voltage junction temperature. Typical values show typical parameters expected from manufacturing. Electrical Characteristics: Protection voltages with respect ground, positive current flowing into unless otherwise specified: VDDA, VDDA= 4.5V 5.5V, +150 Pos. Parameter Symbol Min. Over Load Protection 6.4.1 6.4.2 6.4.3 Over load detection current channels Over load shut-down delay time Thermal shut down temperature
tOFF(OVL) Tj(SC) ID(OVL)
Limit Values Typ. Max. 0.95 1701)
Unit
Conditions
Over Temperature Protection
subject production test, specified design
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Diagnosis Features
Diagnosis Features
SPIDER 7240SL provides diagnosis information about device about load. There following diagnosis flags implemented: diagnosis information protective functions channel latched diagnosis flag open load diagnosis channel latched diagnosis flag OLn. Both flags cleared programming specific channel Standby (STB).
Failure Mode Comment
Open Load short circuit Diagnosis, when channel switched none ground Diagnosis, when channel switched off: according voltage level output pin, flag after time td(OL). When channel there Diagnosis active, Standby Diagnosis enabled Over Temperature When over temperature occurs, according diagnosis flag set. affected channel active switched off. diagnosis flags latched until they have been cleared programming channel STB. When over load detected channel affected channel switched after time tOFF(OVL) dedicated diagnosis flag set. diagnosis flags latched until they have been cleared programming channel
Over Load (Short Circuit)
Diagnosis Characteristics
Note: Characteristics show deviation parameter given supply voltage junction temperature. Typical values show typical parameters expected from manufacturing. Electrical Characteristics: Diagnosis voltages with respect ground, positive current flowing into unless otherwise specified: VDDA, VDDA= 4.5V 5.5V, +150 Pos. Parameter Symbol Min. State Diagnosis 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 Open load detection threshold voltage Limit Values Typ. Max. 0.95 Unit Conditions
VDS(OL)
Output pull-down diagnosis current ID(PD) channel Open load diagnosis delay time Over load detection current Over load detection delay time
13.5
td(OL) ID(OVL) tOFF(OVL)
State Diagnosis
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
diagnosis control interface based serial peripheral interface (SPI). full duplex synchronous serial slave interface, which uses four lines: SCLK Data transferred lines data rate given SCLK. falling edge indicates beginning data access. Data sampled line falling edge SCLK shifted line rising edge SCLK. Each access must terminated rising edge modulo counter ensures that data taken only, when multiple been transferred, while minimum also taken into consideration. Therefore interface provides daisy chain capability even with devices.
SCLK
time
SPI.emf
Figure
Serial peripheral interface
protocol described Section 8.3. reset default values after power-on reset.
Signal Description
Chip Select: system micro controller selects SPIDER 7240SL means pin. Whenever state, data transfer take place. When high state, signals SCLK pins ignored forced into high impedance state. High transition: diagnosis information transferred into shift register. changes from high impedance state high state depending logic combination between transmission error flag (TER) signal level result, even daisy chain configuration, high signal indicates faulty transmission. transmission error flag after kind reset, reset between commands indicated. details, please refer Figure This information stays available first rising edge SCLK.
SCLK
TER.emf
Figure Data Sheet
Transmission Error Flag Line
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Serial Peripheral Interface (SPI) High transition: Data from shift register transferred into input matrix register only, when after falling edge exactly multiple eight SCLK signals have been detected, while minimum valid length course clocks register bits SPIDER-TLE7240SL. SCLK Serial Clock: This input clocks internal shift register. serial input (SI) transfers data into shift register falling edge SCLK while serial output (SO) shifts diagnostic information rising edge serial clock. essential that SCLK state whenever chip select makes transition. Serial Input: Serial input data bits shifted this pin, most significant first. information read falling edge SCLK. Please refer Section further information. Serial Output: Data shifted serially this pin, most significant first. high impedance state until goes state. data will appear following rising edge SCLK. Please refer Section further information.
Daisy Chain Capability
SPIDER 7240SL provides daisy chain capability. this configuration several devices activated same signal MCS. line device connected with line another device (see Figure 10), which builds chain. ends chain connected with output input master device, respectively. master device provides master clock MCLK, which connected SCLK line each device chain.
device
device
device
SCLK
SCLK
MCLK
Figure
Daisy Chain Configuration
block each device, there shift register where from line shifted each SCLK. shifted seen After SCLK cycles, data transfer SPIDER-TLE7240SL been finished. single chip configuration, line must high make device accept transferred data. daisy chain configuration data shifted device been shifted device When using multiple devices daisy chain, number bits must correspond with number register bits. Figure showing example with devices, where SPI. successful transmission, there have 8bit shifted through devices. After that, line must high.
Data Sheet
SCLK
SPI_DasyChain .emf
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Serial Peripheral Interface (SPI)
MCLK
time
device device
device device
device device
SPI_DasyChain2.emf
Figure
Data Transfer Daisy Chain Configuration
Protocol
protocol SPIDER 7240SL provides registers. input register diagnosis register. diagnosis register contains four pairs diagnosis flags, input register contains input multiplexer configuration. After power-on reset, register bits device idle mode.
Default: FFFFH
Field
Bits 15:14, 13:12, 11:10, 9:8, 7:6, 5:4, 3:2,
Type
Description Input Register Channel Stand-by Mode: Fast channel switched off. Diagnosis flags cleared. Diagnosis current disabled. Input Mode: Channel switched according signal input pin. Diagnosis current enabled OFF-state. Mode: Channel switched Mode: Channel switched off. Diagnosis current enabled.
channels Standby Mode, device power down status with minimum current consumption (sleep mode).
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Serial Peripheral Interface (SPI)
CS1)
Reset Value: 10000H
This valid between first SCLK transition. Field Bits Type Description Transmission Error Previous transmission successful (modulo clocks received, minimum bit). Previous transmission failed first transmission after reset. Open Load Flag channel Normal operation. Open load occurred state. Diagnosis Flag channel Normal operation. Over load over temperature switch occurred state.
15,13, 11,9,7, 14,12, 10,8,6,
8.3.1
Timing Diagrams
tCS(lead) tCS(lag) tSCLK(P) tSCLK(H) tSCLK(L)
tCS(td)
SCLK
tSI(su) tSI(h)
tSO(en) tSO(v) tSO(dis)
Timing .emf
Figure
Timing Diagram
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Serial Peripheral Interface (SPI)
Characteristics
Note: Characteristics show deviation parameter given supply voltage junction temperature. Typical values show typical parameters expected from manufacturing. Electrical Characteristics: Serial Peripheral Interface (SPI) voltages with respect ground, positive current flowing into unless otherwise specified: VDDA, VDDA= 4.5V 5.5V, +150 Pos. Parameter Symbol Min. Input Characteristics (CS, SCLK, 8.4.1 level SCLK level SCLK L-input pull-up current through
VCS(L) VSCLK(L) VSI(L)
Limit Values Typ. Max. 0.2*
Unit
Conditions
8.4.2
0.4*
VCS(H) VSCLK(H) VSI(H) ICS(L)
8.4.3 8.4.4 8.4.5
H-input pull-up current through ICS(H) L-input pull-down current through SCLK H-input pull-down current through SCLK level output voltage level output voltage Output tristate leakage current Serial clock frequency Serial clock period Serial clock high time Serial clock time Enable lead time (falling rising SCLK) Enable time (falling SCLK rising Transfer delay time (rising falling
0.4*VDD
ISCLK(L) ISI(L)
VSCLK
8.4.6
ISCLK(H) ISI(H) VSO(L) VSO(H) ISO(OFF) fSCLK tSCLK(P) tSCLK(H) tSCLK(L) tCS(lead) tCS(lag) tCS(td)
VSCLK
Output Characteristics (SO) 8.4.7 8.4.8 8.4.9
Timings
8.4.10 8.4.11 8.4.12 8.4.13 8.4.14 8.4.15 8.4.16 8.4.17
1)2)
Data setup time (required time tSI(su) falling SCLK)
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Serial Peripheral Interface (SPI) Electrical Characteristics: Serial Peripheral Interface (SPI) voltages with respect ground, positive current flowing into unless otherwise specified: VDDA, VDDA= 4.5V 5.5V, +150 Pos. 8.4.18 8.4.19 8.4.20 Parameter Output enable time (falling valid) Output disable time (rising tri-state) Output data valid time with capacitive load Symbol Min.
tSO(en) tSO(dis) tSO(v)
Limit Values Typ. Max.
Unit
Conditions
subject production test, specified design. Diagnosis flag update needs time specified Chapter valid information
Data Sheet
Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Application Information
Application Information
Note: following information given hint implementation device only shall regarded description warranty certain functionality, condition quality device. Figure shows simplified application circuit. VDDA need externally reverse polarity protected.
Vbat
100nF
VDDA
OUT1 OUT2 KL15 Relay KL50 Relay Wiper Relay Horn Relay
Limp Home Circuit
Possibility control Inputs IN1-4 during malfunction
OUT3 OUT4 OUT5 OUT6 OUT7
GPIO
low-side gate control
OUT8
XC2000 SCLK
Limp Home Signal
8264 Hermes)
TLE7240SL.emf
Figure
Application Diagram
Note: This very simplified example application circuit. function must verified real application.
further information contact http://www.infineon.com/spider Data Sheet Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Package Outlines
Package Outlines
0.35
0.175 ±0.07
±0.11)
1.75 MAX. (1.47)
0.19 +0.06
MAX.
MAX. 0°.8°
0.65 0.25 ±0.05
0°.8°
Seating Plane
0.64 ±0.25
±0.2
MAX.
0.17
8.65 ±0.11) Index Marking
Does include plastic metal protrusion 0.15 max. side Does include dambar protrusion 0.13 max.
Figure PG-SSOP-24-7 (Plastic Dual Small Outline Package)
PG-SSOP-24-5,
Green Product (RoHS compliant) meet world-wide customer requirements environmentally friendly products compliant with government regulations device available green product. Green products RoHS-Compliant (i.e Pbfree finish leads suitable Pb-free soldering according IPC/JEDEC J-STD-020). Please specify package needed (e.g. green package) when placing order
find packages, sorts packing others Infineon Internet Page "Products": Data Sheet
Dimensions Rev. 1.1, 2009-04-15
Driver Enhanced Relay Control SPIDER 7240SL
Revision History
Version Rev. Rev.
Revision History
Date 2009-04-15 2009-04-02 Changes fixed typo Figure3, Figure4,Figure7 Chapter channel numbering starts everywhere with released Datasheet
Data Sheet
Rev. 1.1, 2009-04-15
Edition 2009-04-15 Published Infineon Technologies 81726 Munich, Germany 2009 Infineon Technologies Rights Reserved. Legal Disclaimer information given this document shall event regarded guarantee conditions characteristics. With respect examples hints given herein, typical values stated herein and/or information regarding application device, Infineon Technologies hereby disclaims warranties liabilities kind, including without limitation, warranties non-infringement intellectual property rights third party. Information further information technology, delivery terms conditions prices, please contact nearest Infineon Technologies Office (www.infineon.com). Warnings technical requirements, components contain dangerous substances. information types question, please contact nearest Infineon Technologies Office. Infineon Technologies components used life-support devices systems only with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system affect safety effectiveness that device system. Life support devices systems intended implanted human body support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.

SPIDER 7240SL Channel Protected Low-Side Relay Switch Driver

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