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Spartan-6 FPGA Packaging and Pinouts

Advance Product Specification optional

Spartan-6 FPGA Packaging and Pinouts
Advance Product Specification optional
UG385 (v1.0) June 24, 2009 optional
Revision History
The following table shows the revision history for this document.
Date 06 / 24 / 09 Version 1.0 Initial Xilinx release. Revision
Spartan-6 FPGA Packaging (Advance Spec)
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Table of Contents
Preface: About This Guide
Chapter 1: Packaging Overview
Chapter 2: Pinout Tables
Chapter 3: Pinout and SelectIO Bank Diagrams
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Chapter 4: Mechanical Drawings
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPG196 Chip-Scale BGA Package Specifications (0.5 mm Pitch) . . . . . . . . . . . . . TQG144 Thin Quad Flat-Pack Package Specifications (0.5 mm Pitch) . . . . . . . . CSG225 Chip-Scale BGA Package Specifications (0.8 mm Pitch) . . . . . . . . . . . . . FT(G)256 Fine-Pitch Thin BGA Package Specifications (1.00 mm Pitch) . . . . . . CSG324 Chip-Scale BGA Package Specifications (0.8 mm Pitch) . . . . . . . . . . . . . FG(G)484 Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . . . . . . . . . CSG484 Chip-Scale BGA Package Specifications (0.8 mm Pitch) . . . . . . . . . . . . . FG(G)676 Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . . . . . . . . . FG(G)900 Chip-Scale BGA Package Specifications (1.0 mm Pitch) . . . . . . . . . . .
Chapter 5: Thermal Specifications
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Chapter 6: Package Marking
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Preface
About This Guide
This guide describes Spartan®-6 device pinouts and package specifications it also includes pinout diagrams and thermal data.
Organization of This Guide
This document is comprised of the following chapters: · Chapter 1, "Packaging Overview" Provides an introduction to the Spartan-6 family with a summary of maximum I / Os available in each device / package combination. Also includes table of pin definitions. · · · · Chapter 2, "Pinout Tables" Provides pinout information for all Spartan-6 devices and packages. Chapter 3, "Pinout and SelectIO Bank Diagrams" Provides pinout diagrams for all Spartan-6 FPGA package / device combinations. Chapter 4, "Mechanical Drawings" Provides mechanical drawings of Spartan-6 FPGA packages. Chapter 5, "Thermal Specifications" Provides thermal data associated with Spartan-6 FPGA packages. Discusses Spartan-6 FPGA power management strategy and thermal management options. · Chapter 6, "Package Marking" Provides example and description of the marking on top of the package (topmark).
Additional Documentation
The following documents are also available for download at http://www.xilinx.com / 6. · · Spartan-6 Family Overview This overview outlines the features and product selection of the Spartan-6 family. Spartan-6 FPGA Data Sheet: DC and Switching Characteristics This data sheet contains the DC and switching characteristic specifications for the Spartan-6 family. · Spartan-6 FPGA Configuration User Guide This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.
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Preface: About This Guide
Spartan-6 FPGA SelectIO Resources User Guide This guide describes the SelectIO resources available in all Spartan-6 devices. Spartan-6 FPGA Clocking Resources User Guide This guide describes the clocking resources available in all Spartan-6 devices, including the DCMs and PLLs.
Spartan-6 FPGA Configurable Logic Block User Guide This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Spartan-6 devices.
Spartan-6 FPGA Block RAM Resources User Guide This guide describes the Spartan-6 device block RAM capabilities. Spartan-6 FPGA DSP48A1 Slice User Guide This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and provides configuration examples.
Spartan-6 FPGA Memory Controller User Guide This guide describes the Spartan-6 FPGA memory controller block, a dedicated embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 FPGAs to the most popular memory standards.
Spartan-6 FPGA GTP Transceiver User Guide This guide describes the GTP transceivers available in the Spartan-6 LXT FPGAs. Spartan-6 FPGA PCB Design Guide This guide provides information on PCB design for Spartan-6 devices, with a focus on strategies for making design decisions at the PCB and interface level.
Additional Support Resources
To search the database of silicon and software questions and answers, or to create a technical support case in WebCase, visit the following Xilinx website: http://www.xilinx.com / support
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Chapter 1
Packaging Overview
Summary
This chapter covers the following topics: · · · Introduction Device / Package Combinations and Maximum I / Os Pin Definitions
Introduction
This section describes the pinouts for Spartan®-6 devices in various packages. Spartan-6 devices are offered in low-cost, space-saving packages that are optimally designed for the maximum number of user I / Os. Package inductance is minimized as a result of optimal placement and even distribution as well as an increased number of Power and GND pins. All of the Spartan-6 LX devices supported in a particular package are pinout compatible. All of the Spartan-6 LXT devices supported in a particular package are pinout compatible. The Spartan-6 LX devices are not pin compatible with the Spartan-6 LXT devices. Pins that are not available in some of the devices are listed in the "No Connects" column of each table. Each device is split into I / O banks to allow for flexibility in the choice of I / O standards (see Spartan-6 FPGA SelectIO Resources User Guide). Global pins and power / ground pins, are listed at the end of each table. Table 1-5 provides definitions for all pin types. For information on package electrical characteristics and how the characteristics are measured, refer to UG112: Device Package User Guide found on the Xilinx website. Designers targeting a part / package combination not currently supported in software should contact Xilinx technical support before starting board layout. For the latest Spartan-6 FPGA pinout and package information, check the Xilinx website for updates to this document.
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Chapter 1: Packaging Overview
Device / Package Combinations and Maximum I / Os
Table 1-1 shows the package specifications and the maximum number of user I / Os possible in Spartan-6 FPGA packages. Table 1-1: Spartan-6 FPGA Packages
Packages Package Specifications CPG196 TQG144(1) CSG225 FT(G)256(2) CSG324 FG(G)484(2) CSG484 FG(G)676(2) FG(G)900(2) Package Type Pitch (mm) Size (mm) Maximum I / Os
Notes:
1. The footprint for the TQG144 package (22 x 22 mm) is larger than the package body (20 x 20 mm). 2. These devices are available in both Pb and Pb-free (additional G) packages as standard ordering options.
Chip Scale 0.5 8x8 100
Quad Flat Pack 0.5 22 x 22(1) 102
Chip Scale 0.8 13 x 13 160
BGA 1.00 17 x 17 186
Chip Scale 0.8 15 x 15 232
BGA 1.00 23 x 23 338
Chip Scale 1.00 19 x 19 330
BGA 1.00 27 x 27 498
BGA 1.00 31 x 31 570
The number of I / Os per package includes all user I / Os except the dedicated pins listed in Table 1-2 and the GTP serial transceiver I / O channels for the devices listed in Table 1-3. Table 1-2: Spartan-6 FPGA Dedicated Configuration Pins
Notes:
1. Only available in XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T devices.
Table 1-3:
Number of Serial Transceivers (GTs) I / O Channels / Device
Device
I / O Channels LX25T MGTRXP MGTRXN MGTTXP MGTTXN
LX45T
LX75T(1)
LX100T(2)
LX150T(2)
1. The XC6SLX75T has 4 GTP I / O channels in the FG(G)484 and CSG484 packages and 8 GTP I / O channels in the FG(G)676 package. 2. The XC6SLX100T and the XC6SLX150T have 4 GTP I / O channels in the FG(G)484 and CSG484 packages and 8 GTP I / O channels in the FG(G)676 and FG(G)900 packages.
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Device / Package Combinations and Maximum I / Os
Table 1-4 shows the number of available I / Os and the number of differential pairs for each Spartan-6 device / package combination. Table 1-4:
Spartan-6 Device
Available I / O Pin / Device / Package Combinations
Spartan-6 FPGA Package User I / O Pins CPG196 TQG144 CSG225 FT(G)256 CSG324 FG(G)484 CSG484 FG(G)676 FG(G)900
Available User I / Os
XC6SLX4
Differential Pairs Available User I / Os
XC6SLX9
Differential Pairs Available User I / Os
XC6SLX16
Differential Pairs Available User I / Os
XC6SLX25
Differential Pairs Available User I / Os
266 133 316 158 TBD TBD 326 163 338 169 250 125 296 148 TBD TBD 296 148 296 148
XC6SLX45
Differential Pairs Available User I / Os
XC6SLX75
Differential Pairs Available User I / Os
XC6SLX100
Differential Pairs Available User I / Os
XC6SLX150
Differential Pairs Available User I / Os
XC6SLX25T
Differential Pairs Available User I / Os
XC6SLX45T
Differential Pairs Available User I / Os
XC6SLX75T
Differential Pairs Available User I / Os
XC6SLX100T
Differential Pairs Available User I / Os
XC6SLX150T
Differential Pairs
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Chapter 1: Packaging Overview
Pin Definitions
Table 1-5 lists the pin definitions used in Spartan-6 FPGA packages. Table 1-5: Spartan-6 FPGA Pin Definitions
Direction Description
Pin Name User I / O Pins
Input
Input Output
AWAKE
Output
Input / Output Output Output Output Output Output Output
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Pin Definitions
Table 1-5:
Pin Name IRDY1 / 2, TRDY1 / 2
Output
Input Input
Bidirectional (open-drain)
Input
Input Input / Output Input Input
Multi-Function Memory Controller Pins M#DQn M#LDQS M#LDQSN M#UDQS Input / Output Input / Output Input / Output Input / Output Memory controller data D0:15 in bank #. Memory controller lower data strobe in bank #. Memory controller lower data strobe N in bank #. Memory controller upper data strobe in bank #.
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Chapter 1: Packaging Overview
Table 1-5:
Direction Input / Output Output Output Output Output Output Output Output Output Output Output Output Output Description Memory controller upper data strobe N in bank #. Memory controller address A0:14 in bank #. Memory controller bank address BA0:2 in bank #. Memory controller lower data mask in bank #. Memory controller upper data mask in bank #. Memory controller clock in bank #. Memory controller active-Low clock in bank #. Memory controller active-Low column address strobe in bank #. Memory controller active-Low row address strobe in bank #. Memory controller on-die termination control for external memory in bank #. Memory controller write enable in bank #. Memory controller clock enable in bank #. Memory controller reset in bank #.
Pin Name M#UDQSN M#An M#BAn M#LDM M#UDM M#CLK M#CLKN M#CASN M#RASN M#ODT M#WE M#CKE M#RESET Dedicated Pins (1)
Input / Output
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin indicates completion of the configuration process. As an input, a Low level on DONE can be configured to delay the start-up sequence. Active Low asynchronous reset to configuration logic. This pin has a default weak pull-up resistor. Control input pin for the power-saving Suspend mode. SUSPEND is a dedicated pin and AWAKE is a multi-function pin. Must be enabled by configuration option. JTAG Boundary-scan clock. JTAG Boundary-scan data input. JTAG Boundary-scan data output. JTAG Boundary-scan mode select.
Input
Input Input Input Output Input
When found in a table or text file, an NC indicates that this pin is not connected in the specific device / package combination. However, in some devices in the same package, another pin name is used to describe this pin. Reserved. Must connect High.
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Pin Definitions
Table 1-5:
Direction Description
Ground. Decryptor key memory backup supply. When not used, tie this pin to VCC or GND. Only available in the XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T devices. Power-supply pins for auxiliary circuits. Power-supply pins for the internal core logic. Power-supply pins for the output drivers (per bank). Decryptor key EFUSE power supply pin for programming. Only available in the XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T devices. Decryptor key EFUSE resistor for programming. Only available in the XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T devices.
RFUSE
Input
Notes:
1. Dedicated pins without a bank number (JTAG and SUSPEND) are powered by VCCAUX.
N / A N / A N / A N / A Input Input Input Input Input Output Output
Power-supply pin for transceiver mixed-signal circuitry. Power-supply pin for TX and RX circuitry.
Power-supply pin for the resistor calibration circuit. Power-supply pin for PLL. Positive differential reference clock. Negative differential reference clock. Precision reference resistor pin for internal calibration termination. Positive differential receive port. Negative differential receive port. Positive differential transmit port. Negative differential transmit port.
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Chapter 1: Packaging Overview
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Chapter 2
Pinout Tables
Summary
This chapter includes the pinout information tables for the following packages: · · · · · · · · · · · · · · · Table 2-1, CPG196 Package-LX4, LX9, and LX16, on page 18 Data is not currently available on devices in this package. Table 2-2, TQG144 Package-LX4 and LX9, on page 18 Data on the LX4 is not currently available. Table 2-3, CSG225 Package-LX4, LX9, and LX16, on page 23 Data on the LX4 is not currently available. Table 2-4, FT(G)256 Package-LX9, LX16, and LX25, on page 30 Table 2-5, CSG324 Package-LX9, LX16, LX25, and LX45, on page 38 Table 2-6, CSG324 Package-LX25T and LX45T, on page 48 Table 2-7, FG(G)484 Package-LX25, LX45, LX75, LX100, and LX150, on page 58 Data on the LX75 is not currently available. Table 2-8, FG(G)484 Package-LX25T, LX45T, LX75T, LX100T, and LX150T, on page 73 Data on the LX75T is not currently available. Table 2-9, CSG484 Package-LX45, LX75, LX100, and LX150, on page 88 Data is not currently available on devices in this package. Table 2-10, CSG484 Package-LX45T, LX75T, LX100T, and LX150T, on page 88 Data is not currently available on devices in this package. Table 2-11, FG(G)676 Package-LX45, on page 88 Table 2-12, FG(G)676 Package-LX75, LX100, and LX150, on page 109 Data on the LX75 is not currently available. Table 2-13, FG(G)676 Package-LX75T, LX100T, and LX150T, on page 130 Data on the LX75T is not currently available. Table 2-14, FG(G)900 Package-LX150, on page 151 Data is not currently available on devices in this package. Table 2-15, FG(G)900 Package-LX100T and LX150T, on page 151 Data is not currently available on devices in this package.
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Chapter 2: Pinout Tables
CPG196 Package-LX4, LX9, and LX16
Table 2-1:
CPG196 Package-LX4, LX9, and LX16
Pin Description Pin Number No Connect (NC)
Data is not currently available on devices in this package.
TQG144 Package-LX4 and LX9
Data on the LX4 is not currently available. Table 2-2:
TQG144 Package-LX4 and LX9
Pin Description Pin Number P144 P143 P142 P141 P140 P139 P138 P137 P134 P133 P132 P131 P127 P126 P124 P123 P121 P120 P119 P118 P117 P116 P115 P114 P112 No Connect (NC)
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TQG144 Package-LX4 and LX9
Table 2-2:
Pin Description Pin Number P111 P109 P110 P107 P106 P105 P104 P102 P101 P100 P99 P98 P97 P95 P94 P93 P92 P88 P87 P85 P84 P83 P82 P81 P80 P79 P78 P75 P74 P73 P72 P71 P70 No Connect (NC)
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Chapter 2: Pinout Tables
Table 2-2:
Pin Description Pin Number P69 P67 P66 P65 P64 P62 P61 P60 P59 P58 P57 P56 P55 P51 P50 P48 P47 P46 P45 P44 P43 P41 P40 P39 P38 P37 P35 P34 P33 P32 P30 P29 P27 No Connect (NC)
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TQG144 Package-LX4 and LX9
Table 2-2:
Pin Description Pin Number P26 P24 P23 P22 P21 P17 P16 P15 P14 P12 P11 P10 P9 P8 P7 P6 P5 P2 P1 P108 P113 P13 P130 P136 P25 P3 P49 P54 P68 P77 P91 P96 P129 No Connect (NC)
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Chapter 2: Pinout Tables
Table 2-2:
Pin Description Pin Number P20 P36 P53 P90 P128 P19 P28 P52 P89 P122 P125 P135 P103 P76 P86 P42 P63 P18 P31 P4 No Connect (NC)
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CSG225 Package-LX4, LX9, and LX16
Data on the LX4 is not currently available. Table 2-3:
CSG225 Package-LX4, LX9, and LX16
Pin Description Pin Number B2 A2 B3 A3 D5 C5 C4 A4 E6 D6 B5 A5 D7 C7 C6 A6 E7 D8 B7 A7 C8 A8 B9 A9 F8 E8 D10 C9 F10 E9 No Connect (NC)
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Chapter 2: Pinout Tables
Table 2-3:
Pin Description Pin Number C10 A10 B11 A11 D11 C11 B13 A13 C12 A12 A14 E10 E13 D12 B14 B15 G11 G12 F11 F12 H10 H11 C14 C15 H12 G13 D13 D15 J11 J13 E14 E15 K10 No Connect (NC)
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CSG225 Package-LX4, LX9, and LX16
Table 2-3:
Pin Description Pin Number K11 F13 F15 K12 L12 G14 G15 H13 H15 J14 J15 K13 K15 L14 L15 M13 M15 N14 N15 P14 P15 L13 L10 R14 N12 R12 P13 R13 P11 R11 M11 N11 N10 No Connect (NC)
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Chapter 2: Pinout Tables
Table 2-3:
Pin Description Pin Number R10 L9 M10 M9 N9 P9 R9 N8 R8 M8 N7 K8 L8 P7 R7 L7 M6 N6 R6 P5 R5 L6 L5 N4 R4 M5 N5 P3 R3 R2 M4 L3 P2 No Connect (NC)
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CSG225 Package-LX4, LX9, and LX16
Table 2-3:
Pin Description Pin Number P1 N2 N1 M3 M1 L2 L1 K3 K1 J2 J1 H3 H1 K4 J3 G2 G1 K5 J4 F3 F1 J5 H4 G5 G3 H6 H5 F5 F4 E5 E4 E2 E1 No Connect (NC)
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Chapter 2: Pinout Tables
Table 2-3:
Pin Description Pin Number D4 E3 D3 D1 C2 C1 A1 A15 B10 B6 C13 C3 E11 F14 F2 F6 G7 G9 H8 J7 J9 K14 K2 K6 L11 N13 N3 P10 P6 R1 R15 B1 E12 No Connect (NC)
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CSG225 Package-LX4, LX9, and LX16
Table 2-3:
Pin Description Pin Number F7 G10 J6 K9 L4 M12 F9 G6 G8 H7 H9 J10 J8 K7 B12 B4 B8 D9 D14 H14 J12 M14 M7 P12 P4 P8 D2 G4 H2 M2 No Connect (NC)
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Chapter 2: Pinout Tables
FT(G)256 Package-LX9, LX16, and LX25
Table 2-4:
FT(G)256 Package-LX9, LX16, and LX25
Pin Description Pin Number C4 A4 B5 A5 D5 C5 B6 A6 F7 E6 C7 A7 D6 C6 B8 A8 C9 A9 B10 A10 E7 E8 E10 C10 D8 C8 C11 A11 F9 D9 B12 No Connect (NC)
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FT(G)256 Package-LX9, LX16, and LX25
Table 2-4:
Pin Description Pin Number A12 C13 A13 F10 E11 B14 A14 D11 D12 C14 C12 A15 E14 E13 E12 B15 B16 F12 G11 D14 D16 F13 F14 C15 C16 E15 E16 F15 F16 G14 G16 H15 H16 No Connect (NC)
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Chapter 2: Pinout Tables
Table 2-4:
Pin Description Pin Number G12 H11 H13 H14 J11 J12 J13 K14 K12 K11 J14 J16 K15 K16 N14 N16 M15 M16 L14 L16 P15 P16 R15 R16 R14 T15 T14 T13 R12 T12 L12 L13 M13 No Connect (NC)
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FT(G)256 Package-LX9, LX16, and LX25
Table 2-4:
Pin Description Pin Number M14 P14 L11 P13 R11 T11 M12 M11 P10 T10 N12 P12 N11 P11 N9 P9 L10 M10 R9 T9 M9 N8 P8 T8 P7 M7 R7 T7 P6 T6 R5 T5 N5 No Connect (NC)
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Chapter 2: Pinout Tables
Table 2-4:
Pin Description Pin Number P5 L8 L7 P4 T4 M6 N6 R3 T3 T2 M4 M3 M5 N4 R2 R1 P2 P1 N3 N1 M2 M1 L3 L1 K2 K1 J3 J1 H2 H1 G3 G1 F2 No Connect (NC)
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FT(G)256 Package-LX9, LX16, and LX25
Table 2-4:
Pin Description Pin Number F1 K3 J4 J6 H5 H4 H3 L4 L5 E2 E1 K5 K6 C3 C2 D3 D1 C1 B1 G6 G5 B2 A2 F4 F3 E4 E3 F6 F5 B3 A3 A1 A16 No Connect (NC)
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Chapter 2: Pinout Tables
Table 2-4:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Pin Description Pin Number B11 B7 D13 D4 E9 G15 G2 G8 H12 H7 H9 J5 J8 K7 K9 L15 L2 M8 N13 P3 R10 R6 T1 T16 E5 F11 F8 G10 H6 J10 L6 L9 G7 No Connect (NC)
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT
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FT(G)256 Package-LX9, LX16, and LX25
Table 2-4:
Pin Description Pin Number G9 H10 H8 J7 J9 K10 K8 B13 B4 B9 D10 D7 D15 G13 J15 K13 N15 R13 N10 N7 R4 R8 D2 G4 J2 K4 N2 No Connect (NC)
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Chapter 2: Pinout Tables
CSG324 Package-LX9, LX16, LX25, and LX45
Table 2-5:
CSG324 Package-LX9, LX16, LX25, and LX45
Pin Description Pin Number D4 C4 B2 A2 D6 C6 B3 A3 B4 A4 C5 A5 F7 E6 B6 A6 E7 E8 C7 A7 D8 C8 G8 F8 B8 A8 D9 C9 B9 A9 D11 LX9, LX25, LX45 LX9, LX25, LX45 LX9, LX25, LX45 LX9, LX25, LX45 LX9, LX25, LX45 LX9, LX25, LX45 No Connect (NC)
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CSG324 Package-LX9, LX16, LX25, and LX45
Table 2-5:
Pin Description Pin Number C11 C10 A10 G9 F9 B11 A11 G11 F10 B12 A12 F11 E11 D12 C12 C13 A13 F12 E12 B14 A14 F13 E13 C15 A15 D14 C14 B16 A16 A17 D15 B18 D16 LX9, LX45 LX9, LX45 LX9, LX45 LX9, LX45 LX9 LX9 LX9, LX45 LX9, LX45 LX9, LX45 LX9, LX45 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-5:
Pin Description Pin Number F15 F16 C17 C18 F14 G14 D17 D18 H12 G13 E16 E18 K12 K13 F17 F18 H13 H14 H15 H16 G16 G18 J13 K14 L12 L13 K15 K16 L15 L16 H17 H18 J16 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
CSG324 Package-LX9, LX16, LX25, and LX45
Table 2-5:
Pin Description Pin Number J18 K17 K18 L17 L18 M16 M18 N17 N18 P17 P18 N15 N16 T17 T18 U17 U18 M14 N14 L14 M13 P15 P16 R16 P13 V17 R15 T15 U16 V16 R13 T13 U15 LX9 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-5:
Pin Description Pin Number V15 T14 V14 N12 P12 U13 V13 M11 N11 R11 T11 T12 V12 N10 P11 M10 N9 U11 V11 R10 T10 U10 V10 R8 T8 T9 V9 M8 N8 U8 V8 U7 V7 LX9 LX9 LX9 LX9 LX9 LX9 LX9 LX9 LX9 LX9 No Connect (NC) LX9
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
CSG324 Package-LX9, LX16, LX25, and LX45
Table 2-5:
Pin Description Pin Number N7 P8 T6 V6 R7 T7 N6 P7 R5 T5 U5 V5 R3 T3 T4 V4 N5 P6 U3 V3 V2 N4 N3 P4 P3 L6 M5 U2 U1 T2 T1 P2 P1 LX9 LX9 No Connect (NC) LX9 LX9
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-5:
Pin Description Pin Number N2 N1 M3 M1 L2 L1 K2 K1 L4 L3 J3 J1 H2 H1 K4 K3 L5 K5 H4 H3 L7 K6 G3 G1 J7 J6 F2 F1 H6 H5 E3 E1 F4 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
CSG324 Package-LX9, LX16, LX25, and LX45
Table 2-5:
Pin Description Pin Number F3 D2 D1 H7 G6 E4 D3 F6 F5 C2 C1 A1 A18 B13 B7 C16 C3 D10 D5 E15 G12 G17 G2 G5 H10 H8 J11 J15 J4 J9 K10 K8 L11 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-5:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Pin Description Pin Number L9 M17 M2 M6 N13 R1 R14 R18 R4 R9 T16 U12 U6 V1 V18 B1 B17 E14 E5 E9 G10 J12 K7 M9 P10 P14 P5 G7 H11 H9 J10 J8 K11 No Connect (NC)
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
CSG324 Package-LX9, LX16, LX25, and LX45
Table 2-5:
Pin Description Pin Number K9 L10 L8 M12 M7 B10 B15 B5 D13 D7 E10 E17 G15 J14 J17 M15 R17 P9 R12 R6 U14 U4 U9 E2 G4 J2 J5 M4 R2 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
CSG324 Package-LX25T and LX45T
Table 2-6:
CSG324 Package-LX25T and LX45T
Pin Description Pin Number B2 A2 B3 A3 E6 F7 G8 E8 G9 G11 F12 E12 C15 A15 B16 A16 E14 D15 A17 F13 B18 D16 F15 F16 C17 C18 F14 G14 D17 D18 H12 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
CSG324 Package-LX25T and LX45T
Table 2-6:
Pin Description Pin Number G13 E16 E18 K12 K13 F17 F18 H13 H14 H15 H16 G16 G18 J13 K14 L12 L13 K15 K16 L15 L16 H17 H18 J16 J18 K17 K18 L17 L18 M16 M18 N17 N18 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-6:
Pin Description Pin Number P17 P18 N15 N16 T17 T18 U17 U18 M14 N14 L14 M13 P15 P16 R16 P13 V17 R15 T15 U16 V16 R13 T13 U15 V15 T14 V14 N12 P12 U13 V13 M11 N11 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
CSG324 Package-LX25T and LX45T
Table 2-6:
Pin Description Pin Number R11 T11 T12 V12 N10 P11 M10 N9 U11 V11 R10 T10 U10 V10 R8 T8 T9 V9 M8 N8 U8 V8 U7 V7 N7 P8 T6 V6 R7 T7 N6 P7 R5 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-6:
Pin Description Pin Number T5 U5 V5 R3 T3 T4 V4 N5 P6 U3 V3 V2 N4 N3 P4 P3 L6 M5 U2 U1 T2 T1 P2 P1 N2 N1 M3 M1 L2 L1 K2 K1 L4 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
CSG324 Package-LX25T and LX45T
Table 2-6:
Pin Description Pin Number L3 J3 J1 H2 H1 K4 K3 L5 K5 H4 H3 L7 K6 G3 G1 J7 J6 F2 F1 H6 H5 E3 E1 F4 F3 D2 D1 H7 G6 E4 D3 F6 F5 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-6:
Pin Description Pin Number C2 C1 A4 B4 B7 A8 B8 C5 D5 E7 C7 E5 D7 D10 C9 D9 A6 B6 A12 B12 B11 A10 B10 C11 D11 C13 D13 E11 E10 F10 A14 B14 A1 LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
CSG324 Package-LX25T and LX45T
Table 2-6:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Pin Description Pin Number A11 A18 A7 A9 B13 B5 B9 C10 C12 C14 C16 C4 C6 D8 E13 E15 F11 F9 G17 G2 G5 H10 H8 J11 J15 J4 J9 K10 K8 L11 L9 M17 M2 No Connect (NC)
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-6:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Pin Description Pin Number M6 N13 R1 R14 R18 R4 R9 T16 U12 U6 V1 V18 B1 B17 D14 D4 G10 J12 K7 M9 P10 P14 P5 G7 H11 H9 J10 J8 K11 K9 L10 L8 M12 No Connect (NC)
GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
CSG324 Package-LX25T and LX45T
Table 2-6:
Pin Description Pin Number M7 B15 C3 F8 G12 E17 G15 J14 J17 M15 R17 P9 R12 R6 U14 U4 U9 E2 G4 J2 J5 M4 R2 A5 A13 D6 D12 C8 E9 LX25T LX25T LX25T No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
FG(G)484 Package-LX25, LX45, LX75, LX100, and LX150
Data on the LX75 is not currently available. Table 2-7:
FG(G)484 Package-LX25, LX45, LX75, LX100, and LX150
Pin Description Pin Number A3 A4 C5 A5 D6 C6 B6 A6 C7 A7 B8 A8 D9 C8 C9 A9 E8 F8 G8 F9 G9 H10 E10 F10 G11 H11 D7 D8 D10 C10 LX25, LX45 LX25, LX45 LX25, LX45 LX25, LX45 LX25, LX45 LX25, LX45 LX25, LX45 LX25, LX45 LX25, LX45 LX25, LX45 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25, LX45, LX75, LX100, and LX150
Table 2-7:
Pin Description Pin Number B10 A10 C11 A11 D11 C12 B12 A12 C13 A13 E12 D12 H12 F12 F13 D13 H13 G13 E14 F15 F14 H14 D14 C14 B14 A14 C15 A15 D15 C16 B16 A16 C17 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-7:
Pin Description Pin Number A17 B18 A18 E16 D17 G15 E18 C18 A19 C19 B20 G16 G17 F16 F17 B21 B22 A20 A21 K16 J16 H16 H17 D19 D20 F18 F19 D21 D22 C20 C22 G19 F20 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25, LX45, LX75, LX100, and LX150
Table 2-7:
Pin Description Pin Number H19 H18 E20 E22 J17 K17 F21 F22 H20 J19 G20 G22 K20 K19 H21 H22 M20 L19 J20 J22 K21 K22 L20 L22 M21 M22 N20 N22 P21 P22 R20 R22 T21 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-7:
Pin Description Pin Number T22 U20 U22 V21 V22 M19 N19 M16 L15 P19 P20 W20 W22 L17 K18 U19 V20 M17 M18 P17 N16 P18 R19 T19 T20 P16 P15 R17 N15 Y20 Y22 Y21 AA22 LX25, LX45 LX25, LX45 LX25, LX45 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25, LX45, LX75, LX100, and LX150
Table 2-7:
Pin Description Pin Number AA21 AB21 AA20 AB20 T18 T17 Y19 AB19 W18 Y18 T16 T15 U17 U16 V19 V18 R16 R15 V17 W17 U14 U13 U15 V15 AA18 AB18 Y17 AB17 AA14 AB14 Y16 W15 V13 LX100 LX100 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-7:
Pin Description Pin Number W13 AA16 AB16 W14 Y14 Y15 AB15 T12 U12 T14 R13 W12 Y12 Y13 AB13 AA12 AB12 Y11 AB11 R11 T11 AA10 AB10 V11 W11 Y9 AB9 W10 Y10 AA8 AB8 W8 V7 LX25, LX100 LX25, LX100 LX25 LX25 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25, LX45, LX75, LX100, and LX150
Table 2-7:
Pin Description Pin Number W9 Y8 Y7 AB7 AA6 AB6 U9 V9 T8 U8 T10 U10 W6 Y6 Y5 AB5 AA4 AB4 Y3 AB3 R9 R8 T7 R7 W4 Y4 U6 V5 AA2 AB2 T6 T5 AA1 LX25, LX100 LX25, LX100 LX25, LX100 LX25, LX100 LX100 LX100 LX100 LX100 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-7:
Pin Description Pin Number Y2 Y1 W3 W1 P8 P7 P6 P5 T4 T3 U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4 M5 M4 V2 V1 U3 U1 T2 T1 R3 R1 P2 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25, LX45, LX75, LX100, and LX150
Table 2-7:
Pin Description Pin Number P1 N3 N1 M2 M1 L3 L1 K2 K1 J3 J1 M3 L4 K5 K4 K3 J4 K6 J6 H4 H3 H2 H1 G3 G1 H6 H5 F2 F1 G4 F3 E3 E1 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-7:
Pin Description Pin Number D2 D1 C3 C1 G6 F5 K7 K8 D5 E4 J7 H8 B2 B1 G7 F7 D3 C4 E5 E6 A2 B3 A1 A22 AA13 AA17 AA5 AA9 AB1 AB22 B13 B17 B5 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25, LX45, LX75, LX100, and LX150
Table 2-7:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Pin Description Pin Number B9 D18 D4 E11 E15 E2 E21 E7 G18 G5 H7 J11 J13 J15 J2 J21 J9 K10 K12 K14 L11 L13 L18 L5 L9 M10 M12 M14 N11 N13 N17 N2 N21 No Connect (NC)
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-7:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Pin Description Pin Number N9 P10 P12 P14 R18 R5 U2 U21 U7 V10 V14 V4 W16 W19 W7 D16 F11 G12 H15 H9 K15 L8 M15 N8 R10 R12 R6 U11 V6 J10 J12 J14 J8 No Connect (NC)
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25, LX45, LX75, LX100, and LX150
Table 2-7:
Pin Description Pin Number K11 K13 K9 L10 L12 L14 M11 M13 M9 N10 N12 N14 P11 P13 P9 R14 B11 B15 B19 B4 B7 E13 E17 E9 G10 G14 C21 E19 G21 J18 L16 L21 N18 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-7:
Pin Description Pin Number R21 U18 W21 AA11 AA15 AA19 AA3 AA7 T13 T9 V12 V16 V8 W5 C2 F4 F6 G2 J5 L2 L7 N5 R2 U5 W2 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25T, LX45T, LX75T, LX100T, and LX150T
Data on the LX75T is not currently available. Table 2-8:
FG(G)484 Package-LX25T, LX45T, LX75T, LX100T, and LX150T
Pin Description Pin Number C3 D3 D4 D5 B2 A2 E5 E6 B3 A3 C4 A4 F7 F8 C5 A5 A6 B6 B9 B10 A10 C7 D7 E9 C9 E8 D9 D12 D11 C11 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-8:
Pin Description Pin Number A8 B8 G8 F9 H10 H11 G9 F10 H12 G11 F14 F15 E16 F16 H13 G13 A14 B14 B13 B12 A12 C13 D13 C15 D15 E13 F12 E12 A16 B16 H14 G15 C17 LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25T, LX45T, LX75T, LX100T, and LX150T
Table 2-8:
Pin Description Pin Number A17 G16 F17 D18 D19 B18 A18 C19 A19 B20 A20 D17 C18 A21 E18 D20 G17 F18 F19 H16 H17 B21 B22 J16 J17 C20 C22 L15 K16 D21 D22 G19 F20 LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-8:
Pin Description Pin Number H18 H19 F21 F22 E20 E22 J19 H20 K19 K18 G20 G22 K17 L17 H21 H22 K20 L19 J20 J22 M20 M19 K21 K22 P20 N19 L20 L22 M21 M22 N20 N22 P21 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25T, LX45T, LX75T, LX100T, and LX150T
Table 2-8:
Pin Description Pin Number P22 R20 R22 T21 T22 U20 U22 V21 V22 W20 W22 Y21 Y22 P19 R19 M16 N15 U19 T20 N16 P16 M17 M18 R15 R16 P17 P18 R17 T17 T19 T18 V19 V20 LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-8:
Pin Description Pin Number U17 P15 T16 AA22 V18 AB21 Y20 AA21 V17 W18 AA20 AB20 U16 V15 W17 Y18 AA14 AB14 R13 T14 Y19 AB19 AA18 AB18 Y17 AB17 U14 U13 Y16 W15 V13 W13 AA16 LX25T LX25T No Connect (NC) LX25T, LX45T LX25T, LX45T LX25T, LX45T
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25T, LX45T, LX75T, LX100T, and LX150T
Table 2-8:
Pin Description Pin Number AB16 W14 Y14 Y15 AB15 R11 T11 T15 U15 T12 U12 Y13 AB13 AA12 AB12 Y11 AB11 W12 Y12 AA10 AB10 V11 W11 Y9 AB9 W10 Y10 AA8 AB8 T10 U10 Y7 AB7 LX25T LX25T LX25T LX25T No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-8:
Pin Description Pin Number W9 Y8 AA6 AB6 U9 V9 T8 U8 V7 W8 R9 R8 W6 Y6 Y5 AB5 AA4 AB4 T7 U6 Y4 AA3 AB2 R7 P8 W4 Y3 T6 T5 V5 V3 P5 P4 LX25T LX25T LX25T LX25T No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25T, LX45T, LX75T, LX100T, and LX150T
Table 2-8:
Pin Description Pin Number AA2 AA1 N6 N7 U4 T4 P6 P7 T3 R4 M7 M8 Y2 Y1 W3 W1 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1 N3 N1 M2 M1 L3 L1 P3 LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-8:
Pin Description Pin Number N4 M5 M4 M3 L4 M6 L6 K4 K3 K2 K1 J3 J1 K6 K5 H2 H1 J4 H3 G3 G1 F2 F1 E3 E1 J6 H5 K7 K8 H4 G4 D2 D1 LX25T LX25T LX25T LX25T No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25T, LX45T, LX75T, LX100T, and LX150T
Table 2-8:
Pin Description Pin Number F3 E4 H6 G7 J7 H8 F5 G6 C1 B1 A1 A11 A13 A22 A9 AA13 AA17 AA5 AA9 AB1 AB22 B11 B15 B17 B5 B7 C12 C14 C16 C6 C8 D10 D16 LX25T LX25T LX25T LX25T LX25T LX25T No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-8:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Pin Description Pin Number D6 E11 E14 E15 E2 E21 E7 F13 G18 G5 H7 J11 J13 J15 J2 J21 J9 K10 K12 K14 L11 L13 L18 L5 L9 M10 M12 M14 N11 N13 N17 N2 N21 No Connect (NC)
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25T, LX45T, LX75T, LX100T, and LX150T
Table 2-8:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Pin Description Pin Number N9 P10 P12 P14 R18 R5 U2 U21 U7 V10 V14 V4 W16 W19 W7 C10 E10 D8 D14 A7 A15 F11 G12 H15 H9 K15 L8 M15 N8 R10 R12 R6 U11 LX25T LX25T LX25T No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-8:
Pin Description Pin Number V6 J10 J12 J14 J8 K11 K13 K9 L10 L12 L14 M11 M13 M9 N10 N12 N14 P11 P13 P9 R14 B19 B4 E17 F6 G10 G14 C21 E19 G21 J18 L16 L21 No Connect (NC)
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Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)484 Package-LX25T, LX45T, LX75T, LX100T, and LX150T
Table 2-8:
Pin Description Pin Number N18 R21 U18 W21 AA11 AA15 AA19 AA7 AB3 T13 T9 V12 V16 V8 W5 C2 F4 G2 J5 L2 L7 N5 R2 U5 W2 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
CSG484 Package-LX45, LX75, LX100, and LX150
Table 2-9:
CSG484 Package-LX45, LX75, LX100, and LX150
Pin Description Pin Number No Connect (NC)
Data is not currently available on devices in this package.
CSG484 Package-LX45T, LX75T, LX100T, and LX150T
Table 2-10:
CSG484 Package-LX45T, LX75T, LX100T, and LX150T
Pin Description Pin Number No Connect (NC)
Data is not currently available on devices in this package.
FG(G)676 Package-LX45
Table 2-11:
FG(G)676 Package-LX45
Pin Description Pin Number A3 A2 B4 A4 C5 A5 B6 A6 C7 A7 B8 A8 C9 A9 D6 C6 C11 A11 B12 A12 No Connect (NC)
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Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)676 Package-LX45
Table 2-11:
Pin Description Pin Number C13 A13 B14 A14 D14 C14 C15 A15 B16 A16 C17 A17 D18 C18 D21 C20 B18 A18 C19 A19 B20 A20 C21 A21 B22 A22 E21 F20 C23 A24 B23 A23 B24 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-11:
Pin Description Pin Number A25 C25 C26 B25 B26 E25 E26 D24 D26 F24 F26 H24 H26 G25 G26 K24 K26 J25 J26 M24 M26 L25 L26 N25 N26 L19 K19 L23 L24 P20 N21 M23 N24 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)676 Package-LX45
Table 2-11:
Pin Description Pin Number L17 K18 P24 P26 M19 L18 R25 R26 M18 N19 N22 N23 N17 N18 R23 R24 N20 M21 P21 P22 V23 W24 U25 U26 W25 W26 V24 V26 T24 T26 Y24 Y26 AD24 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-11:
Pin Description Pin Number AD26 AB24 AB26 AC25 AC26 AA25 AA26 AE25 AE26 T23 U24 R20 R19 T22 U23 T18 T19 U21 U22 AA23 AA24 T20 U20 AC23 AC24 V18 V19 AE24 AF25 W18 W19 U17 V17 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)676 Package-LX45
Table 2-11:
Pin Description Pin Number U19 V20 V22 W22 Y20 Y21 Y22 AA22 AE23 AF24 AD23 AC22 AF23 AD22 AF22 AE21 AF21 AD20 AF20 AE19 AF19 AC20 AD21 Y18 AA19 AC19 AD19 V16 W17 AD18 AF18 Y16 AA17 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-11:
Pin Description Pin Number AA18 AB18 AE17 AF17 AD16 AF16 AE15 AF15 AB17 AC17 AC15 AD15 AC16 AD17 V15 W16 AB15 AC14 Y15 AA15 Y14 AA14 AD14 AF14 AE13 AF13 AC13 AD13 AD12 AF12 AA13 AB13 AA12 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)676 Package-LX45
Table 2-11:
Pin Description Pin Number AC12 U15 V14 AA11 AB11 V13 W14 AC11 AD11 V12 W12 AE11 AF11 AE9 AF9 AD10 AF10 U13 U12 Y10 AB10 V11 W11 AC9 AD9 AD8 AF8 AE7 AF7 AD6 AF6 AE5 AF5 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-11:
Pin Description Pin Number AE4 AF4 AF3 AC7 AD7 AE3 AF2 AC4 AD4 AA7 Y6 AB7 AB6 AC5 AD5 AA5 AB5 W8 W7 AB4 AC3 AA4 AA3 W5 Y5 U8 U7 U5 V5 U4 U3 T8 T6 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)676 Package-LX45
Table 2-11:
Pin Description Pin Number R5 T4 R7 R6 AB3 AB1 AD3 AD1 AC2 AC1 AE2 AE1 AA2 AA1 Y3 Y1 W2 W1 V3 V1 U2 U1 T3 T1 V4 W3 N8 P8 R2 R1 P7 P6 R4 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-11:
Pin Description Pin Number R3 N7 N6 P3 P1 P10 R9 P5 N5 M10 N9 N4 N3 M9 M8 L4 L3 M6 M4 L7 L6 N2 N1 M3 M1 L2 L1 K3 K1 J2 J1 H3 H1 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)676 Package-LX45
Table 2-11:
Pin Description Pin Number G2 G1 F3 F1 E2 E1 D3 D1 E4 E3 C2 C1 B2 B1 C4 C3 A1 A26 AB12 AB16 AB2 AB20 AB25 AC8 AE10 AE14 AE18 AE22 AE6 AF1 AF26 B13 B17 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-11:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Pin Description Pin Number B21 B5 B9 D4 E11 E15 E22 E7 F19 F2 F25 H11 H23 H4 J19 J8 K16 K2 K25 L11 L13 L15 M12 M14 M16 M22 M5 N11 N13 N15 P12 P14 P16 No Connect (NC)
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
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Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)676 Package-LX45
Table 2-11:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Pin Description Pin Number P19 P2 P25 R11 R13 R15 R8 T12 T14 T16 T21 T5 U11 V2 V25 W15 W20 Y11 Y23 Y4 Y7 AA10 AA16 AA21 AA6 F21 F6 G12 G15 J18 J9 K13 L22 No Connect (NC)
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-11:
Pin Description Pin Number L5 M17 N10 U14 U6 V9 Y19 K11 K17 L10 L12 L14 L16 M11 M13 M15 N12 N14 N16 P11 P13 P15 R12 R14 R16 T11 T13 T15 T17 U10 U16 B11 B15 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)676 Package-LX45
Table 2-11:
Pin Description Pin Number B19 B3 B7 C22 D17 D9 E13 G10 G18 H14 AB23 AD25 M20 P23 T25 U18 V21 W23 Y25 AB14 AC10 AC18 AC21 AE12 AE16 AE20 AE8 Y12 Y17 AC6 AD2 M7 P4 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-11:
Pin Description Pin Number P9 T2 T7 W4 W6 Y2 D2 F4 H2 J6 K4 M2 D25 F23 H25 J21 K23 M25 A10 AA20 AA8 AB19 AB8 C10 C12 C16 C24 C8 B10 D10 D11 D12 D13 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 No Connect (NC)
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)676 Package-LX45
Table 2-11:
Bank NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
Pin Description Pin Number D15 D16 D19 D20 D22 D23 D5 D7 D8 E10 E12 E14 E16 E17 E18 E19 E20 E23 E24 E5 E6 E8 E9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F22 No Connect (NC) LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45
No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-11:
Bank NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
Pin Description Pin Number F5 F7 F8 F9 G11 G13 G14 G16 G17 G19 G20 G21 G22 G23 G24 G3 G4 G5 G6 G7 G8 G9 H10 H12 H13 H15 H16 H17 H18 H19 H20 H21 H22 No Connect (NC) LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45
No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect
www.xilinx.com
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)676 Package-LX45
Table 2-11:
Bank NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
Pin Description Pin Number H5 H6 H7 H8 H9 J10 J11 J12 J13 J14 J15 J16 J17 J20 J22 J23 J24 J5 J7 K10 K12 K14 K15 K20 K21 K22 K5 K6 K7 K8 K9 L20 L21 No Connect (NC) LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45
No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com
Chapter 2: Pinout Tables
Table 2-11:
Bank NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
Pin Description Pin Number J3 J4 L8 L9 P17 P18 R10 R17 R18 R21 R22 T10 T9 AA9 AB9 U9 V10 W10 W13 W21 W9 Y13 Y8 Y9 V6 V7 V8 AB21 AB22 No Connect (NC) LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45
No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect
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Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
FG(G)676 Package-LX75, LX100, and LX150
Data on the LX75 is not currently available. Table 2-12:
FG(G)676 Package-LX75, LX100, and LX150
Pin Description Pin Number A3 A2 B4 A4 E6 D5 C5 A5 G8 F7 B6 A6 G9 F8 D6 C6 K12 J11 H10 H9 C7 A7 E8 D7 D8 C8 F9 E9 B8 A8 LX100 LX100 LX100 LX100 LX100 LX100 No Connect (NC)
Spartan-6 FPGA Packaging (Advance Spec) UG385 (v1.0) June 24, 2009
www.xilinx.com