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UG366 (v1.0) June 2009 [optional]
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Revision History
following table shows revision history this document.
Date 06/24/09 Version Initial Xilinx release. Revision
Virtex-6 FPGA Transceivers User Guide
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UG366 (v1.0) June 2009
Table Contents
Revision History
Preface: About This Guide
Guide Contents Additional Documentation Additional Resources
Chapter Transceiver Tool Overview
Overview Port Attribute Summary Virtex-6 FPGA Transceiver Wizard Simulation
Functional Description Ports Attributes SIM_GTXRESET_SPEEDUP SIM_RECEIVER_DETECT_PASS SIM_RXREFCLK_SOURCE. SIM_TXREFCLK_SOURCE SIM_VERSION SIM_TX_ELEC_IDLE_LEVEL Functional Description FF484 Package Placement Diagrams FF784 Package Placement Diagrams FF1156 Package Placement Diagrams FF1759 Package Placement Diagrams
Implementation
Chapter Shared Transceiver Features
Reference Clock Selection
Functional Description Ports Attributes
Single External Reference Clock Model
Functional Description Ports Attributes Settings Common Protocols
Power Down
Functional Description Ports Attributes Generic Power-Down Capabilities Power Down Power Down Power-Down Features Express Operation
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Power-Down Transition Times
Loopback
Functional Description Ports Attributes
Dynamic Reconfiguration Port
Functional Description Ports Attributes
Chapter Transmitter
Overview FPGA Interface
Functional Description Interface Width Configuration TXUSRCLK TXUSRCLK2 Generation Ports Attributes
Initialization
Functional Description Ports Attributes
8B/10B Encoder
Functional Description 8B/10B Byte Ordering Characters Running Disparity Ports Attributes Enabling Disabling 8B/10B Encoding Functional Description Ports Attributes Enabling Gearbox Gearbox Byte Ordering Gearbox Operating Modes External Sequence Counter Operating Mode Internal Sequence Counter Operating Mode Functional Description Ports Attributes Using Buffer Using Buffer Oversampling Mode Functional Description Ports Attributes Using Phase-Alignment Circuit Bypass Buffer Using Phase Alignment Circuit Minimize Lane-to-Lane Skew
Gearbox
Buffer
Buffer Bypass
Pattern Generator
Functional Description Ports Attributes Models
Oversampling
Functional Description Ports Attributes
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Polarity Control
Functional Description Ports Attributes Using Polarity Control
Clock Divider Control
Functional Description Serial Clock Divider Parallel Clock Divider Selector Ports Attributes Express Clocking Mode
Configurable Driver
Functional Description Ports Attributes Modes Driver General PCIe Mode Customizable User Presets Mode Resistor Calibration
Receiver Detect Support Express Designs
Functional Description Ports Attributes
Out-of-Band Signaling
Functional Description Ports Attributes
Chapter Receiver
Overview Analog Front
Functional Description Ports Attributes Modes Termination Mode Resistor Calibration
Out-of-Band Signaling
Functional Description Ports Attributes
Equalizer
Functional Description Ports Attributes Mode Continuous Time Linear Equalizer
Functional Description Ports Attributes
Clock Divider Control
Functional Description Serial Clock Divider Parallel Clock Divider Selector Ports Attributes
Margin Analysis
Functional Description Horizontal Margin Scan
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Ports Attributes
Polarity Control
Functional Description Ports Attributes Using Polarity Control
Oversampling
Feature Description Ports Attributes
Pattern Checker
Functional Description Ports Attributes Models
Byte Word Alignment
Functional Description Enabling Comma Alignment Configuring Comma Patterns Activating Comma Alignment Alignment Status Signals Alignment Boundaries Ports Attributes
Loss-of-Sync State Machine
Functional Description Ports Attributes
8B/10B Decoder
Functional Description 8B/10B Decoder Byte Order Running Disparity
Buffer Bypass
Functional Description Ports Attributes Using Phase Alignment Circuit Bypass Buffer
Elastic Buffer
Functional Description Ports Attributes Using Elastic Buffer Channel Bonding Clock Correction
Clock Correction
Functional Description Ports Attributes Using Clock Correction Enabling Clock Correction Setting Elastic Buffer Limits Setting Clock Correction Sequences Clock Correction Options Monitoring Clock Correction Functional Description Ports Attributes Using Channel Bonding Enabling Channel Bonding Channel Bonding Mode Connecting Channel Bonding Ports
Channel Bonding
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Setting Channel Bonding Sequences Setting Maximum Skew Precedence between Channel Bonding Clock Correction
Gearbox
Functional Description Ports Attributes Enabling Gearbox Gearbox Operating Modes Gearbox Block Synchronization
Initialization
Functional Description Ports Attributes
FPGA Interface
Functional Description Interface Width Configuration RXUSRCLK RXUSRCLK2 Generation Ports Attributes
Chapter Board Design Guidelines
Overview Description Design Guidelines
Transceiver Descriptions Termination Resistor Calibration Circuit Managing Unused Transceivers Analog Power Supply Pins Unused Quad Column Partially Unused Quad Column Partially Used Quad Quad Usage Priority Overview Reference Clock Checklist Reference Clock Interface LVDS. LVPECL Coupled Reference Clock Unused Reference Clocks Reference Clock Power Overview Power Supply Regulators Linear Switching Regulators Linear Regulator Switching Regulator Power Supply Distribution Network Staged Decoupling Power Supply Decoupling Capacitors Printed Circuit Board Design Board Stackup Transceiver Power Connections Signal Breakout
Reference Clock
Power Supply Filtering
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Crosstalk
SelectIO Usage Guidelines
Appendix 8B/10B Valid Characters
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Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
Preface
About This Guide
This document shows transceivers Virtex®-6 FPGAs. this document: Virtex-6 FPGA transceiver abbreviated transceiver. GTXE1 name instantiation primitive that instantiates Virtex-6 FPGA transceiver. Quad cluster four transceivers that share differential reference clock pairs analog supply pins.
Guide Contents
This manual contains following chapters: Chapter "Transceiver Tool Overview" Chapter "Shared Transceiver Features" Chapter "Transmitter" Chapter "Receiver" Chapter "Board Design Guidelines" Appendix "8B/10B Valid Characters"
Additional Documentation
following documents also available download http://www.xilinx.com/6. Virtex-6 Family Overview features product selection Virtex-6 family outlined this overview. Virtex-6 FPGA Data Sheet: Switching Characteristics This data sheet contains Switching Characteristic specifications Virtex-6 family. Virtex-6 FPGA Packaging Pinout User Guide This specification includes tables device/package combinations maximum I/Os, definitions, pinout tables, pinout diagrams, mechanical drawings, thermal specifications. Virtex-6 FPGA Configuration User Guide This all-encompassing configuration guide includes chapters configuration interfaces (serial SelectMAP), bitstream encryption, boundary-scan JTAG
Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
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Preface: About This Guide
configuration, reconfiguration techniques, readback through SelectMAP JTAG interfaces. Virtex-6 FPGA SelectIO Resources User Guide This guide describes SelectIOresources available Virtex-6 devices. Virtex-6 FPGA Clocking Resources User Guide This guide describes clocking resources available Virtex-6 devices, including MMCM PLLs. Virtex-6 FPGA Memory Resources User Guide functionality block FIFO described this user guide. Virtex-6 FPGA Configurable Logic Blocks User Guide This guide describes capabilities configurable logic blocks (CLBs) available Virtex-6 devices. Virtex-6 FPGA DSP48E1 Slice User Guide This guide describes DSP48E1 slice available Virtex-6 FPGAs. Virtex-6 FPGA Embedded Tri-Mode Ethernet MACs User Guide This guide describes dedicated Tri-Mode Ethernet Media Access Controller available Virtex-6 FPGAs except XC6VLX760. Virtex-6 FPGA System Monitor User Guide System Monitor functionality available Virtex-6 devices outlined this guide. Virtex-6 FPGA Designer's Guide This guide provides information design Virtex-6 FPGA transceivers, with focus strategies making design decisions interface level.
Additional Resources
find additional documentation, Xilinx website search Answer Database silicon, software, questions answers, create technical support WebCase, Xilinx website http://www.xilinx.com/support.
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Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
Chapter
Transceiver Tool Overview
Overview
Virtex®-6 FPGA transceiver power-efficient transceiver. transceiver highly configurable tightly integrated with programmable logic resources FPGA. provides following features support wide variety applications: Current Mode Logic (CML) serial drivers/buffers with configurable termination, voltage swing Programmable pre-emphasis/post-emphasis, equalization, linear decision feedback equalization (DFE) optimized signal integrity. Line rates from Mb/s Gb/s, with optional digital oversampling required rates between Mb/s Mb/s. Optional built-in features, such 8B/10B encoding, comma alignment, channel bonding, clock correction. Fixed latency modes minimized, deterministic datapath latency. Beacon signaling Express® designs Out-of-Band signaling including signal support SATA designs. RX/TX Gearbox provides header insertion extraction support 64B/66B 64B/67B (Interlaken) protocols. Receiver scan Horizontal scan time domain testing purposes first-time user recommended read High-Speed Serial Made Simple, which discusses high-speed serial transceiver technology applications. Xilinx® CORE Generatortool includes Wizard automatically configure transceivers support configurations different protocols perform custom configuration (see "Virtex-6 FPGA Transceiver Wizard," page 28). transceiver offers data rate range features that allow physical layer support various protocols. Figure illustrates block view Virtex-6 FPGA transceiver.
Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
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Chapter Transceiver Tool Overview
X-Ref Target Figure
Driver PCIe
Pre/ Post
Gearbox Pattern Generator Phase Adjust FIFO Oversampling PIPE Control FPGA Interface
PISO
Polarity
PCIe Beacon SATA
TX-PMA
Parallel Data (Near-End Loopback) From Parallel Data (Far-End Loopback) From Parallel Data (Far-End Loopback)
TX-PCS
Pattern Checker
Loss Sync
Polarity
Comma Detect Align
PIPE Control FPGA Interface
Status Control Gearbox Elastic Buffer
Oversampling SIPO
RX-PMA
RX-PCS
UG366_c1_01_051509
Figure 1-1:
Virtex-6 FPGA Transceiver Simplified Block Diagram
Details about different functional blocks transmitter receiver including their models described Chapter "Transmitter," Chapter "Receiver." Figure shows transceiver placement example Virtex-6 device (XC6VLX75T). Additional information functional blocks Figure available following locations:
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Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
Overview
Virtex-6 FPGA Configuration User Guide provides more information Configuration Clock, MMCM, blocks. Virtex-6 FPGA Embedded Tri-Mode Ethernet MACs User Guide provides detailed information Ethernet MAC.
Figure illustrates location transceiver inside Virtex-6 XC6VLX75T FPGA.
X-Ref Target Figure
Virtex-6 FPGA (XC6VLX75T) GTXE1 Column GTXE1_ X0Y11
MMCM
Ethernet Ethernet
GTXE1_ X0Y10 GTXE1_ X0Y9 GTXE1_ X0Y8 GTXE1_ X0Y7 GTXE1_ X0Y6 GTXE1_ X0Y5 GTXE1_ X0Y4 GTXE1_ X0Y3 GTXE1_ X0Y2
Column
Column
MMCM
Column
Integrated Block Express Operation
Configuration
MMCM
Ethernet Ethernet
GTXE1_ X0Y1 GTXE1_ X0Y0
UG366_c1_02_051509
Figure 1-2: Transceiver Inside Virtex-6 XC6VLX75T FPGA transceivers clustered together four called Quad Figure illustrates clustering four transceivers Quad. Refer "Implementation," page placement information mapping each transceiver into specific Quad.
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Chapter Transceiver Tool Overview
X-Ref Target Figure
From/To Adjacent Quad
FPGA Logic
TX-P2S
From FPGA Logic
CLKs
DFE, CDR,
CLKs
FPGA Logic
TX-P2S
From FPGA Logic
CLKs
DFE, CDR,
CLKs
MGTREFCLK0 MGTREFCLK1
FPGA Logic
TX-P2S
From FPGA Logic
CLKs
DFE, CDR,
CLKs
FPGA Logic
TX-P2S
From FPGA Logic
CLKs
DFE, CDR,
CLKs
From/To Adjacent Quad
UG366_c1_03_051509
Figure 1-3:
Quad Configuration
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Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
Port Attribute Summary
This cluster four transceivers share differential reference clock pairs clock routing. Chapter "Shared Transceiver Features," discusses details about reference clock sources routing.
Port Attribute Summary
ports attributes grouped tables each functionality group (e.g., reference clock selection). port attribute appears multiple chapters, listed group first appearance. Table summarizes ports attributes according functionality group. Table 1-1: Port Attribute Summary
Port/Attribute Simulation Attributes: SIM_GTXRESET_SPEEDUP SIM_RECEIVER_DETECT_PASS SIM_RXREFCLK_SOURCE SIM_TX_ELEC_IDLE_LEVEL SIM_TXREFCLK_SOURCE SIM_VERSION page page page page page page Section, Page
Clocking Ports: GREFCLKRX GREFCLKTX MGTREFCLKRX[1:0] MGTREFCLKTX[1:0] NORTHREFCLKRX[1:0] NORTHREFCLKTX[1:0] PERFCLKRX PERFCLKTX SOUTHREFCLKRX[1:0] SOUTHREFCLKTX[1:0] TXPLLREFSELDY[2:0] page page page page page page page page page page page page page page
Attributes: PMA_CAS_CLK_EN SIM_RXREFCLK_SOURCE[2:0] SIM_TXREFCLK_SOURCE[2:0]
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Chapter Transceiver Tool Overview
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Ports: PLLTXRESET PLLRXRESET TXPLLLKDET RXPLLLKDET TXPLLLKDETEN RXPLLLKDETEN TXPLLPOWERDOWN RXPLLPOWERDOWN TX_CLK_SOURCE TX_TDCC_CFG TXPLL_COM_CFG RXPLL_COM_CFG TXPLL_CP_CFG RXPLL_CP_CFG TXPLL_DIVSEL_FB RXPLL_DIVSEL_FB TXPLL_DIVSEL_OUT RXPLL_DIVSEL_OUT TXPLL_DIVSEL_REF RXPLL_DIVSEL_REF TXPLL_DIVSEL45_FB RXPLL_DIVSEL45_FB TXPLL_LKDET_CFG RXPLL_LKDET_CFG TXPLL_SATA page page page page page page page page page page page page page page page page page page page page page page page page page
Attributes:
Power Down Ports: RXPLLPOWERDOWN RXPOWERDOWN[1:0] TXPDOWNASYNCH TXPLLPOWERDOWN TXPOWERDOWN[1:0] POWER_SAVE TRANS_TIME_FROM_P2 TRANS_TIME_NON_P2 TRANS_TIME_RATE TRANS_TIME_TO_P2 page page page page page page page page page page
Attributes:
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Port Attribute Summary
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Loopback Attributes: LOOPBACK[2:0] Ports: DADDR[6:0] DCLK DI[15:0] DO[15:0] DRDY page page page page page page page page
FPGA Interface Ports: MGTREFCLKFAB[1:0] TXCHARDISPMODE[3:0] TXCHARDISPVAL[3:0] TXDATA[31:0] TXUSRCLK TXUSRCLK2 page page page page page page page page
Attributes: GEN_TXUSRCLK TX_DATA_WIDTH Initialization Ports: GTXTEST[12:0] GTXTXRESET PLLTXRESET TSTIN[19:0] TXDLYALIGNRESET TXRESET TXRESETDONE page page page page page page page page
Attributes: TX_EN_RATE_RESET_BUF
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Chapter Transceiver Tool Overview
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Encoder Ports: TXBYPASS8B10B[3:0] TXCHARDISPMODE[3:0] TXCHARDISPVAL[3:0] TXCHARISK[3:0] TXENC8B10BUSE TXKERR[3:0] TXRUNDISP[3:0] page page page page page page page
Gearbox Ports: TXGEARBOXREADY TXHEADER[2:0] TXSEQUENCE[6:0] TXSTARTSEQ page page page page page page
Attributes: GEARBOX_ENDEC TXGEARBOX_USE Buffer Ports: TXBUFSTATUS[2:0] TXRESET Attributes: TX_BUFFER_USE TX_OVERSAMPLE_MODE Buffer Bypass Ports: TXDLYALIGNDISABLE TXDLYALIGNMONITOR[7:0] TXDLYALIGNOVERRIDE TXDLYALIGNRESET TXDLYALIGNUPDSW TXENPMAPHASEALIGN TXOUTCLK TXPLLLKDET TXPLLLKDETEN TXPMASETPHASE TXUSRCLK page page page page page page page page page page page page page page page
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Port Attribute Summary
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Attributes: TX_BUFFER_USE TX_BYTECLK_CFG[5:0] TX_DATA_WIDTH TX_DLYALIGN_CTRINC TX_DLYALIGN_LPFINC TX_DLYALIGN_MONSEL TX_DLYALIGN_OVRDSETTING TX_PMADATA_OPT TX_XCLK_SEL TXOUTCLK_CTRL page page page page page page page page page page
Pattern Generator Ports: TXENPRBSTST[2:0] TXPRBSFORCEERR Attributes: RXPRBSERR_LOOPBACK Oversampling Attributes: PMA_RX_CFG TX_OVERSAMPLE_MODE Polarity Control Ports: TXPOLARITY Clock Divider Control Ports: MGTREFCLKFAB[0] ODIV2 PHYSTATUS TXOUTCLK TXOUTCLKPCS TXRATE TXRATEDONE TRANS_TIME_RATE TX_EN_RATE_RESET_BUF TXOUTCLK_CTRL TXPLL_DIVSEL_OUT page page page page page page page page page page page page page page page page page page
Attributes:
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Chapter Transceiver Tool Overview
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Configurable Driver Ports: TXBUFDIFFCTRL[2:0] TXDEEMPH TXDIFFCTRL[3:0] TXELECIDLE TXINHIBIT TXMARGIN[2:0] TXPDOWNASYNCH TXPOSTEMPHASIS[4:0] TXPREEMPHASIS[3:0] TXSWING TX_DEEMPH_0[4:0] TX_DEEMPH_1[4:0] TX_DRIVE_MODE TX_MARGIN_FULL_0[6:0] TX_MARGIN_FULL_1[6:0] TX_MARGIN_FULL_2[6:0] TX_MARGIN_FULL_3[6:0] TX_MARGIN_FULL_4[6:0] TX_MARGIN_LOW_0[6:0] TX_MARGIN_LOW_1[6:0] TX_MARGIN_LOW_2[6:0] TX_MARGIN_LOW_3[6:0] TX_MARGIN_LOW_4[6:0] page page page page page page page page page page page page page page page page page page page page page page page page
Attributes:
Receiver Detect Support Express Designs Ports: PHYSTATUS RXPOWERDOWN[1:0] TXPOWERDOWN[1:0] RXSTATUS[2:0] TXDETECTRX page page page page page
Ports: TXCOMINIT TXCOMSAS TXCOMWAKE TXELECIDLE[1:0] TXPOWERDOWN[1:0] page page page page page
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Port Attribute Summary
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Attributes: COM_BURST_VAL TXPLL_SATA Ports: Attributes: AC_CAP_DIS CM_TRIM[1:0] RCV_TERM_GND RCV_TERM_VTTRX TERMINATION_CTRL[4:0] TERMINATION_OVRD page page page page page page page page page page
Ports: COMINITDET COMSASDET COMWAKEDET RXELECIDLE RXSTATUS[2:0] RXVALID SAS_MAX_COMSAS SAS_MIN_COMSAS SATA_BURST_VAL SATA_IDLE_VAL SATA_MAX_BURST SATA_MAX_INIT SATA_MAX_WAKE SATA_MIN_BURST SATA_MIN_INIT SATA_MIN_WAKE page page page page page page page page page page page page page page page page
Attributes:
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Chapter Transceiver Tool Overview
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Equalizer Ports: DFECLKDLYADJ[5:0] DFECLKDLYADJMON[5:0] DFEDLYOVRD DFEEYEDACMON[4:0] DFESENSCAL[2:0] DFETAP1[4:0] DFETAP1MONITOR[4:0] DFETAP2[4:0] DFETAP2MONITOR[4:0] DFETAP3[3:0] DFETAP3MONITOR[3:0] DFETAP4[3:0] DFETAP4MONITOR[3:0] DFETAPOVRD RXEQMIX[9:0] page page page page page page page page page page page page page page page page page page
Attributes: DFE_CAL_TIME[4:0] DFE_CFG[7:0] RX_EN_IDLE_HOLD_DFE Ports: RXCDRRESET RXRATE[1:0] Attributes: CDR_PH_ADJ_TIME PMA_CDR_SCAN PMA_RX_CFG RX_EN_IDLE_HOLD_CDR RX_EN_IDLE_RESET_FR RX_EN_IDLE_RESET_PH RX_EYE_SCANMODE RXPLL_DIVSEL_OUT page page page page page page page page page page
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Port Attribute Summary
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Clock Divider Control Ports: MGTREFCLKFAB[1] ODIV2 PHYSTATUS RXRATE RXRATEDONE RXRECCLK RXRECCLKPCS RX_EN_RATE_RESET_BUF RXPLL_DIVSEL_OUT RXRECCLK_CTRL TRANS_TIME_RATE page page page page page page page page page page page page
Attributes:
Margin Analysis Ports: RXDATA[31:0] Attributes: RX_EYE_OFFSET RX_EYE_SCANMODE Polarity Control Ports: RXPOLARITY Oversampling Ports: RXENSAMPLEALIGN RXOVERSAMPLER Attributes: PMA_RX_CFG RX_OVERSAMPLE_MODE Pattern Checker Ports: PRBSCNTRESET RXENPRBSTST[2:0] RXPRBSERR Attributes: RX_PRBS_ERR_CNT RXPRBSERR_LOOPBACK page page page page page page page page page page page page page
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Chapter Transceiver Tool Overview
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Byte Word Alignment Ports: RXBYTEISALIGNED RXBYTEREALIGN RXCOMMADET RXCOMMADETUSE RXENMCOMMAALIGN RXENPCOMMAALIGN page page page page page page page page page
Attributes: ALIGN_COMMA_WORD COMMA_10B_ENABLE COMMA_DOUBLE Loss-of-Sync State Machine Ports: RXLOSSOFSYNC Attributes: RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM Buffer Bypass Ports: RXDLYALIGNDISABLE RXDLYALIGNMONITOR[7:0] RXDLYALIGNOVERRIDE RXDLYALIGNRESET RXDLYALIGNSWPPRECURB RXDLYALIGNUPDSW RXENPMAPHASEALIGN RXPLLLKDET RXPLLLKDETEN RXPMASETPHASE RXRECCLK RXUSRCLK page page page page page page page page page page page page page page page page
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Port Attribute Summary
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Attributes: RX_BUFFER_USE RX_DATA_WIDTH RX_DLYALIGN_CTRINC RX_DLYALIGN_EDGESET RX_DLYALIGN_LPFINC RX_DLYALIGN_MONSEL RX_DLYALIGN_OVRDSETTING RX_XCLK_SEL RXRECCLK_CTRL RXUSRCLK_DLY page page page page page page page page page page
Elastic Buffer Ports: RXBUFRESET RXBUFSTATUS[2:0] Attributes: RX_BUFFER_USE RX_EN_IDLE_RESET_BUF RX_FIFO_ADDR_MODE RX_IDLE_HI_CNT RX_IDLE_LO_CNT RX_XCLK_SEL page page page page page page page page
Clock Correction Ports: RXBUFRESET RXBUFSTATUS[2:0] RXCLKCORCNT[2:0] page page page
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Chapter Transceiver Tool Overview
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Attributes: CLK_COR_ADJ_LEN CLK_COR_DET_LEN CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_MAX_LAT CLK_COR_MIN_LAT CLK_COR_PRECEDENCE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_1_ENABLE CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_ENABLE CLK_COR_SEQ_2_USE CLK_CORRECT_USE RX_DATA_WIDTH RX_DECODE_SEQ_MATCH page page page page page page page page page page page page page page page page page page page page page page
Channel Bonding Ports: RXCHANBONDSEQ RXCHANISALIGNED RXCHANREALIGN RXCHBONDI[3:0] RXCHBONDO[3:0] RXCHBONDLEVEL[2:0] RXCHBONDMASTER RXCHBONDSLAVE RXENCHANSYNC page page page page page page page page page
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Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
Port Attribute Summary
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Attributes: CHAN_BOND_1_MAX_SKEW CHAN_BOND_2_MAX_SKEW CHAN_BOND_KEEP_ALIGN CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_1_ENABLE CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_ENABLE CHAN_BOND_SEQ_2_CFG CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN PCI_EXPRESS_MODE RX_DATA_WIDTH page page page page page page page page page page page page page page page page page page
Gearbox Ports: RXDATAVALID RXGEARBOXSLIP RXHEADER[2:0] RXHEADERVALID RXSTARTOFSEQ page page page page page page page
Attributes: GEARBOX_ENDEC RXGEARBOX_USE Initialization Ports: GTXRXRESET GTXTEST[12:0] PLLRXRESET RXBUFRESET RXCDRRESET RXDLYALIGNRESET RXRESET RXRESETDONE TSTIN[19:0] page page page page page page page page page
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Chapter Transceiver Tool Overview
Table 1-1:
Port Attribute Summary (Cont'd)
Port/Attribute Section, Page
Attributes: CDR_PH_ADJ_TIME[4:0] RX_EN_IDLE_HOLD_CDR RX_EN_IDLE_HOLD_DFE RX_EN_IDLE_RESET_BUF RX_EN_IDLE_RESET_PH RX_EN_IDLE_RESET_FR RX_EN_MODE_RESET_BUF RX_EN_RATE_RESET_BUF RX_EN_REALIGN_RESET_BUF RX_IDLE_HI_CNT[3:0] RX_IDLE_LO_CNT[3:0] page page page page page page page page page page page
FPGA Interface Ports: MGTREFCLKFAB[1:0] RXCHARISK[3:0] RXDATA[31:0] RXDISPERR[3:0] RXUSRCLK RXUSRCLK2 page page page page page page page page
Attributes: GEN_RXUSRCLK RX_DATA_WIDTH
Virtex-6 FPGA Transceiver Wizard
Virtex-6 FPGA Transceiver Wizard preferred tool generate wrapper instantiate transceiver primitive called GTXE1. Wizard found Xilinx CORE Generatortool. sure download most up-to-date Update before using Wizard. Details this Wizard found Virtex-6 FPGA ransceiver Getting Started Guide. Start Xilinx CORE Generator tool. Locate Transceiver Wizard taxonomy tree under:
/FPGA Features Design/IO Interfaces
Figure 1-4.
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Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
Simulation
X-Ref Target Figure
UG366_c1_04_051509
Figure 1-4:
Virtex-6 FPGA Transceiver Wizard
Double-click Wizard launch Wizard.
Simulation
Functional Description
Simulations using transceivers have specific prerequisites that simulation environment test bench must fulfill. Synthesis Simulation Design Guide explains simulation environment supported simulators depending used Hardware Description Language (HDL). This design guide downloaded from Xilinx website. prerequisites simulating design with transceivers are: Simulator with support SecureIP models, which encrypted versions Verilog used implementation modeled block. SecureIP encryption methodology. support SecureIP models, Verilog IEEE 1364-2005 encryption compliant simulator required.
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Mixed-language simulator VHDL simulation. SecureIP models Verilog standard. them VHDL design, mixedlanguage simulator required. simulator must capable simulating VHDL Verilog simultaneously.
Installed SecureIP model. Correct setup simulator SecureIP (initialization file, environment variable(s)). Running COMPXLIB (which compiles simulation libraries (e.g. UNISIM, SIMPRIMS, etc.) correct order. Correct simulator resolution (Verilog) user guide simulator Synthesis Simulation Design Guide provide detailed list settings SecureIP support.
Ports Attributes
There simulation-only ports. GTXE1 primitive attributes intended only simulation. Table lists simulation-only attributes GTXE1 primitive. names these attributes start with SIM_. Table 1-2: GTXE1 Simulation-Only Attributes
Attribute SIM_GTXRESET_SPEEDUP Type Integer Description This attribute shortens time takes finish GTXRESET sequence lock during simulation. GTXRESET sequence simulated with original duration (standard initialization approximately µs). Shorten GTXRESET cycle time (fast initialization approximately ns). SIM_RECEIVER_DETECT_PASS Boolean This attribute simulates TXDETECTRX feature transceiver. TRUE: Simulates connection serial ports. TXDETECTRX initiates receiver detection, RXSTATUS[2:0] reports that port connected. FALSE (default): Simulates disconnected port. TXDETECTRX initiates receiver detection, RXSTATUS[2:0] reports that port connected.
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Simulation
Table 1-2:
GTXE1 Simulation-Only Attributes (Cont'd)
Attribute Type Description
SIM_RXREFCLK_SOURCE
3-Bit Binary This attribute selects reference clock source used drive simulation designs where always driven same reference clock source. RXPLLREFSELDY port must this attribute select reference clock source. multi-rate designs that require reference clock source changed fly, RXPLLREFSELDY port used dynamically select source instead. 000: Selects MGTREFCLKRX[0] port source 001: Selects MGTREFCLKRX[1] port source 010: Selects NORTHREFCLKRX[0] port source 011: Selects NORTHREFCLKRX[1] port source 100: Selects SOUTHREFCLKRX[0] port source 101: Selects SOUTHREFCLKRX[1] port source 110: Reserved 111: Selects clock from FPGA logic which either port GREFCLKRX PERFCLKRX source
SIM_TX_ELEC_IDLE_LEVEL
1-Bit Binary This attribute sets value during simulation electrical idle. This attribute default this attribute 3-Bit Binary This attribute selects reference clock source used drive simulation designs where always driven same reference clock source. TXPLLREFSELDY port must this attribute select reference clock source. multi-rate designs that require reference clock source changed fly, TXPLLREFSELDY port used dynamically select source instead. 000: Selects MGTREFCLKTX[0] port source 001: Selects MGTREFCLKTX[1] port source 010: Selects NORTHREFCLKTX[0] port source 011: Selects NORTHREFCLKTX[1] port source 100: Selects SOUTHREFCLKTX[0] port source 101: Selects SOUTHREFCLKTX[1] port source 110: Selects recovered clock from channel source 111: Selects clock from FPGA logic that either GREFCLKTX PERFCLKTX port source
SIM_TXREFCLK_SOURCE
SIM_VERSION
Real
This attribute selects simulation version match different steppings silicon. default this attribute 1.0.
SIM_GTXRESET_SPEEDUP
SIM_GTXRESET_SPEEDUP attribute used shorten simulated lock time PLL.
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TXOUTCLK RXRECCLK used generate clocks design, these clocks occasionally flatline while transceiver locking. MMCM used divide TXOUTCLK RXRECCLK, final output clock ready until both transceiver MMCM have locked. Equation provides estimate time required before stable source from TXOUTCLK RXRECCLK available simulation, including time required MMCMs used. Equation USRCLKstable GTXRESETsequence locktimeMMCM MMCM used, term removed from lock time equation.
SIM_RECEIVER_DETECT_PASS
transceiver includes TXDETECTRX feature that allows transmitter detect whether serial ports currently connected receiver measuring rise time TXP/TXN differential pair (see Receiver Detect Support Express Designs," page 108). GTXE1 SecureIP model includes attribute simulating TXDETECTRX called SIM_RECEIVER_DETECT_PASS. This attribute allows TXDETECTRX simulated transceiver without modeling measurement rise time TXP/TXN differential pair. default, SIM_RECEIVER_DETECT_PASS FALSE. When FALSE, attribute models disconnected receiver TXDETECTRX operations indicate receiver disconnected. model connected receiver, SIM_RECEIVER_DETECT_PASS transceiver TRUE.
SIM_RXREFCLK_SOURCE
GTXE1 SecureIP model includes attribute select reference clock source used drive simulation called SIM_RXREFCLK_SOURCE. This attribute used designs where PLL's clock input always driven same reference clock source. Reference clock sources include dedicated clock pins Quad that transceiver belongs north-running reference clocks, south-running reference clocks, clock from FPGA logic. Table 1-2, page shows possible settings this attribute. multi-rate designs requiring reference clock source driving changed fly, RXPLLREFSELDY port used dynamically select reference clock source instead.
SIM_TXREFCLK_SOURCE
GTXE1 SecureIP model includes attribute select reference clock source used drive simulation called SIM_TXREFCLK_SOURCE. This attribute used designs where PLL's clock input always driven same reference clock source. Reference clock sources include dedicated clock pins Quad that transceiver belongs north-running reference clocks, south-running reference clocks, clock from FPGA logic. Table 1-2, page shows possible settings this attribute. multi-rate designs requiring reference clock source driving changed fly, TXPLLREFSELDY port used dynamically select reference clock source instead.
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Implementation
SIM_VERSION
SIM_VERSION attribute selects simulation version match different steppings silicon. default this attribute 1.0.
SIM_TX_ELEC_IDLE_LEVEL
SIM_TX_ELEC_IDLE_LEVEL attribute sets value transceiver's differential transmitter output pair during simulation electrical idle. This attribute default this attribute
Implementation
Functional Description
This section provides information needed Virtex-6 FPGA transceivers instantiated design device resources, including: location transceiver available device package combinations. numbers external signals associated with each transceiver. transceiver clocking resources instantiated design mapped available locations with user constraints file (UCF).
common practice define location transceivers early design process ensure correct usage clock resources facilitate signal integrity analysis during board design. implementation flow facilitates this practice through location constraints UCF. While this section describes instantiate clocking components, details different transceiver clocking options discussed "Reference Clock Selection," page position transceiver specified coordinate system that describes column number relative position within that column. current members Virtex-6 platform, transceivers located single column along side die. transceiver with coordinates "X0Y0" given device/package combination always located lowest position lowest available bank. combination package with large count (for example, 1759) smaller device (for example, XC6VLX240T), transceivers higher lower banks available. There ways create designs that utilize transceiver. preferred method Virtex-6 FPGA Transceiver Wizard (see "Virtex-6 FPGA Transceiver Wizard," page 28). Wizard automatically generates templates that configure transceivers contain placeholders placement information. UCFs generated Wizard then edited customize operating parameters placement information application. second approach create hand. When using this approach, designer must enter both configuration attributes that control transceiver operation well tile location parameters. Care must taken ensure that parameters needed configure transceiver correctly entered.
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Figure 1-5, page through Figure 1-23, page provide transceiver position information available device package combinations along with numbers external signals associated with each transceiver.
FF484 Package Placement Diagrams
Figure through Figure show placement diagrams FF484 package.
X-Ref Target Figure
LX75T: GTXE1_X0Y7 LX130T: GTXE1_X0Y15
MGTRXP3_115 MGTRXN3_115
MGTTXP3_115 MGTTXN3_115
LX75T: GTXE1_X0Y6 LX130T: GTXE1_X0Y14 QUAD_115 LX75T: GTXE1_X0Y5 LX130T: GTXE1_X0Y13
MGTRXP2_115 MGTRXN2_115
MGTTXP2_115 MGTTXN2_115
MGTREFCLK1P_115 MGTREFCLK1N_115
MGTREFCLK0P_115 MGTREFCLK0N_115
MGTRXP1_115 MGTRXN1_115
MGTTXP1_115 MGTTXN1_115
LX75T: GTXE1_X0Y4 LX130T: GTXE1_X0Y12
MGTRXP0_115 MGTRXN0_115
MGTTXP0_115 MGTTXN0_115
UG366_c1_05_051509
Figure 1-5:
Placement Diagram FF484 Package
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Implementation
X-Ref Target Figure
LX75T: GTXE1_X0Y3 LX130T: GTXE1_X0Y11
MGTRXP3_114 MGTRXN3_114
MGTTXP3_114 MGTTXN3_114
LX75T: GTXE1_X0Y2 LX130T: GTXE1_X0Y10 QUAD_114 LX75T: GTXE1_X0Y1 LX130T: GTXE1_X0Y9
MGTRXP2_114 MGTRXN2_114
MGTTXP2_114 MGTTXN2_114
MGTREFCLK1P_114 MGTREFCLK1N_114
MGTREFCLK0P_114 MGTREFCLK0N_114
MGTRXP1_114 MGTRXN1_114
MGTTXP1_114 MGTTXN1_114
LX75T: GTXE1_X0Y0 LX130T: GTXE1_X0Y8
MGTRXP0_114 MGTRXN0_114
MGTTXP0_114 MGTTXN0_114
UG366_c1_06_051509
Figure 1-6:
Placement Diagram FF484 Package
Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
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Chapter Transceiver Tool Overview
FF784 Package Placement Diagrams
Figure through Figure show placement diagrams FF784 package.
X-Ref Target Figure
LX75T: GTXE1_X0Y11 LX130T: GTXE1_X0Y19 LX195T: GTXE1_X0Y19 LX240T: GTXE1_X0Y19
MGTRXP3_116 MGTRXN3_116
MGTTXP3_116 MGTTXN3_116
LX75T: GTXE1_X0Y10 LX130T: GTXE1_X0Y18 LX195T: GTXE1_X0Y18 LX240T: GTXE1_X0Y18
MGTRXP2_116 MGTRXN2_116
MGTTXP2_116 MGTTXN2_116
MGTREFCLK1P_116 MGTREFCLK1N_116
QUAD_116
LX75T: GTXE1_X0Y9 LX130T: GTXE1_X0Y17 LX195T: GTXE1_X0Y17 LX240T: GTXE1_X0Y17
MGTREFCLK0P_116 MGTREFCLK0N_116
MGTRXP1_116 MGTRXN1_116
MGTTXP1_116 MGTTXN1_116
LX75T: GTXE1_X0Y8 LX130T: GTXE1_X0Y16 LX195T: GTXE1_X0Y16 LX240T: GTXE1_X0Y16
MGTRXP0_116 MGTRXN0_116
MGTTXP0_116 MGTTXN0_116
UG366_c1_07_051509
Figure 1-7:
Placement Diagram FF784 Package
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Implementation
X-Ref Target Figure
LX75T: GTXE1_X0Y7 LX130T: GTXE1_X0Y15 LX195T: GTXE1_X0Y15 LX240T: GTXE1_X0Y15
MGTRXP3_115 MGTRXN3_115
MGTTXP3_115 MGTTXN3_115
LX75T: GTXE1_X0Y6 LX130T: GTXE1_X0Y14 LX195T: GTXE1_X0Y14 LX240T: GTXE1_X0Y14
MGTRXP2_115 MGTRXN2_115
MGTTXP2_115 MGTTXN2_115
MGTREFCLK1P_115 MGTREFCLK1N_115
QUAD_115
LX75T: GTXE1_X0Y5 LX130T: GTXE1_X0Y13 LX195T: GTXE1_X0Y13 LX240T: GTXE1_X0Y13
MGTREFCLK0P_115 MGTREFCLK0N_115
MGTRXP1_115 MGTRXN1_115
MGTTXP1_115 MGTTXN1_115
LX75T: GTXE1_X0Y4 LX130T: GTXE1_X0Y12 LX195T: GTXE1_X0Y12 LX240T: GTXE1_X0Y12
MGTRXP0_115 MGTRXN0_115
MGTTXP0_115 MGTTXN0_115
UG366_c1_08_051509
Figure 1-8:
Placement Diagram FF784 Package
Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
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Chapter Transceiver Tool Overview
X-Ref Target Figure
LX75T: GTXE1_X0Y3 LX130T: GTXE1_X0Y11 LX195T: GTXE1_X0Y11 LX240T: GTXE1_X0Y11
MGTRXP3_114 MGTRXN3_114
MGTTXP3_114 MGTTXN3_114
LX75T: GTXE1_X0Y2 LX130T: GTXE1_X0Y10 LX195T: GTXE1_X0Y10 LX240T: GTXE1_X0Y10
MGTRXP2_114 MGTRXN2_114
MGTTXP2_114 MGTTXN2_114
MGTREFCLK1P_114 MGTREFCLK1N_114
QUAD_114
LX75T: GTXE1_X0Y0 LX130T: GTXE1_X0Y9 LX195T: GTXE1_X0Y9 LX240T: GTXE1_X0Y9
MGTREFCLK0P_114 MGTREFCLK0N_114
MGTRXP1_114 MGTRXN1_114
MGTTXP1_114 MGTTXN1_114
LX75T: GTXE1_X0Y0 LX130T: GTXE1_X0Y8 LX195T: GTXE1_X0Y8 LX240T: GTXE1_X0Y8
MGTRXP0_114 MGTRXN0_114
MGTTXP0_114 MGTTXN0_114
UG366_c1_09_051509
Figure 1-9:
Placement Diagram FF784 Package
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Implementation
FF1156 Package Placement Diagrams
Figure 1-10 through Figure 1-14 show placement diagrams FF1156 package.
X-Ref Target Figure 1-10
LX130T: GTXE1_X0Y19 LX195T: GTXE1_X0Y19 LX240T: GTXE1_X0Y19 LX365T: GTXE1_X0Y19 SX315T: GTXE1_X0Y19 SX475T: GTXE1_X0Y27
MGTRXP3_116 MGTRXN3_116
MGTTXP3_116 MGTTXN3_116
LX130T: GTXE1_X0Y18 LX195T: GTXE1_X0Y18 LX240T: GTXE1_X0Y18 LX365T: GTXE1_X0Y18 SX315T: GTXE1_X0Y18 SX475T: GTXE1_X0Y26
MGTRXP2_116 MGTRXN2_116
MGTTXP2_116 MGTTXN2_116
MGTREFCLK1P_116 MGTREFCLK1N_116
QUAD_116
LX130T: GTXE1_X0Y17 LX195T: GTXE1_X0Y17 LX240T: GTXE1_X0Y17 LX365T: GTXE1_X0Y17 SX315T: GTXE1_X0Y17 SX475T: GTXE1_X0Y25
MGTREFCLK0P_116 MGTREFCLK0N_116
MGTRXP1_116 MGTRXN1_116
MGTTXP1_116 MGTTXN1_116
LX130T: GTXE1_X0Y16 LX195T: GTXE1_X0Y16 LX240T: GTXE1_X0Y16 LX365T: GTXE1_X0Y16 SX315T: GTXE1_X0Y16 SX475T: GTXE1_X0Y24
MGTRXP0_116 MGTRXN0_116
MGTTXP0_116 MGTTXN0_116
UG366_c1_10_051509
Figure 1-10:
Placement Diagram FF1156 Package
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Chapter Transceiver Tool Overview
X-Ref Target Figure 1-11
LX130T: GTXE1_X0Y15 LX195T: GTXE1_X0Y15 LX240T: GTXE1_X0Y15 LX365T: GTXE1_X0Y15 SX315T: GTXE1_X0Y15 SX475T: GTXE1_X0Y23
MGTRXP3_115 MGTRXN3_115
MGTTXP3_115 MGTTXN3_115
LX130T: GTXE1_X0Y14 LX195T: GTXE1_X0Y14 LX240T: GTXE1_X0Y14 LX365T: GTXE1_X0Y14 SX315T: GTXE1_X0Y14 SX475T: GTXE1_X0Y22
MGTRXP2_115 MGTRXN2_115
MGTTXP2_115 MGTTXN2_115
MGTREFCLK1P_115 MGTREFCLK1N_115
QUAD_115
LX130T: GTXE1_X0Y13 LX195T: GTXE1_X0Y13 LX240T: GTXE1_X0Y13 LX365T: GTXE1_X0Y13 SX315T: GTXE1_X0Y13 SX475T: GTXE1_X0Y21
MGTREFCLK0P_115 MGTREFCLK0N_115
MGTRXP1_115 MGTRXN1_115
MGTTXP1_115 MGTTXN1_115
LX130T: GTXE1_X0Y12 LX195T: GTXE1_X0Y12 LX240T: GTXE1_X0Y12 LX365T: GTXE1_X0Y12 SX315T: GTXE1_X0Y12 SX475T: GTXE1_X0Y20
MGTRXP0_115 MGTRXN0_115
MGTTXP0_115 MGTTXN0_115
UG366_c1_11_051509
Figure 1-11:
Placement Diagram FF1156 Package
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Implementation
X-Ref Target Figure 1-12
LX130T: GTXE1_X0Y11 LX195T: GTXE1_X0Y11 LX240T: GTXE1_X0Y11 LX365T: GTXE1_X0Y11 SX315T: GTXE1_X0Y11 SX475T: GTXE1_X0Y19
MGTRXP3_114 MGTRXN3_114
MGTTXP3_114 MGTTXN3_114
LX130T: GTXE1_X0Y10 LX195T: GTXE1_X0Y10 LX240T: GTXE1_X0Y10 LX365T: GTXE1_X0Y10 SX315T: GTXE1_X0Y10 SX475T: GTXE1_X0Y18
MGTRXP2_114 MGTRXN2_114
MGTTXP2_114 MGTTXN2_114
MGTREFCLK1P_114 MGTREFCLK1N_114
QUAD_114
LX130T: GTXE1_X0Y9 LX195T: GTXE1_X0Y9 LX240T: GTXE1_X0Y9 LX365T: GTXE1_X0Y9 SX315T: GTXE1_X0Y9 SX475T: GTXE1_X0Y17
MGTREFCLK0P_114 MGTREFCLK0N_114
MGTRXP1_114 MGTRXN1_114
MGTTXP1_114 MGTTXN1_114
LX130T: GTXE1_X0Y8 LX195T: GTXE1_X0Y8 LX240T: GTXE1_X0Y8 LX365T: GTXE1_X0Y8 SX315T: GTXE1_X0Y8 SX475T: GTXE1_X0Y16
MGTRXP0_114 MGTRXN0_114
MGTTXP0_114 MGTTXN0_114
UG366_c1_12_051509
Figure 1-12:
Placement Diagram FF1156 Package
Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
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Chapter Transceiver Tool Overview
X-Ref Target Figure 1-13
LX130T: GTXE1_X0Y7 LX195T: GTXE1_X0Y7 LX240T: GTXE1_X0Y7 LX365T: GTXE1_X0Y7 SX315T: GTXE1_X0Y7 SX475T: GTXE1_X0Y15
MGTRXP3_113 MGTRXN3_113
MGTTXP3_113 MGTTXN3_113
LX130T: GTXE1_X0Y6 LX195T: GTXE1_X0Y6 LX240T: GTXE1_X0Y6 LX365T: GTXE1_X0Y6 SX315T: GTXE1_X0Y6 SX475T: GTXE1_X0Y14
MGTRXP2_113 MGTRXN2_113
MGTTXP2_113 MGTTXN2_113
MGTREFCLK1P_113 MGTREFCLK1N_113
QUAD_113
LX130T: GTXE1_X0Y5 LX195T: GTXE1_X0Y5 LX240T: GTXE1_X0Y5 LX365T: GTXE1_X0Y5 SX315T: GTXE1_X0Y5 SX475T: GTXE1_X0Y13
MGTREFCLK0P_113 MGTREFCLK0N_113
MGTRXP1_113 MGTRXN1_113
MGTTXP1_113 MGTTXN1_113
LX130T: GTXE1_X0Y4 LX195T: GTXE1_X0Y4 LX240T: GTXE1_X0Y4 LX365T: GTXE1_X0Y4 SX315T: GTXE1_X0Y4 SX475T: GTXE1_X0Y12
MGTRXP0_113 MGTRXN0_113
MGTTXP0_113 MGTTXN0_113
UG366_c1_13_051509
Figure 1-13:
Placement Diagram FF1156 Package
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Implementation
X-Ref Target Figure 1-14
LX130T: GTXE1_X0Y3 LX195T: GTXE1_X0Y3 LX240T: GTXE1_X0Y3 LX365T: GTXE1_X0Y3 SX315T: GTXE1_X0Y3 SX475T: GTXE1_X0Y11
MGTRXP3_112 MGTRXN3_112
MGTTXP3_112 MGTTXN3_112
LX130T: GTXE1_X0Y2 LX195T: GTXE1_X0Y2 LX240T: GTXE1_X0Y2 LX365T: GTXE1_X0Y2 SX315T: GTXE1_X0Y2 SX475T: GTXE1_X0Y10
MGTRXP2_112 MGTRXN2_112
MGTTXP2_112 MGTTXN2_112
MGTREFCLK1P_112 MGTREFCLK1N_112
QUAD_112
LX130T: GTXE1_X0Y1 LX195T: GTXE1_X0Y1 LX240T: GTXE1_X0Y1 LX365T: GTXE1_X0Y1 SX315T: GTXE1_X0Y1 SX475T: GTXE1_X0Y9
MGTREFCLK0P_112 MGTREFCLK0N_112
MGTRXP1_112 MGTRXN1_112
MGTTXP1_112 MGTTXN1_112
LX130T: GTXE1_X0Y0 LX195T: GTXE1_X0Y0 LX240T: GTXE1_X0Y0 LX365T: GTXE1_X0Y0 SX315T: GTXE1_X0Y0 SX475T: GTXE1_X0Y8
MGTRXP0_112 MGTRXN0_112
MGTTXP0_112 MGTTXN0_112
UG366_c1_14_051509
Figure 1-14:
Placement Diagram FF1156 Package
Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
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Chapter Transceiver Tool Overview
FF1759 Package Placement Diagrams
Figure 1-15 through Figure 1-23 show placement diagrams FF1759 package.
X-Ref Target Figure 1-15
LX240T: available LX365T: available LX550T: GTXE1_X0Y35 SX315T: available SX475T: GTXE1_X0Y35
MGTRXP3_118 MGTRXN3_118
MGTTXP3_118 MGTTXN3_118
LX240T: available LX365T: available LX550T: GTXE1_X0Y34 SX315T: available SX475T: GTXE1_X0Y34
MGTRXP2_118 MGTRXN2_118
MGTTXP2_118 MGTTXN2_118
MGTREFCLK1P_118 MGTREFCLK1N_118
QUAD_118 LX240T: available LX365T: available LX550T: GTXE1_X0Y33 SX315T: available SX475T: GTXE1_X0Y33 MGTREFCLK0P_118 MGTREFCLK0N_118
MGTRXP1_118 MGTRXN1_118
MGTTXP1_118 MGTTXN1_118
LX240T: available LX365T: available LX550T: GTXE1_X0Y32 SX315T: available SX475T: GTXE1_X0Y32
MGTRXP0_118 MGTRXN0_118
MGTTXP0_118 MGTTXN0_118
UG366_c1_15_051509
Figure 1-15:
Placement Diagram FF1759 Package
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Implementation
X-Ref Target Figure 1-16
LX240T: GTXE1_X0Y23 LX365T: GTXE1_X0Y23 LX550T: GTXE1_X0Y31 SX315T: GTXE1_X0Y23 SX475T: GTXE1_X0Y31
MGTRXP3_117 MGTRXN3_117
MGTTXP3_117 MGTTXN3_117
LX240T: GTXE1_X0Y22 LX365T: GTXE1_X0Y22 LX550T: GTXE1_X0Y30 SX315T: GTXE1_X0Y22 SX475T: GTXE1_X0Y30
MGTRXP2_117 MGTRXN2_117
MGTTXP2_117 MGTTXN2_117
MGTREFCLK1P_117 MGTREFCLK1N_117
QUAD_117 LX240T: GTXE1_X0Y21 LX365T: GTXE1_X0Y21 LX550T: GTXE1_X0Y29 SX315T: GTXE1_X0Y21 SX475T: GTXE1_X0Y29 MGTREFCLK0P_117 MGTREFCLK0N_117
MGTRXP1_117 MGTRXN1_117
MGTTXP1_117 MGTTXN1_117
LX240T: GTXE1_X0Y20 LX365T: GTXE1_X0Y20 LX550T: GTXE1_X0Y28 SX315T: GTXE1_X0Y20 SX475T: GTXE1_X0Y28
MGTRXP0_117 MGTRXN0_117
MGTTXP0_117 MGTTXN0_117
UG366_c1_16_051509
Figure 1-16:
Placement Diagram FF1759 Package
Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
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Chapter Transceiver Tool Overview
X-Ref Target Figure 1-17
LX240T: GTXE1_X0Y19 LX365T: GTXE1_X0Y19 LX550T: GTXE1_X0Y27 SX315T: GTXE1_X0Y19 SX475T: GTXE1_X0Y27
MGTRXP3_116 MGTRXN3_116
MGTTXP3_116 MGTTXN3_116
LX240T: GTXE1_X0Y18 LX365T: GTXE1_X0Y18 LX550T: GTXE1_X0Y26 SX315T: GTXE1_X0Y18 SX475T: GTXE1_X0Y26
MGTRXP2_116 MGTRXN2_116
MGTTXP2_116 MGTTXN2_116
MGTREFCLK1P_116 MGTREFCLK1N_116
QUAD_116 LX240T: GTXE1_X0Y17 LX365T: GTXE1_X0Y17 LX550T: GTXE1_X0Y25 SX315T: GTXE1_X0Y17 SX475T: GTXE1_X0Y25 MGTREFCLK0P_116 MGTREFCLK0N_116
MGTRXP1_116 MGTRXN1_116
MGTTXP1_116 MGTTXN1_116
LX240T: GTXE1_X0Y16 LX365T: GTXE1_X0Y16 LX550T: GTXE1_X0Y24 SX315T: GTXE1_X0Y16 SX475T: GTXE1_X0Y24
MGTRXP0_116 MGTRXN0_116
MGTTXP0_116 MGTTXN0_116
UG366_c1_17_051509
Figure 1-17:
Placement Diagram FF1759 Package
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Implementation
X-Ref Target Figure 1-18
LX240T: GTXE1_X0Y15 LX365T: GTXE1_X0Y15 LX550T: GTXE1_X0Y23 SX315T: GTXE1_X0Y15 SX475T: GTXE1_X0Y23
MGTRXP3_115 MGTRXN3_115
MGTTXP3_115 MGTTXN3_115
LX240T: GTXE1_X0Y14 LX365T: GTXE1_X0Y14 LX550T: GTXE1_X0Y22 SX315T: GTXE1_X0Y14 SX475T: GTXE1_X0Y22
MGTRXP2_115 MGTRXN2_115
MGTTXP2_115 MGTTXN2_115
MGTREFCLK1P_115 MGTREFCLK1N_115
QUAD_115 LX240T: GTXE1_X0Y13 LX365T: GTXE1_X0Y13 LX550T: GTXE1_X0Y21 SX315T: GTXE1_X0Y13 SX475T: GTXE1_X0Y21 MGTREFCLK0P_115 MGTREFCLK0N_115
MGTRXP1_115 MGTRXN1_115
MGTTXP1_115 MGTTXN1_115
LX240T: GTXE1_X0Y12 LX365T: GTXE1_X0Y12 LX550T: GTXE1_X0Y20 SX315T: GTXE1_X0Y12 SX475T: GTXE1_X0Y20
MGTRXP0_115 MGTRXN0_115
MGTTXP0_115 MGTTXN0_115
UG366_c1_18_051509
Figure 1-18:
Placement Diagram FF1759 Package
Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
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Chapter Transceiver Tool Overview
X-Ref Target Figure 1-19
LX240T: GTXE1_X0Y11 LX365T: GTXE1_X0Y11 LX550T: GTXE1_X0Y19 SX315T: GTXE1_X0Y11 SX475T: GTXE1_X0Y19
MGTRXP3_114 MGTRXN3_114
MGTTXP3_114 MGTTXN3_114
LX240T: GTXE1_X0Y10 LX365T: GTXE1_X0Y10 LX550T: GTXE1_X0Y18 SX315T: GTXE1_X0Y10 SX475T: GTXE1_X0Y18
MGTRXP2_114 MGTRXN2_114
MGTTXP2_114 MGTTXN2_114
MGTREFCLK1P_114 MGTREFCLK1N_114
QUAD_114 LX240T: GTXE1_X0Y9 LX365T: GTXE1_X0Y9 LX550T: GTXE1_X0Y17 SX315T: GTXE1_X0Y9 SX475T: GTXE1_X0Y17 MGTREFCLK0P_114 MGTREFCLK0N_114
MGTRXP1_114 MGTRXN1_114
MGTTXP1_114 MGTTXN1_114
LX240T: GTXE1_X0Y8 LX365T: GTXE1_X0Y8 LX550T: GTXE1_X0Y16 SX315T: GTXE1_X0Y8 SX475T: GTXE1_X0Y16
MGTRXP0_114 MGTRXN0_114
MGTTXP0_114 MGTTXN0_114
UG366_c1_19_051509
Figure 1-19:
Placement Diagram FF1759 Package
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Implementation
X-Ref Target Figure 1-20
LX240T: GTXE1_X0Y7 LX365T: GTXE1_X0Y7 LX550T: GTXE1_X0Y15 SX315T: GTXE1_X0Y7 SX475T: GTXE1_X0Y15
MGTRXP3_113 MGTRXN3_113
MGTTXP3_113 MGTTXN3_113
LX240T: GTXE1_X0Y6 LX365T: GTXE1_X0Y6 LX550T: GTXE1_X0Y14 SX315T: GTXE1_X0Y6 SX475T: GTXE1_X0Y14
MGTRXP2_113 MGTRXN2_113
MGTTXP2_113 MGTTXN2_113
MGTREFCLK1P_113 MGTREFCLK1N_113
QUAD_113 LX240T: GTXE1_X0Y5 LX365T: GTXE1_X0Y5 LX550T: GTXE1_X0Y13 SX315T: GTXE1_X0Y5 SX475T: GTXE1_X0Y13 MGTREFCLK0P_113 MGTREFCLK0N_113
MGTRXP1_113 MGTRXN1_113
MGTTXP1_113 MGTTXN1_113
LX240T: GTXE1_X0Y4 LX365T: GTXE1_X0Y4 LX550T: GTXE1_X0Y12 SX315T: GTXE1_X0Y4 SX475T: GTXE1_X0Y12
MGTRXP0_113 MGTRXN0_113
MGTTXP0_113 MGTTXN0_113
UG366_c1_20_051509
Figure 1-20:
Placement Diagram FF1759 Package
Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
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Chapter Transceiver Tool Overview
X-Ref Target Figure 1-21
LX240T: GTXE1_X0Y3 LX365T: GTXE1_X0Y3 LX550T: GTXE1_X0Y11 SX315T: GTXE1_X0Y3 SX475T: GTXE1_X0Y11
MGTRXP3_112 MGTRXN3_112
MGTTXP3_112 MGTTXN3_112
LX240T: GTXE1_X0Y2 LX365T: GTXE1_X0Y2 LX550T: GTXE1_X0Y10 SX315T: GTXE1_X0Y2 SX475T: GTXE1_X0Y10
MGTRXP2_112 MGTRXN2_112
MGTTXP2_112 MGTTXN2_112
MGTREFCLK1P_112 MGTREFCLK1N_112
QUAD_112 LX240T: GTXE1_X0Y1 LX365T: GTXE1_X0Y1 LX550T: GTXE1_X0Y9 SX315T: GTXE1_X0Y1 SX475T: GTXE1_X0Y9 MGTREFCLK0P_112 MGTREFCLK0N_112
MGTRXP1_112 MGTRXN1_112
MGTTXP1_112 MGTTXN1_112
LX240T: GTXE1_X0Y0 LX365T: GTXE1_X0Y0 LX550T: GTXE1_X0Y8 SX315T: GTXE1_X0Y0 SX475T: GTXE1_X0Y8
MGTRXP0_112 MGTRXN0_112
MGTTXP0_112 MGTTXN0_112
UG366_c1_21_051509
Figure 1-21:
Placement Diagram FF1759 Package
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Implementation
X-Ref Target Figure 1-22
LX240T: available LX365T: available LX550T: GTXE1_X0Y7 SX315T: available SX475T: GTXE1_X0Y7
MGTRXP3_111 MGTRXN3_111
MGTTXP3_111 MGTTXN3_111
LX240T: available LX365T: available LX550T: GTXE1_X0Y6 SX315T: available SX475T: GTXE1_X0Y6
MGTRXP2_111 MGTRXN2_111
MGTTXP2_111 MGTTXN2_111
MGTREFCLK1P_111 MGTREFCLK1N_111
QUAD_111 AU10 LX240T: available LX365T: available LX550T: GTXE1_X0Y5 SX315T: available SX475T: GTXE1_X0Y5 MGTREFCLK0P_111 MGTREFCLK0N_111
MGTRXP1_111 MGTRXN1_111
MGTTXP1_111 MGTTXN1_111
LX240T: available LX365T: available LX550T: GTXE1_X0Y4 SX315T: available SX475T: GTXE1_X0Y4
MGTRXP0_111 MGTRXN0_111
MGTTXP0_111 MGTTXN0_111
UG366_c1_22_051509
Figure 1-22:
Placement Diagram FF1759 Package
Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
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Chapter Transceiver Tool Overview
X-Ref Target Figure 1-23
LX240T: available LX365T: available LX550T: GTXE1_X0Y3 SX315T: available SX475T: GTXE1_X0Y3
MGTRXP3_110 MGTRXN3_110
MGTTXP3_110 MGTTXN3_110
LX240T: available LX365T: available LX550T: GTXE1_X0Y2 SX315T: available SX475T: GTXE1_X0Y2
MGTRXP2_110 MGTRXN2_110
AW10
MGTTXP2_110 MGTTXN2_110
MGTREFCLK1P_110 MGTREFCLK1N_110
QUAD_110 BA10 LX240T: available LX365T: available LX550T: GTXE1_X0Y1 SX315T: available SX475T: GTXE1_X0Y1 MGTREFCLK0P_110 MGTREFCLK0N_110
MGTRXP1_110 MGTRXN1_110
MGTTXP1_110 MGTTXN1_110
LX240T: available LX365T: available LX550T: GTXE1_X0Y0 SX315T: available SX475T: GTXE1_X0Y0
MGTRXP0_110 MGTRXN0_110
MGTTXP0_110 MGTTXN0_110
UG366_c1_23_051509
Figure 1-23:
Placement Diagram FF1759 Package
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Chapter
Shared Transceiver Features
Reference Clock Selection
Functional Description
transceivers provide several available reference clock inputs. Clock selection availability changed slightly across first three generations Virtex® FPGA transceivers. Virtex-6 FPGA transceiver significantly enhances reference clock capabilities adding dedicated clock routing multiplexer resources. Architecturally, concept Quad contains grouping four GTXE1 primitives, dedicated reference clock pairs, dedicated reference clock routing. term Quad this document describes reference clocking architecture Virtex-6 FPGA transceivers. Reference clock features include: Clock routing north south bound clocks. Clock inputs available PLL. Static dynamic selection reference clock transmitter receiver PLLs.
Figure shows Quad architecture with four transceivers, dedicated reference clock pairs, dedicated north/south reference clock routing. Each transceiver Quad seven clock inputs available: local reference clock pairs, MGTREFCLK[0/1] reference clock pairs from Quads above, SOUTHREFCLK[0/1] reference clocks pairs below, NORTHREFCLK[0/1] Internal each transceiver, clock from receiver forwarded transmit reference clock, CAS_CLK. CAS_CLK must only used diagnostics purposes.
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Chapter Shared Transceiver Features
X-Ref Target Figure
MGTREFCLK0[P/N] MGTREFCLK1[P/N]
PERFCLK GREFCLK
CAS_CLK
(n+1)
Q(n+1)SouthClk0 Q(n+1)SouthClk1 Q(n+1)NorthClk0 Q(n+1)NorthClk1 Q(n+1)RefClk0 Q(n+1)RefClk1
GTX0
Controlled Software
CAS_CLK
GTX3 MGTREFCLK0[P/N] MGTREFCLK1[P/N]
NORTHREFCLK0 NORTHREFCLK1 SOUTHREFCLK0 SOUTHREFCLK1
GTX2
PERFCLK
MGTREFCLK0
GTX1
GREFCLK
GREFCLK PERFCLK
MGTREFCLK1
CAS_CLK
GTX0
Q(n)SouthClk0 Q(n)SouthClk1 Q(n)NorthClk0 Q(n)NorthClk1
Q(n)RefClk0
(n-1)
Q(n)RefClk1
Controlled Software
CAS_CLK
GTX3 MGTREFCLK0[P/N] MGTREFCLK1[P/N] PERFCLK GREFCLK
UG366_c2_01_051509
Figure 2-1:
Conceptual View Transceiver Reference Clocking
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Reference Clock Selection
Figure shows detailed view reference clock multiplexer structure within single GTXE1 primitive. TXPLLREFSELDY RXPLLREFSELDY ports required when multiple reference clocks used. single reference clock most commonly used. this case, TXPLLREFSELDY RXPLLREFSELDY ports connected 000, Xilinx software tools handle complexity multiplexers associated routing. "Single External Reference Clock Model" more information.
X-Ref Target Figure
Transceiver
TXPLLREFSELDY[2:0]
MGTREFCLKTX[0] MGTREFCLKTX[1] NORTHREFCLKTX[0] NORTHREFCLKTX[1] SOUTHREFCLKTX[0] SOUTHREFCLKTX[1]
CORECLK
REFCLK
GREFCLKTX PERFCLKTX
Note
CAS_CLK
RXPLLREFSELDY[2:0]
MGTREFCLKRX[0] MGTREFCLKRX[1] NORTHREFCLKRX[0] NORTHREFCLKRX[1] SOUTHREFCLKRX[0] SOUTHREFCLKRX[1]
CORECLK
REFCLK
GREFCLKRX PERFCLKRX
Note Default Configuration
NC(2)
UG366_c2_02_051509
Notes:
CORECLK multiplexer controlled software. GREFCLK connected, software configures multiplexer GREFCLK. PERFCLK connected, software configures multiplexer PERFCLK. There user-controllable attribute switch multiplexer. Only inputs connected time. CAS_CLK input used configured.
Figure 2-2:
Transceiver Detailed Diagram
four transceivers that make Quad share dedicated reference clock pairs. user design accesses these reference clocks instantiating IBUFDS IBUFDS_GTXE1 primitives. These reference clocks used locally four
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Chapter Shared Transceiver Features
transceivers within Quad. addition, they routed transceivers north south neighboring Quads using dedicated reference clock routing shown Figure 2-1. Each transceiver also select reference clocks from Quad below (Q(n-1)) sourced from NORTHREFCLKTX[0/1] NORTHREFCLKRX[0/1] ports; reference clocks from Quad above (Q(n+1)) sourced from SOUTHREFCLKTX[0/1] SOUTHREFCLKRX[0/] ports; reference clocks from FPGA logic sourced from PERFCLKTX PERFCLKRX, GREFCLKTX GREFCLKRX. Xilinx software tools handle complexity multiplexers associated routing designs that require single reference clock transceiver PLL. dynamic switching reference clocks required, user must reference clock multiplexers using TXPLLREFSELDY RXPLLREFSELDY ports. dedicated reference clock routing between Quads Xilinx software tools both single multiple reference clock modes. Internal clock nets FPGA provide reference clocks transceiver connecting output global clocking resource PERFCLK GREFCLK port. Only these inputs connected time. These reference clock ports have lowest performance available clocking methods because FPGA clocking resources introduce jitter operation high data rates. PERFCLK GREFCLK reserved internal test purposes only.
Ports Attributes
Table defines clocking ports. Table 2-1: Clocking Ports
Port GREFCLKRX GREFCLKTX MGTREFCLKRX[1:0] MGTREFCLKTX[1:0] NORTHREFCLKRX[1:0] NORTHREFCLKTX[1:0] PERFCLKRX PERFCLKTX SOUTHREFCLKRX[1:0] Clock Domain Clock Clock Clock Clock Clock Clock Clock Clock Clock Description Internal FPGA logic clock. Reserved internal testing purposes only. Internal FPGA logic clock. Reserved internal testing purposes only. External jitter stable clock driven IBUFDS_GTXE1 External jitter stable clock driven IBUFDS_GTXE1 North-bound clocks from Quad below North-bound clocks from Quad below Internal FPGA logic clock. Reserved internal testing purposes only. Internal FPGA logic clock. Reserved internal testing purposes only. South-bound clocks from Quad above
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Single External Reference Clock Model
Table 2-1:
Clocking Ports (Cont'd)
Port Clock Domain Clock Async Description South-bound clocks from Quad above Transmitter reference clock dynamic selection. when reference clock used. When multiple reference clocks connected, TXPLLREFSELDY provides dynamic selection follows: 000: MGTREFCLKTX[0] selected 001: MGTREFCLKTX[1] selected 010: NORTHREFCLKTX[0] selected 011: NORTHREFCLKTX[1] selected 100: SOUTHREFCLKTX[0] selected 101: SOUTHREFCLKTX[1] selected 110: CAS_CLK (Internal clock generated from PLL) 111: GREFCLKTX PERFCLKTX selected (only these used time)
SOUTHREFCLKTX[1:0] TXPLLREFSELDY[2:0]
Table defines clocking attributes. Table 2-2: Clocking Attributes
Attribute PMA_CAS_CLK_EN Type Boolean Description This attribute enable CAS_CLK from receiver forwarded transmitter PLL. TRUE: Enables CAS_CLK. TXPLLREFSELDY[2:0] unused this case. FALSE: Disables CAS_CLK. SIM_RXREFCLK_SOURCE[2:0] SIM_TXREFCLK_SOURCE[2:0] 3-bit Binary 3-bit Binary Simulation control reference clock selection. This attribute must contain same binary value RXPLLREFSELDY port. Simulation control reference clock selection. This attribute same binary value TXPLLREFSELDY port.
Single External Reference Clock Model
Each Quad pair dedicated reference clock pins that connected external clock source. IBUFDS_GTXE1 primitive must instantiated these dedicated reference clock pairs. user design connects IBUFDS_GTXE1 output MGTREFCLKRX[0] MGTREFCLKTX[0] ports GTXE1 primitive. MGTREFCLKTX[0] must connected even used design. IBUFDS_GTXE1 input pins constrained User Constraints File (UCF). simulation-only attributes must GTXE1 primitive match clock input used. single external reference clock model, following settings must applied (these default settings): SIM_RXREFCLK_SOURCE SIM_TXREFCLK_SOURCE
Figure shows single reference clock connected single transceiver.
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Chapter Shared Transceiver Features
X-Ref Target Figure
IBUFDS_GTXE1 MGTREFCLKP MGTREFCLKN
Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0]
UG366_c2_03_051509
Figure 2-3:
Single External Reference Clock
Figure shows single reference clock connected multiple transceivers.
X-Ref Target Figure
Q(n+1)
Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0] Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0] Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0] Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0]
Q(n)
IBUFDS_GTXE1 MGTREFCLKP MGTREFCLKN
Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0] Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0] Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0] Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0]
Q(n-1)
Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0] Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0] Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0] Transceiver MGTREFCLKTX[0] MGTREFCLKRX[0]
UG366_c2_04_051509
Figure 2-4:
Multiple Transceivers with Shared Reference Clock
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Xilinx implementation tools make necessary adjustments north/south routing shown Figure well swapping necessary clock inputs route clocks from Quad another when required. following rules must observed when sharing reference clock ensure that jitter margins high-speed designs met: number Quads above sourcing Quad must exceed one. number Quads below sourcing Quad must exceed one. total number Quads sourced external clock pair (MGTREFCLKN/MGTREFCLKP) must exceed Quads transceivers).
maximum number transceivers that sourced single clock pair Designs with more than transceivers require multiple external clock pins ensure that rules controlling jitter followed. When multiple clock pins used, external buffer used drive them from same oscillator.
Functional Description
Each transceiver contains PLL, which allows datapaths operate asynchronous frequencies using different reference clock inputs. applications where datapaths operate same line rate range, shared between datapaths powered down conserve power. transceiver cannot shared with other transceivers, only within same transceiver. nominal operation range between 3.25 GHz, which supports Gb/s Gb/s line rate range. Refer Virtex-6 FPGA Data Sheet operating limits. output divided four Clock Dividers block support Gb/s 3.25 Gb/s 0.75 Gb/s 1.625 Gb/s frequency ranges, respectively. Lower line rate support requires built-in oversampling block.
X-Ref Target Figure
REFCLK Distribution
Clock Dividers
Clock Dividers
UG366_c2_05_051509
Figure 2-5:
Top-Level Architecture
input clock selection described "Reference Clock Selection," page outputs feed clock divider blocks, which control generation serial parallel clocks used blocks. These blocks described Clock Divider Control," page Clock Divider Control," page 129.
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Chapter Shared Transceiver Features
Figure illustrates conceptual view architecture. phase noise input clock recommended best jitter performance. input clock divided factor before feeding into phase frequency detector. feedback dividers, determine multiplication ratio output frequency. lock indicator block compares frequencies reference clock feedback clock determine frequency lock been achieved.
X-Ref Target Figure
CLKIN
Lock Indicator Phase Frequency Detector Charge Pump Loop Filter
LOCKED
CLKOUT
UG366_c2_06_051509
Figure 2-6:
Detail
Equation shows determine output frequency (GHz). PLLClkout PLLClkin Equation
Equation shows determine line rate (Gb/s). output divider that resides clock divider block. PLLClkout Equation LineRate Table lists actual attribute commonly used divider values. Table 2-3: Divider Attribute Common Values
Attribute Name TXPLL_DIVSEL_REF RXPLL_DIVSEL_REF TXPLL_DIVSEL45_FB RXPLL_DIVSEL45_FB TXPLL_DIVSEL_FB RXPLL_DIVSEL_FB TXPLL_DIVSEL_OUT RXPLL_DIVSEL_OUT Valid Settings
Factor
Ports Attributes
Table defines ports.
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Table 2-4:
Ports
Port Clock Domain Async Async Description These active-High ports reset dividers inside well lock indicator block. This active-High frequency lock signal indicates that frequency within predetermined tolerance. transceiver clock outputs reliable until this condition met. This port enables lock detector must always tied High. These active-High signals provide power down.
PLLTXRESET PLLRXRESET TXPLLLKDET RXPLLLKDET TXPLLLKDETEN RXPLLLKDETEN TXPLLPOWERDOWN RXPLLPOWERDOWN
Async Async
Table defines attributes. Table 2-5: Attributes
Type String Description This attribute multiplexer select signal Figure 2-5, which determines whether supplies clock datapath. applications where have same line rate with small frequency offset, using supply both datapaths allows some power savings. Valid values "TXPLL" "RXPLL". TX_TDCC_CFG TXPLL_COM_CFG RXPLL_COM_CFG TXPLL_CP_CFG RXPLL_CP_CFG TXPLL_DIVSEL_FB RXPLL_DIVSEL_FB TXPLL_DIVSEL_OUT RXPLL_DIVSEL_OUT TXPLL_DIVSEL_REF RXPLL_DIVSEL_REF TXPLL_DIVSEL45_FB RXPLL_DIVSEL45_FB TXPLL_LKDET_CFG RXPLL_LKDET_CFG TXPLL_SATA 3-bit Binary 2-bit Binary Integer Integer Integer 2-bit Binary 24-bit 8-bit Integer Reserved. only recommended values from Virtex-6 FPGA Transceiver Wizard. Reserved. only recommended values from Virtex-6 FPGA Transceiver Wizard. Reserved. only recommended values from Virtex-6 FPGA Transceiver Wizard. This attribute Figure 2-6. This attribute specifies feedback dividers. Common settings This attribute Equation 2-2. specifies value output divider, which resides clock divider block. Valid settings This attribute Figure 2-6. specifies value reference clock input divider. Common settings This attribute Figure 2-6. specifies feedback dividers. Valid settings Reserved. only recommended values from Virtex-6 FPGA Transceiver Wizard. Reserved. only recommended values from Virtex-6 FPGA Transceiver Wizard.
Attribute TX_CLK_SOURCE
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Chapter Shared Transceiver Features
Settings Common Protocols
Table shows example divider settings several standard protocols. Table 2-6: Divider Settings Common Protocols
Internal Line Rate Data Width Frequency [Gb/s] [16b/20b] [GHz] 4.25 2.125 1.0625 Fibre Channel (Multi-Rate) 4.25 2.125 1.0625 XAUI GigE Aurora (Single Rate) 3.125 1.25 6.25 3.125 1.25 Aurora (Multi-Rate) 6.25 3.125 1.25 Serial RapidIO (Single Rate) 3.125 1.25 Serial RapidIO (Multi-Rate) 3.125 1.25 SATA PCIe Optimal Jitter 2.125 2.125 2.125 2.125 2.125 2.125 3.125 3.125 3.125 3.125 3.125 3.125 3.125 REFCLK Frequency [MHz] Typical 212.5 212.5 106.25 212.5 212.5 212.5 312.5 312.5 312.5 312.5 312.5 312.5 312.5 312.5 312.5 312.5 312.5 312.5 212.5 106.25 106.25 212.5 212.5 212.5 156.25 62.5 312.5 156.25 62.5 312.5 312.5 312.5 312.5 312.5 156.25 62.5 156.25 156.25 156.25 Using REFCLK Frequency
Standard
Fibre Channel (Single Rate)
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Table 2-6:
Divider Settings Common Protocols (Cont'd)
Internal Line Rate Data Width Frequency [Gb/s] [16b/20b] [GHz] 3.072 2.4576 1.2288 3.072 2.4576 2.4576 3.072 1.536 2.97 2.97 3.125 2.125 3.125 3.125 2.488 2.666 REFCLK Frequency [MHz] 491.52 491.52 491.52 614.4 614.4 390.625 531.25 390.625 390.625 333.25 Typical 245.76 245.76 245.76 307.2 307.2 148.5 390.625 265.625 390.625 390.625 333.25 122.88 122.88 122.88 153.6 153.6 148.5 74.25 390.625 265.625 195.3125 195.3125 155.5 166.625 Using REFCLK Frequency
Standard
PCIe REFCLK CPRI (Multi-Rate)
OBSAI (Multi-Rate) HD-SDI
3.072 1.536 2.97 1.485
Interlaken
6.25 4.25 3.125
SFI-5 OC-48 OTU-1
3.125 2.488 2.666
Some protocols shown twice single-rate configuration multi-rate configuration. single-rate configurations, only line rate required, reference clock optimized that particular line rate. multi-rate configurations, reference clock selected highest line rate, appropriate dividers selected support lower line rates. Reference clock frequencies provided range. general guidelines maximum, typical, minimum frequencies are: Maximum frequency selected minimum multiplication ratio. This option usually provides highest jitter performance. Typical reference clock frequency selected limit multiplication either depending protocol. lower line rate operation, minimum frequency selected allow multiplication Performance impact needs carefully considered reference clock below minimum recommended frequency used.
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Chapter Shared Transceiver Features
Power Down
Functional Description
transceiver supports range power-down modes. These modes support both generic power management capabilities well those defined Express SATA standards. transceiver offers different levels power control. Each channel each direction powered down separately using TXPOWERDOWN RXPOWERDOWN. TXPLLPOWERDOWN RXPLLPOWERDOWN port directly affects shared.
Ports Attributes
Table defines power-down ports. Table 2-7: Power-Down Ports
Port RXPLLPOWERDOWN RXPOWERDOWN[1:0] Clock Domain Async Async Description Input power down PLL. Powers down lane according PCIe® protocol encoding. (normal operation) (low recovery time power down) (longer recovery time) (lowest power state) TXPDOWNASYNCH Async Determines whether TXELECIDLE TXPOWERDOWN should treated synchronous asynchronous signals. Input power down PLL. Powers down lane according PCIe protocol encoding. (normal operation) (low recovery time power down) (longer recovery time; Receiver Detection still (lowest power state) Attributes control transition times between these power-down states.
TXPLLPOWERDOWN TXPOWERDOWN[1:0]
Async TXUSRCLK2 (TXPDOWNASYNCH makes this asynchronous)
Table defines power-down attributes. Table 2-8: Power Down Attributes
Type 10-bit Binary 12-bit Description Places several circuits power state when those blocks unused. Counter settings programmable transition time from state PCIe operation.
Attribute POWER_SAVE TRANS_TIME_FROM_P2
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Power Down
Table 2-8:
Power Down Attributes (Cont'd)
Type 8-bit 8-bit 10-bit Description Counter settings programmable transition time to/from states except PCIe operation. Counter settings programmable transition time when rate changed using RATE pins protocols including PCIe protocol (Gen2/Gen1 data rates). maximum value PCIe modes. Counter settings programmable transition time state PCIe operation.
Attribute TRANS_TIME_NON_P2 TRANS_TIME_RATE
TRANS_TIME_TO_P2
Generic Power-Down Capabilities
transceiver provides several power-down features that used wide variety applications. Table summarizes these capabilities. Table 2-9: Basic Power-Down Functions Summary
Controlled TXPLLPOWERDOWN Affects transceiver. Powers down well some circuits. transceiver. Powers down well some circuits. transceiver. transceiver.
Function Power Down
Power Down RXPLLPOWERDOWN
Power Down Power Down
TXPOWERDOWN[1:0] RXPOWERDOWN[1:0]
Power Down
activate power-down mode, active-High TXPLLPOWERDOWN RXPLLPOWER DOWN signal asserted. When either PLLPOWERDOWN asserted, corresponding some part circuits powered down. result, clocks derived from stopped. Recovery from this power state indicated assertion corresponding lock signal that either TXPLLLKDET RXPLLLKDET signal transceiver.
Power Down
When power control signals used Express implementations, TXPOWERDOWN RXPOWERDOWN used independently. However, when these interfaces used Express applications, only power states supported, shown Table 2-10. When using this power-down mechanism, following must TRUE: TXPOWERDOWN[1] TXPOWERDOWN[0] connected together. RXPOWERDOWN[1] RXPOWERDOWN[0] connected together. TXDETECTRX must strapped Low. TXELECIDLE must strapped TXPOWERDOWN[1] TXPOWERDOWN[0].
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Chapter Shared Transceiver Features
Table 2-10:
Power States Operation that Express Designs
Description Normal mode. active sending receiving data. Power-down mode. idle.
TXPOWERDOWN[1:0] RXPOWERDOWN[1:0]
Power-Down Features Express Operation
transceiver implements functions needed power-down states compatible with those defined Express PIPE specifications. When implementing Express compatible power control, following conditions must met: Table 2-11: TXPOWERDOWN RXPOWERDOWN signals each transceiver must connected together ensure that they same state times. TXPLLPOWERDOWN RXPLLPOWERDOWN signals must held inactive states.
Power States Express Operation
TXELECIDLE Description transmitting data. provides data bytes sent every clock cycle. transmitting electrical idle state. goes into loopback mode. permitted. must always into electrical idle state while state. behavior undefined TXELECIDLE deasserted while transmitting electrical idle state. permitted. must always into electrical idle state while behavior undefined TXELECIDLE deasserted while idle. does receiver detection operation. transmits beacon signaling idle.
TXPOWERDOWN[1:0] TXDETECTRX RXPOWERDOWN[1:0] State) (P0s state) Don't Care
state) Don't Care
state) Don't Care
Power-Down Transition Times
delays between changes power-down state when TXPOWERDOWN RXPOWERDOWN changed controlled TRANS_TIME_FROM_P2, TRANS_TIME_NON_P2, TRANS_TIME_TO_P2 attributes described Table 2-8. transition time when user changed line rate RATE input controlled TRANS_TIME_RATE attribute described Table 2-8.
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Loopback
Each TRANS_TIME delay terms internal clock cycles. internal clock rate using either TX_CLK25_DIVIDER RX_CLK25_DIVIDER attribute reference clock rate. Equation determines actual rate. TX_CLK25_DIVIDER RX_CLK25_DIVIDER Transition Time TRANS_TIME PLL_CLKIN Equation
Loopback
Functional Description
Loopback modes specialized configurations transceiver datapath where traffic stream folded back source. Typically, specific traffic pattern transmitted then compared check errors. Figure illustrates loopback test configuration with four different loopback modes.
X-Ref Target Figure
Link Near-End Test Structures Test Logic Near-End
RX-PCS RX-PMA
Link Far-End Test Structures Far-End
Traffic Checker
TX-PMA TX-PCS TX-PCS
TX-PMA
Traffic Generator
RX-PMA RX-PCS
UG366_c2_07_051509
Figure 2-7:
Loopback Testing Overview
Loopback test modes fall into broad categories: Near-end loopback modes loop transmit data back transceiver closest traffic generator. Far-end loopback modes loop received data back transceiver link.
Loopback testing used either during development deployed equipment fault isolation. traffic patterns used either application traffic patterns specialized pseudo-random sequences. Each transceiver built-in PRBS generator checker. Each transceiver features several loopback modes facilitate testing: Near-End Loopback (path Figure 2-7) Near-End Loopback (path Figure 2-7) Far-End Loopback (path Figure 2-7) Far-End Loopback (path Figure 2-7)
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Chapter Shared Transceiver Features
Ports Attributes
Table 2-12 defines loopback ports. Table 2-12: Loopback Ports
Clock Domain Async Description 000: Normal operation 001: Near-End Loopback 010: Near-End Loopback 011: Reserved 100: Far-End Loopback 101: Reserved 110: Far-End Loopback
Port LOOPBACK[2:0]
There loopback attributes.
Dynamic Reconfiguration Port
Functional Description
dynamic reconfiguration port (DRP) allows dynamic change parameters GTXE1 primitive. interface processor-friendly synchronous interface with address (DADDR) separated data buses reading (DO) writing (DI) configuration data GTXE1 primitive. enable signal (DEN), read/write signal (DWE), ready/valid signal (DRDY) control signals that implement read write operations, indicate operation completion, indicate availability data. Refer Virtex-6 FPGA Configuration User Guide detailed descriptions timing diagrams operations.
Ports Attributes
Table 2-13 defines ports. Table 2-13:
Port DADDR[6:0] DCLK
Ports
Clock Domain DCLK DCLK address bus. interface clock. enable signal. read write operation performed. Enables read write operation. Description
DI[15:0] DO[15:0]
DCLK DCLK
Data writing configuration data from FPGA logic resources transceiver. Data reading configuration data from transceiver FPGA logic resources.
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Dynamic Reconfiguration Port
Table 2-13:
Port DRDY
Ports (Cont'd)
Clock Domain DCLK DCLK Description Indicates operation complete write operations data valid read operations. write enable. Read operation when Write operation when
There attributes. Note: Attributes that have impact entire Quad (the cluster four transceivers)
writing first transceiver Quad. first transceiver Quad lowest coordinates. Refer "Implementation," page details transceiver placement numbering.
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Chapter
Transmitter
Overview
This chapter shows configure each functional blocks inside transmitter. Each transceiver includes independent transmitter, which consists PMA. Figure shows functional blocks transmitter. Parallel data flows from FPGA into FPGA interface, through PMA, then driver high-speed serial data.
X-Ref Target Figure
Driver PCIe
Pre/ Post
Gearbox Pattern Generator Phase Adjust FIFO Oversampling PIPE Control FPGA Interface
PISO
Polarity
Divider
PCIe Beacon SATA
TX-PMA
Parallel Data (Near-End Loopback)
TX-PCS
From Parallel Data (Far-End Loopback) From Parallel Data (Far-End Loopback)
UG366_c3_01_051509
Figure 3-1:
Transmitter Block Diagram
elements transmitter are: "FPGA Interface," page Initialization," page 8B/10B Encoder," page Gearbox," page Buffer," page Buffer Bypass," page Pattern Generator," page
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Chapter Transmitter
Oversampling," page Polarity Control," page
Clock Divider Control," page Configurable Driver," page Receiver Detect Support Express Designs," page Out-of-Band Signaling," page
FPGA Interface
Functional Description
FPGA interface FPGA's gateway datapath transceiver. Applications transmit data through transceiver writing data TXDATA port positive edge TXUSRCLK2. width port configured one, two, four bytes wide. actual width port depends TX_DATA_WIDTH attribute TXENC8B10BUSE port settings. Port widths bits. rate parallel clock (TXUSRCLK2) interface determined line rate, width TXDATA port, whether 8B/10B encoding enabled. some operating modes, second parallel clock (TXUSRCLK) must provided internal logic transmitter. This section shows drive parallel clocks explains constraints those clocks correct operation. highest transmitter data rates require 4-byte interface achieve TXUSRCLK2 rate specified operating range.
Interface Width Configuration
Virtex®-6 FPGA transceiver contains internal 2-byte datapath. FPGA interface width configurable setting TX_DATA_WIDTH attribute. When 8B/10B encoder enabled, FPGA interface must configured bits, bits, bits. When 8B/10B encoder bypassed, FPGA interface configured available widths: bits. Table shows interface width datapath selected. 8B/10B encoding described more detail 8B/10B Encoder," page Table 3-1: FPGA Interface Datapath Configuration
TX_DATA_WIDTH FPGA Interface Width bits bits bits bits bits bits bits bits bits Internal Data Width bits bits bits bits bits bits bits bits bits
TXENC8B10BUSE
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FPGA Interface
When 8B/10B encoder bypassed TX_DATA_WIDTH TXCHARDISPMODE TXCHARDISPVAL ports used extend TXDATA port from bits, bits, bits. Table shows data transmitted when 8B/10B encoder disabled. Table 3-2: Data Transmitted when 8B/10B Encoder Bypassed
Data transmission order right left
TXCHARDISPMODE[3] TXCHARDIPSVAL[3]
TXCHARDISPMODE[2] TXCHARDIPSVAL[2]
TXCHARDISPMODE[1] TXCHARDIPSVAL[1]
TXCHARDISPMODE[0] TXCHARDIPSVAL[0]
TXDATA[31:24]
TXDATA[23:16]
TXDATA[15:8]
Data Transmitted
TXUSRCLK TXUSRCLK2 Generation
FPGA interface includes parallel clocks: TXUSRCLK TXUSRCLK2. TXUSRCLK internal clock logic transmitter. required rate TXUSRCLK depends internal datapath width GTXE1 primitive line rate transmitter. Equation shows calculate required rate TXUSRCLK. Line Rate Equation TXUSRCLK Rate -Internal Datapath Width TXUSRCLK generated internally transceiver. This functionality controlled GEN_TXUSRCLK attribute. Table describes situations which TXUSRCLK generated internally transceiver. these cases, TXUSRCLK port must tied Low. Table 3-3: TXUSRCLK Internal Generation Configurations
TX_DATA_WIDTH 1-Byte 2-Byte 4-Byte
Notes:
single lane protocols such Gb/s Ethernet, "GTX Lanes Channel" multiple lane protocols like XAUI, "GTX Lanes Channel" more.
Lanes Channel(1) more
GEN_TXUSRCLK TRUE FALSE TRUE FALSE
TXUSRCLK2 main synchronization clock signals into side transceiver. Most signals into side transceiver sampled positive edge TXUSRCLK2. TXUSRCLK2 TXUSRCLK have fixed-rate relationship based TX_DATA_WIDTH setting. Table shows relationship between TXUSRCLK2 TXUSRCLK TX_DATA_WIDTH values.
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TXDATA[7:0]
Chapter Transmitter
Table 3-4:
TXUSRCLK2 Frequency Relationship TXUSRCLK
TX_DATA_WIDTH TXUSRCLK2 Frequency FTXUSRCLK2 FTXUSRCLK FTXUSRCLK2 FTXUSRCLK FTXUSRCLK2 FTXUSRCLK
Byte Byte Byte
These rules about relationships between clocks must observed TXUSRCLK TXUSRCLK2: TXUSRCLK TXUSRCLK2 must positive-edge aligned, with little skew possible between them. result, low-skew clock resources (BUFGs BUFRs) should used drive TXUSRCLK TXUSRCLK2. Table Table describe appropriate GEN_TXUSRCLK setting TXUSRCLK2 frequency requirements. cases where TXUSRCLK generated user, designer must ensure that TXUSRCLK TXUSRCLK2 positive-edge aligned. Even though they might different frequencies, TXUSRCLK, TXUSRCLK2, transmitter reference clock must have same oscillator their source. Thus TXUSRCLK TXUSRCLK2 must multiplied divided versions transmitter reference clock.
Ports Attributes
Table defines FPGA Interface ports. Table 3-5: FPGA Interface Ports
Port MGTREFCLKFAB[1:0] TXCHARDISPMODE[3:0] TXCHARDISPVAL[3:0] TXDATA[31:0] Clock Domain Clock TXUSRCLK2 TXUSRCLK2 TXUSRCLK2 Description Reserved. this port. When 8B/10B encoding disabled, TXCHARDISPMODE used extend data 20-bit interfaces. When 8B/10B encoding disabled, TXCHARDISPVAL used extend data 20-bit interfaces. transmitting data. width this port depends TX_DATA_WIDTH: TXDATAWIDTH 8,10: TXDATA[7:0] bits wide TXDATAWIDTH 16,20: TXDATA[15:0] bits wide TXDATAWIDTH 32,40: TXDATA[31:0] bits wide When 10-bit, 20-bit, 40-bit required, TXCHARDISPVAL TXCHARDISPMODE ports from 8B/10B encoder concatenated with TXDATA port. Table 3-2. TXUSRCLK Clock This port used provide clock internal datapath. some cases, this clock internally generated. Table 3-3. This port used synchronize FPGA logic with interface. This clock must positive-edge aligned TXUSRCLK when TXUSRCLK provided user.
TXUSRCLK2
Clock
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Initialization
Table defines FPGA Interface attributes. Table 3-6: FPGA Interface Attributes
Type Boolean Description Controls internal generation TXUSRCLK available certain modes operation. "TXUSRCLK TXUSRCLK2 Generation," page more details. TRUE: TXUSRCLK internally generated. TXUSRCLK must tied Low. FALSE: TXUSRCLK must provided user. TX_DATA_WIDTH Integer Sets width TXDATA port. When 8B/10B encoding enabled, TX_DATA_WIDTH must Valid settings "Interface Width Configuration," page more details.
Attribute GEN_TXUSRCLK
Initialization
Functional Description
transceiver must reset before used. There three ways reset transceiver: Power configure FPGA. Power-up reset covered this section. Drive GTXTXRESET/GTXRXRESET port High trigger full asynchronous reset transceiver. GTXTXRESET covered this section.
reset ports described this section initiate internal reset state machines when driven High. internal reset state machines held reset state until these same reset ports driven Low. completion these state machines signaled through TXRESETDONE/RXRESETDONE ports.
Ports Attributes
Table defines initialization ports. Table 3-7: Initialization Ports
Port GTXTEST[12:0] GTXTXRESET Clock Domain Async Async Description Reserved. Tied 1000000000000. This port driven High then deasserted start full reset sequence. This sequence takes about seconds complete, systematically resets subcomponents transmitter. This port resets transceiver when driven High. affects clock generated from PMA. When this reset asserted deasserted, TXRESET must also asserted deasserted. Reserved. Must tied 11111111111111111111. This port resets delay aligner buffer bypass mode. Buffer Bypass," page
PLLTXRESET
Async
TSTIN[19:0] TXDLYALIGNRESET
Async Async
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Chapter Transmitter
Table 3-7:
TXRESET
Initialization Ports (Cont'd)
Port Clock Domain Async Async Description system reset. Resets FIFO, 8B/10B encoder other transmitter registers. This reset subset GTXTXRESET. This port goes High when transmitter finished reset ready use. this signal work correctly, reference clock clock inputs individual transceiver (TXUSRCLK, TXUSRCLK2) must driven.
TXRESETDONE
Table defines initialization attributes. Table 3-8: Initialization Attributes
Attribute TX_EN_RATE_RESET_BUF Type Boolean Description When TRUE, this attribute enables automatic buffer reset during rate change event initiated change TXRATE[1:0].
8B/10B Encoder
Functional Description
Many protocols 8B/10B encoding outgoing data. 8B/10B industry-standard encoding scheme that trades bits overhead byte improved performance. transceiver includes 8B/10B encoder encode data without consuming FPGA resources. encoding needed, block disabled minimize latency.
8B/10B Byte Ordering
8B/10B encoding requires transmitted first, transceiver always transmits right-most first. match with 8B/10B, 8B/10B encoder transceiver automatically reverses order (Figure 3-2). same reason, when 2-byte interface used, first byte transmitted (byte must placed TXDATA[7:0], second placed TXDATA[15:8]. When 4-byte interface used, byte must placed TXDATA[7:0], byte must placed TXDATA[15:8], byte must placed TXDATA[23:16], byte must placed TXDATA[31:24]. This placement ensures that byte bits sent before byte bits, required 8B/10B encoding.
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8B/10B Encoder
X-Ref Target Figure
TX_DATA_WIDTH
TX_DATA_WIDTH
TXDATA
TXDATA
8B/10B
8B/10B
Transmitted Last
Transmitted Transmitted First Last TX_DATA_WIDTH
Transmitted First
TXDATA
8B/10B
Transmitted Last
Transmitted First
UG366_c3_02_051509
Figure 3-2:
8B/10B Encoding
Characters
8B/10B table includes special characters characters) that often used control functions. transmit TXDATA character instead regular data, TXCHARISK port must driven High. TXDATA valid character, encoder drives TXKERR High.
Running Disparity
8B/10B uses running disparity balance number ones zeros transmitted. Whenever character transmitted, encoder recalculates running disparity. current running disparity read from TXCHARDISP port. This running disparity calculated several cycles after TXDATA clocked into FPGA interface, cannot used decide next value send, required some protocols. Normally, running disparity used determine whether positive negative 10-bit code transmitted next. encoder allows next disparity value controlled directly well, accommodate protocols that disparity send control information. example, Idle character sent with reversed disparity might used trigger clock correction. Table shows TXCHARDISPMODE TXCHARDISPVAL ports used control outgoing disparity values.
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Chapter Transmitter
Table 3-9:
TXCHARDISPMODE TXCHARDISPVAL Outgoing Disparity
TXCHARDISPVAL Outgoing Disparity Calculated normally 8B/10B encoder Inverts normal running disparity when encoding TXDATA Forces running disparity negative when encoding TXDATA Forces running disparity positive when encoding TXDATA
TXCHARDISPMODE
Ports Attributes
Table 3-10 defines encoder ports. Table 3-10: Encoder Ports
Port TXBYPASS8B10B[3:0] Clock Domain TXUSRCLK2 Description TXBYPASS8B10B controls operation 8B/10B encoder per-byte basis. only effective when TXENC8B10B High (8B/10B enabled) RX_DATA_WIDTH {10, 40}. Table 4-43, page additional information RX_DATA_WIDTH. TXBYPASS8B10B[3] corresponds TXDATA[31:24] TXBYPASS8B10B[2] corresponds TXDATA[23:16] TXBYPASS8B10B[1] corresponds TXDATA[15:8] TXBYPASS8B10B[0] corresponds TXDATA[7:0] TXBYPASS8B10B[x] encoder byte bypassed TXBYPASS8B10B[x] encoder byte used TXCHARDISPMODE[3:0] TXUSRCLK2 TXCHARDISPMODE TXCHARDISPVAL allow 8B/10B disparity outgoing data controlled when 8B/10B encoding enabled. When 8B/10B encoding disabled, TXCHARDISPMODE used extend data interfaces with width that multiple TXCHARDISPMODE[3] corresponds TXDATA[31:24] TXCHARDISPMODE[2] corresponds TXDATA[23:16] TXCHARDISPMODE[1] corresponds TXDATA[15:8] TXCHARDISPMODE[0] corresponds TXDATA[7:0] TXCHARDISPVAL[3:0] TXUSRCLK2 TXCHARDISPVAL TXCHARDISPMODE allow 8B/10B disparity outgoing data disparity controlled when 8B/10B encoding enabled. When 8B/10B encoding disabled, TXCHARDISPVAL used extend data 20-bit interfaces (see "FPGA Interface," page 72). TXCHARDISPVAL[3] corresponds TXDATA[31:24] TXCHARDISPVAL[2] corresponds TXDATA[23:16] TXCHARDISPVAL[1] corresponds TXDATA[15:8] TXCHARDISPVAL[0] corresponds TXDATA[7:0]
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Gearbox
Table 3-10:
Encoder Ports (Cont'd)
Port Clock Domain TXUSRCLK2 Description TXCHARISK High send TXDATA 8B/10B character. TXCHARISK should only asserted TXDATA values representing valid K-characters. TXCHARISK[3] corresponds TXDATA[31:24] TXCHARISK[2] corresponds TXDATA[23:16] TXCHARISK[1] corresponds TXDATA[15:8] TXCHARISK[0] corresponds TXDATA[7:0] TXCHARISK undefined bytes that bypass 8B/10B encoding.
TXCHARISK[3:0]
TXENC8B10BUSE
TXUSRCLK2
TXENC8B10BUSE High enable 8B/10B encoder. TX_DATA_WIDTH must when 8B/10B encoder enabled. 8B/10B encoder bypassed. This option reduces latency. 8B/10B encoder enabled.
TXKERR[3:0]
TXUSRCLK2
TXKERR indicates invalid code character specified. TXKERR[3] corresponds TXDATA[31:24] TXKERR[2] corresponds TXDATA[23:16] TXKERR[1] corresponds TXDATA[15:8] TXKERR[0] corresponds TXDATA[7:0]
TXRUNDISP[3:0]
TXUSRCLK2
TXRUNDISP indicates current running disparity 8B/10B encoder. This disparity corresponds TXDATA clocked several cycles earlier. TXRUNDISP[3] corresponds previous TXDATA[31:24] data TXRUNDISP[2] corresponds previous TXDATA[23:16] data TXRUNDISP[1] corresponds previous TXDATA[15:8] data TXRUNDISP[0] corresponds previous TXDATA[7:0] data
There encoder attributes.
Enabling Disabling 8B/10B Encoding
enable 8B/10B encoder, TXENC8B10BUSE must driven High. disable 8B/10B encoder given transceiver, TXENC8B10BUSE must driven Low. When encoder turned off, operation TXDATA port described "FPGA Interface," page
Gearbox
Functional Description
Some high-speed data rate protocols 64B/66B encoding reduce overhead 8B/10B encoding while retaining benefits encoding scheme. gearbox provides support 64B/66B 64B/67B header payload combining. Interlaken interface protocol specification uses 64B/67B encoding scheme. Refer Interlaken specification further information. Interlaken specification
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Chapter Transmitter
downloaded from: gearbox only supports 2-byte 4-byte interfaces. 1-byte interface supported. Scrambling data done FPGA logic. Virtex-6 FPGA Transceiver Wizard example code scrambler.
Ports Attributes
Table 3-11 defines gearbox ports. Table 3-11: Gearbox Ports
Clock Domain TXUSRCLK2 Description This output indicates data applied 64/66 64/67 gearbox when GEARBOX_ENDEC gearbox. data applied Data must applied TXHEADER[2:0] TXSEQUENCE[6:0] TXUSRCLK2 TXUSRCLK2 These ports header inputs. [1:0] used 64/66 gearbox, [2:0] used 64/67 gearbox. These inputs used fabric sequence counter when gearbox used. [5:0] used 64/66 gearbox, [6:0] used 64/67 gearbox. This input indicates first word applied after reset 64/66 64/67 gearbox. internal sequencer counter must enabled GEARBOX_ENDEC attribute.
Port TXGEARBOXREADY
TXSTARTSEQ
TXUSRCLK2
Table 3-12 defines gearbox attributes. Table 3-12: Gearbox Attributes
Type Description
Attribute GEARBOX_ENDEC
3-Bit Binary This attribute indicates gearbox modes: Always enable gearbox decoder encoding this external sequence counter apply inputs TXSEQUENCE internal sequence counter, gate input header data with TXGEARBOXREADY output encoding this 64B/67B Gearbox mode Interlaken 64B/66B Gearbox
TXGEARBOX_USE
Boolean
When TRUE, this attribute enables gearbox.
Enabling Gearbox
enable gearbox transceiver, TXGEARBOX_USE attribute TRUE. GEARBOX_ENDEC attribute must enable Gearbox decoder. decoder controls transceiver's gearbox gearbox. transceiver's gearbox gearbox same mode.
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Gearbox
Gearbox Byte Ordering
Figure shows example first five cycles data entering data exiting gearbox 64B/66B encoding when using two-byte logic interface. input consists 2-bit header bits data. first cycle, header bits data exit gearbox. second cycle, remaining data bits from previous cycle's TXDATA input along with data bits from current TXDATA input exit gearbox. This continues third fourth cycle. fifth cycle, output gearbox contains remaining data bits from first 66-bit block, header second 66-bit block, data bits from second 66-bit block. shown Figure 3-3, header bits serialized first followed data bits.
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X-Ref Target Figure
Transmitted First Cycle
Transmitted Last
Output Gearbox
TXHEADER
TXDATA
Transmitted First Cycle
Transmitted Last
Output Gearbox
TXDATA Transmitted First Cycle
Transmitted Last
Output Gearbox
TXDATA Transmitted First Cycle
Transmitted Last
Output Gearbox
TXDATA Transmitted First Cycle
Transmitted Last
Output Gearbox
TXHEADER
TXDATA
UG366_c3_03_051509
Figure 3-3:
Gearbox Ordering
Gearbox Operating Modes
gearbox operating modes. external sequence counter operating mode must implemented user logic. second mode uses internal sequence counter. gearbox only supports 2-byte 4-byte interfaces FPGA logic.
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Gearbox
External Sequence Counter Operating Mode
shown Figure 3-4, external sequence counter operating mode uses TXSEQUENCE[6:0], TXDATA[31:0], TXHEADER[2:0] inputs. binary counter must exist user logic drive TXSEQUENCE input port. 64B/66B encoding, counter increments from repeats from 64B/67B encoding, counter increments from repeats from When using 64B/66B encoding, TXSEQUENCE[6] logic unused TXHEADER[2] logic sequence counter increment ranges 32}, 66}) identical both 2-byte 4-byte interfaces. However, counter must increment once every TXUSRCLK2 cycles when using 2-byte interface every TXUSRCLK2 cycle when using 4-byte interface.
X-Ref Target Figure
Design FPGA Logic
TXDATA[15:0] TXDATA[31:0] Data Source Gearbox Transceiver) TXHEADER[2:0] Pause TXSEQUENCE[6:0] Sequence Counter 0-32 0-66
UG366_c3_04_051509
Figure 3-4:
Gearbox External Sequence Counter Mode
nature 64B/66B 64B/67B encoding schemes, user data held (paused) during various sequence counter values. Data then paused TXUSRCLK2 cycles 2-byte mode TXUSRCLK2 cycle 4-byte mode. Valid data transfer resumed next TXUSRCLK2 cycle. data pause only applies TXDATA TXHEADER. 64B/67B encoding: data held (paused) sequence counter values 64B/66B encoding, data held (paused) counter value
Figure shows pause occurs counter value when using 4-byte interface, external sequence counter mode, 64B/66B encoding.
X-Ref Target Figure
TXUSRCLK20 TXHEADER0 TXSEQUENCE0 TXDATA0
87964daa 629a1470 8d14111a e3828711 8777acf1 7c580498 4e1fea87
120459d5
5714e976 523cd413 53365af5 4e658bf8 d3892141 c1a9308d
Pause USRCLK2 cycle. Data ignored.
UG366_c3_05_051509
Figure 3-5:
Pause Sequence Counter Value
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Chapter Transmitter
Figure shows pause occurs counter value when using 2-byte interface, external sequence counter mode, 64B/67B encoding.
X-Ref Target Figure
TXHEADER0 TXUSRCLK20 TXSEQUENCE0 TXDATA0
10ea 79e6 d48c c995 c9ec 651c 1921 2751 119e 3475 98e9 2043 87c7 a738
c5d4 aaeb 2467 0959 aced 0509 0e26 0646 0996 812a e700 b320 6859
Pause USRCLK2 cycles. Data ignored.
UG366_c3_06_051509
Figure 3-6:
Pause Sequence Counter Value
sequence transmitting 64B/67B data external sequence counter mode Assert TXRESET wait until reset cycle completed. During reset, drive 7'h00 TXSEQUENCE, header information TXHEADER[2:0], initial data TXDATA. This state held indefinitely readiness data transmission. count drive data TXDATA header information TXHEADER. 2-byte interface, drive second bytes TXDATA while still count sequence counter increments while driving data TXDATA. After applying bytes data, counter increments drives data TXDATA header information TXHEADER[2:0]. count stop data pipeline. count drive data TXDATA. count stop data pipeline. count drive data TXDATA.
count stop data pipeline. count drive data TXDATA. sequence transmitting 64B/66B data external sequence counter mode Assert TXRESET wait until reset cycle completed. During reset, drive 6'h00 TXSEQUENCE, header information TXHEADER[1:0], initial data TXDATA. This state held indefinitely readiness data transmission. count drive data TXDATA header information TXHEADER[1:0]. 2-byte interface, drive second bytes TXDATA while still count sequence counter increments while driving data TXDATA. After applying bytes data, counter increments drives data TXDATA header information TXHEADER. count stop data pipeline. count drive data TXDATA.
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Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
Gearbox
Internal Sequence Counter Operating Mode
shown Figure 3-7, internal sequence counter operating mode uses TXSTARTSEQ input TXGEARBOXREADY output addition TXDATA data inputs TXHEADER header inputs. this model, TXSEQUENCE inputs used. model similar previous model except that TXGEARBOXREADY output used.
X-Ref Target Figure
Design FPGA Logic
TXDATA[15:0] TXDATA[31:0]
Gearbox Transceiver)
TXHEADER[2:0] Data Source TXSTARTSEQ
TXGEARBOXREADY
UG366_c3_07_051509
Figure 3-7:
Gearbox Internal Sequence Counter Mode
TXSTARTSEQ input indicates gearbox when first byte data after reset valid. TXSTARTSEQ asserted High when first byte valid data applied after reset condition. TXDATA TXHEADER inputs must held stable after reset, TXSTARTSEQ must held until data applied continuously. There requirements long user wait before starting transmit data. TXSTARTSEQ asserted High along with first bytes/four bytes valid data before. After first bytes data, TXSTARTSEQ held value that convenient. After data driven, TXGEARBOXREADY deasserted either TXUSRCLK2 cycles (4-byte mode) three TXUSRCLK2 cycles (2-byte mode). Figure Figure show behavior TXGEARBOXREADY 4-byte interface 2-byte interface, respectively. When TXGEARBOXREADY deasserted Low, only TXUSRCLK2 cycle remains before data pipe must stopped. one-cycle latency fixed cannot changed. After cycle latency, data must held through bytes (one TXUSRCLK2 cycle 4-byte mode TXUSRCLK2 cycles 2-byte mode) then data continued driven. Only data must held. TXGEARBOXREADY transitions High cycle where data must driven. this mode operation, number hold points identical when using external sequence counter mode 64B/67B 64B/66B.
Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
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Chapter Transmitter
X-Ref Target Figure
RESETDONE0 TXGEARBOXREADY0 TXHEADER TXSTARTSEQ0 TXDATA0 TXUSRCLK20
81300de0 18c72cde 19928750 80209e96
GEARBOXREADY Data still taken this cycle.
GEARBOXREADY High Data latched Gearbox.
UG366_c3_8_051509
GEARBOXREADY Data latched Gearbox.
Figure 3-8:
X-Ref Target Figure
Gearbox Internal Sequence Mode, 4-Byte Interface, 64B/67B
TXHEADER TXSTARTSEQ0 TXUSRCLK20 TXGEARBOXREADY0 TXDATA0
1ca6
919a
4a95
2e71
58c3
1298
dac0
406e
036b
GEARBOXREADY Data still taken this cycle.
GEARBOXREADY Data latched Gearbox. GEARBOXREADY High Data latched Gearbox.
GEARBOXREADY Data latched Gearbox.
UG366_c3_9_051509
Figure 3-9:
Gearbox Internal Sequence Mode, 2-Byte Interface, 64B/66B
sequence transmitting data internal sequence counter mode Hold TXSTARTSEQ Low. Assert TXRESET wait until reset cycle completed. TXGEARBOXREADY goes High. During reset, place appropriate header data TXHEADER initial data TXDATA. This state held indefinitely readiness data transmission. Drive TXSTARTSEQ High place first valid header information TXHEADER data TXDATA. Continue drive header information data until TXGEARBOXREADY goes Low. When TXGEARBOXREADY goes Low, drive last bytes data header information (4-byte input mode). Hold data pipeline four bytes data (one TXUSRCLK2 cycle 4-byte input TXUSRCLK2 cycles 2-byte input). next TXUSRCLK2 cycle, drive data TXDATA inputs. TXGEARBOXREADY asserted High previous TXUSRCLK2 cycle.
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Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
Buffer
Buffer
Functional Description
datapath internal parallel clock domains used PCS: parallel clock domain (XCLK) TXUSRCLK domain. transmit data, XCLK rate must match TXUSRCLK rate, phase differences between domains must resolved. Figure 3-10 shows XCLK TXUSRCLK domains.
X-Ref Target Figure 3-10
Serial Clock
Parallel Clock (XCLK)
Parallel Clock (TXUSRCLK)
FPGA Parallel Clock (TXUSRCLK2)
Pre/ Driver Post PCIe
PCIe Beacon PISO Polarity SATA
Gearbox Pattern Generator PIPE CONTROL
FPGA Interface
Divider
Phase Adjust FIFO Oversampling
TX-PMA
TX-PCS
Parallel Data (Near-End Loopback) From Parallel Data (Far-End Loopback) From Parallel Data (Far-End Loopback)
UG366_c3_10_051509
Figure 3-10:
Clock Domains
transmitter includes buffer phase-alignment circuit resolve phase differences between PMACLK TXUSRCLK domains. datapaths must these circuits. Table 3-13 shows trade-offs between buffering phase alignment. Table 3-13: Buffering Phase Alignment
Buffer Ease Latency Skew Reduction Oversampling buffer used when possible. robust easy operate. latency critical, buffer must bypassed. buffer required skew reduction. buffer required oversampling. Phase Alignment Phase alignment requires extra logic additional constraints clock sources. TXOUTCLK cannot used. Phase alignment uses fewer registers datapath. phase-alignment circuit used reduce skew between separate transceivers. transceivers involved must same line rate.
Virtex-6 FPGA Transceivers User Guide UG366 (v1.0) June 2009
www.xilinx.com
Chapter Transmitter
Ports Attributes
Table 3-14 defines buffer ports. Table 3-14: Buffer Ports
Clock Domain TXUSRCLK2 buffer status. TXBUFSTATUS[1]: buffer overflow underflow FIFO overflowed underflowed overflow/underflow error TXBUFSTATUS[0]: buffer fullness FIFO least half full FIFO less than half full When TXBUFSTATUS[1] goes High, remains High until TXRESET asserted. TXRESET Async system reset. This input resets FIFO, 8B/10B encoder, other transmitter registers. This reset subset GTXTXRESET. Description
Port TXBUFSTATUS[2:0]
Table 3-14 defines buffer attributes. Table 3-15: Buffer Attributes
Type Boolean bypass buffer. TRUE: buffer. FALSE: Bypass buffer. TX_OVERSAMPLE_MODE Boolean Enables/disables built-in digital oversampling. TRUE: Built-in digital oversampling enabled. This option used slow line rates. FALSE: Built-in digital oversampling disabled. This option used normal mode. Description
Attribute TX_BUFFER_USE
Using Buffer
buffer resolve phase differences between
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