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UG198 (v2.1) November 2008
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Revision History
following table shows revision history this document.
Date 03/31/08 05/08/08 Version Initial Xilinx release. Table 5-3: Corrected Express parameter values. Table 7-14: Corrected Nominal Threshold Voltage sub-table OOBDETECT_THRESHOLD_0/1 Table 7-35 Table 7-37: Corrected RXBUFSTATUS0/1 description. Table Table E-2: Replaced with tables. Revision
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UG198 (v2.1) November 2008
Date 09/04/08
Version
Revision Added 3G-SDI Table Table 5-3. Added (Pad) pins Table 1-2. Revised bulleted conditions under Equation 5-1. Revised descriptions DFEEYEDACMONITOR0/1, DFETAP20/1,
DFETAP2MONITOR0/1, DFETAP30/1, DFETAP3MONITOR0/1, DFETAP40/1, DFETAP4MONITOR0/1 Table 7-5.
Revised descriptions DFE_CAL_TIME, DFE_CFG_0/1, RX_EN_IDLE_HOLD_DFE_0/1 Table 7-6. Added "Channel Optimization Approach", "Use Mode Fixed Mode", "Example Linear Equalizer Settings Chip-to-Chip Applications", "Example Linear Equalizer Settings Backplane Applications" "Decision Feedback Equalization" Chapter Corrected encodings RXSTATUS0/1 Table 7-13. Revised second sentence Overview section "Configurable Channel Bonding (Lane Deskew)" Chapter Added note about channel-bonded transceivers being same column page Figure 7-34. Added nominal rating RREF footnote Table 10-2 note following table. Added Boundary-Scan footnote page 267. Revised "Special Conditions: Unused GTX_DUAL Column" Chapter Added notes about adjacency guidelines "SelectIO Crosstalk Guidelines" Chapter 09/23/08 Added device throughout document:
Inserted device descriptions paragraphs page Inserted Figure 1-2, page showing GTX_DUAL tiles XC5VTX150T. Added analog pins Table 1-2, page Table 10-1, page 249. Added device footnote Table 1-5, page Described columns "Description" Chapter page Added packages "Package Placement Information" Chapter page Inserted Table 4-2, page showing GTX_DUAL analog placement. Inserted placement diagrams (Figure 4-8, page through Figure 4-19, page 81). Clarified cases "Channel Bonding Mode," page 220. Added device footnote Table 10-2, page 250. Inserted descriptions external precision resistor requirements resistor calibration circuits device "Description" Chapter page 251. Inserted device Table A-1, page 309, Table A-2, page 310, Table A-3, page 312, Table A-4, page 313, Table A-6, page 314, Table A-7, page 314, Table A-11, page 317, Table A-12, page 317, Table A-13, page 318.
Moved note about adjacency guidelines above Table 10-8, page 270.
UG198 (v2.1) November 2008
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RocketIO Transceiver
Date 11/17/08
Version
Revision Added SIM_MODE attribute Table 1-5, page Table 3-1, page Added "SIM_MODE," page Corrected MGTAVTTRXC_L/R pins 1759 package Table 4-2, page Revised "power control" "power down" throughout "Generic Power-Down Capabilities," page 109. Removed Relative Power Savings Recovery Time columns from Table 5-12, page 109. Table 6-4, page 126, corrected encoding TXKERR[3:0] TXRUNDISP[3:0] defined them based interface width. Added notes regarding GTX_DUAL tile connections devices above Figure 10-2, page 252. Revised Figure 10-2, page 252. Added Figure 10-3, page Figure 10-4, page 253. Revised caption Figure 10-7, page include reference column. Added bulleted notes regarding calibration powering devices page 257. Rewrote "Partially used GTX_DUAL column," page 268. Table 10-6, page 268, revised table note added table note Added bullet regarding adjacency guideline devices page 269.
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UG198 (v2.1) November 2008
Table Contents
Revision History
Preface: About This Guide
Guide Contents Additional Documentation Additional Support Resources Typographical Conventions
Online Document
Section FPGA Level Design Chapter Introduction RocketIO Transceiver
Overview Ports Attributes
Chapter RocketIO Transceiver Wizard Chapter Simulation
Overview Ports Attributes Description
Limitations SmartModel Attributes SIM_GTXRESET_SPEEDUP SIM_MODE. SIM_PLL_PERDIV2 SIM_RECEIVER_DETECT_PASS Power-Up Reset Link Idle Reset Toggling Providing Clocks Simulation Simulating Verilog Defining Test Bench Simulating VHDL Simulation Environment Setup Example (ModelSim 6.1e Linux) SIM_PLL_PERDIV2 Calculation Example Example Express Design Example Gigabit Ethernet Design Example XAUI Design
Examples
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Chapter Implementation
Overview Ports Attributes Description Example GTX_DUAL Placement Package Placement Information
Chapter Tile Features
Tile Features Overview Shared
Overview Ports Attributes Description Examples Configuring Shared XAUI Operation Configuring Shared OC-48 Operation Configuring Shared Gigabit Ethernet Operation Configuring Shared Express Operation Overview Ports Attributes Description Clocking from External Source Clocking from Neighboring GTX_DUAL Tile Clocking using GREFCLK
Clocking
Reset
Overview Ports Attributes Description Reset Response Completion Configuration Reset When GTXRESET Port Asserted Component-Level Resets Link Idle Reset Support Resetting GTX_DUAL Tile Examples Power-up Configuration After Turning Reference Clock After Changing Reference Clock Parallel Clock Source Reset After Remote Power-up Electrical Idle Reset After Connecting RXP/RXN After Buffer Error After Buffer Error Before Channel Bonding After PRBS Error After Oversampler Error
Power Control
Overview Ports Attributes
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RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Description Generic Power-Down Capabilities Power Control Features Express Operation Power-Down Transition Times Examples
Dynamic Reconfiguration Port
Overview Ports Attributes Description
Chapter Transmitter (TX)
Transmitter Overview FPGA Interface
Overview Ports Attributes Description Configuring Width Interface Connecting TXUSRCLK TXUSRCLK2 Examples TXOUTCLK Driving 2-Byte Mode TXOUTCLK Driving 4-Byte Mode TXOUTCLK Driving 1-Byte Mode TXOUTCLK Driving Multiple Transceivers 4-Byte Interface REFCLKOUT Driving Multiple Transceivers with 4-Byte Interface. Overview Ports Attributes Description Enabling 8B/10B Encoding 8B/10B Byte Ordering Characters Running Disparity 8B/10B Bypass Overview Ports Attributes Description Enabling Gearbox Gearbox Byte Ordering Gearbox Operating Modes Overview Ports Attributes Description Using Buffer Using Phase-Alignment Circuit Minimize Skew Clocking Phase-Alignment Circuit Minimize Skew
Configurable 8B/10B Encoder
Gearbox
Buffering, Phase Alignment, Skew Reduction
Polarity Control
Overview Ports Attributes Description
RocketIO Transceiver User Guide UG198 (v2.1) November 2008
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PRBS Generator
Overview Ports Attributes Description
Parallel Serial
Overview Ports Attributes Description
Configurable Driver
Overview Ports Attributes Description Differential Voltage Control Pre-emphasis Configurable Termination Impedance TXINHIBIT
Receive Detect Support Express Operation
Overview Ports Attributes Description
Out-of-Band/Beacon Signaling
Overview Ports Attributes Description Beacon Signaling Express Operations. Signaling SATA Operations
Chapter Receiver (RX)
Receiver Overview Termination Equalization
Overview Ports Attributes Description Optional Built-in Coupling Configurable Termination Impedance Configurable Termination Voltage Optional 4-Mode Active Linear Equalization Overview Ports Attributes Description Channel Optimization Approach Mode Fixed Mode Example Linear Equalizer Settings Chip-to-Chip Applications Example Linear Equalizer Settings Backplane Applications. Overview Ports Attributes Description Detecting Electrical Idle Express Operation Detecting SATA Operation
Decision Feedback Equalization
OOB/Beacon Signaling
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RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Example
Clock Data Recovery
Overview Ports Attributes Description Reset Horizontal Sample Point Shift
Serial Parallel
Overview Ports Attributes Description
Oversampling
Overview Ports Attributes Description Configuring Line Rate Configuring Internal Datapath Clocks Activating Operating Oversampling Block
Polarity Control
Overview Ports Attributes Description
PRBS Detection
Overview Ports Attributes Description
Configurable Comma Alignment Detection
Overview Ports Attributes Description Enabling Comma Alignment Configuring Comma Patterns Activating Comma Alignment Alignment Status Signals Alignment Boundaries Manual Alignment
Configurable Loss-of-Sync State Machine
Overview Ports Attributes Description
Configurable 8B/10B Decoder
Overview Ports Attributes Description Enabling 8B/10B Decoder 8B/10B Decoder Byte Order Characters 8B/10B Commas. Running Disparity Disparity Errors Not-in-Table Errors
Configurable Elastic Buffer Phase Alignment
Overview
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Ports Attributes Description Using Elastic Buffer Using Phase Alignment Bypassing Elastic Buffer while Using Built-in Oversampling Overview Ports Attributes Description Enabling Clock Correction Setting Elastic Buffer Limits Setting Clock Correction Sequences Clock Correction Options Monitoring Clock Correction Overview Ports Attributes Description Enabling Channel Bonding Channel Bonding Mode Connecting Channel Bonding Ports Setting Channel Bonding Sequence Setting Maximum Skew Precedence between Channel Bonding Clock Correction Overview Ports Attributes Description Enabling Gearbox Gearbox Operating Modes Block Synchronization Overview Ports Attributes Description Configuring Width Interface Connecting RXUSRCLK RXUSRCLK2
Configurable Clock Correction
Configurable Channel Bonding (Lane Deskew)
Gearbox
FPGA Interface
Chapter Cyclic Redundancy Check
Overview Ports Attributes Description
Using Error Checking Primitive Using Blocks Integrating Blocks Integrating Blocks Implementation Block References
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RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Chapter Loopback
Overview Ports Attributes Description
Near-End Loopback Near-End Loopback Marginal Conditions Limitations Far-End Loopback Marginal Conditions Limitations Far-End Loopback
Chapter GTX-to-Board Interface
Analog Design Guidelines
Overview Ports Attributes Description
REFCLK Guidelines.
Overview Reference Clock Checklist. Description Oscillator Selection Sourcing More Than Differential Clock Input Pair from Oscillator Switching between Different Reference Clocks Coupling Unused Reference Clock Inputs GTX_DUAL Tiles Clock Forwarding Examples Vendors Devices Overview Description Linear Regulator Selection Criteria Regulator Design Guidelines Ferrite Selection Guidelines Capacitor Selection Guidelines Filter Network Design Guidelines Boundary-Scan Testing Guidelines Special Conditions: Unused GTX_DUAL Column
Providing Power
SelectIO Crosstalk Guidelines
Section Board Level Design Chapter Design Constraints Overview
Powering Transceivers
Power Distribution Architecture Regulator Selection Filtering
Reference Clock
Clock Sources Clock Traces
Coupling.
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Coupling Coupling External Capacitor Value Selection SelectIO Serial Transceiver Crosstalk Guidelines
Chapter Materials Traces
Fast Fast? Dielectric Losses
Relative Permittivity Loss Tangent Skin Effect Resistive Losses Choosing Substrate Material Trace Geometry Trace Characteristic Impedance Design Trace Routing Plane Splits Return Currents Simulating Lossy Transmission Lines.
Traces
Cable
Connectors Skew Between Conductors
Chapter Design Transitions
Excess Capacitance Inductance Time Domain Reflectometry Package Pads Differential Vias Crossover Vias Connectors Backplane Connectors Microstrip/Stripline Bends
Chapter Guidelines Examples
Summary Guidelines Escape Example HM-Zd Design Example.
Section Appendices Appendix Transceiver Design Migration
Overview Primary Differences
MGTs Device Clocking
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RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Serial Rate Support Encoding Support Clock Multipliers Flexibility Board Guidelines Power Supply Filtering Termination FPGA Logic Interface Loopback Serialization Defining Clock Correction Channel Bonding Sequences RXSTATUS
Other Minor Differences
Pre-emphasis, Differential Swing, Equalization
Appendix OOB/Beacon Signaling
Signaling SATA Operation Beacon Signaling Express Operation
Appendix 8B/10B Valid Characters Appendix Address GTX_DUAL Tile
Address Attribute. Address Location
Appendix Latency Design
Latency Latency
Appendix Advanced Clocking
Example
Index
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RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Preface
About This Guide
This document shows RocketIOGTX transceivers Virtex®-5 FPGAs. Complete up-to-date documentation Virtex-5 family FPGAs available Xilinx website http://www.xilinx.com/virtex5.
Guide Contents
This manual contains following chapters appendices: "Section FPGA Level Design"
Chapter "Introduction RocketIO Transceiver" Chapter "RocketIO Transceiver Wizard" Chapter "Simulation" Chapter "Implementation" Chapter "Tile Features" Chapter "GTX Transmitter (TX)" Chapter "GTX Receiver (RX)" Chapter "Cyclic Redundancy Check" Chapter "Loopback" Chapter "GTX-to-Board Interface" Chapter "Design Constraints Overview" Chapter "PCB Materials Traces" Chapter "Design Transitions" Chapter "Guidelines Examples" Appendix "MGT Transceiver Design Migration" Appendix "OOB/Beacon Signaling" Appendix "8B/10B Valid Characters" Appendix "DRP Address GTX_DUAL Tile" Appendix "Low Latency Design" Appendix "Advanced Clocking"
"Section Board Level Design"
"Section Appendices"
RocketIO Transceiver User Guide UG198 (v2.1) November 2008
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Preface: About This Guide
Additional Documentation
following documents also available download http://www.xilinx.com/virtex5. Virtex-5 Family Overview features product selection Virtex-5 family outlined this overview. Virtex-5 FPGA Data Sheet: Switching Characteristics This data sheet contains Switching Characteristic specifications Virtex-5 family. Virtex-5 FPGA User Guide This user guide includes chapters
Clocking Resources Clock Management Technology (CMT) Phase-Locked Loops (PLLs) Block Configurable Logic Blocks (CLBs) SelectIOResources SelectIO Logic Resources Advanced SelectIO Logic Resources
Virtex-5 FPGA RocketIO Transceiver User Guide This guide describes RocketIOGTP transceivers available Virtex-5 platforms.
Virtex-5 FPGA Embedded Processor Block PowerPC® Designs This reference guide description embedded processor block available Virtex-5 platform.
Virtex-5 FPGA Tri-Mode Ethernet Media Access Controller This guide describes dedicated Tri-Mode Ethernet Media Access Controller available Virtex-5 LXT, SXT, FXT, platforms.
Virtex-5 FPGA Integrated Endpoint Block User Guide Express Designs This guide describes integrated Endpoint blocks Virtex-5 LXT, SXT, FXT, platforms used Express® designs.
XtremeDSP Design Considerations This guide describes XtremeDSPslice includes reference designs using DSP48E slice.
Virtex-5 FPGA Configuration Guide This all-encompassing configuration guide includes chapters configuration interfaces (serial SelectMAP), bitstream encryption, Boundary-Scan JTAG configuration, reconfiguration techniques, readback through SelectMAP JTAG interfaces.
Virtex-5 FPGA System Monitor User Guide System Monitor functionality available Virtex-5 devices outlined this guide.
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RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Additional Support Resources
Virtex-5 FPGA Packaging Pinout Specifications This specification includes tables device/package combinations maximum I/Os, definitions, pinout tables, pinout diagrams, mechanical drawings, thermal specifications.
Virtex-5 FPGA Designer's Guide This guide provides information design Virtex-5 devices, with focus strategies making design decisions interface level.
following documents provide supplemental material useful this user guide:
Athavale, Abhijit Carl Christensen. High-Speed Serial Made Simple. UG200, Embedded Processor Block Virtex-5 FPGAs Reference Guide. Synthesis Simulation Design Guide Granberg, Tom. Handbook Digital Techniques High-Speed Design. Prentice-Hall. ISBN-10: 0-13-142291-X. ISBN-13: 978-0131422919. Grover, Frederick Ph.D. 1946. Inductance Calculations: Working Formulas Tables. York: Nostrand Company, Inc. Johnson, Howard. Signal Integrity Techniques Loss Budgeting RocketIO Transceivers. Johnson, Howard, Martin Graham. High-Speed Signal Propagation: Advanced Black Magic. Prentice-Hall. ISBN-10: 0-13-084408-X. ISBN-13: 978-0130844088. Montrose, Mark 1999. Printed Circuit Board. Institute Electrical Electronics Engineers, Inc. ISBN 0-7803-4703-X. Smith, Larry November 1984. Decoupling Capacitor Calculations CMOS Circuits. Proceedings EPEP Conference.
Williams, Ross Painless Guide Error Detection Algorithms. http://www.ross.net/crc/ (CRC pitstop). Schlichthaerle, Dietrich. Digital Filters: Basics Design. Springer. ISBN-10 3-540-66841-1. DS083, Virtex-II Virtex-II Platform FPGAs Complete Data Sheet. UG024, RocketIO Transceiver User Guide. UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide. XAPP209, IEEE 802.3 Cyclic Redundancy Check. XAPP562, Configurable LocalLink Reference Design. UG196, Virtex-5 FPGA RocketIO Transceiver User Guide. UG204, Virtex-5 FPGA RocketIO Transceiver Wizard Getting Started Guide.
Additional Support Resources
search database silicon software questions answers, create technical support case WebCase, Xilinx website http://www.xilinx.com/support.
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Preface: About This Guide
Typographical Conventions
This document uses following typographical conventions. example illustrates each convention.
Convention Meaning Example
References other documents Italic font Emphasis text Underlined Text Indicates link page.
Virtex-5 Configuration Guide more information. address asserted after clock event http://www.xilinx.com/virtex5
Online Document
following conventions used this document:
Convention Meaning Example section "Additional Documentation" details. Refer "Clock Management Technology (CMT)" Chapter details. Figure Virtex-5 FPGA Data Sheet http://www.xilinx.com latest documentation.
Blue text
Cross-reference link location current document
text Blue, underlined text
Cross-reference link location another document Hyperlink website (URL)
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RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Section FPGA Level Design
This section provides information needed incorporate RocketIOGTX transceivers into FPGA design, including: features characteristics transceivers RocketIO Wizard configure transceivers Mapping transceiver instances device resources Simulation transceiver designs Board-level clocking power requirements
This section includes following chapters:
"Introduction RocketIO Transceiver" "RocketIO Transceiver Wizard" "Simulation" "Implementation" "Tile Features" "GTX Transmitter (TX)" "GTX Receiver (RX)" "Cyclic Redundancy Check" "Loopback" "GTX-to-Board Interface"
RocketIO Transceiver User Guide UG198 (v2.1) November 2008
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RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Chapter
Introduction RocketIO Transceiver
Overview
RocketIOGTX transceiver power-efficient transceiver Virtex®-5 FPGAs. transceiver highly configurable tightly integrated with programmable logic resources FPGA. provides following features support wide variety applications: Current Mode Logic (CML) serial drivers/buffers with configurable termination, voltage swing, coupling. Programmable pre-emphasis, equalization, linear decision feedback equalization (DFE) optimized signal integrity. Line rates from Mb/s Gb/s, with optional digital oversampling required rates between Mb/s Mb/s. nominal operation range shared from 3.25 GHz. These nominal values, DS202: Virtex-5 FPGA Data Sheet specifications. Optional built-in features, such 8B/10B encoding, comma alignment, channel bonding, clock correction. Fixed latency modes minimized, deterministic datapath latency. Beacon signaling Express® designs Out-of-Band signaling including signal support SATA designs. RX/TX Gearbox provides header insertion extraction support 64B/66B 64B/67B (Interlaken) protocols. Receiver scan:
Vertical scan voltage domain testing purposes Horizontal scan time domain testing purposes
first-time user recommended read High-Speed Serial Made Simple [Ref which discusses high-speed serial transceiver technology applications. Table lists some standard protocols designers implement using transceiver. Xilinx CORE Generatortool includes Wizard automatically configure transceivers support these protocols perform custom configuration (see Chapter "RocketIO Transceiver Wizard"). GTX_DUAL tile offers data rate range features that allow physical layer support various protocols illustrated Table 1-1.
RocketIO Transceiver User Guide UG198 (v2.1) November 2008
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Chapter Introduction RocketIO Transceiver
Table 1-1:
List Standards Supported GTX_DUAL Tile
Data Rates Gb/s Gb/s Miscellaneous Features receive detect Loss Signal (LOS)/Idle state detect power states Beacon signaling Ground referenced termination
Compatible Protocols Express, Rev. 1.0a Express, Rev. Express, Rev.
Interlaken XAUI 802.3ae D5p0 OIF-CEI6G OC-12/48
3.125 Gb/s, 6.25 Gb/s 3.125 Gb/s 6.25 Gb/s 622.08/2488.32 Mb/s
Header insertion/extraction 64B/67B Equalizer (EQ), power mode 4-tap adaptive Allows FIFO bypassing synchronous operation digital oversampling Rate negotiation (allows operating different speeds)
FC-1, Revision FC-2, Revision FC-4, Revision 10GFC HD-SDI DVB-ASI 3G-SDI Base-CX4 802.3ak/D4.0 Gigabit Ethernet (1000BASE-CX 802.3z/D5.0) SATA Generation 1/2, Rev. 1.0a SATA Generation Rev. 1.0a SATA Generation Rev. 1.0a Serial RapidIO CPRI, Version Infiniband, Volume Release SFI-5 OBSAI RP3, Spec. Issue Aurora
1.0625 Gb/s 2.125 Gb/s 4.25 Gb/s 3.1875 Gb/s 176/270/360 Mb/s 1.485/1.4835 Gb/s Mb/s 2.970 Gb/s 3.125 Gb/s 1.25 Gb/s Gb/s Gb/s Gb/s 1.25/2.5/3.125/6.25 Gb/s 614.4/1228.8/2457.6 Mb/s Gb/s 2.488 3.125 Gb/s 768/1536/3072 Mb/s Mb/s Gb/s Synchronous clocking (bypass FIFOs) digital oversampling Rate negotiation Generation (entire link operates Generation 1/Generation speeds) beacon digital oversampling
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RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Overview
transceivers placed dual transceiver GTX_DUAL tiles Virtex-5 platform devices. This configuration allows transceivers share single with functions both, reducing size power consumption. Figure shows GTX_DUAL tile placement example Virtex-5 device (XC5VFX100T). GTX_DUAL tiles form single GTX_DUAL column right side device shown Figure 1-1. devices have GTX_DUAL column left side device column right side device shown Figure 1-2. embedded processor blocks Virtex-5 devices contain PowerPC® processor along with several additional modules. Additional information functional blocks Figure available following locations: Embedded Processor Block Virtex-5 FPGAs Reference Guide [Ref provides more information embedded processor block Virtex-5 FPGAs. Chapter "Cyclic Redundancy Check," provides more details blocks Figure 1-1. Virtex-5 FPGA Configuration Guide provides more information Configuration Clock, CMT, blocks. Virtex-5 FPGA Embedded Tri-Mode Ethernet User Guide provides detailed information Ethernet MAC. Virtex-5 FPGA Integrated Endpoint Block User Guide Express Designs provides detailed information Express compliance.
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Chapter Introduction RocketIO Transceiver
Virtex-5 FPGA (XC5VFX100T)
GTX_ DUAL Column Blocks Integrated Block Express Operation GTX_ DUAL X0_Y7
Embedded Processor Block
Blocks
GTX_ DUAL X0_Y6
Ethernet
Blocks
GTX_ DUAL X0_Y5
Blocks Column Configuration Clock Column Ethernet
GTX_ DUAL X0_Y4
Blocks Integrated Block Express Operation
GTX_ DUAL X0_Y3
Blocks
GTX_ DUAL X0_Y2
Embedded Processor Block
Integrated Block Express Operation
Blocks
GTX_ DUAL X0_Y1
Blocks
GTX_ DUAL X0_Y0
UG198_c1_01_071508
Notes:
This figure does illustrate exact size, location, scale functional blocks each other. does show correct number available resources. improve clarity, this figure does show CLB, DSP, block columns.
Figure 1-1:
GTX_DUAL Tile Inside Virtex-5 XC5VFX100T FPGA
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RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Overview
Virtex-5 FPGA (XC5VTX150T) GTX_ DUAL Column GTX_ DUAL X0_Y9 Blocks Blocks GTX_ DUAL Column GTX_ DUAL X1_Y9
GTX_ DUAL X0_Y8
Blocks
Blocks
GTX_ DUAL X1_Y8
GTX_ DUAL X0_Y7
Blocks
Blocks
GTX_ DUAL X1_Y7
GTX_ DUAL X0_Y6
Blocks
Blocks
GTX_ DUAL X1_Y6
GTX_ DUAL X0_Y5
Blocks
Ethernet
Blocks
GTX_ DUAL X1_Y5
Blocks Column Configuration Clock Column
GTX_ DUAL X0_Y4
Blocks Ethernet
GTX_ DUAL X1_Y4
GTX_ DUAL X0_Y3
Blocks Integrated Block Express Operation
Blocks
GTX_ DUAL X1_Y3
GTX_ DUAL X0_Y2 Blocks
Blocks
GTX_ DUAL X1_Y2
GTX_ DUAL X0_Y1
Blocks
Blocks
GTX_ DUAL X1_Y1
GTX_ DUAL X0_Y0
Blocks
Blocks
GTX_ DUAL X1_Y0
UG198_c1_03_071508
Notes: This figure does illustrate exact size, location, scale functional blocks each other. does show correct number available resources. improve clarity, this figure does show CLB, DSP, block columns. Channel bonding multiple transceivers different columns advanced feature. Contact your System specialist details. GTX_DUAL tiles column must used when connecting Ethernet blocks Integrated Block Express operation. When migrating design from device device, indices GTX_DUAL instantiations must changed from
Figure 1-2:
GTX_DUAL Tile Inside Virtex-5 XC5VTX150T FPGA
RocketIO Transceiver User Guide UG198 (v2.1) November 2008
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Chapter Introduction RocketIO Transceiver
Figure shows diagram GTX_DUAL tile, containing transceivers shared resources block. GTX_DUAL tile primitive used operate transceivers FPGA.
GTX_DUAL Tile Package Pins MGTTXP0 MGTTXN0 TXP0 TXN0 TX-PMA GTX0 FPGA Pins Data From FPGA
TX-PCS
TXDATA0[31:0] TXBYPASS8B10B0[3:0] TXCHARISK0[3:0] TXCHARDISPMODE0[3:0] TXCHARDISPVAL0[3:0] RXPOWERDOWN0[1:0] RXSTATUS0[2:0] RXDATA0[31:0]
Data FPGA
MGTRXP0 MGTRXN0
RXP0 RXN0
RX-PMA RX-PCS Shared Resources
RXDISPERR0[3:0] RXCHARISCOMMA0[3:0] RXCHARISSK0[3:0] RXRUNDISP0[3:0] RXVALID0[1:0] TXOUTCLK0 TXUSRCLK0 TXUSRCLK20 RXUSRCLK0 RXUSRCLK20 RXRECCLK0 CLKIN(1) TXOUTCLK1 TXUSRCLK1 TXUSRCLK21 RXUSRCLK1 RXUSRCLK21 RXRECCLK1
MGTAVTTTX MGTAVTTRX MGTAVTTTX
AVTTTX AVTTRX AVTTTX
Shared Lock Detection
Reset Control
MGTAVCC MGTAVCCPLL MGTAVCC
AVCC AVCCPLL AVCC
Clocking
Power Control
GTX1 MGTTXP1 MGTTXN1 TXP1 TXN1 TX-PMA
Data From FPGA
TXDATA1[31:0] TXBYPASS8B10B1[3:0] TXCHARISK1[3:0] TXCHARDISPMODE1[3:0]
TX-PCS RXPOWERDOWN1[1:0] RXSTATUS1[2:0] RXDATA1[31:0]
Data FPGA
MGTRXP1 MGTRXN1
RXP1 RXN1
RX-PMA RX-PCS
RXDISPERR1[3:0] RXCHARISCOMMA1[3:0] RXCHARISSK1[3:0] RXVALID1[1:0]
UG198_c1_02_010308
Notes:
CLKIN simplification clock source. Figure 5-3, page details CLKIN.
Figure 1-3:
GTX_DUAL Tile Block Diagram
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RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Ports Attributes
procedures configuring using each seven major blocks GTX_DUAL tile shown Figure discussed detail following sections: "Shared PLL," page (Chapter "Reset," page (Chapter "Clocking," page (Chapter "Power Control," page (Chapter "Dynamic Reconfiguration Port," page (Chapter "GTX Transmitter (TX)," page (Chapter "GTX Receiver (RX)," page (Chapter
Ports Attributes
This section contains alphabetical tables pins (Table 1-2), ports (Table Table 1-4), attributes (Table Table 1-6). Port Attribute tables this guide, names that with GTX0 transceiver tile, names that with GTX1 transceiver. Names that with shared. Table lists alphabetically signal names, directions, descriptions GTX_DUAL analog pins, provides links their detailed descriptions. Table 1-2:
MGTAVCC MGTAVCCPLL
GTX_DUAL Analog Summary
(Pad) (Pad) Description Section (Page)
Analog supply internal analog Analog Design circuits GTX_DUAL tile. Guidelines (page 249) Analog supply shared GTX_DUAL tile. Analog Design Guidelines (page 249)
MGTAVTTRX
Analog supply receiver circuits Analog Design (Pad) termination Guidelines (page 249) GTX_DUAL tile. only: Analog supply (Pad) resistor calibration standby circuit entire device. only: Analog supply (Pad) resistor calibration standby circuits column. only: Analog supply (Pad) resistor calibration standby circuits column. Analog supply transmitter termination driver circuits (Pad) clock routing muxing network GTX_DUAL tile. Analog Design Guidelines (page 249) Analog Design Guidelines (page 250) Analog Design Guidelines (page 250)
MGTAVTTRXC
MGTAVTTRXC_
MGTAVTTRXC_L
MGTAVTTTX
Analog Design Guidelines (page 250)
MGTREFCLKP MGTREFCLKN MGTRREF
Differential clock input pair Analog Design (Pad) reference clock GTX_DUAL Guidelines (page 250) tile. (Pad) only: Reference resistor input Analog Design entire device. Guidelines (page 250)
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Table 1-2:
GTX_DUAL Analog Summary (Cont'd)
(Pad) (Pad) Description Section (Page)
MGTRREF_R MGTRREF_L MGTRXN0 MGTRXP0 MGTRXN1 MGTRXP1 MGTTXN0 MGTTXP0 MGTTXN1 MGTTXP1
only: Reference resistor input Analog Design column. Guidelines (page 250) only: Reference resistor input Analog Design column. Guidelines (page 250) Termination Equalization (page 158)
Differential complements forming (Pad) differential receiver input pair each transceiver.
(Pad)
Differential complements forming Termination differential transmitter output pair Equalization each transceiver. (page 158)
Table lists alphabetically signal names, clock domains, directions, descriptions GTX_DUAL ports, provides links their detailed descriptions. Table 1-3: GTX_DUAL Port Summary
Port CLKIN Domain Async Description Reference clock input shared PLL. address bus. interface clock. Enables read write operations. clock delay adjust control each transceiver. clock delay adjust monitor each transceiver. Section (Page) Shared (page 85), Clocking (page 95), Power Control (page 107) Dynamic Reconfiguration Port (page 113) Dynamic Reconfiguration Port (page 113) Dynamic Reconfiguration Port (page 113) Decision Feedback Equalization (page 163) Decision Feedback Equalization (page 163) Decision Feedback Equalization (page 163) Decision Feedback Equalization (page 163) Decision Feedback Equalization (page 163)
DADDR[6:0] DCLK DFECLKDLYADJ0[5:0] DFECLKDLYADJ1[5:0]
DFECLKDLYADJMONITOR0[5:0] DFECLKDLYADJMONITOR1[5:0]
DCLK DCLK RXUSRCLK2 RXUSRCLK2 RXUSRCLK2 RXUSRCLK2
DFEEYEDACMONITOR0[4:0] DFEEYEDACMONITOR1[4:0] DFESENSCAL0[2:0] DFESENSCAL1[2:0] DFETAP10[4:0] DFETAP11[4:0] DFETAP1MONITOR0[4:0] DFETAP1MONITOR1[4:0]
Vertical Scan each transceiver (voltage domain).
calibration status. weight value control each transceiver (5-bit resolution).
RXUSRCLK2
RXUSRCLK2
weight value monitor Decision Feedback each transceiver (5-bit Equalization (page 163) resolution).
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Ports Attributes
Table 1-3:
GTX_DUAL Port Summary (Cont'd)
Port Domain RXUSRCLK2 Description weight value control each transceiver (4-bit resolution plus 1-bit sign). Section (Page) Decision Feedback Equalization (page 163)
DFETAP20[4:0] DFETAP21[4:0] DFETAP2MONITOR0[4:0] DFETAP2MONITOR1[4:0] DFETAP30[3:0] DFETAP31[3:0] DFETAP3MONITOR0[3:0] DFETAP3MONITOR1[3:0] DFETAP40[3:0] DFETAP41[3:0] DFETAP4MONITOR0[3:0] DFETAP4MONITOR1[3:0]
RXUSRCLK2
weight value monitor Decision Feedback each transceiver (4-bit Equalization (page 163) resolution plus 1-bit sign). weight value control each transceiver (3-bit resolution plus 1-bit sign). Decision Feedback Equalization (page 163)
RXUSRCLK2
RXUSRCLK2
weight value monitor Decision Feedback each transceiver (3-bit Equalization (page 164) resolution plus 1-bit sign). weight value control each transceiver (3-bit resolution plus 1-bit sign). Decision Feedback Equalization (page 164)
RXUSRCLK2
RXUSRCLK2
weight value monitor Decision Feedback each transceiver (3-bit Equalization (page 164) resolution plus 1-bit sign). Data writing configuration data from FPGA logic GTX_DUAL tile. Data reading configuration data from GTX_DUAL tile FPGA logic. Dynamic Reconfiguration Port (page 113)
DI[15:0]
DCLK
DO[15:0]
DCLK
Dynamic Reconfiguration Port (page 113)
DRDY
DCLK
Indicates operation complete write operations data valid read operations.
Indicates whether operation read write. Starts full GTX_DUAL reset sequence. Factory test pins. change default value.
Dynamic Reconfiguration Port (page 113) Dynamic Reconfiguration Port (page 113) Reset (page
GTXRESET GTXTEST[13:0]
DCLK Async Async
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Table 1-3:
GTX_DUAL Port Summary (Cont'd)
Port Domain Description Section (Page)
INTDATAWIDTH
Async
Shared (page 85), FPGA Interface (page 116), Parallel Serial Sets internal datapath width (page 146), Serial Parallel (page 181), PRBS GTX_DUAL tile. Detection (page 188), 16-bit internal datapath Configurable Elastic width Buffer Phase Alignment 20-bit internal datapath (page 203), Configurable width Clock Correction (page 211), Configurable Channel Bonding (Lane Deskew) (page 217), FPGA Interface (page 231) Sets loopback mode. Loopback (page 244)
LOOPBACK0[2:0] LOOPBACK1[2:0] PHYSTATUS0 PHYSTATUS1
Async
Async
Indicates completion several Receive Detect Support functions, including power Express Operation management state transitions (page 151) receiver detection. Indicates that rate within acceptable tolerances desired rate. Enables lock detector. Powers down shared PLL. Resets PRBS error counter. Shared (page Shared (page Power Control (page 107) PRBS Detection (page 188) Shared (page 85), Clocking (page 95), FPGA Interface (page 116), Buffering, Phase Alignment, Skew Reduction (page 140), FPGA Interface (page 231)
PLLLKDET PLLLKDETEN PLLPOWERDOWN PRBSCNTRESET0 PRBSCNTRESET1
Async Async Async RXUSRCLK2
REFCLKOUT
Provides access reference clock provided shared (CLKIN).
REFCLKPWRDNB RESETDONE0 RESETDONE1
Async
Powers down reference Power Control (page 107) clock circuit (active Low). Indicates when transceiver finished reset ready use. Reset (page 99), Clock Data Recovery (page 177)
Async
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Table 1-3:
GTX_DUAL Port Summary (Cont'd)
Port Domain Description Section (Page)
RXBUFRESET0 RXBUFRESET1
Async
Reset (page 99), Configurable Elastic Buffer Phase Alignment Resets elastic buffer logic. (page 203), Configurable Clock Correction (page 211) Indicates overflow/underflow status elastic buffer. Indicates parallel data stream properly aligned byte boundaries according comma detection. Configurable Elastic Buffer Phase Alignment (page 203), Configurable Clock Correction (page 211)
RXBUFSTATUS0[2:0] RXBUFSTATUS1[2:0]
RXUSRCLK2
RXBYTEISALIGNED0 RXBYTEISALIGNED1
RXUSRCLK2
When PCOMMA_ALIGN TRUE, asserted alignment PCOMMA value. When MCOMMA_ALIGN TRUE, asserted alignment MCOMMA value.
Configurable Comma Alignment Detection (page 190)
RXBYTEREALIGN0 RXBYTEREALIGN1 RXCDRRESET0 RXCDRRESET1 RXCHANBONDSEQ0 RXCHANBONDSEQ1
RXUSRCLK2
Indicates byte alignment Configurable Comma within serial data stream Alignment Detection changed comma (page 190) detection. Reset CDR. Also resets rest PCS. Indicates when RXDATA contains start channel bonding sequence. Reset (page 99), Clock Data Recovery (page 177) Configurable Channel Bonding (Lane Deskew) (page 217)
RXUSRCLK2
RXUSRCLK2
RXCHANISALIGNED0 RXCHANISALIGNED1
RXUSRCLK2
Indicates channel properly aligned with master Configurable Channel transceiver according Bonding (Lane Deskew) observed channel bonding (page 217) sequences data stream. Held High least cycle when receiver changed. Configurable Channel Bonding (Lane Deskew) (page 217)
RXCHANREALIGN0 RXCHANREALIGN1
RXUSRCLK2
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Table 1-3:
GTX_DUAL Port Summary (Cont'd)
Port Domain Description Section (Page)
RXCHARISCOMMA0[3:0] RXCHARISCOMMA1[3:0]
RXUSRCLK2
Asserted when RXDATA 8B/10B comma. RXCHARISCOMMA influenced setting these Configurable 8B/10B attributes: Decoder (page 198) DEC_MCOMMA_DETECT_0 DEC_MCOMMA_DETECT_1 DEC_PCOMMA_DETECT_0 DEC_PCOMMA_DETECT_1 Asserted when RXDATA 8B/10B character. FPGA channel bonding control. Used only slaves. Configurable 8B/10B Decoder (page 198) Configurable Channel Bonding (Lane Deskew) (page 217) Configurable Channel Bonding (Lane Deskew) (page 217) Configurable Clock Correction (page 211) Configurable Comma Alignment Detection (page 190) Configurable Comma Alignment Detection (page 190) FPGA Interface (page 231) Gearbox (page 226)
RXCHARISK0[3:0] RXCHARISK1[3:0] RXCHBONDI0[3:0] RXCHBONDI1[3:0] RXCHBONDO0[3:0] RXCHBONDO1[3:0] RXCLKCORCNT0[2:0] RXCLKCORCNT1[2:0] RXCOMMADET0 RXCOMMADET1 RXCOMMADETUSE0 RXCOMMADETUSE1 RXDATA0[31:0] RXDATA1[31:0] RXDATAVALID0 RXDATAVALID1 RXDATAWIDTH0[1:0] RXDATAWIDTH1[1:0] RXDEC8B10BUSE0 RXDEC8B10BUSE1 RXDISPERR0[3:0] RXDISPERR1[3:0] RXELECIDLE0 RXELECIDLE1 RXENCHANSYNC0 RXENCHANSYNC1
RXUSRCLK2
RXUSRCLK
RXUSRCLK
FPGA channel bonding control. Reports status elastic buffer clock correction. Asserted when comma alignment block detects comma. Activates comma detection alignment circuit. Receive data receive interface FPGA. Data valid Gearbox.
RXUSRCLK2
RXUSRCLK2
RXUSRCLK2
RXUSRCLK2 RXUSRCLK2
RXUSRCLK2
Selects width RXDATA Configurable 8B/10B receive data connection Decoder (page 198), FPGA FPGA. Interface (page 231) Enables 8B/10B decoder. Indicates RXDATA received with disparity error. Configurable 8B/10B Decoder (page 198) Configurable 8B/10B Decoder (page 198)
RXUSRCLK2 RXUSRCLK2
Async
Indicates differential voltage OOB/Beacon Signaling between dropped (page 171) below minimum threshold. Enables channel bonding. Configurable Channel Bonding (Lane Deskew) (page 217)
RXUSRCLK2
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Table 1-3:
GTX_DUAL Port Summary (Cont'd)
Port Domain Async Description This port effect transceiver performance. Aligns byte boundary when comma minus detected. Aligns byte boundary when comma plus detected. Enables alignment XCLK with RXURSCLK (independently) each transceiver GTX_DUAL tile. High when bypassing elastic buffer. Receiver test pattern checker control. Configurable Comma Alignment Detection (page 190) Configurable Comma Alignment Detection (page 191) Section (Page)
RXENEQB0 RXENEQB1 RXENMCOMMAALIGN0 RXENMCOMMAALIGN1 RXENPCOMMAALIGN0 RXENPCOMMAALIGN1
RXUSRCLK2
RXUSRCLK2
RXENPMAPHASEALIGN0 RXENPMAPHASEALIGN1
RXUSRCLK2
Configurable Elastic Buffer Phase Alignment (page 204)
RXENPRBSTST0[1:0] RXENPRBSTST1[1:0]
RXUSRCLK2
PRBS Detection (page 188)
RXENSAMPLEALIGN0 RXENSAMPLEALIGN1
RXUSRCLK2
When High, oversampler continually adjusts sample point. When Low, Oversampling (page 184) samples only point that active before port went Low. Sets wideband/high-pass ratio equalizer. Termination Equalization (page 158)
RXEQMIX0[1:0] RXEQMIX1[1:0] RXGEARBOXSLIP0 RXGEARBOXSLIP1 RXHEADER0[2:0] RXHEADER1[2:0] RXHEADERVALID0 RXHEADERVALID1
Async RXUSRCLK2 RXUSRCLK2 RXUSRCLK2
Slips Gearbox position Gearbox (page 226) cycle. header bits from Gearbox. Gearbox (page 226) Indicates when header bits from Gearbox valid. FPGA status related byte stream synchronization, depending state RX_LOSS_OF_SYNC_FSM attribute. Gearbox (page 226)
RXLOSSOFSYNC0[1:0] RXLOSSOFSYNC1[1:0]
RXUSRCLK2
Configurable Loss-of-Sync State Machine (page 195)
RXNOTINTABLE0[3:0] RXNOTINTABLE1[3:0] RXOVERSAMPLEERR0 RXOVERSAMPLEERR1
RXUSRCLK2
Indicates RXDATA result Configurable 8B/10B 8B/10B code that error. Decoder (page 199) Indicates FIFO oversampling circuit either overflowed underflowed. Oversampling (page 184)
RXUSRCLK2
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Table 1-3:
GTX_DUAL Port Summary (Cont'd)
Port Domain Description Aligns receiver recovered clock with user clocks, allowing elastic buffer bypassed. Inverts polarity incoming data. Section (Page) Configurable Elastic Buffer Phase Alignment (page 204) Polarity Control (page 187) Power Control (page 107), Receive Detect Support Express Operation (page 152)
RXPMASETPHASE0 RXPMASETPHASE1 RXPOLARITY0 RXPOLARITY1 RXPOWERDOWN0[1:0] RXPOWERDOWN1[1:0]
RXUSRCLK2
RXUSRCLK2
Async
Powers down lanes.
RXPRBSERR0 RXPRBSERR1
RXUSRCLK2
Indicates number errors PRBS testing exceeds value PRBS Detection (page 188) PRBS_ERR_THRESHOLD attribute. Recovered clocks derived from Clock Data Recovery circuit. Clocks logic between elastic buffer.
RXRECCLK0 RXRECCLK1
FPGA Interface (page 231)
RXRESET0 RXRESET1 RXRUNDISP0[3:0] RXRUNDISP1[3:0]
Async
Active-High reset Reset (page 99), FPGA logic. Interface (page 231) Shows running disparity 8B/10B encoder when RXDATA received. Configurable 8B/10B Decoder (page 199)
RXUSRCLK2
RXSLIDE0 RXSLIDE1
RXUSRCLK2
Implements comma alignment bump control, allowing manual comma alignment. Both Configurable Comma provide RXSLIDE Alignment Detection functionality depending (page 191) value RX_SLIDE_MODE_0 RX_SLIDE_MODE_1 attribute. Indicates when internal sequence counter Gearbox Shows status Express SATA operations. decoding depends setting RX_STATUS_FMT. Gearbox (page 226) Out-of-Band/Beacon Signaling (page 154), OOB/Beacon Signaling (page 171), Receive Detect Support Express Operation (page 151)
RXSTARTOFSEQ0 RXSTARTOFSEQ1
RXUSRCLK2
RXSTATUS0[2:0] RXSTATUS1[2:0]
RXUSRCLK2
RXUSRCLK0 RXUSRCLK1
Input clock used internal FPGA Interface (page 232) logic after elastic buffer.
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Table 1-3:
GTX_DUAL Port Summary (Cont'd)
Port Domain Description Section (Page)
RXUSRCLK20 RXUSRCLK21 RXVALID0 RXVALID1 TXBUFDIFFCTRL0[2:0] TXBUFDIFFCTRL1[2:0] TXBUFSTATUS0[1:0] TXBUFSTATUS1[1:0] TXBYPASS8B10B0[3:0] TXBYPASS8B10B1[3:0]
Input clock used interface between FPGA FPGA Interface (page 232) transceiver. Indicates symbol lock valid data RXDATA RXCHARISK[3:0] Express operations. Controls strength pre-drivers. buffer status. Indicates buffer overflow underflow. OOB/Beacon Signaling (page 171) Configurable Driver (page 148) Buffering, Phase Alignment, Skew Reduction (page 140)
RXUSRCLK2
Async
TXUSRCLK2
TXUSRCLK2
Controls operation Configurable 8B/10B 8B/10B encoder per-byte Encoder (page 126) basis. TXCHARDISPMODE TXCHARDISPVAL allow 8B/10B disparity outgoing data controlled when FPGA Interface 8B/10B encoding enabled. (page 116), Configurable When 8B/10B encoding 8B/10B Encoder (page 126) disabled, TXCHARDISPMODE used extend data interfaces whose width multiple TXCHARDISPVAL TXCHARDISPMODE allow disparity outgoing data controlled when 8B/10B encoding enabled. When 8B/10B encoding disabled, TXCHARDISPVAL used extend data 10-bit, 20-bit, 40-bit interfaces.
TXCHARDISPMODE0[3:0] TXCHARDISPMODE1[3:0]
TXUSRCLK2
TXCHARDISPVAL0[3:0] TXCHARDISPVAL1[3:0]
TXUSRCLK2
FPGA Interface (page 117), Configurable 8B/10B Encoder (page 126)
TXCHARISK0[3:0] TXCHARISK1[3:0] TXCOMSTART0 TXCOMSTART1 TXCOMTYPE0 TXCOMTYPE1 TXDATA0[31:0] TXDATA1[31:0] TXDATAWIDTH0[1:0] TXDATAWIDTH1[1:0]
TXUSRCLK2
High send TXDATA Configurable 8B/10B 8B/10B character. Encoder (page 127) Initiates transmission sequence selected TXCOMTYPE (SATA only). Out-of-Band/Beacon Signaling (page 154)
TXUSRCLK2
TXUSRCLK2 TXUSRCLK2 TXUSRCLK2
Selects type signal Out-of-Band/Beacon send (SATA only). Signaling (page 154) Transmitting data bus. Selects width transmitting data port. FPGA Interface (page 117) FPGA Interface (page 117)
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Table 1-3:
GTX_DUAL Port Summary (Cont'd)
Port Domain Description Activates receiver detection feature Express operations also initiates loopback described PIPE specification. Controls transmitter differential output swing. Section (Page) Power Control (page 107), Receive Detect Support Express Operation (page 151) Configurable Driver (page 148)
TXDETECTRX0 TXDETECTRX1
TXUSRCLK2
TXDIFFCTRL0[2:0] TXDIFFCTRL1[2:0] TXELECIDLE0 TXELECIDLE1 TXENC8B10BUSE0 TXENC8B10BUSE1
Async
TXUSRCLK2
Drives same Power Control (page 107), voltage perform electrical Out-of-Band/Beacon idle/beaconing Express Signaling (page 154) operations. Enables 8B/10B encoder. Configurable 8B/10B Encoder (page 127), FPGA Interface (page 117)
TXUSRCLK2
TXENPMAPHASEALIGN0 TXENPMAPHASEALIGN1
Async
Allows both transceivers GTX_DUAL tile align their Buffering, Phase XCLKs with their TXUSRCLKs Alignment, Skew allows XCLKs Reduction (page 140) multiple transceivers synchronized. Transmitter test pattern generation control. Indicates when data must applied Gearbox. header input data Gearbox. Inhibits data transmission. PRBS Generator (page 145) Gearbox (page 131) Gearbox (page 131) Configurable Driver (page 148)
TXENPRBSTST0[1:0] TXENPRBSTST1[1:0] TXGEARBOXREADY0 TXGEARBOXREADY1 TXHEADER0[2:0] TXHEADER1[2:0] TXINHIBIT0 TXINHIBIT1 TXKERR0[3:0] TXKERR1[3:0]
TXUSRCLK2 TXUSRCLK2 TXUSRCLK2 TXUSRCLK2 TXUSRCLK2
Indicates invalid code Configurable 8B/10B character specified. Encoder (page 127) Provides parallel clock generated internal dividers transceiver.
TXOUTCLK0 TXOUTCLK1
Note: When INTDATAWIDTH High, duty cycle 60/40 instead 50/50. TXOUTCLK cannot drive TXUSRCLK when phase-alignment circuit used.
FPGA Interface (page 117), Buffering, Phase Alignment, Skew Reduction (page 140)
TXPMASETPHASE0 TXPMASETPHASE1 TXPOLARITY0 TXPOLARITY1
Async
Aligns XCLK with TXUSRCLK Buffering, Phase both transceivers Alignment, Skew GTX_DUAL tile. Reduction (page 140) Specifies final transmitter output inverted. Polarity Control (page 144)
TXUSRCLK2
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Ports Attributes
Table 1-3:
GTX_DUAL Port Summary (Cont'd)
Port Domain Description Section (Page) Power Control (page 108), Receive Detect Support Express Operation (page 152), Out-ofBand/Beacon Signaling (page 154) Configurable Driver (page 148)
TXPOWERDOWN0[1:0] TXPOWERDOWN1[1:0]
TXUSRCLK2(1) Powers down lanes.
TXPREEMPHASIS0[3:0] TXPREEMPHASIS1[3:0] TXRESET0 TXRESET1 TXRUNDISP0[3:0] TXRUNDISP1[3:0] TXSEQUENCE0[6:0] TXSEQUENCE1[6:0] TXSTARTSEQ0 TXSTARTSEQ1 TXUSRCLK0 TXUSRCLK1 TXUSRCLK20 TXUSRCLK21
Notes:
Async
Controls pre-emphasis.
Async
Resets transmitter, including phase Reset (page 99), FPGA adjust FIFO, 8B/10B encoder, Interface (page 118) FPGA interface. Indicates current running Configurable 8B/10B disparity 8B/10B encoder. Encoder (page 127) Input Gearbox from sequence counter implemented FPGA logic. Gearbox (page 131)
TXUSRCLK2
TXUSRCLK2
TXUSRCLK2
Input Gearbox from FPGA logic indicating start Gearbox (page 131) sequence. Provides clock internal datapath. Synchronizes FPGA logic with interface. FPGA Interface (page 118), Buffering, Phase Alignment, Skew Reduction (page 140) FPGA Interface (page 118)
TXPOWERDOWN0[1:0] TXPOWERDOWN1[1:0] GTX_DUAL tile belong TXUSRCLK2 clock domain. This different from GTP_DUAL tile implementation where TXPOWERDOWN0[1:0] TXPOWERDOWN1[1:0] asynchronous.
Table lists alphabetically signal names, clock domains, directions, descriptions ports, provides links their detailed descriptions. Table 1-4: Port Summary
Port CRCCLK CRCDATAVALID CRCDATAVALIDA CRCDATAWIDTH[2:0] Domain CRCCLK CRCCLK CRCCLK Description clock. Indicates valid data 32-bit CRCIN inputs. Indicates valid data 64-bit CRCIN inputs. Indicates many input data bytes valid. Section (Page) Cyclic Redundancy Check (page 236) Cyclic Redundancy Check (page 237) Cyclic Redundancy Check (page 236) Cyclic Redundancy Check (page 236)
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Table 1-4:
Port Summary (Cont'd)
Port Domain CRCCLK Description input data. maximum datapath width eight bytes. Section (Page) Cyclic Redundancy Check (page 236)
CRCIN[63:0]
CRCOUT[31:0]
CRCCLK
32-bit output. CRCOUT byte-reversed, bit-inverted value corresponding calculation valid bytes Cyclic Redundancy Check from previous clock cycle (page 236) previous value. CRCDATAVALIDA must driven High.
CRCRESET
CRCCLK
Synchronous reset registers.
Cyclic Redundancy Check (page 236)
Table lists alphabetically attribute names, default values, directions GTX_DUAL attributes, provides links their detailed descriptions. Table 1-5: GTX_DUAL Attribute Summary
Attribute AC_CAP_DIS_0 AC_CAP_DIS_1 ALIGN_COMMA_WORD_0 ALIGN_COMMA_WORD_1 CB2_INH_CC_PERIOD_0 CB2_INH_CC_PERIOD_1 Type Boolean Description Disables built-in coupling capacitors receiver inputs when TRUE. Controls alignment detected commas within multi-byte datapath. Specific Express designs, allows removal retaining control characters during channel bonding clock correction. Defines waiting time after deassertion phase reset before optional reset sequence Express designs complete during electrical idle. Sets maximum amount lane skew allowed when using channel bonding. Must less than one-half minimum distance between channel bonding sequences. Specific Express designs, allows lanes remember previous skew during periods electrical idle. Indicates amount internal pipelining used elastic buffer control signals. Section (Page) Termination Equalization (page 159) Configurable Comma Alignment Detection (page 191) Configurable Channel Bonding (Lane Deskew) (page 217)
Integer
Integer
CDR_PH_ADJ_TIME
5-bit Binary
Reset (page 100), Clock Data Recovery (page 177)
CHAN_BOND_1_MAX_SKEW_0 CHAN_BOND_1_MAX_SKEW_1 CHAN_BOND_2_MAX_SKEW_0 CHAN_BOND_2_MAX_SKEW_1 CHAN_BOND_KEEP_ALIGN_0 CHAN_BOND_KEEP_ALIGN_1 CHAN_BOND_LEVEL_0 CHAN_BOND_LEVEL_1 Boolean Integer
Configurable Channel Bonding (Lane Deskew) (page 217) Configurable Channel Bonding (Lane Deskew) (page 217) Configurable Channel Bonding (Lane Deskew) (page 218)
Integer
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Table 1-5:
GTX_DUAL Attribute Summary (Cont'd)
Attribute Type String Description Defines channel bonding mode operation transceiver. Section (Page) Configurable Channel Bonding (Lane Deskew) (page 218)
CHAN_BOND_MODE_0 CHAN_BOND_MODE_1 CHAN_BOND_SEQ_1_1_0 CHAN_BOND_SEQ_1_1_1 CHAN_BOND_SEQ_1_2_0 CHAN_BOND_SEQ_1_2_1 CHAN_BOND_SEQ_1_3_0 CHAN_BOND_SEQ_1_3_1 CHAN_BOND_SEQ_1_4_0 CHAN_BOND_SEQ_1_4_1 CHAN_BOND_SEQ_1_ENABLE_0 CHAN_BOND_SEQ_1_ENABLE_1 CHAN_BOND_SEQ_2_1_0 CHAN_BOND_SEQ_2_1_1 CHAN_BOND_SEQ_2_2_0 CHAN_BOND_SEQ_2_2_1 CHAN_BOND_SEQ_2_3_0 CHAN_BOND_SEQ_2_3_1 CHAN_BOND_SEQ_2_4_0 CHAN_BOND_SEQ_2_4_1 CHAN_BOND_SEQ_2_ENABLE_0 CHAN_BOND_SEQ_2_ENABLE_1 CHAN_BOND_SEQ_2_USE_0 CHAN_BOND_SEQ_2_USE_1 CHAN_BOND_SEQ_LEN_0 CHAN_BOND_SEQ_LEN_1 CLK_COR_ADJ_LEN_0 CLK_COR_ADJ_LEN_1 CLK_COR_DET_LEN_0 CLK_COR_DET_LEN_1 CLK_COR_INSERT_IDLE_FLAG_0 CLK_COR_INSERT_IDLE_FLAG_1
10-bit Binary
Used conjunction with CHAN_BOND_SEQ_1_ENABLE define channel bonding sequence
Configurable Channel Bonding (Lane Deskew) (page 218)
4-bit Binary
Sets which parts channel bonding sequence don't cares.
Configurable Channel Bonding (Lane Deskew) (page 218)
10-bit Binary
Used conjunction with CHAN_BOND_SEQ_2_ENABLE define second channel bonding sequence.
Configurable Channel Bonding (Lane Deskew) (page 219)
4-bit Binary
Sets which parts channel bonding sequence don't cares. Determines second channel bonding sequence used. Defines length bytes channel bonding sequence that transceiver matches detect opportunities channel bonding. Defines size adjustment (number bytes repeated skipped) clock correction. Defines length sequence that transceiver matches detect opportunities clock correction. Controls whether RXRUNDISP input status indicates running disparity inserted-idle (clock correction sequence) flag.
Configurable Channel Bonding (Lane Deskew) (page 219) Configurable Channel Bonding (Lane Deskew) (page 219) Configurable Channel Bonding (Lane Deskew) (page 219) Configurable Clock Correction (page 211) Configurable Clock Correction (page 212)
Boolean
Integer
Integer
Integer
Boolean
Configurable Clock Correction (page 212)
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Table 1-5:
GTX_DUAL Attribute Summary (Cont'd)
Attribute Type Boolean Description Controls whether elastic buffer must retain least clock correction sequence byte stream. Specifies maximum elastic buffer latency.
Specifies minimum elastic buffer latency.
Section (Page) Configurable Clock Correction (page 212) Configurable Clock Correction (page 212) Configurable Clock Correction (page 212)
CLK_COR_KEEP_IDLE_0 CLK_COR_KEEP_IDLE_1 CLK_COR_MAX_LAT_0 CLK_COR_MAX_LAT_1 CLK_COR_MIN_LAT_0 CLK_COR_MIN_LAT_1
Integer Integer
CLK_COR_PRECEDENCE_0 CLK_COR_PRECEDENCE_1
Boolean
Determines whether clock correction channel bonding takes precedence when both operations triggered same time. TRUE give clock correction precedence. Specifies minimum number RXUSRCLK cycles without clock correction that must occur between successive clock corrections.
Configurable Clock Correction (page 212)
CLK_COR_REPEAT_WAIT_0 CLK_COR_REPEAT_WAIT_1 CLK_COR_SEQ_1_1_0 CLK_COR_SEQ_1_1_1 CLK_COR_SEQ_1_2_0 CLK_COR_SEQ_1_2_1 CLK_COR_SEQ_1_3_0 CLK_COR_SEQ_1_3_1 CLK_COR_SEQ_1_4_1 CLK_COR_SEQ_1_ENABLE_0 CLK_COR_SEQ_1_ENABLE_1 CLK_COR_SEQ_2_1_0 CLK_COR_SEQ_2_1_1 CLK_COR_SEQ_2_2_0 CLK_COR_SEQ_2_2_1 CLK_COR_SEQ_2_3_0 CLK_COR_SEQ_2_3_1 CLK_COR_SEQ_2_4_0 CLK_COR_SEQ_2_4_1 CLK_COR_SEQ_2_ENABLE_0 CLK_COR_SEQ_2_ENABLE_1 CLK_COR_SEQ_2_USE_0 CLK_COR_SEQ_2_USE_1 CLK_CORRECT_USE_0 CLK_CORRECT_USE_1
Integer
Configurable Clock Correction (page 212)
10-bit Binary
CLK_COR_SEQ_1 attributes used conjunction with CLK_COR_SEQ_1_ENABLE define clock correction sequence
Configurable Clock Correction (page 213)
4-bit Binary
Sets which parts clock correction sequence don't cares.
Configurable Clock Correction (page 213)
10-bit Binary
Used conjunction with CLK_COR_SEQ_2_ENABLE define second clock correction sequence.
Configurable Clock Correction (page 213)
4-bit Binary Boolean Boolean
Sets which parts clock correction sequence don't cares. Determines second clock correction sequence used. TRUE enable clock correction.
Configurable Clock Correction (page 213) Configurable Clock Correction (page 213) Configurable Clock Correction (page 211)
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Ports Attributes
Table 1-5:
GTX_DUAL Attribute Summary (Cont'd)
Attribute Type Integer Description Sets divider used divide CLKIN down internal rate close MHz. Must TRUE. Oscillators driving dedicated reference clock inputs must coupled. When TRUE, switches differential clock input pair's internal termination resistors. Adjusts input common mode values. Number bursts transmitted SATA sequence. Sets which bits MCOMMA/PCOMMA must matched incoming data which bits don't cares. When TRUE, PCOMMA match followed immediately MCOMMA match required comma detection. Used detect A1/A2 framing characters SONET. Enables detection negative 8B/10B commas. Enables detection positive 8B/10B commas. Limits commas which RXCHARISCOMMA responds. calibration time. configuration settings. Selects Gearbox mode. Defines comma minus raise RXCOMMADET align parallel data. TRUE allow minus comma detection alignment. Sets squelch clock rate based CLKIN. Section (Page) Clocking (page 95), Power Control (page 108) Clocking (page 95), Analog Design Guidelines (page 250) Clocking (page 95), Analog Design Guidelines (page 250) Termination Equalization (page 159) Out-of-Band/Beacon Signaling (page 155) Configurable Comma Alignment Detection (page 191)
CLK25_DIVIDE
CLKINDC_B
Boolean
CLKRCV_TRST CM_TRIM_0 CM_TRIM_1 COM_BURST_VAL_0[3:0] COM_BURST_VAL_1[3:0] COMMA_10B_ENABLE_0 COMMA_10B_ENABLE_1
Boolean 2-bit Binary 4-bit Binary 10-bit Binary
COMMA_DOUBLE_0 COMMA_DOUBLE_1
Boolean
Configurable Comma Alignment Detection (page 191) Configurable 8B/10B Decoder (page 199) Configurable 8B/10B Decoder (page 199) Configurable 8B/10B Decoder (page 199) Decision Feedback Equalization (page 164) Decision Feedback Equalization (page 164) Gearbox (page 132), Gearbox (page 227) Configurable Comma Alignment Detection (page 192) Configurable Comma Alignment Detection (page 192) OOB/Beacon Signaling (page 172)
DEC_MCOMMA_DETECT_0 DEC_MCOMMA_DETECT_1 DEC_PCOMMA_DETECT_0 DEC_PCOMMA_DETECT_1 DEC_VALID_COMMA_ONLY_0 DEC_VALID_COMMA_ONLY_1 DFE_CAL_TIME DFE_CFG_0[9:0] DFE_CFG_1[9:0] GEARBOX_ENDEC_0 GEARBOX_ENDEC_1 MCOMMA_10B_VALUE_0 MCOMMA_10B_VALUE_1 MCOMMA_DETECT_0 MCOMMA_DETECT_1 OOB_CLK_DIVIDE
Boolean Boolean Boolean 5-bit Binary 10-bit Binary 3-bit Binary 10-bit Binary
Boolean
Integer
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Table 1-5:
GTX_DUAL Attribute Summary (Cont'd)
Attribute Type Description Sets minimum differential voltage between before signal recognized valid electrical idle Express operation SATA signal. Section (Page)
OOBDETECT_THRESHOLD_0 OOBDETECT_THRESHOLD_1
3-bit Binary
OOB/Beacon Signaling (page 172)
OVERSAMPLE_MODE
Boolean
Enables oversampling.
Shared (page 85), Buffering, Phase Alignment, Skew Reduction (page 141), Parallel Serial (page 146), Serial Parallel (page 181), Oversampling (page 184), Configurable Elastic Buffer Phase Alignment (page 204) Power Control (page 108), Configurable Channel Bonding (Lane Deskew) (page 219) Configurable Comma Alignment Detection (page 192) Configurable Comma Alignment Detection (page 192)
PCI_EXPRESS_MODE_0 PCI_EXPRESS_MODE_1 PCOMMA_10B_VALUE_0 PCOMMA_10B_VALUE_1 PCOMMA_DETECT_0 PCOMMA_DETECT_1 PLL_COM_CFG PLL_CP_CFG PLL_DIVSEL_FB PLL_DIVSEL_REF
Boolean
Enables specific Express operations. Defines comma plus raise RXCOMMADET align parallel data. TRUE allow plus comma detection alignment. Controls configuration.
10-bit Binary
Boolean 24-bit
8-bit Controls feedback loop. Integer Integer Controls feedback divider shared PLL. Controls reference clock divider shared PLL. enable. FALSE (default) disable. TRUE enable. Configuration shared lock detect circuit. Sets divider line rate each transceiver. FALSE. When FALSE, allows SATA operations work SATA Generation (1.5 Gb/s) SATA Generation Gb/s) rate. Shared (page 85), Serial Parallel (page 181) Out-of-Band/Beacon Signaling (page 155) Shared (page Shared (page
PLL_FB_DCCEN
Boolean 3-bit Binary Integer
PLL_LKDET_CFG PLL_RXDIVSEL_OUT_0 PLL_RXDIVSEL_OUT_1 PLL_SATA_0 PLL_SATA_1
Boolean
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Ports Attributes
Table 1-5:
GTX_DUAL Attribute Summary (Cont'd)
Attribute Type 3-bit Binary Description Configuration shared duty-cycle correction circuit. Shared (page 85), Buffering, Phase Alignment, Skew Reduction (page 141), Parallel Serial (page 146), Out-ofBand/Beacon Signaling (page 155) Clock Data Recovery (page 177) Section (Page)
PLL_TDCC_CFG
PLL_TXDIVSEL_OUT_0 PLL_TXDIVSEL_OUT_1
Integer
Sets divider line rate each transceiver.
PMA_CDR_SCAN_0 PMA_CDR_SCAN_1 PMA_COM_CFG PMA_RX_CFG_0 PMA_RX_CFG_1 PMA_RXSYNC_CFG_0 PMA_RXSYNC_CFG_1 PMA_TX_CFG_0 PMA_TX_CFG_1 PRBS_ERR_THRESHOLD_0 PRBS_ERR_THRESHOLD_1
27-bit 69-bit 25-bit 7-bit 20-bit 32-bit
Allows direct control sampling point. Common configuration attribute PMA. Adjusts operation oversampling PLL_RXDIVSEL_OUT settings. Configuration latency mode. channel specific settings. Sets error threshold PRBS checker. Sets termination voltage GND. Used with internal external coupling support TXDETECTRX functionality Express operation. Sets termination voltage MGTAVTTRX.
Clock Data Recovery (page 177) Oversampling (page 184) Buffering, Phase Alignment, Skew Reduction (page 141) PRBS Detection (page 188)
RCV_TERM_GND_0 RCV_TERM_GND_1
Boolean
Termination Equalization (page 159)
RCV_TERM_VTTRX_0 RCV_TERM_VTTRX_1 RX_BUFFER_USE_0 RX_BUFFER_USE_1 RX_DECODE_SEQ_MATCH_0 RX_DECODE_SEQ_MATCH_1
Boolean
Termination Equalization (page 159)
Boolean
Configurable Elastic TRUE elastic buffer. Buffer Phase Alignment (page 204) Determines whether sequences matched against 8B/10B decoded data undecoded data. Enables hold data during optional reset sequence electrical idle state Express designs. Configurable Clock Correction (page 213)
Boolean
RX_EN_IDLE_HOLD_CD
Boolean
Reset (page 100), Clock Data Recovery (page 177)
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Table 1-5:
GTX_DUAL Attribute Summary (Cont'd)
Attribute Type Description When TRUE, restores contents from internal registers after termination electrical idle state Express designs. When TRUE, valid signal present inputs, resets elastic buffer. When TRUE, enables reset frequency circuits using optional reset sequence while electrical idle state Express designs. When TRUE, enables reset phase circuits using optional reset sequence while electrical idle state Express designs. Determines long valid data inputs must absent before asserting reset signal elastic buffer. Determines long valid data inputs must present before deasserting reset signal elastic buffer. Defines number valid characters required decrement error count purpose loss-of-sync determination. Defines error count required move Loss Sync state machine from SYNC_ACQUIRED SYNC_LOST state. Defines behavior RXLOSSOFSYNC outputs.
Selects between sliding PCS.
Section (Page) Reset (page 100), Decision Feedback Equalization (page 164) Reset (page 100), Configurable Elastic Buffer Phase Alignment (page 204)
RX_EN_IDLE_HOLD_DFE_0 RX_EN_IDLE_HOLD_DFE_1
Boolean
RX_EN_IDLE_RESET_BUF_0 RX_EN_IDLE_RESET_BUF_1
Boolean
RX_EN_IDLE_RESET_F
Boolean
Reset (page 100), Clock Data Recovery (page 178)
RX_EN_IDLE_RESET_PH
Boolean
Reset (page 100), Clock Data Recovery (page 178)
RX_IDLE_HI_CNT_0 RX_IDLE_HI_CNT_1
4-bit Binary
Reset (page 100), Configurable Elastic Buffer Phase Alignment (page 204) Reset (page 100), Configurable Elastic Buffer Phase Alignment (page 204) Configurable Loss-of-Sync State Machine (page 196)
RX_IDLE_LO_CNT_0 RX_IDLE_LO_CNT_1
4-bit Binary
RX_LOS_INVALID_INCR_0 RX_LOS_INVALID_INCR_1
Integer
RX_LOS_THRESHOLD_0 RX_LOS_THRESHOLD_1 RX_LOSS_OF_SYNC_FSM_0 RX_LOSS_OF_SYNC_FSM_1 RX_SLIDE_MODE_0 RX_SLIDE_MODE_1 RX_STATUS_FMT_0 RX_STATUS_FMT_1
Integer
Configurable Loss-of-Sync State Machine (page 196) Configurable Loss-of-Sync State Machine (page 196) Configurable Comma Alignment Detection (page 192) OOB/Beacon Signaling (page 172)
Boolean
String
String
Sets whether RX_STATUS port used report status Express SATA features.
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Ports Attributes
Table 1-5:
GTX_DUAL Attribute Summary (Cont'd)
Attribute Type Description Selects which clock used side elastic buffer. default setting RXREC recovered clock). RXUSR (RXUSRCLK) when bypassing elastic buffer. Enables Gearbox. Number bursts required SATA detector declare match. Section (Page)
RX_XCLK_SEL_0 RX_XCLK_SEL_1
String
Configurable Elastic Buffer Phase Alignment (page 204)
RXGEARBOX_USE_0 RXGEARBOX_USE_1 SATA_BURST_VAL_0 SATA_BURST_VAL_1 SATA_IDLE_VAL_0 SATA_IDLE_VAL_1 SATA_MAX_BURST_0 SATA_MAX_BURST_1 SATA_MAX_INIT_0 SATA_MAX_INIT_1 SATA_MAX_WAKE_0 SATA_MAX_WAKE_1 SATA_MIN_BURST_0 SATA_MIN_BURST_1 SATA_MIN_INIT_0 SATA_MIN_INIT_1 SATA_MIN_WAKE_0 SATA_MIN_WAKE_1
Boolean 3-bit Binary 3-bit Binary Integer
Gearbox (page 227) OOB/Beacon Signaling (page 172)
Number idles required SATA OOB/Beacon Signaling detector declare match. (page 172) Sets threshold SATA detector reject burst terms squelch clock cycles. Sets maximum time allowed COMINIT/COMRESET idle SATA detector terms squelch clock cycles. Sets maximum time allowed COMWAKE idle SATA detector terms squelch clock cycles. Sets threshold SATA detector reject burst terms squelch clock cycles. Sets minimum time allowed COMINIT/COMRESET idle SATA detector terms squelch clock cycles. Sets minimum time allowed COMWAKE idle SATA detector terms squelch clock cycles. Shortens time takes finish GTXRESET sequence lock during simulation. This simulation-only attribute chooses between FAST LEGACY simulation models. Specifies length symbol picoseconds simulation. Controls receiver detect modeling simulation intended Express designs only. OOB/Beacon Signaling (page 172)
Integer
OOB/Beacon Signaling (page 172)
Integer
OOB/Beacon Signaling (page 172) OOB/Beacon Signaling (page 173)
Integer
Integer
OOB/Beacon Signaling (page 173)
Integer
OOB/Beacon Signaling (page 173)
SIM_GTXRESET_SPEEDUP
Integer
Simulation (page
SIM_MODE
String
Simulation (page
SIM_PLL_PERDIV2 SIM_RECEIVER_DETECT_PASS0 SIM_RECEIVER_DETECT_PASS1
9-bit
Simulation (page
Boolean
Simulation (page
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Table 1-5:
GTX_DUAL Attribute Summary (Cont'd)
Attribute Type 5-bit Binary Description Controls internal termination calibration circuit. Implies terminated inputs outputs with differential impedance 100. Selects whether external 59(2) precision resistor connected MGTRREF override value used, defined TERMINATION_CTRL. Transition time from powerdown state internal clock cycles. exact time depends CLKIN rate setting CLK25_DIVIDER. Section (Page) Analog Design Guidelines (page 250) Termination Equalization (page 159), Analog Design Guidelines (page 251)
TERMINATION_CTRL[4:0]
TERMINATION_IMP_0 TERMINATION_IMP_1
Integer
TERMINATION_OVRD
Boolean
Analog Design Guidelines (page 251)
TRANS_TIME_FROM_P2_0 TRANS_TIME_FROM_P2_1
12-bit
Power Control (page 108)
TRANS_TIME_NON_P2_0 TRANS_TIME_NON_P2_1
Transition time from powerdown state except internal 8-bit clock cycles. exact time depends CLKIN rate setting CLK25_DIVIDER. Transition time power-down state internal clock cycles. exact time depends CLKIN rate setting CLK25_DIVIDER. Indicates whether buffer used. Configuration transmitter detect remote receiver circuit. Enables Gearbox. Sets idle delay. Controls inverters that optimize clock paths within transceiver. When bypassing buffer, 111. Otherwise, 011.
Power Control (page 108)
TRANS_TIME_TO_P2_0 TRANS_TIME_TO_P2_1
10-bit
Power Control (page 108)
TX_BUFFER_USE_0 TX_BUFFER_USE_1 TX_DETECT_RX_CFG_0 TX_DETECT_RX_CFG_1 TXGEARBOX_USE_0 TXGEARBOX_USE_1 TX_IDLE_DELAY_0 TX_IDLE_DELAY_1 TXRX_INVERT0 TXRX_INVERT1
Boolean 14-bit Boolean 3-bit Binary 3-bit Binary
Buffering, Phase Alignment, Skew Reduction (page 141)
Gearbox (page 132)
Buffering, Phase Alignment, Skew Reduction (page 141)
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Ports Attributes
Table 1-5:
GTX_DUAL Attribute Summary (Cont'd)
Attribute Type Description Selects clock used drive clock domain following buffer. TXOUT (TXOUTCLK) when using buffer. TXUSR (TXUSRCLK) when bypassing buffer. Section (Page)
TX_XCLK_SEL_0 TX_XCLK_SEL_1
String
Buffering, Phase Alignment, Skew Reduction (page 141)
Notes:
Refer Appendix information about mapping these attributes binary values. nominal value external precision resistor RREF connected MGTRREF different LXT/SXT devices FXT/TXT devices. LXT/SXT devices with GTP_DUAL tiles, RREF FXT/TXT devices with GTX_DUAL tiles, RREF devices need RREF resistor each column GTX_DUAL tiles.
Table lists attribute name, default value, direction attribute, provides link detailed description. Table 1-6: Attribute Summary
Attribute CRC_INIT[31:0] Type 32-bit Description 32-bit value initial state internal registers CRC32/CRC64 block. Section (Page) Cyclic Redundancy Check (page 237)
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Chapter
RocketIO Transceiver Wizard
RocketIO Transceiver Wizard preferred tool generate wrapper instantiate GTX_DUAL primitive. Wizard found Xilinx CORE Generatortool. sure download most up-to-date Update before using Wizard. Details this wizard found UG204, RocketIO Transceiver Getting Started Guide. Start Xilinx CORE Generator tool. Locate RocketIO Wizard taxonomy tree under:
/FPGA Features Design/IO Interfaces
Figure 2-1.
UG198_c2_01_070507
Figure 2-1:
Locating RocketIO Wizard
Double click RocketIO Wizard launch Wizard.
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Chapter
Simulation
Overview
Simulations using GTX_DUAL tiles have specific prerequisites that simulation environment test bench must fulfill. Synthesis Simulation Design Guide [Ref explains simulation environment supported simulators depending used Hardware Description Language (HDL). This design guide downloaded from Xilinx website prerequisites simulating design with transceivers are: Simulator with SWIFT interface support SmartModels, which encrypted versions used implementation modeled block Installed GTX_DUAL SmartModel Correct setting environment variable that points SmartModel installation directory Correct setup simulator SmartModel (initialization file, environment variable(s)) Compilation SmartModel wrapper files into UNISIM SIMPRIM libraries Compilation GTX_DUAL SmartModel into simulation library Correct simulator resolution (Verilog) Correct compilation order simulation libraries
user guide simulator Synthesis Simulation Design Guide provide detailed list settings SmartModel support. COMPXLIB tool with sl_admin facilitates setup supported simulator.
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Chapter Simulation
Ports Attributes
GTX_DUAL primitive attributes intended only simulation. Table lists simulation-only attributes GTX_DUAL tile. names these attributes start with SIM_. Table 3-1: GTX_DUAL Simulation-Only Attributes
Attribute Type Description This attribute shortens time takes finish GTXRESET sequence lock shared during simulation. Must used together with correct setting SIM_PLL_PERDIV2. Shorten GTXRESET cycle time (fast initialization approximately ns). value SIM_PLL_PERDIV2 defines frequency this mode. Because SIM_PLL_PERDIV2 cannot changed during simulation, this mode cannot used multirate designs. GTXRESET sequence simulated with original duration (standard initialization approximately µs). This mode must used multirate designs. This simulation-only attribute chooses between available UNISIM/SIMPRIM simulation models. SIM_MODE String FAST: When this attribute FAST, faster simulation model used simulation time. LEGACY: When this attribute LEGACY, legacy simulation model used, which results longer simulation time. This attribute specifies 9-bit value equal half period clock frequency picoseconds. example, (decimal) equal 0x190 (hexadecimal), which default value. SIM_PLL_PERDIV2 correctly, poor locking behavior incorrect clock frequencies occur simulation. This attribute used simulate TXDETECTRX feature each transceiver. SIM_RECEIVER_DETECT_PASS0 SIM_RECEIVER_DETECT_PASS1 Boolean TRUE (default): Simulates connection serial ports. TXDETECTRX reports that port connected. FALSE: Simulates disconnected port. TXDETECTRX reports that port detected.
SIM_GTXRESET_SPEEDUP
Integer
SIM_PLL_PERDIV2
9-bit
There simulation-only ports.
Description
behavior GTX_DUAL tile modeled using SmartModel. SmartModel allows design containing GTX_DUAL tiles simulated following design phases: Register Transfer Level (RTL)/Pre-Synthesis Simulation Post-Synthesis Simulation/Pre-NGDBuild Simulation
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Description
Post-NGDBuild/Pre-Map Simulation Post-Map/Partial Timing Simulation Post-Place Route/Timing Simulation
Limitations
analog nature some blocks inside GTX_DUAL tile generates some restrictions when simulated using simulator. Receiver detection OOB/beacon signaling analog features GTX_DUAL tile that only modeled limited with simulator. shared another analog block GTX_DUAL tile that difficult model precisely. simulation-only attributes SIM_GTXRESET_SPEEDUP SIM_PLL_PERDIV2 speed simulation shortening locking time shared PLL.
SmartModel Attributes
SIM_GTXRESET_SPEEDUP
SIM_GTXRESET_SPEEDUP attribute used shorten simulated lock time shared PLL. TXOUTCLK RXRECCLK used generate clocks design, these clocks occasionally flatline while GTX_DUAL tile locking. digital clock manager (DCM) used divide TXOUTCLK RXRECCLK, final output clock ready until both GTX_DUAL tile have locked. Equation provides estimate time required before stable source from TXOUTCLK RXRECCLK available simulation, including time required PLLs DCMs used. Equation USRCLKstable GTXRESETsequence locktimePLL locktimeDCM either used, respective term removed from lock time equation. When simulating multirate designs where shared frequency REFCLK frequency changes, SIM_GTXRESET_SPEEDUP must FALSE. Appendix "Advanced Clocking" illustrates multirate design examples.
SIM_MODE
This simulation-only attribute chooses between available UNISIM/SIMPRIM simulation models. LEGACY setting selects legacy simulation model transceiver. FAST setting selects faster simulation model transceiver simulation time. Legacy model available existing users have been using simulation models with 11.1 older software their designs; however, this legacy model will phased after ISE® 11.1 software. FAST setting highly recommended customer designs. This attribute used independently SIM_GTXRESET_SPEEDUP attribute.
SIM_PLL_PERDIV2
GTX_DUAL tile contains analog generate transmit receive clocks reference clock. Because simulators fully model analog PLL, GTX_DUAL Smartmodel includes equivalent behavioral model simulate
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Chapter Simulation
output. SIM_PLL_PERDIV2 attribute used behavioral model generate output accurately possible. must one-half period shared PLL. "Examples," page calculate SIM_PLL_PERDIV2 given rate.
SIM_RECEIVER_DETECT_PASS
GTX_DUAL includes TXDETECTRX feature that allows transmitter detect whether serial ports currently connected receiver measuring rise time TXP/TXN differential pair (see "Receive Detect Support Express Operation," page 151). GTX_DUAL SmartModel includes attribute simulating TXDETECTRX called SIM_RECEIVER_DETECT_PASS. This attribute allows TXDETECTRX simulated each transceiver without modelling measurement rise time TXP/TXN differential pair. default, SIM_RECEIVER_DETECT_PASS TRUE. When TRUE, attribute models connected receiver, TXDETECTRX operations indicate receiver connected. model disconnected receiver, SIM_RECEIVER_DETECT_PASS transceiver FALSE.
Power-Up Reset
Link Idle Reset
simulate correctly, Link Idle Reset circuit, described in"Link Idle Reset Support," page 102, must implemented connected each GTX_DUAL instance. This circuit included automatically when Wizard used configure GTX_DUAL instance.
Toggling GSThe signal global routing nets design that provide means setting resetting applicable components device during configuration. simulation behavior this signal modeled using glbl module Verilog ROC/ROCBUF components VHDL.
Providing Clocks Simulation
simulation, clocks inside generated using SIM_PLL_PERDIV2 parameter picoseconds). other clocks driven into user clock must have same level precision, buffer errors (and buffer errors systems without clock correction) result. When generating USRCLK, USRCLK2, reference clock signals test bench, clock periods must related SIM_PLL_PERDIV2 also round number picoseconds). some cases, simulation clock rate slightly different from clock rate used actual design.
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Description
Simulating Verilog
signal defined $XILINX/verilog/src/glbl.v module. Because glbl.v module connects global signal design, necessary compile this module with other design files load along with design.v testfixture.v files simulation. Note: There important difference between simulating GTP_DUAL tiles GTX_DUAL tiles
Verilog. simulation model GTP_DUAL tile requires additional global 3-state signal (GTS). GTX_DUAL tile simulation model does this additional signal.
Defining Test Bench
There ways handle test bench: most cases, need defined test bench. glbl.v file declares signals automatically pulses This handling sufficient back-end simulations functional simulations well. simulation model GTX_DUAL does signal. needs emulated test bench, following snippet code must added testfixture.v file:
assign glbl.GSR gsr_r; initial begin gsr_r 1'b1; #(16*CLOCKPERIOD); gsr_r 1'b0;
Simulating VHDL
ROCBUF cell controls emulated signal test bench. This component creates buffer signal provides input port buffer drive GSR. This port must declared entity list driven through test bench. VHDL code this cell, located EX_ROCBUF.vhd, listed here:
library IEEE; IEEE.std_logic_1164.all; IEEE.std_logic_unsigned.all; library UNISIM; UNISIM.all; entity EX_ROCBUF port CLOCK, ENABLE, SRP,RESET std_logic; C_OUT: std_logic_vector downto EX_ROCBUF; architecture EX_ROCBUF signal std_logic; signal COUNT std_logic_vector downto component ROCBUF port std_logic; std_logic component;
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begin ROCBUF port SRP, GSR); //dummy process COUNTER process (CLOCK, ENABLE, RESET) begin process COUNTER;
VHDL code this test bench, located EX_ROCBUF_tb.vhd, listed here:
entity EX_ROCBUF_tb EX_ROCBUF_tb; architecture behavior EX_ROCBUF_tb declare component EX_ROCBUF declare signals begin EX_ROCBUF_inst: EX_ROCBUF PORT MAP( CLOCK CLOCK, ENABLE ENABLE, SRP, RESET RESET, COUT COUT Clk_generation: process Begin process reset '1', after CLK_PERIOD '1', after CLK_PERIOD
Further details found Synthesis Simulation Design Guide [Ref
Examples
Simulation Environment Setup Example (ModelSim 6.1e Linux)
This section provides example simulation environment SmartModel support. This prerequisite simulating designs containing GTX_DUAL tile(s). This example uses ModelSim 6.1e, simulator from Mentor Graphics, with RedHat Enterprise Linux operating system version 9.1i Xilinx ISE® development system. Synthesis Simulation Guide provides guidelines examples different simulator development system (1).
there contradiction between this example documentation your simulator, simulator documentation precedence. newer version Xilinx development system used, check Xilinx website additional information.
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Examples
setenv these environment variables:
XILINX MODEL_TECH LMC_HOME LMC_CONFIG Location installed Xilinx system (for example, /opt/Xilinx/ise_9_1_i) Location installed ModelSim simulator (for example, $LMC_HOME/data/linux.lmc
LD_LIBRARY_PATH
initialization file (Modelsim.ini) contains these settings:
libsm $MODEL_TECH/libsm.sl libswift Resolution ;(one picosecond simulator resolution)
location SmartModel directory tree
selected options COMPXLIB tool are:
compxlib mti_se -arch -smartmodel_setup
These options COMPXLIB tool compile libraries languages ModelSim 6.1e simulator. default output directory compiled libraries specified written $XILINX/vhdl/mti_se $XILINX/verilog/mti_se.
SIM_PLL_PERDIV2 Calculation Example
This section provides examples calculate correct value simulationonly attribute SIM_PLL_PERDIV2. period calculated using Equation Equation 3-3. REFCLK SPEED PLL_DIVSEL_FB PLL_DIVSEL_REF SIM_PLL_PERDIV2 SPEED terms used Equation Equation defined follows: REFCLK speed clock tied CLKIN input GTX_DUAL tile MHz. PLL_DIVSEL_REF attribute that defines dividing factor reference clock divider shared PLL. PLL_DIVSEL_FB attribute that defines dividing factor feedback divider (which acts like multiplication factor) shared PLL. when INTDATAWIDTH (20-bit mode) when OVERSAMPLE_MODE TRUE when INTDATAWIDTH (16-bit mode) OVERSAMPLE_MODE FALSE Equation
Equation
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Example Express Design
calculate SPEED SIM_PLL_PERDIV2 Express example, following values assigned: REFCLK PLL_DIVSEL_REF PLL_DIVSEL_FB
Using Equation 3-2, SPEED GHz, meaning that period Using Equation 3-3, SIM_PLL_PERDIV2 divided equal decimal hexadecimal).
Example Gigabit Ethernet Design
calculate SPEED SIM_PLL_PERDIV2 Gigabit Ethernet example, following values assigned: REFCLK PLL_DIVSEL_REF PLL_DIVSEL_FB
Using Equation 3-2, SPEED GHz, meaning that period Using Equation 3-3, SIM_PLL_PERDIV2 divided decimal hexadecimal).
Example XAUI Design
calculate SPEED SIM_PLL_PERDIV2 XAUI example, following values assigned: REFCLK 312.5 PLL_DIVSEL_REF PLL_DIVSEL_FB
Using Equation 3-2, SPEED 1.5625 GHz, meaning that period Using Equation 3-3, SIM_PLL_PERDIV2 divided decimal (140 hexadecimal).
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Chapter
Implementation
Overview
This chapter provides information needed GTX_DUAL tiles instantiated design device resources, including: location GTX_DUAL tiles available device package combinations. numbers external signals associated with each GTX_DUAL tile. GTX_DUAL tiles clocking resources instantiated design mapped available locations with user constraints file (UCF).
common practice define location transceivers early design process ensure correct usage clock resources facilitate signal integrity analysis during board design. implementation flow facilitates this practice through location constraints UCF. While this chapter describes instantiate GTX_DUAL clocking components, details different GTX_DUAL tile clocking options discussed "Clocking," page
Ports Attributes
Table shows external ports associated with each GTX_DUAL tile. Table 4-1: GTX_DUAL Tile External Ports
Port MGTTXP0 MGTTXN0 MGTTXP1 MGTTXN1 MGTRXP0 MGTRXN0 MGTRXP1 MGTRXN1 MGTREFCLKP MGTREFCLKN MGTAVCCPLL Analog Analog Differential reference clock input pair 1.0V supply Embedded Clock Differential receive data pairs transceivers Embedded Clock Differential transmit data pairs transceivers Domain Description
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Chapter Implementation
Table 4-1:
GTX_DUAL Tile External Ports (Cont'd)
Port Analog Analog Analog Domain Analog Analog Analog Description pads 1.0V supply transceiver mixed signal circuitry 1.2V supply circuitry pads 1.2V supply circuitry
MGTAVCC MGTAVTTRX MGTAVTTTX
Notes:
These port names have prefix identify them easily file that often used create symbols board design schematics. this document, prefix removed from those names; however, names with without prefix synonymous with each other.
There attributes this section.
Description
position GTX_DUAL tiles specified coordinate system that describes column number relative position within that column. current members Virtex-5 platform, GTX_DUAL tiles located single column along side die. devices have column GTX_DUAL tiles right side column GTX_DUAL tiles left side device. result coordinate GTX_DUAL tiles devices. devices, left column right column "Package Placement Information," page lists GTX_DUAL tile position information available device package combinations along with numbers external signals associated with each tile. Virtex-5 devices have columns GTX_DUAL tiles. left column indices right column indices There ways create designs that utilize GTX_DUAL tiles. preferred method using RocketIO Wizard (see Chapter "RocketIO Transceiver Wizard"). Wizard automatically generates templates that configure transceivers contain placeholders GTX_DUAL placement information. UCFs generated Wizard then edited customize operating parameters placement information application. second approach create hand. When using this approach, designer must enter both configuration attributes that control transceiver operation well tile location parameters. Care must taken ensure that parameters needed configure GTX_DUAL tile correctly entered.
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Example GTX_DUAL Placement
Example GTX_DUAL Placement
This section shows elements that instantiates seven GTX_DUAL tiles. file implements example configuration shown Figure 5-5, page device package combination chosen this example XC5VFX100T-FF1136.
Instantiate GTX_DUAL tiles locations X0Y7 X0Y1 INST LOC=GTX_DUAL_X0Y1; INST LOC=GTX_DUAL_X0Y2; INST LOC=GTX_DUAL_X0Y3; INST LOC=GTX_DUAL_X0Y4; INST LOC=GTX_DUAL_X0Y5; INST LOC=GTX_DUAL_X0Y6; INST LOC=GTX_DUAL_X0Y7; Connect REFCLK_PAD_(N/P) differential pair middle GTX_DUAL tile (GTX_DUAL_X0Y4) refclk_pad_n LOC=P3; refclk_pad_p LOC=P4;
instantiation GTX_DUAL tiles IBUFDS primitive typically done code within design hierarchy. That code also connects output IBUFDS primitive CLKIN inputs GTX_DUAL tiles, illustrated following Verilog code fragment:
Instantiate GTX_DUAL tiles genvar tile_num; generate (tile_num tile_num ++tile_num) begin: gtx_dual GTX_DUAL gtx_dual .CLKIN(refclk), remaining GTX_DUAL ports shown endgenerate
Instantiate IBUFDS reference clock IBUFDS ref_clk_buffer (refclk), (refclk_pad_p), (refclk_pad_n)
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Chapter Implementation
Package Placement Information
diagrams this section illustrate GTX_DUAL placement following packages: packages:
XC5VFX30T-FF665 XC5VFX70T-FF665 XC5VFX70T-FF1136 XC5VFX100T-FF1136 XC5VFX100T-FF1738 XC5VFX130T-FF1738 XC5VFX200T-FF1738 XC5VTX150T-FF1156 XC5VTX150T-FF1759 XC5VTX240T-FF1759
packages:
Figure illustrates nomenclature used each these diagrams. GTX_DUAL placement name name used GTX_DUAL tiles instantiated design specific tiles device. board-level names numbers names placed file generated design flow. This file typically used board-level schematic capture layout tools create component symbols layout footprints.
Board-Level Names
GTX_DUAL Placement Name
GTX_DUAL_X0Y3
MGTREFCLKP_116 MGTREFCLKN_116 MGTRXP1_116 MGTRXN1_116 MGTRXP0_116 MGTRXN0_116 MGTTXP1_116 MGTTXN1_116 MGTTXP0_116 MGTTXN0_116
MGTAVCCPLL_116 MGTAVCC_116 MGTAVCC_116 MGTAVTTRX_116 MGTAVTTTX_116 MGTAVTTTX_116
Board-Level Numbers
UG198_c4_01_040207
Figure 4-1:
Placement Diagram Nomenclature
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Package Placement Information
Table defines location MGTRREF, MGTAVTTRXC, MGTRREF_R (TXT only), MGTAVTTRXC_R (TXT only) different packages. Table 4-2:
Package 1136 1156 1738 1759
GTX_DUAL Analog Placement
MGTRREF (FXT only) MGTAVTTRXC (FXT only) MGTRREF_L (TXT only) AB39 MGTAVTTRXC_L (TXT only) AA39 MGTRREF_R (TXT only) MGTAVTTRXC_R (TXT only)
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Chapter Implementation
Right Edge XC5VFX30T: GTX_DUAL_X0Y3 XC5VFX70T: GTX_DUAL_X0Y5 MGTREFCLKP_116 MGTREFCLKN_116 MGTRXP1_116 MGTRXN1_116 MGTRXP0_116 MGTRXN0_116 MGTTXP1_116 MGTTXN1_116 MGTTXP0_116 MGTTXN0_116
Power Pins MGTAVCCPLL_116 MGTAVCC_116 MGTAVCC_116 MGTAVTTRX_116 MGTAVTTTX_116 MGTAVTTTX_116
MGTREFCLKP_112 MGTREFCLKN_112 MGTRXP1_112 MGTRXN1_112 MGTRXP0_112 MGTRXN0_112 MGTTXP1_112 MGTTXN1_112 MGTTXP0_112 MGTTXN0_112
MGTAVCCPLL_112 MGTAVCC_112 MGTAVCC_112 MGTAVTTRX_112 MGTAVTTTX_112 MGTAVTTTX_112
XC5VFX30T: GTX_DUAL_X0Y2 XC5VFX70T: GTX_DUAL_X0Y4
MGTREFCLKP_114 MGTREFCLKN_114 MGTRXP1_114 MGTRXN1_114 MGTRXP0_114 MGTRXN0_114 MGTTXP1_114 MGTTXN1_114 MGTTXP0_114 MGTTXN0_114
MGTAVCCPLL_114 MGTAVCC_114 MGTAVCC_114 MGTAVTTRX_114
XC5VFX30T: GTX_DUAL_X0Y1 XC5VFX70T: GTX_DUAL_X0Y3
MGTAVTTTX_114 MGTAVTTTX_114
MGTREFCLKP_118 MGTREFCLKN_118 MGTRXP1_118 MGTRXN1_118 MGTRXP0_118 MGTRXN0_118 MGTTXP1_118 MGTTXN1_118 MGTTXP0_118 MGTTXN0_118
MGTAVCCPLL_118 MGTAVCC_118 MGTAVCC_118 MGTAVTTRX_118 MGTAVTTTX_118 MGTAVTTTX_118
XC5VFX30T: GTX_DUAL_X0Y0 XC5VFX70T: GTX_DUAL_X0Y2
UG198_c4_02_041507
Figure 4-2: XC5VFX30T-FF665, XC5VFX70T-FF665 Placement
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Package Placement Information
Right Edge XC5VFX70T: GTX_DUAL_X0Y7 XC5VFX100T: GTX_DUAL_X0Y7 MGTREFCLKP_124 MGTREFCLKN_124 MGTRXP1_124 MGTRXN1_124 MGTRXP0_124 MGTRXN0_124 MGTTXP1_124 MGTTXN1_124 MGTTXP0_124 MGTTXN0_124
Power Pins MGTAVCCPLL_124 MGTAVCC_124 MGTAVCC_124 MGTAVTTRX_124 MGTAVTTTX_124 MGTAVTTTX_124
MGTREFCLKP_120 MGTREFCLKN_120 MGTRXP1_120 MGTRXN1_120 MGTRXP0_120 MGTRXN0_120 MGTTXP1_120 MGTTXN1_120 MGTTXP0_120 MGTTXN0_120
MGTAVCCPLL_120 MGTAVCC_120 MGTAVCC_120 MGTAVTTRX_120 MGTAVTTTX_120 MGTAVTTTX_120
XC5VFX70T: GTX_DUAL_X0Y6 XC5VFX100T: GTX_DUAL_X0Y6
MGTREFCLKP_116 MGTREFCLKN_116 MGTRXP1_116 MGTRXN1_116 MGTRXP0_116 MGTRXN0_116 MGTTXP1_116 MGTTXN1_116 MGTTXP0_116 MGTTXN0_116
MGTAVCCPLL_116 MGTAVCC_116 MGTAVCC_116 MGTAVTTRX_116 MGTAVTTTX_116 MGTAVTTTX_116
XC5VFX70T: GTX_DUAL_X0Y5 XC5VFX100T: GTX_DUAL_X0Y5
XC5VFX70T: GTX_DUAL_X0Y4 XC5VFX100T: GTX_DUAL_X0Y4
MGTREFCLKP_112 MGTREFCLKN_112 MGTRXP1_112 MGTRXN1_112 MGTRXP0_112 MGTRXN0_112 MGTTXP1_112 MGTTXN1_112 MGTTXP0_112 MGTTXN0_112
MGTAVCCPLL_112 MGTAVCC_112 MGTAVCC_112 MGTAVTTRX_112 MGTAVTTTX_112 MGTAVTTTX_112
UG198_c4_03_041607
Figure 4-3: XC5VFX70T-FF1136, XC5VFX100T-FF1136 Placement
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Right Edge XC5VFX70T: GTX_DUAL_X0Y3 XC5VFX100T: GTX_DUAL_X0Y3 MGTREFCLKP_114 MGTREFCLKN_114 MGTRXP1_114 MGTRXN1_114 MGTRXP0_114 MGTRXN0_114 MGTTXP1_114 MGTTXN1_114 MGTTXP0_114 MGTTXN0_114
Power Pins MGTAVCCPLL_114 MGTAVCC_114 MGTAVCC_114 MGTAVTTRX_114
MGTAVTTTX_114 MGTAVTTTX_114
MGTREFCLKP_118 MGTREFCLKN_118 MGTRXP1_118 MGTRXN1_118 MGTRXP0_118 MGTRXN0_118 MGTTXP1_118 MGTTXN1_118 MGTTXP0_118 MGTTXN0_118
MGTAVCCPLL_118 MGTAVCC_118 MGTAVCC_118 MGTAVTTRX_118 MGTAVTTTX_118 MGTAVTTTX_118
XC5VFX70T: GTX_DUAL_X0Y2 XC5VFX100T: GTX_DUAL_X0Y2
MGTREFCLKP_122 MGTREFCLKN_122 MGTRXP1_122 MGTRXN1_122 MGTRXP0_122 MGTRXN0_122 MGTTXP1_122 MGTTXN1_122 MGTTXP0_122 MGTTXN0_122
MGTAVCCPLL_122 MGTAVCC_122 MGTAVCC_122 MGTAVTTRX_122
XC5VFX70T: GTX_DUAL_X0Y1 XC5VFX100T: GTX_DUAL_X0Y1
MGTAVTTTX_122 MGTAVTTTX_122
AN10
MGTREFCLKP_126 MGTREFCLKN_126 MGTRXP1_126 MGTRXN1_126 MGTRXP0_126 MGTRXN0_126 MGTTXP1_126 MGTTXN1_126 MGTTXP0_126 MGTTXN0_126
MGTAVCCPLL_126 MGTAVCC_126 MGTAVCC_126 MGTAVTTRX_126 AM10 MGTAVTTTX_126 MGTAVTTTX_126
XC5VFX70T: GTX_DUAL_X0Y0 XC5VFX100T: GTX_DUAL_X0Y0
UG198_c4_04_041607
Figure 4-4: XC5VFX70T-FF1136, XC5VFX100T-FF1136 Placement
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Package Placement Information
Right Edge XC5VFX100T: Available XC5VFX130T: Available XC5VFX200T: GTX_DUAL_X0Y11 MGTREFCLKP_132 MGTREFCLKN_132 MGTRXP1_132 MGTRXN1_132 MGTRXP0_132 MGTRXN0_132 MGTTXP1_132 MGTTXN1_132 MGTTXP0_132 MGTTXN0_132
Power Pins MGTAVCCPLL_132 MGTAVCC_132 MGTAVCC_132 MGTAVTTRX_132 MGTAVTTTX_132 MGTAVTTTX_132
XC5VFX100T: Available XC5VFX130T: GTX_DUAL_X0Y09 XC5VFX200T: GTX_DUAL_X0Y10
MGTREFCLKP_128 MGTREFCLKN_128 MGTRXP1_128 MGTRXN1_128 MGTRXP0_128 MGTRXN0_128 MGTTXP1_128 MGTTXN1_128 MGTTXP0_128 MGTTXN0_128
MGTAVCCPLL_128 MGTAVCC_128 MGTAVCC_128 MGTAVTTRX_128 MGTAVTTTX_128 MGTAVTTTX_128
XC5VFX100T: GTX_DUAL_X0Y7 XC5VFX130T: GTX_DUAL_X0Y8 XC5VFX200T: GTX_DUAL_X0Y9
MGTREFCLKP_124 MGTREFCLKN_124 MGTRXP1_124 MGTRXN1_124 MGTRXP0_124 MGTRXN0_124 MGTTXP1_124 MGTTXN1_124 MGTTXP0_124 MGTTXN0_124
MGTAVCCPLL_124 MGTAVCC_124 MGTAVCC_124 MGTAVTTRX_124 MGTAVTTTX_124 MGTAVTTTX_124
XC5VFX100T: GTX_DUAL_X0Y6 XC5VFX130T: GTX_DUAL_X0Y7 XC5VFX200T: GTX_DUAL_X0Y8
MGTREFCLKP_120 MGTREFCLKN_120 MGTRXP1_120 MGTRXN1_120 MGTRXP0_120 MGTRXN0_120 MGTTXP1_120 MGTTXN1_120 MGTTXP0_120 MGTTXN0_120
MGTAVCCPLL_120 MGTAVCC_120 MGTAVCC_120 MGTAVTTRX_120 MGTAVTTTX_120 MGTAVTTTX_120
UG198_c4_05_041607
Figure 4-5:
XC5VFX100T-FF1738, XC5VFX130T-FF1738, XC5VFX200T-FF1738 Placement
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Chapter Implementation
Right Edge XC5VFX100T: GTX_DUAL_X0Y5 XC5VFX130T: GTX_DUAL_X0Y6 XC5VFX200T: GTX_DUAL_X0Y7 MGTREFCLKP_116 MGTREFCLKN_116 MGTRXP1_116 MGTRXN1_116 MGTRXP0_116 MGTRXN0_116 MGTTXP1_116 MGTTXN1_116 MGTTXP0_116 MGTTXN0_116
Power Pins MGTAVCCPLL_116 MGTAVCC_116 MGTAVCC_116 MGTAVTTRX_116 MGTAVTTTX_116 MGTAVTTTX_116
XC5VFX100T: GTX_DUAL_X0Y4 XC5VFX130T: GTX_DUAL_X0Y5 XC5VFX200T: GTX_DUAL_X0Y6
MGTREFCLKP_112 MGTREFCLKN_112 MGTRXP1_112 MGTRXN1_112 MGTRXP0_112 MGTRXN0_112 MGTTXP1_112 MGTTXN1_112 MGTTXP0_112 MGTTXN0_112
MGTAVCCPLL_112 MGTAVCC_112 MGTAVCC_112 MGTAVTTRX_112
MGTAVTTTX_112 MGTAVTTTX_112
XC5VFX100T: GTX_DUAL_X0Y3 XC5VFX130T: GTX_DUAL_X0Y4 XC5VFX200T: GTX_DUAL_X0Y5
MGTREFCLKP_114 MGTREFCLKN_114 MGTRXP1_114 MGTRXN1_114 MGTRXP0_114 MGTRXN0_114 MGTTXP1_114 MGTTXN1_114 MGTTXP0_114 MGTTXN0_114
MGTAVCCPLL_114
MGTAVCC_114 MGTAVCC_114 MGTAVTTRX_114 MGTAVTTTX_114 MGTAVTTTX_114
XC5VFX100T: GTX_DUAL_X0Y2 XC5VFX130T: GTX_DUAL_X0Y3 XC5VFX200T: GTX_DUAL_X0Y4
MGTREFCLKP_118 MGTREFCLKN_118 MGTRXP1_118 MGTRXN1_118 MGTRXP0_118 MGTRXN0_118 MGTTXP1_118 MGTTXN1_118 MGTTXP0_118 MGTTXN0_118
MGTAVCCPLL_118 MGTAVCC_118 MGTAVCC_118 MGTAVTTRX_118
MGTAVTTTX_118 MGTAVTTTX_118
UG198_c4_06_041607
Figure 4-6:
XC5VFX100T-FF1738, XC5VFX130T-FF1738, XC5VFX200T-FF1738 Placement
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Package Placement Information
Right Edge XC5VFX100T: GTX_DUAL_X0Y1 XC5VFX130T: GTX_DUAL_X0Y2 XC5VFX200T: GTX_DUAL_X0Y3 MGTREFCLKP_122 MGTREFCLKN_122 MGTRXP1_122 MGTRXN1_122 MGTRXP0_122 MGTRXN0_122 MGTTXP1_122 MGTTXN1_122 MGTTXP0_122 MGTTXN0_122
Power Pins MGTAVCCPLL_122 MGTAVCC_122 MGTAVCC_122 MGTAVTTRX_122 MGTAVTTTX_122 MGTAVTTTX_122
XC5VFX100T: GTX_DUAL_X0Y0 XC5VFX130T: GTX_DUAL_X0Y1 XC5VFX200T: GTX_DUAL_X0Y2
MGTREFCLKP_126 MGTREFCLKN_126 MGTRXP1_126 MGTRXN1_126 MGTRXP0_126 MGTRXN0_126 MGTTXP1_126 MGTTXN1_126 MGTTXP0_126 MGTTXN0_126
MGTAVCCPLL_126 MGTAVCC_126 MGTAVCC_126 MGTAVTTRX_126 MGTAVTTTX_126 MGTAVTTTX_126
BB11 BB10 XC5VFX100T: Available XC5VFX130T: GTX_DUAL_X0Y0 XC5VFX200T: GTX_DUAL_X0Y1 BA12 BA11
MGTREFCLKP_130 MGTREFCLKN_130 MGTRXP1_130 MGTRXN1_130 MGTRXP0_130 MGTRXN0_130 MGTTXP1_130 MGTTXN1_130 MGTTXP0_130 MGTTXN0_130
AY11 MGTAVCCPLL_130 AY10 MGTAVCC_130 AW10 MGTAVCC_130 MGTAVTTRX_130
AY12 MGTAVTTTX_130 MGTAVTTTX_130
AW15 AY15 BB17 BB16 XC5VFX100T: Available XC5VFX130T: Available XC5VFX200T: GTX_DUAL_X0Y0 BB14 BB15 BA18 BA17 BA13 BA14
MGTREFCLKP_134 MGTREFCLKN_134 MGTRXP1_134 MGTRXN1_134 MGTRXP0_134 MGTRXN0_134 MGTTXP1_134 MGTTXN1_134 MGTTXP0_134 MGTTXN0_134
AY17 MGTAVCCPLL_134 AY16 MGTAVCC_134 AW16 MGTAVCC_134 AY14 MGTAVTTRX_134 AY13 MGTAVTTTX_134 AY18 MGTAVTTTX_134
UG198_c4_07_041607
Figure 4-7:
XC5VFX100T-FF1738, XC5VFX130T-FF1738, XC5VFX200T-FF1738 Placement
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Chapter Implementation
Right Edge XC5VTX150T: GTX_DUAL_X1Y9 MGTREFCLKP_128 MGTREFCLKN_128 MGTRXP1_128 MGTRXN1_128 MGTRXP0_128 MGTRXN0_128 MGTTXP1_128 MGTTXN1_128 MGTTXP0_128 MGTTXN0_128
Power Pins MGTAVCCPLL_128 MGTAVCC_128 MGTAVTTRX_128 MGTAVTTTX_128
XC5VTX150T: GTX_DUAL_X1Y8
MGTREFCLKP_124 MGTREFCLKN_124 MGTRXP1_124 MGTRXN1_124 MGTRXP0_124 MGTRXN0_124 MGTTXP1_124 MGTTXN1_124 MGTTXP0_124 MGTTXN0_124
MGTAVCCPLL_124 MGTAVCC_124 MGTAVTTRX_124 MGTAVTTTX_124
XC5VTX150T: GTX_DUAL_X1Y7
MGTREFCLKP_120 MGTREFCLKN_120 MGTRXP1_120 MGTRXN1_120 MGTRXP0_120 MGTRXN0_120 MGTTXP1_120 MGTTXN1_120 MGTTXP0_120 MGTTXN0_120
MGTAVCCPLL_120 MGTAVCC_120 MGTAVTTRX_120 MGTAVTTTX_120
XC5VTX150T: GTX_DUAL_X1Y6
MGTREFCLKP_116 MGTREFCLKN_116 MGTRXP1_116 MGTRXN1_116 MGTRXP0_116 MGTRXN0_116 MGTTXP1_116 MGTTXN1_116 MGTTXP0_116 MGTTXN0_116
MGTAVCCPLL_116 MGTAVCC_116 MGTAVTTRX_116 MGTAVTTTX_116
UG198_c4_08_071608
Figure 4-8:
XC5VTX150T-FF1156 Placement
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Package Placement Information
Right Edge XC5VTX150T: GTX_DUAL_X1Y5 MGTREFCLKP_112 MGTREFCLKN_112 MGTRXP1_112 MGTRXN1_112 MGTRXP0_112 MGTRXN0_112 MGTTXP1_112 MGTTXN1_112 MGTTXP0_112 MGTTXN0_112
Power Pins MGTAVCCPLL_112 MGTAVCC_112 MGTAVTTRX_112 MGTAVTTTX_112
XC5VTX150T: GTX_DUAL_X1Y4
MGTREFCLKP_114 MGTREFCLKN_114 MGTRXP1_114 MGTRXN1_114 MGTRXP0_114 MGTRXN0_114 MGTTXP1_114 MGTTXN1_114 MGTTXP0_114 MGTTXN0_114
MGTAVCCPLL_114 MGTAVCC_114 MGTAVTTRX_114
MGTAVTTTX_114
XC5VTX150T: GTX_DUAL_X1Y3
MGTREFCLKP_118 MGTREFCLKN_118 MGTRXP1_118 MGTRXN1_118 MGTRXP0_118 MGTRXN0_118 MGTTXP1_118 MGTTXN1_118 MGTTXP0_118 MGTTXN0_118
MGTAVCCPLL_118 MGTAVCC_118 MGTAVTTRX_118 MGTAVTTTX_118
XC5VTX150T: GTX_DUAL_X1Y2
MGTREFCLKP_122 MGTREFCLKN_122 MGTRXP1_122 MGTRXN1_122 MGTRXP0_122 MGTRXN0_122 MGTTXP1_122 MGTTXN1_122 MGTTXP0_122 MGTTXN0_122
MGTAVCCPLL_122 MGTAVCC_122 MGTAVTTRX_122
MGTAVTTTX_122
UG198_c4_09_01608
Figure 4-9:
XC5VTX150T-FF1156 Placement
RocketIO Transceiver User Guide UG198 (v2.1) November 2008
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Chapter Implementation
Right Edge XC5VTX150T: GTX_DUAL_X1Y1 MGTREFCLKP_126 MGTREFCLKN_126 MGTRXP1_126 MGTRXN1_126 MGTRXP0_126 MGTRXN0_126 MGTTXP1_126 MGTTXN1_126 MGTTXP0_126 MGTTXN0_126
Power Pins MGTAVCCPLL_126 MGTAVCC_126 MGTAVTTRX_126 AM10 MGTAVTTTX_126
AL13 AM13 AP14 AP13 XC5VTX150T: GTX_DUAL_X1Y0 AP11 AP12 AN15 AN14 AN10 AN11
MGTREFCLKP_130 MGTREFCLKN_130 MGTRXP1_130 MGTRXN1_130 MGTRXP0_130 MGTRXN0_130 MGTTXP1_130 MGTTXN1_130 MGTTXP0_130 MGTTXN0_130
AM15 MGTAVCCPLL_130 AM14 MGTAVCC_130 AM12 MGTAVTTRX_130 AP16 MGTAVTTTX_130
UG198_c4_10_071608
Figure 4-10:
XC5VTX150T-FF1156 Placement
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Package Placement Information
Power Pins MGTAVCCPLL_127 MGTAVCC_127 MGTAVTTRX_127 MGTAVTTTX_127 MGTREFCLKP_127 MGTREFCLKN_127 MGTRXP1_127 MGTRXN1_127 MGTRXP0_127 MGTRXN0_127 MGTTXP1_127 MGTTXN1_127 MGTTXP0_127 MGTTXN0_127
Left Edge XC5VTX150T: GTX_DUAL_X0Y9
MGTAVCCPLL_123 MGTAVCC_123 MGTAVTTRX_123 MGTAVTTTX_123
MGTREFCLKP_123 MGTREFCLKN_123 MGTRXP1_123 MGTRXN1_123 MGTRXP0_123 MGTRXN0_123 MGTTXP1_123 MGTTXN1_123 MGTTXP0_123 MGTTXN0_123
XC5VTX150T: GTX_DUAL_X0Y8
MGTAVCCPLL_119 MGTAVCC_119 MGTAVTTRX_119 MGTAVTTTX_119
MGTREFCLKP_119 MGTREFCLKN_119 MGTRXP1_119 MGTRXN1_119 MGTRXP0_119 MGTRXN0_119 MGTTXP1_119 MGTTXN1_119 MGTTXP0_119 MGTTXN0_119
XC5VTX150T: GTX_DUAL_X0Y7
MGTAVCCPLL_115 MGTAVCC_115 MGTAVTTRX_115 MGTAVTTTX_115
MGTREFCLKP_115 MGTREFCLKN_115 MGTRXP1_115 MGTRXN1_115 MGTRXP0_115 MGTRXN0_115 MGTTXP1_115 MGTTXN1_115 MGTTXP0_115 MGTTXN0_115
UG198_c4_11_071608
XC5VTX150T: GTX_DUAL_X0Y6
Figure 4-11:
XC5VTX150T-FF1156 Placement
RocketIO Transceiver User Guide UG198 (v2.1) November 2008
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Chapter Implementation
Power Pins MGTAVCCPLL_111 MGTAVCC_111 MGTAVTTRX_111 MGTAVTTTX_111 MGTREFCLKP_111 MGTREFCLKN_111 MGTRXP1_111 MGTRXN1_111 MGTRXP0_111 MGTRXN0_111 MGTTXP1_111 MGTTXN1_111 MGTTXP0_111 MGTTXN0_111
Left Edge XC5VTX150T: GTX_DUAL_X0Y5
MGTAVCCPLL_113 MGTAVCC_113 MGTAVTTRX_113 MGTAVTTTX_113
AB32 AA32 AC32
MGTREFCLKP_113 MGTREFCLKN_113 MGTRXP1_113 MGTRXN1_113 MGTRXP0_113 MGTRXN0_113 MGTTXP1_113 MGTTXN1_113 MGTTXP0_113 MGTTXN0_113
AB34 AA34 AC33 AB33 XC5VTX150T: GTX_DUAL_X0Y4
MGTAVCCPLL_117 MGTAVCC_117 MGTAVTTRX_117 MGTAVTTTX_117
AH32 AG32 AE32 AJ32
MGTREFCLKP_117 MGTREFCLKN_117 MGTRXP1_117 MGTRXN1_117 MGTRXP0_117 MGTRXN0_117 MGTTXP1_117 MGTTXN1_117 MGTTXP0_117 MGTTXN0_117
AF31 AF32 AH34 AG34 AE34 AF34 AJ33 AH33 AD33 AE33 XC5VTX150T: GTX_DUAL_X0Y3
MGTAVCCPLL_121 MGTAVCC_121 MGTAVTTRX_121 MGTAVTTTX_121
AM32 AL31 AL32 AM32
MGTREFCLKP_121 MGTREFCLKN_121 MGTRXP1_121 MGTRXN1_121 MGTRXP0_121 MGTRXN0_121 MGTTXP1_121 MGTTXN1_121 MGTTXP0_121 MGTTXN0_121
AK30 AL30 AP33 AP34 AL34 AM34 AN32 AN33 AK33 AL33
UG198_c4_12_071608
XC5VTX150T: GTX_DUAL_X0Y2
Figure 4-12:
XC5VTX150T-FF1156 Placement
www.xilinx.com
RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Package Placement Information
Power Pins MGTAVCCPLL_125 MGTAVCC_125 MGTAVTTRX_125 MGTAVTTTX_125 AM26 AM27 AM29 AM25 MGTREFCLKP_125 MGTREFCLKN_125 MGTRXP1_125 MGTRXN1_125 MGTRXP0_125 MGTRXN0_125 MGTTXP1_125 MGTTXN1_125 MGTTXP0_125 MGTTXN0_125
Left Edge AL28 AM28 AP27 AP28 AP30 AP29 AN26 AN27 AN31 AN30 XC5VTX150T: GTX_DUAL_X0Y1
MGTAVCCPLL_129 MGTAVCC_129 MGTAVTTRX_129 MGTAVTTTX_129
AM20 AM21 AM23 AP19
MGTREFCLKP_129 MGTREFCLKN_129 MGTRXP1_129 MGTRXN1_129 MGTRXP0_129 MGTRXN0_129 MGTTXP1_129 MGTTXN1_129 MGTTXP0_129 MGTTXN0_129
AL22 AM22 AP21 AP22 AP24 AP23 AN20 AN21 AN25 AN24
UG198_c4_13_071608
XC5VTX150T: GTX_DUAL_X0Y0
Figure 4-13:
XC5VTX150T-FF1156 Placement
RocketIO Transceiver User Guide UG198 (v2.1) November 2008
www.xilinx.com
Chapter Implementation
Right Edge XCV5TX150T: Available XCV5TX240T: GTX_DUAL_X1Y11 MGTREFCLKP_132 MGTREFCLKN_132 MGTRXP1_132 MGTRXN1_132 MGTRXP0_132 MGTRXN0_132 MGTTXP1_132 MGTTXN1_132 MGTTXP0_132 MGTTXN0_132
Power Pins MGTAVCCPLL_132 MGTAVCC_132 MGTAVTTRX_132 MGTAVTTTX_132
XCV5TX150T: GTX_DUAL_X1Y9 XCV5TX240T: GTX_DUAL_X1Y10
MGTREFCLKP_128 MGTREFCLKN_128 MGTRXP1_128 MGTRXN1_128 MGTRXP0_128 MGTRXN0_128 MGTTXP1_128 MGTTXN1_128 MGTTXP0_128 MGTTXN0_128
MGTAVCCPLL_128 MGTAVCC_128 MGTAVTTRX_128 MGTAVTTTX_128
XCV5TX150T: GTX_DUAL_X1Y8 XCV5TX240T: GTX_DUAL_X1Y9
MGTREFCLKP_124 MGTREFCLKN_124 MGTRXP1_124 MGTRXN1_124 MGTRXP0_124 MGTRXN0_124 MGTTXP1_124 MGTTXN1_124 MGTTXP0_124 MGTTXN0_124
MGTAVCCPLL_124 MGTAVCC_124 MGTAVTTRX_124 MGTAVTTTX_124
XCV5TX150T: GTX_DUAL_X1Y7 XCV5TX240T: GTX_DUAL_X1Y8
MGTREFCLKP_120 MGTREFCLKN_120 MGTRXP1_120 MGTRXN1_120 MGTRXP0_120 MGTRXN0_120 MGTTXP1_120 MGTTXN1_120 MGTTXP0_120 MGTTXN0_120
MGTAVCCPLL_120 MGTAVCC_120 MGTAVTTRX_120 MGTAVTTTX_120
UG198_c4_17_090508
Figure 4-14:
XC5VTX150T-FF1759 XC5VTX240T-FF1759 Placement
www.xilinx.com
RocketIO Transceiver User Guide UG198 (v2.1) November 2008
Package Placement Information
Right Edge XCV5TX150T: GTX_DUAl_X1Y6 XCV5TX240T: GTX_DUAL_X1Y7 MGTREFCLKP_116 MGTREFCLKN_116 MGTRXP1_116 MGTRXN1_116 MGTRXP0_116 MGTRXN0_116 MGTTXP1_116 MGTTXN1_116 MGTTXP0_116 MGTTXN0_116
Power Pins MGTAVCCPLL_116 MGTAVCC_116 MGTAVTTRX_116 MGTAVTTTX_116
XCV5TX150T: GTX_DUAL_X1Y5 XCV5TX240T: GTX_DUAL_X1Y6
MGTREFCLKP_112 MGTREFCLKN_112 MGTRXP1_112 MGTRXN1_112 MGTRXP0_112 MGTRXN0_112 MGTTXP1_112 MGTTXN1_112 MGTTXP0_112 MGTTXN0_112
MGTAVCCPLL_112 MGTAVCC_112 MGTAVTTRX_112
MGTAVTTTX_112
XCV5TX150T: GTX_DUAL_X1Y4 XCV5TX240T: GTX_DUAL_X1Y5
MGTREFCLKP_114 MGTREFCLKN_114 MGTRXP1_114 MGTRXN1_114 MGTRXP0_114 MGTRXN0_114 MGTTXP1_114 MGTTXN1_114 MGTTXP0_114 MGTTXN0_114
MGTAVCCPLL_114
MGTAVCC_114 MGTAVTTRX_114 MGTAVTTTX_114
XCV5TX150T: GTX_DUAL_X1Y3 XCV5TX240T: GTX_DUAL_X1Y4
MGTREFCLKP_118 MGTREFCLKN_118 MGTRXP1_118 MGTRXN1_118 MGTRXP0_118 MGTRXN0_118 MGTTXP1_118 MGTTXN1_118 MGTTXP0_118 MGTTXN0_118
MGTAVCCPLL_118 MGTAVCC
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