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Virtex-4 FPGA Designer's Guide
UG072 (1.2) June 2008
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Revision History
following table shows revision history this document. Version 08/02/04 09/09/04 06/24/08 Revision Initial Xilinx release. Chapter printed Handbook Chapter version 1.1. Added Preface Chapters Minimal revisions Chapter Removed SSTL3 rows from Table 2-1, page Updated Appendix "References".
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UG072 (1.2) June 2008
Table Contents
Revision History
Preface: About This Guide
Guide Contents Additional Documentation Additional Support Resources Typographical Conventions
Chapter Technology Basics
Structures
Traces Planes Vias Pads Anti-Pads Lands Dimensions
Transmission Lines Return Currents
Chapter SelectIO Signaling
Interface Types.
Single-Ended versus Differential Interfaces versus Interfaces
Single-Ended Signaling
Modes Attributes Input Thresholds Topologies Termination Unidirectional Topologies Termination Bidirectional Topology Termination Bidirectional Multi-Point Topologies
Chapter Multi-Gigabit Serial Signaling Chapter Power Distribution System
Power Distribution Design Overview Basic Decoupling Network Principles
What Role Inductance? Capacitor Parasitic Inductance. Inductance from Current Paths Mounting Inductance Plane Inductance Stackup Layer Order
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Capacitor Effective Frequency Capacitor Anti-Resonance Capacitor Placement
Design Verification
Step Determining Critical Parameters FPGA Step Designing Generic Bypassing Network Step Simulation Step Building Design Step Measuring Performance Noise Magnitude Measurement Noise Spectrum Measurements Step Optimum Bypassing Network Design (Optional) Possibility Excessive Noise from Other Devices Board Possibility Parasitic Inductance Planes, Vias, Connecting Traces Possibility Signals Stronger Than Necessary Possibility Signal Return Current Travelling Sub-Optimal Paths
Other Concerns Causes
Calculation Inductance SPICE Simulation Examples
HSPICE Netlist HSPICE Output Schematic Circuit
Tools Design Simulation
Appendix References
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Virtex-4 FPGA Designer's Guide UG072 (1.2) June 2008
Preface
About This Guide
This designer's guide provides information design PCBs Virtex®-4 devices. considers aspects from system level down minute details. Instead providing information device features specifications, this design guide focuses strategies making design decisions interface level.
Guide Contents
This manual contains following chapters: Chapter "PCB Technology Basics" Discusses basics current technology focusing physical structures common assumptions. Chapter "SelectIO Signaling" Contains information choice SelectIOstandards, topologies, termination strategies well information simulation measurement techniques. Chapter "Multi-Gigabit Serial Signaling" Provides information electrical requirements related serial transceivers. Chapter "Power Distribution System" Covers power distribution system Virtex-4 FPGAs, including details decoupling capacitor selection, voltage regulators geometries, simulation measurement. Appendix "References" Provides additional information references listed this document.
Additional Documentation
following documents also available download http://www.xilinx.com/virtex4. Virtex-4 Family Overview features product selection Virtex-4 family outlined this overview. Virtex-4 FPGA Data Sheet: Switching Characteristics This data sheet contains Switching Characteristic specifications Virtex-4 family.
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Preface: About This Guide
Virtex-4 FPGA User Guide This guide includes chapters
Clocking Resources Digital Clock Manager (DCM) Phase-Matched Clock Dividers (PMCD) Block FIFO memory Configurable Logic Blocks (CLBs) SelectIO Resources SelectIO Logic Resources Advanced SelectIO Logic Resources System Monitor
XtremeDSPDesign Considerations This guide describes XtremeDSP slice includes reference designs using DSP48 math functions various filters.
Virtex-4 FPGA Configuration Guide This all-encompassing configuration guide includes chapters configuration interfaces (serial SelectMAP), bitstream encryption, Boundary-Scan JTAG configuration, reconfiguration techniques, readback through SelectMAP JTAG interfaces.
Virtex-4 FPGA Packaging Pinout Specification This specification includes tables device/package combinations maximum I/Os, definitions, pinout tables, pinout diagrams, mechanical drawings, thermal specifications.
Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide This guide describes RocketIO Multi-Gigabit Transceivers available Virtex-4-FX family.
Virtex-4 FPGA Embedded Tri-Mode Ethernet User Guide This guide describes Tri-mode Ethernet Media Access Controller available Virtex-4 family.
PowerPC® Processor Block Reference Guide This guide updated include PowerPC processor block available Virtex-4 family.
Additional Support Resources
search database silicon software questions answers, create technical support case WebCase, Xilinx website http://www.xilinx.com/support.
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Typographical Conventions
Typographical Conventions
This document uses following typographical conventions. example illustrates each convention. Convention Meaning References other documents Italic font Emphasis text Underlined Text Indicates link page. Example Virtex-4 FPGA Configuration Guide more information. address asserted after clock event http://www.xilinx.com/virtex4
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Chapter
Technology Basics
Printed Circuit Boards (PCBs) electrical systems, having electrical properties just complicated discrete components devices mounted them. designer complete control over many aspects PCB. same time, current technology places constraints limits geometries resulting electrical properties. following information provided first primer, also guide freedoms, limitations, techniques designs using FPGAs. This chapter contains following sections: "PCB Structures" "Transmission Lines" "Return Currents"
Structures
technology changed significantly last decades. insulative substrate material (usually FR4, epoxy/glass composite) with copper plating both sides portions copper etched away form conductive paths. number layers plated etched substrates glued together stack with additional insulative substrates in-between etched substrates. Holes drilled through stack. Conductive plating applied these holes, selectively forming conductive connections between etched copper different layers. While there advancements areas material properties, number stacked layers, geometries, drilling techniques (allowing holes that only penetrate only portion stackup), basic structures PCBs have changed. These structures, formed through processes outlined above, abstracted physical/electrical structures: Traces, Planes planelets), vias, pads.
Traces
trace physical strip metal (usually copper) making electrical connection between more points coordinate PCB. Traces carry signals between these points.
Planes
plane uninterrupted area metal covering entirety layer. planelet, variation plane, uninterrupted area metal covering only portion layer. Typically number planelets exist layer. Planes planelets distribute power number points PCB. They very important transmission signals along traces.
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Chapter Technology Basics
Vias
physical piece metal making electrical connection between more points z-space PCB. Vias carry signals power between layers PCB. current plated-through-hole (PTH) technology, formed plating inner surface hole drilled through PCB. formed current microvia technology (also known High Density Interconnect HDI) with laser ablating substrate material deforming conductive plating, process forming conductive connection. These types Microvias formed cannot penetrate more than layers, however, they stacked stair-stepped form vias traversing full board thickness.
Pads Anti-Pads
Pads small areas copper prescribed shapes. Anti-pads small areas prescribed shapes where copper removed. Pads used both with vias exposed outer-layer copper mounting surface-mount components. Anti-pads used mainly with vias. Since plated through-hole vias conductive over whole length, method needed selectively making electrical connections traces, planes planelets various layers PCB. This function pads anti-pads. make solid connection trace layer, must present mechanical stability. size must meet drill tolerance/registration restrictions. Anti-pads used similar capacity reverse. Since plane planelet copper otherwise uninterrupted, travelling through makes electrical connection Where vias intended make electrical connection planes planelets passed through, anti-pad removes copper area layer where penetrates.
Lands
purposes soldering surface mount components, pads outer layers typically referred lands solder lands. Making electrical connections these lands usually requires vias. manufacturing constraints technology, rarely possible place inside area land. Instead, this technology uses short section trace connecting surface pad, minimum dimension specifications exist defining minimum length connecting trace. Microvia technology constrainted vias placed directly area solder land.
Dimensions
major factors defining dimensions FPGA package geometries, manufacturing limits, system compliance. Other factors such Design Manufacturing (DFM) reliability impose further limits, these application specific, they covered here. dimensions FPGA package, combination with manufacturing limits define most geometric aspects above structures, both directly indirectly. This itself constrains designer significantly. package ball pitch (1.0 packages; packages) defines land layout. minimum surface feature sizes current technology define arrangement area under device. Minimum diameters "keep-out areas" around those vias defined
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Transmission Lines
manufacturer limit amount space available in-between vias routing signals array underneath device. This defines maximum trace width these "breakout" traces. manufacturing limits constrain minimum trace width minimum spacing. number signal layers necessary accommodate FPGA defined number signal layers number plane layers. number signal layers defined number signal traces routed FPGA package (usually following total User count package). number plane layers defined number power ground plane layers necessary bring power FPGA provide references isolation signal layers. Most PCBs large FPGAs range from layers. System compliance often defines total thickness board. Along with number board layers, this defines maximum layer thickness, therefore spacing direction signal plane layers other signal plane layers. Z-direction spacing signal trace layers other signal trace layers affects crosstalk. Z-direction spacing signal trace layers reference plane layers affects signal trace impedance. Z-direction spacing plane layers other plane layers affects power system parasitic inductance. Z-direction spacing signal trace layers reference plane layers (defined total board thickness number board layers) defining factor trace impedance.Trace width (defined FPGA package ball pitch manufacturing constraints) another factor trace impedance. designer little control over trace impedance area array beneath FPGA. When traces escape array, their width change width target impedance (usually single-ended differential). Bypass capacitor placement discrete termination resistor placement other areas trade-off optimization. constraints often define keep-out area around perimeter FPGA (device footprint) where discrete components placed. purpose this allow room rework where necessary. this reason, area just outside keep-out area where components will compete placement. designer determine high priority components. Bypass capacitor placement constraints described Chapter "Power Distribution System". Termination resistor placement constraints must determined through signal integrity simulation, using IBIS SPICE.
Transmission Lines
combination signal trace reference plane forms transmission line. signals system travel through transmission lines. single-ended interfaces, both signal trace reference plane necessary transmit signal from place another PCB. differential interfaces, transmission line formed combination traces reference plane. While presence reference plane strictly necessary case differential signals, necessary practical implementation differential traces PCBs. Good signal integrity system dependent having transmission lines with controlled impedance. Impedance determined geometry traces dielectric constant material space around signal trace between signal trace reference plane. dielectric constant material vicinity trace reference plane property laminate materials, case surface traces, property fluid surrounding board. laminate typically variant FR4, though also exotic material.
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Chapter Technology Basics
While dielectric constant laminate varies from board board, fairly constant within board. Therefore relative impedance transmission lines defined most strongly trace geometries tolerances.
Return Currents
often neglected aspect transmission lines their signal integrity return current. incorrect assume that signal trace itself forms transmission line. Currents flowing signal trace have equal opposite complimentary current flowing reference plane beneath them. relationship trace voltage trace current reference plane voltage reference plane current defines characteristic impedance transmission line formed trace reference plane. While interruption reference plane continuity beneath trace dramatic effect severing signal trace, performance transmission line devices sharing reference plane affected. important attention reference plane continuity return current paths. Interruptions reference plane continuity, such holes, slots isolation splits, cause significant impedance discontinuities signal traces. They also significant contributor ground bounce Power Distribution System (PDS) noise from simultaneously switching outputs. importance return current paths cannot underestimated.
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Chapter
SelectIO Signaling
SelectIOterm Virtex-4 device family refers general-purpose various settings. With over standards over variants within these standards, highly flexible SelectIO resource offers wide array choices designing interfaces. This chapter provides some strategies choosing standard, topology, termination, offers guidance simulation measurement more detailed decision making verification. many cases, higher-level aspects system (other device choices standards support) define interfaces used. cases where such constraints present, system designer choose interface standards optimize them according purpose system. This chapter contains following sections: "Interface Types" "Single-Ended Signaling"
Interface Types
better address specifics various interface types, necessary first break interfaces into categories. relevant divisions made: Single-Ended interfaces versus Differential interfaces Single Data Rate (SDR) interfaces versus Double Data Rate (DDR) interfaces
Single-Ended versus Differential Interfaces
Traditional digital logic uses single-ended signaling convention that transmits signal assumes Ground common driver receiver. single-ended interfaces, signal's assertion (whether High Low) based voltage level relative fixed voltage threshold that referenced Ground. When voltage signal higher than threshold, state considered High. When voltage signal lower than threshold, state considered Low. common example single-ended standard. Higher-performance interfaces typically make differential signaling convention that transmits complementary signals referenced another. differential interfaces, signal's assertion (whether High Low) based relative voltage levels complementary signals. When voltage signal higher than voltage signal, state considered High. When voltage signal higher than voltage signal, state considered Low. Typically signals have similar swing relative Ground, although this always case. LVDS common example differential standard.
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Chapter SelectIO Signaling
versus Interfaces
difference between Single Data Rate (SDR) Double Data Rate (DDR) interfaces with relationship data signals clock signal that bus. systems, data only registered input flip-flops receiving device either rising falling edge clock. full clock period equivalent time. systems, data registered input flip-flops receiving device both rising falling edges clock. full clock period equivalent times. distinction nothing with whether standard carrying signals single-ended differential. single-ended interface DDR, differential interface also DDR.
Single-Ended Signaling
variety single-ended standards available Virtex-4 FPGA configuration options. Table lists available single-ended standards. checkmarks indicate which features available configured each standard. Table 2-1: Virtex-4 FPGA Single-Ended Standards
Configurable Attribute Standard VREF Input Threshold Drive Strength Slew Rate Pull-up Pull-down Weak Keeper Recommended Mode Unidirectional Bidirectional
LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVDCI33 LVDCI25 LVDCI18 LVDCI15 HSLVDCI33 HSLVDCI25 HSLVDCI18 HSLVDCI15 HSTL Class HSTL Class HSTL Class HSTL Class HSTL18 Class HSTL18 Class HSTL18 Class
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Single-Ended Signaling
Table 2-1:
Virtex-4 FPGA Single-Ended Standards (Continued)
Configurable Attribute Recommended Mode Weak Keeper Unidirectional Bidirectional VREF Input Threshold
Standard
Drive Strength
Slew Rate
Pull-up
Pull-down
HSTL18 Class HSTL Class HSTL Class HSTL Class HSTL Class HSTL18 Class HSTL18 Class HSTL18 Class HSTL18 Class SSTL2 Class SSTL2 Class SSTL18 Class SSTL18 Class SSTL2 Class SSTL2 Class SSTL18 Class SSTL18 Class GTL+ GTL+ PCI-33 PCI-66 PCI-X
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Chapter SelectIO Signaling
Modes Attributes
Some these standards used only unidirectional mode, while some used bidirectional mode unidirectional mode. Some standards have attributes control drive strength slew rate, well presence weak pull-up pull-down weak-keeper circuits (not intended parallel termination). Drive strength slew rate used tune interface adequate speed while overdriving signals. Weak pull-ups, weak pull-downs, weak keepers used ensure known steady level floating 3-stated signal. Table denotes which standards support these attributes. SelectIO chapter Virtex-4 FPGA User Guide more information. LVCMOS_6F drivers other "weak" drivers have output impedance close allowing them used crude approximation controlled-impedance driver. Note that impedance match weak driver transmission line only approximate varies with voltage temperature. LVDCI, true controlled-impedance driver, adaptive, maintains much closer impedance match, remains constant over voltage temperature.
Input Thresholds
input circuitry single-ended standards listed Table fall into categories: those with fixed input thresholds those with input thresholds VREF voltage. VREF three advantages: allows tighter control input threshold levels removes dependence Ground threshold reference allows input thresholds closer together, which reduces need large voltage swing signal input receiver
2.5V standards that illustrate this LVCMOS25 SSTL2 Class thresholds 2.5V LVCMOS 0.7V 1.7V (necessitating that signal receiver swing full 1.0V minimum make logic transition). thresholds SSTL2 Class VREF 0.15V VREF 0.15V, nominal VREF 1.25V, 1.1V 1.4V (necessitating that signal receiver only swing 0.3V minimum make logic transition). This smaller required swing allows higher frequency operation overall link. smaller swing driver means reduced power required with less transient current. drawback VREF that semi-dedicated VREF pins bank cannot used I/Os they must connected external reference voltage with decoupling capacitor each VREF pin. more information VREF decoupling decoupling other supplies, Chapter "Power Distribution System."
Topologies Termination
Topology generally refers arrangement drivers, receivers, interconnect terminations interface. techniques used unidirectional topologies different from those used bidirectional topologies, these treated separately. SelectIO standards used countless topologies depending requirements system. SelectIO drivers receivers adhering standard (SSTL, LVCMOS, etc.) either used according letter standard (published standards body such EIA/TIA JEDEC) they mixed matched with drivers receivers from another standard hybrid I/O. standard specification might define
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Single-Ended Signaling
something limited receiver, might define every aspect interface, including driver impedance slew rate, trace length topology, value position passive termination, maximum input capacitance receiving device, even maximum number receivers. designer apply standard question system which working. There many decisions make with respect topologies termination, which determine signal integrity interface. utmost importance that signal integrity each interface verified through both simulation measurement. Termination generally refers impedance-matching impedance-compensating devices that used maintain signal integrity interface. While many types elements used terminators (such resistors, capacitors, diodes), this discussion limited resistive termination. general, capacitor diode termination techniques more complicated covered here.
Unidirectional Topologies Termination
basic subsets unidirectional topologies point-to-point multi-drop. point-to-point topology driver receiver, while multi-drop topology driver many receivers. Whether topology point-to-point multi-drop defines important aspects interface that determine which termination strategies appropriate which not.
Unidirectional Point-to-Point Topologies
simplest unidirectional topology point-to-point. That there driver receiver. Termination, present, consist parallel termination receiver (Figure 2-1), series termination driver (Figure 2-2), controlled-impedance driver (Figure Figure 2-4). Always IBIS simulation determine optimal resistor values, voltage level, VRN/VRP reference resistors these terminations.
ug072_c3_01_082904
Figure 2-1:
Parallel-Terminated Unidirectional, Point-to-Point Topology
ug072_c3_02_082904
Figure 2-2:
Series-Terminated Unidirectional, Point-to-Point Topology
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Chapter SelectIO Signaling
LVDCI RVRN RVRP
ug072_c3_03_082904
Figure 2-3:
DCI-Controlled Impedance Driver Unidirectional, Point-to-Point Topology
LVCMOS_6F
ug072_c3_04_082904
Figure 2-4:
"Weak Driver" Unidirectional, Point-to-Point Topology
general, parallel resistive termination (RP) value equal characteristic impedance (Z0) transmission line terminating. Series resistive terminations (RS) have value equal characteristic impedance transmission line (Z0) minus output impedance driver (RO) which they connected. Controlled-impedance drivers tuned such that driver output impedance (RO) equal characteristic impedance (Z0) transmission line terminating. Assuming transmission lines with characteristic impedance driver output impedance (RO) series termination (Figure 2-2) parallel termination (Figure 2-1) appropriate. Controlled-impedance drivers, whether implemented with with weak LVCMOS drivers, should sized have output impedance (RO) This corresponds resistors equal DCI. Weak LVCMOS drivers drive strength have output impedance approximately equal (Figure 2-3). Typically, parallel terminations have best performance when (the voltage source connected parallel termination resistor) equal half signaling voltage. 2.5V signals (VCCO 2.5V), ideally 1.25V. cases where this voltage available, advisable Thevenin parallel termination. Thevenin parallel termination consists voltage divider with parallel equivalent resistance (RPEQ) equal characteristic impedance transmission line most cases). divided voltage point designed VTT. Figure illustrates Thevenin parallel termination powered from 2.5V VCCO, made resistors, resulting 1.25V parallel equivalent resistance (RPEQ) Parallel termination less desirable than series termination controlled-impedance drivers because dissipates more power. This trade-off must weighed against other trade-offs determine optimum termination topology interface.
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Virtex-4 FPGA Designer's Guide UG072 (1.2) June 2008
Single-Ended Signaling
VCCO 2.5V
(100 Parallel Equivalent Resistance RPEQ
VTTEQ 1.25V
(100
ug072_c3_05_082904
Figure 2-5:
Thevenin Parallel Termination
Table lists interface types that used with unidirectional point-to-point topology. Table 2-2: LVTTL LVCMOS LVDCI SSTL Class HSTL Class HSTL Class GTL+ GTLDCI GTL+DCI LVTTL LVCMOS specify canonical termination method. Series termination driver parallel termination receiver both appropriate. LVDCI implicitly uses controlled-impedance driver termination. form termination needed receiver. HSTL Class HSTL Class specify parallel termination receiver. case HSTL Class termination voltage defined half supply voltage VCC. case HSTL Class III, termination voltage defined equal supply voltage VCC. designer elect either termination different termination, such series termination driver. There number reasons this selection might advantageous given system. designer verify through simulation measurement that signal integrity receiver adequate. SSTL Class specifies both series termination driver parallel termination receiver. termination voltage defined half supply voltage VCC. designer elect either termination different termination, such only series termination driver only parallel termination receiver. There number reasons this might advantageous given system. Interface Type Unidirectional Point-to-Point Topologies
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Chapter SelectIO Signaling
designer verify through simulation measurement that signal integrity receiver adequate. GTL+ specify require parallel termination both driver receiver. designer elect omit either these terminations because driver open drain, meaning that driver capable driving High signal depends parallel termination generate High logic levels.
Unidirectional Multi-Drop Topologies
more complex topologies, single driver drive multiple receivers. receivers represent loads that must individual transmission line stubs. From signal integrity standpoint, best topology this case single long transmission line with driver parallel termination other, with receivers connected main trace short stubs between. This type topology often referred flyby multi-drop topology. There critical aspects this topology. first presence parallel termination transmission line. Series termination driver must never used. Parallel termination only applicable termination type this topology. second critical aspect length connecting stubs each receiver. These must remain short: more than length. stubs become longer, they present larger impedance discontinuity signal travelling down transmission line, support significant reflections. These impedance discontinuities corrupt signal. With increasing numbers loads increasing length stubs, signal corrupted point where longer usable. Star topologies recommended. constraints involved designing star topology with good signal integrity beyond scope this document. stated "Unidirectional Point-to-Point Topologies", ideal parallel resistive termination value equal characteristic impedance transmission line terminating. best performance achieved when equal half signaling voltage, when this voltage available, Thevenin parallel termination recommended, defined previous subsection. Figure illustrates Thevenin parallel termination powered from VCCO, made resistors, resulting VCCO/2 parallel equivalent resistance This figure shows topology with driver LVCMOS driver) four receivers. driver left side, receivers spaced interim points across transmission line, Thevenin parallel termination resistors right side.
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Single-Ended Signaling
Output
length
Input Main Transmission Line
length length
main transmission line should kept short possible. Lengths inches more practical most standards long precise trace impedance maintained crosstalk sources avoided. lengths interim segments main transmission line need equal. Their relative lengths arbitrary. Receivers different points along main transmission line receive signal with varying amounts delay, signal rise times similar. Stubs stretching from main transmission line individual receivers must kept short possible. longer these stubs become, more corrupted received waveforms are. Simulation measurement required assess signal integrity individual receivers. Table lists interface types that used with unidirectional point-to-point multi-drop topology. Table 2-3: LVTTL LVCMOS LVTTL LVCMOS specify canonical termination method. Parallel termination long t-line only appropriate termination method. Interface Types Multi-Drop Point-to-Point Topologies
Bidirectional Topology Termination
basic subsets bidirectional topologies point-to-point multi-point. point-to-point topology transceivers (driver receiver sharing device pin), while multi-point topology have many transceivers. Whether topology point-to-point multi-point defines important aspects interface that determine which termination strategies appropriate which not.
Bidirectional Point-to-Point Topologies
simplest bidirectional topology point point. That there transceivers connected transmission line. Because bidirectional interfaces need operate equally well both directions, symmetry topology desirable. While asymmetrical topologies designed with reasonably good signal integrity, easiest ensure
Virtex-4 FPGA Designer's Guide UG072 (1.2) June 2008
VCCO (100
Input
Input
Input
(100
ug072_c3_06_082904
Figure 2-6:
Basic Multi-Drop Topology
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Chapter SelectIO Signaling
good signal integrity keep topology symmetrical. Thus termination used side link should also used other side link. Series termination (Figure 2-8) rarely appropriate bidirectional interfaces incoming signals attenuated series resistor receiving transceiver. Parallel termination (Figure 2-7) always achieves better signal levels both receivers. Controlled-impedance drivers, whether crudely controlled form weak LVCMOS driver adaptively controlled form LVDCI HSLVDCI, also have good results shown Figure 2-9, Figure 2-10, Figure 2-11 (implemented with low-drive strength LVCMOS driver). Always IBIS simulation determine optimal resistor, voltage level VRN/VRP reference resistor values these terminations.
ug072_c3_07_082904
Figure 2-7:
Parallel Terminated Bidirectional Point-to-Point Topology
ug072_c3_08_082904
Figure 2-8:
Series Terminated Bidirectional Point-to-Point Topology: Recommended
RVRN RVRP LVDCI RVRN RVRP LVDCI
ug072_c3_09_082904
Figure 2-9:
Controlled Impedance Bidirectional Point-to-Point Topology
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Single-Ended Signaling
RVRN RVRP HSLVDCI VREF RVRN RVRP HSLVDCI
VREF
ug072_c3_10_082904
Figure 2-10:
HSLVDCI Controlled Impedance Driver Bidirectional Point-to-Point Topology
LVCMOS_6F LVCMOS_6F
ug072_c3_11_082904
Figure 2-11:
"Weak Driver" Bidirectional Point-to-Point Topology
general, parallel resistive termination (RP) value equal characteristic impedance transmission line terminating. Controlled-impedance drivers tuned such that driver output impedance (RO) equal characteristic impedance (Z0) transmission line terminating. Assuming transmission lines with characteristic impedance driver output impedance parallel terminations appropriate (Figure 2-7). Controlledimpedance drivers, whether implemented with with weak LVCMOS drivers, should sized have output impedance (RO) This corresponds resistors equal (Figure Figure 2-10). Weak LVCMOS drivers drive strength have output impedance approximately equal (Figure 2-11). Typically, parallel terminations have best performance when (the voltage source connected parallel termination resistor) equal half signaling voltage. 2.5V signals (VCCO 2.5V), ideally 1.25V. cases where this voltage available, advisable Thevenin parallel termination. Thevenin parallel termination consists voltage divider with parallel resistance equal characteristic impedance transmission line most cases). divided voltage point designed VTT. Figure 2-12 illustrates Thevenin parallel termination powered from 2.5V VCCO, made resistors, resulting 1.25V parallel equivalent resistance (RPEQ) Parallel termination less desirable than series termination controlled-impedance drivers because dissipates more power. This trade-off must weighed against other trade-offs determine optimum termination topology interface.
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Chapter SelectIO Signaling
VCCO 2.5V
VCCO 2.5V
(100 (100 VTTEQ 1.25V
(100
(100
ug072_c3_12_082904
Figure 2-12:
Thevenin Parallel Termination (Bidirectional Point-to-Point Topology)
Table lists interface types that used with bidirectional point-to-point topology. Table 2-4: LVTTL LVCMOS LVDCI HSLVDCI SSTL CLASS SSTL CLASS HSTL CLASS HSTL CLASS HSTL CLASS HSTL CLASS GTL+ LVTTL LVCMOS specify canonical termination method. Series termination recommended bidirectional interfaces. Parallel termination weak drivers, however, both appropriate. LVDCI HSLVDCI both implicitly controlled-impedance driver termination. HSTL Class HSTL Class specify parallel termination both transceivers. case HSTL Class termination voltage defined half supply voltage VCCO. case HSTL Class termination voltage defined equal supply voltage VCCO. designer elect either termination different termination. designer verify through simulation measurement that signal integrity receiver adequate. Interface Types Bidirectional Point-to-Point Topologies
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Single-Ended Signaling
SSTL Class specifies both series termination parallel termination. termination voltage defined half supply voltage VCCO. While canonical standard calls this, better performance achieved when only parallel termination used both transceivers. designer elect either canonical standard termination modified termination termination all). designer verify through simulation measurement that signal integrity receiver adequate. GTL+ specify require parallel termination both transceivers. designer elect omit either these terminations because driver open drain, meaning that driver capable driving High signal depends parallel termination generate High logic levels.
Bidirectional Multi-Point Topologies
more complex topologies, transceiver multi-point transmit other transceivers. Usually these topologies only very slow clock rates because they only support very slow signal rise times ns). While useful some situations, drawbacks usually outweigh benefits. constraints involved designing these topologies with good signal integrity beyond scope this document.
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Chapter
Multi-Gigabit Serial Signaling
This chapter intentionally left blank further updates.
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Chapter Multi-Gigabit Serial Signaling
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Virtex-4 FPGA Designer's Guide UG072 (1.2) June 2008
Chapter
Power Distribution System
This chapter covers power distribution system Virtex-4 FPGAs, including details decoupling capacitor selection, voltage regulators geometries. This chapter contains following sections: "Power Distribution Design Overview" "Basic Decoupling Network Principles" "PDS Design Verification" "Other Concerns Causes" "Calculation Inductance" "SPICE Simulation Examples" "EDA Tools Design Simulation"
Power Distribution Design Overview
FPGA designers faced with unique task when comes designing power distribution systems (PDS). Most other large, dense (such large microprocessors) come with very specific bypass capacitor requirements. Since these devices only designed implement specific tasks their hard silicon, their power supply demands fixed only fluctuate within certain range. FPGAs share this property. Since FPGAs implement practically infinite number applications undetermined frequencies multiple clock domains, very complicated predict what their transient current demands will Since exact transient current behavior cannot known FPGA design, only choice when designing first version FPGA with conservative worstcase design. Transient current demands digital devices cause ground bounce, bane high-speed digital designs. low-noise high-power situations, power supply decoupling network must tailored very closely these transient current needs, otherwise ground bounce power supply noise will exceed limits device. transient currents FPGA different from design design. This chapter provides comprehensive method designing bypassing network suit individual needs specific FPGA design. first step this process examine utilization FPGA rough idea transient current requirements. Next, conservative decoupling network designed these requirements. third step refine network through simulation modification capacitor numbers values. fourth step, full design built fifth step measured. Measurements made consisting oscilloscope possibly spectrum analyzer readings power supply noise. Depending measured
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Chapter Power Distribution System
results, further iterations through part selection simulation steps could necessary optimize specific application. sixth optional step also given cases where perfectly optimized needed.
Basic Decoupling Network Principles
Before starting into design flow, important understand basic electrical principles involved. This section discusses purpose properties components. also describes important aspects discrete capacitor placement mounting well geometry stackup recommendations. Each device system only wattage requirements operation, also requirement cleanliness that power. Most digital devices, including Virtex-4 FPGAs, have requirement that supplies, must fluctuate more than above below nominal value. this document used generically refer FPGA power supplies: VCCINT, VCCO, VCCAUX, VREF. Multigigabit transceiver (MGT) system monitor analog supplies (AVCCAUXTX, AVCCAUXRX, VTTX, VTRX, AVDD, AVSS) covered here. specific instructions these supplies, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (Reference Virtex-4 FPGA User Guide (Reference #2). This requirement specifies maximum amount noise present power supply, often referred "ripple voltage." device requirements state that must within nominal voltage, that means peak peak voltage ripple must more than nominal VCC. This assumes that nominal exactly nominal value given data sheet. this case, then VRIPPLE must adjusted value correspondingly less than 10%. power consumed digital device varies over time, this variance occurs frequency scales. frequency variance power consumption usually result devices large portions devices being enabled disabled. This occur time scales from milliseconds days. High frequency variance power consumption result individual switching events inside device, this happens scale clock frequency first harmonics clock frequency. Since voltage level device fixed, changing power demands manifested changing current demand. must accommodate these variances current draw with little change power supply voltage possible. When current draw device changes, power distribution system cannot respond that change instantaneously. short time before responds, voltage device changes. This where power supply noise appears. There main causes this corresponding major components PDS. first major component voltage regulator. observes output voltage adjusts amount current being supplied keep voltage constant. Most common voltage regulators make this adjustment order milliseconds microseconds. They effective maintaining output voltage events frequencies from hundred kilohertz (depending regulator). transient events that occur frequencies above this range, there time before voltage regulator respond level demand. example, current demand device increases matter nanoseconds, voltage device sags some amount until voltage regulator adjust new, higher level current must provide. This might take from microseconds milliseconds, during which time voltage sags. second major component bypass decoupling capacitors. this document, words "bypass" "decoupling" used interchangeably. Their function
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Basic Decoupling Network Principles
local energy storage device. They cannot provide power, only small amount energy stored them (the voltage regulator present provide power). function this local energy storage respond very quickly changing current demands. capacitors effective maintaining power supply voltage frequencies from hundreds kilohertz hundreds megahertz milliseconds nanoseconds range. Decoupling capacitors events occurring above below this range. example, current demand device increases picoseconds, voltage device sags some amount until capacitors supply extra charge device. current demand device changes maintains this level number milliseconds, voltage regulator circuit, operating parallel with bypass capacitors, effectively takes over them, changing output supply this current. Figure shows major components PDS: power supply, decoupling capacitors, active device being powered this case, FPGA).
FPGA
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Figure 4-1:
Simplified Circuit
Figure shows further simplified circuit, showing reactive components decomposed frequency-dependent resistor.
ltransient VRIPPLE
FPGA
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Figure 4-2:
Further Simplified Circuit
What Role Inductance?
There property capacitors current paths that retards changes current flow. This reason capacitors cannot respond instantaneously transient currents, changes that occur frequencies higher than their effective range. This property called inductance. Inductance thought momentum charge. Where charge moving some rate through conductor, this implies some amount current. level current change, charge must move different rate. Because there momentum (stored magnetic field energy) associated with this charge, takes some amount time charge slow down speed greater inductance, greater resistance change, longer takes current level change.
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Chapter Power Distribution System
purpose accommodate whatever current demands device(s) could have, respond changes that demand quickly possible. When these demands met, voltage across device's power supply changes. This observed noise. Since inductance retards abilities bypass capacitors quickly respond changing current demands, should minimized. Figure shows inductances between FPGA device capacitors, between capacitors voltage regulator. These inductances arise parasitics capacitors themselves current paths PCB. important that each these minimized.
Capacitor Parasitic Inductance
capacitor's various properties, capacitance value often considered most important. However domain design, property parasitic inductance (ESL Equivalent Series Inductance) same greater importance. factor that influences parasitic inductance more than other dimensions package. Very simply, physically small capacitors tend have lower parasitic inductance than physically large capacitors. Just short wire less inductance than long wire, short capacitor less inductance than long capacitor. Likewise, wide wire less inductance than narrow wire, does capacitor have less inductance than narrow capacitor. these reasons, when choosing decoupling capacitors, smallest package should chosen given value. Similarly, given package size (essentially fixed inductance value), highest capacitance value available that package should chosen. Surface-mount chip capacitors smallest capacitors available, making them good choice discrete bypass capacitors. values from down very small values such 0.001 type capacitors usually used. These have parasitic inductance, acceptable temperature characteristic. larger values, such 1000 tantalum capacitors used. These have parasitic inductance relatively high equivalent series resistance (ESR), giving them low-quality factor consequently very wide range effective frequencies. They also provide comparatively high capacitance value small package size, thus reducing board real-estate costs. cases where tantalum capacitors available, low-inductance electrolytic capacitors used. Other technologies with similar characteristics also available. real capacitor characteristics only capacitance also inductance resistance. Figure shows parasitic model real capacitor. real capacitor should treated circuit.
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Figure 4-3:
Parasitics Real, Non-Ideal Capacitor
Figure shows impedance characteristic real capacitor. Overlaid this plot curves corresponding capacitor's capacitance parasitic inductance (ESL).
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Basic Decoupling Network Principles
These curves combine form total impedance characteristic circuit formed parasitics capacitor.
Total Impedance Characteristic
Inductive Contribution (ESL)
Impedance
Capacitive Contribution
Frequency
Figure 4-4:
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Contribution Parasitics Total Impedance Characteristics
capacitive value increased, capacitive curve moves down left. parasitic inductance decreased, inductive curve moves down right. Since parasitic inductance capacitors given package essentially fixed, inductance curve remains fixed. different capacitor values selected that same package, capacitive curve moves down relative fixed inductance curve. only decrease total impedance capacitor package fixed increase value capacitor. only move parasitic inductance curve down (and consequently lower total impedance characteristic), connect additional capacitors parallel.
Inductance from Current Paths
parasitic inductance current paths have distinct sources: capacitor mounting, power ground planes PCB.
Mounting Inductance
this context, mounting refers capacitor's solder land PCB, trace any) between land via, itself. vias, traces, pads capacitor mounting contribute anywhere from inductance depending specific geometry. Since inductance current path proportional area loop current traverses, important minimize size this loop. loop consists path through power plane, through via, through connecting trace land, through capacitor, through other
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Chapter Power Distribution System
land connecting trace, down through other via, into other plane, shown Figure 4-5.
0402 Capacitor Body Surface Trace
Solderable Terminal Capacitor Solder Land
Power Ground planes
Mounted Capacitor Current Loop
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Figure 4-5:
Cutaway View with Capacitor Mounting
shortening connecting traces, area this loop minimized inductance reduced. Similarly, reducing length through which current flows, loop area minimized inductance reduced.
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Basic Decoupling Network Principles
0402 Land Pattern, vias, long traces,
0402 Land Pattern, vias, 0.8nH
0402 Land Pattern, side vias, 0.6nH 0402 Land Pattern, double side vias, 0.4nH
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Figure 4-6: Example Capacitor Land Mounting Geometries existence and/or length connecting trace impact parasitic inductance mounting. Wherever possible, there should connecting trace (Figure 4-6a) should butt against land itself (Figure 4-6b). Additionally, connecting trace should made wide possible. Further improvements made mounting placing vias side capacitor lands (Figure 4-6c), doubling number vias (Figure 4-6d). Currently, very manufacturing processes allow via-in-pad geometries, this another good option. technique using multiple vias land important when using ultra-low inductance capacitors, such reverse aspect ratio capacitors (AVX's LICC). Many times effort squeeze more parts into small area, layout engineers share vias among multiple capacitors. This technique should used under circumstances. capacitor mounting (lands, traces, vias) typically contributes about same amount more inductance than capacitor's parasitic inductance. second capacitor connected into vias existing capacitor, only improves very small amount. better reduce total number capacitors maintain one-to-one ratio lands vias.
Plane Inductance
power ground planes have some amount inductance associated with them. geometry these planes determines their inductance. Since power ground planes definition planar structure, current does just flow through them direction. tends spread travels from point another, accordance with property similar skin effect. this reason, inductance planes described "spreading inductance," specified units henries square. square dimensionless, shape section plane, size, that determines inductance. Spreading inductance acts like other inductance resist changes amount current conductor. this case, conductor power plane planes. This
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Chapter Power Distribution System
quantity should reduced much possible, since retards ability capacitors respond transient currents device. Since shape plane typically something designer little control over, only controllable factor spreading inductance value. This primarily determined thickness dielectric separating power plane from associated ground plane. high-frequency power distribution systems type discussed here, power ground planes work pairs. Their inductances exist independently each other. spacing (and dielectric constant material) between power ground planes determines spreading inductance pair. closer spacing (the thinner dielectric), lower spreading inductance. Table gives approximate values spreading inductance different thicknesses dielectric (Reference #3). Table 4-1: Capacitance Spreading Inductance Values Various Thicknesses Power-Ground Plane Sandwiches Dielectric Thickness (mil, microns) Inductance (pH/square) Capacitance (pF/in2, pF/cm2) 225, 450, 900,
Since closer spacing results decreased spreading inductance, best, wherever possible, place planes directly adjacent planes stackup. Facing planes sometimes referred "sandwiches." While sandwiches necessary past previous technologies, speeds involved sheer amount power required fast, dense devices demands Besides offering low-inductance current path, power-ground sandwiches also offer some high-frequency decoupling capacitance. plane area increases separation between power ground planes decreases, value this capacitance increases. same time, since parasitic inductance this capacitance decreasing, effective frequency band center frequency increases. Capacitance square inch also given Table 4-1. This capacitance alone usually enough give power-ground sandwiches compelling advantage. However, when viewed bonus spreading inductance, advantage most designers gladly take.
Stackup Layer Order
placement Ground planes stackup (determined layer order) significant impact parasitic inductances power current paths. this reason, designers need consider layer order early stages design cycle, putting high-priority supplies half stackup low-priority supplies bottom half stackup. Power supplies with high transient current should have their associated planes close surface (FPGA side) stackup decrease distance vertical direction that currents travel through vias before reaching associated planes. mentioned previous section, every plane should have plane adjacent stackup reduce spreading inductance. Since highfrequency currents couple tightly skin effect, plane adjacent given
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Basic Decoupling Network Principles
plane tends carry majority current complementary that plane. this reason, adjacent planes considered pair. plane pairs reside half stackup, because manufacturing constraints typically require stackup symmetrical about center with respect dielectric thicknesses etched copper areas. designer must determine which plane pairs have high priority carry highfrequency energy, which pairs have priority carry lower frequency energy.
Capacitor Effective Frequency
Every capacitor narrow frequency band where most effective decoupling capacitor. Outside this band, does have some contribution general much smaller. frequency bands some capacitors wider than others. capacitor determines quality factor capacitor, which determines width effective frequency band. Tantalum capacitors generally have very wide effective band, while chip capacitors, with their lower ESR, generally have very narrow effective band. effective frequency band corresponds capacitor's resonant frequency. While ideal capacitor only capacitive characteristic, real non-ideal capacitors also have parasitic inductance parasitic resistance ESR. These parasitics series form circuit (Figure 4-3). resonant frequency associated with that circuit resonant frequency capacitor. determine resonant frequency circuit, Equation used: Equation Alternatively, frequency sweep SPICE simulation circuit could performed, frequency where minimum impedance value occurs would resonant frequency. important distinguish between capacitor's self-resonant frequency effective resonant frequency mounted capacitor when part system. This simply difference between taking into account only capacitor's parasitic inductance, taking into account parasitic inductance well that vias, planes, connecting traces lying between FPGA. self-resonant frequency capacitor FRSELF (the value reported capacitor data sheet), considerably higher than effective mounted resonant frequency system, FRIS. Since mounted capacitor's performance what important, mounted resonant frequency that used when evaluating capacitor part larger PDS. main contributors mounted parasitic inductance capacitor's parasitic inductance, inductance lands connecting traces, inductance vias, power plane inductance. Vias traverse full board stackup their device when capacitors mounted underside board. These vias contribute something range 1,500 board with finished thickness mils; vias thicker boards have higher inductance. Because there these paths series with each capacitor, twice this value should added capacitor's parasitic inductance. This quantity, parasitic inductance capacitor mounting, designated LMOUNT. determine total parasitic inductance capacitor in-system, LIS, capacitor's parasitic inductance LSELF added parasitic inductance mounting, LMOUNT: LSELF LMOUNT
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Chapter Power Distribution System
Example
Ceramic Chip capacitor (AVX capacitor data used here) 0.01 LSELF FRSELF LMOUNT determine effective in-system parasitic inductance (LIS), parasitics: LSELF LMOUNT Plugging values from example:
FRIS: Mounted Capacitor Resonant Frequency: Since decoupling capacitor only effective narrow band frequencies around resonant frequency, important that resonant frequency taken into account when choosing collection capacitors build decoupling network.
Capacitor Anti-Resonance
common problem associated with capacitors FPGA anti-resonant spikes aggregate impedance. These spikes caused combinations energy storage devices (such discrete capacitors, parasitic inductances, power ground planes). inter-plane capacitance power ground planes especially with high-quality factor, crossover point between highfrequency discrete capacitors this plane capacitance might exhibit high-impedance anti-resonance peak. FPGA high transient current demand this frequency (acting stimulus), large noise voltage results. improved only bringing down impedance anti-resonant spike. mitigate this problem, either characteristics high-frequency discrete capacitors characteristics Ground planes must changed.
Capacitor Placement
Capacitors need close device perform decoupling function. There basic reasons this requirement. First, increased spacing between device decoupling capacitor increases distance travelled current power ground planes, hence, inductance current path between device capacitor. Since inductance this path (the loop followed current goes from side capacitor pin[s] FPGA, from pin[s] FPGA side capacitor[s]), proportional loop area, decreasing inductance matter decreasing loop area. Shortening distance between device decoupling capacitor(s) reduces inductance resulting less impeded transient current flow.
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Basic Decoupling Network Principles
Because dimensions PCBs, this reason tends less important with regard placement than second reason. second reason deals with phase relationship between FPGA noise source mounted capacitor. Their phase relationship determines capacitor's effectiveness. capacitor effective providing transient current certain frequency (for instance, optimum frequency that capacitor), must within fraction wavelength associated with that frequency. placement capacitor determines length transmission line interconnect this case, power ground plane pair) between capacitor FPGA. propagation delay this interconnect relevant factor. Noise from FPGA falls into certain frequency bands, different sizes decoupling capacitors take care different frequency bands. this reason, capacitor placement determined based effective frequency each capacitor. When FPGA initiates change current demand, causes small local disturbance voltage point power ground planes). decoupling capacitor counteract this, capacitor first voltage difference. There finite time delay between start disturbance FPGA power pins start capacitor's view disturbance. This time delay equal distance from FPGA power pins capacitor, divided propagation speed current through dielectric (the substrate where power planes embedded). There another delay same duration compensation current from capacitor reach FPGA. Therefore, transient current demand FPGA, there round-trip delay capacitor before relief seen FPGA. placement distances greater than quarter wavelength some frequency, energy transferred FPGA negligible. decreasing distances less than quarter wavelength, energy transferred FPGA increases 100% zero distance. Efficient energy transfer from capacitor FPGA requires placement capacitor fraction quarter wavelength FPGA power pins. This fraction should small because capacitor also effective frequencies slightly above resonant frequency, where corresponding wavelength shorter. practical applications, tenth quarter wavelength good target. This leads placing capacitor within fortieth wavelength power pins decoupling. wavelength corresponds FRIS, capacitor's mounted resonant frequency.
Example
0.001 Ceramic Chip capacitor, 0402 package 125.8MHz 0.001 Equation calculates TRIS, mounted period resonance, from FRIS. 7.95 125.8 Equation
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Chapter Power Distribution System
Equation computes wavelength based TRIS propagation velocity dielectric. Wavelength PROP
Equation
where PROP
-inch
7.95 47.9inches PROP
PLACE 47.9 inches PLACE 1.20 inches
Equation
this example, effective frequency, equal resonant frequency, determined Equation This effective frequency determined 125.8 MHz. reciprocal this taken give resonant period, 7.95 using Equation Using propagation speed current (approximately inch), wavelength associated with this capacitor computed approximately inches using Equation computed Equation fortieth this inches. Therefore target placement radius (RPLACE) capacitors this size within inches (3.0 power ground pins they decoupling. other capacitor sizes follow same manner. radius inches terribly difficult achieve current technology. does require placing capacitors directly underneath device opposite side PCB. acceptable capacitors mounted around periphery device, provided target radius maintained. 0.001 capacitors among smallest decoupling network, placement radii less than inch unnecessary. larger capacitors, target placement radius expands quickly resonant frequency goes down. capacitor, example, placed anywhere board, target radius inches much bigger than most PCBs (corresponding resonant frequency 1.56 MHz).
Example Capacitor Layout
Figure example bottom-side artwork showing capacitor layout. Black fill hatch represents plated copper, represents vias, blue represents silkscreen labels, purple represents package outlines. FPGA footprint seen regular array dots upper portion figure center. absence vias cross pattern center device indicates that solder lands surface their associated vias escape toward corners.
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Basic Decoupling Network Principles
package outline
silkscreen label
plated copper
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Figure 4-7: Example Layout Showing Capacitor Placement Bottom Surface this example, many high-frequency 0402 decoupling capacitors placed within footprint FPGA opposite side board (C150, C117). There also handful 0603 decoupling capacitors termination resistors (C307, R274). Larger capacitors placed outside footprint FPGA, moving farther away from FPGA with increasing size (C247, C288). Traces connecting capacitor lands vias kept short possible. Also largepackage capacitors with large separation between solder lands (C42, C224), vias inserted between solder lands reduce parasitic inductance mounting. necessary place high-frequency capacitors within footprint FPGA. perfectly acceptable place capacitors around periphery device, provided planes have Ground plane adjacent them, separated dielectric less than mils thickness. Also, cases where Ground plane pairs half stackup (closer device), advantageous place capacitors surface board, around periphery device. cases where large numbers external termination resistors used, placement termination resistors takes priority over decoupling capacitors. Moving away from device concentric rings, termination resistors should closest device, followed smallest-value decoupling capacitors, then followed larger-value decoupling capacitors.
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Chapter Power Distribution System
Design Verification
Having discussed basic operating principles power distribution systems, this section introduces step-by-step process designing verifying PDS.
Step Determining Critical Parameters FPGA
designing first iteration decoupling capacitor network, basic objective have capacitor used device. Therefore, effective number pins each supply must determined. Very designs 100% various resources FPGA. FPGA package inside very carefully sized meet needs fully utilized without being overly conservative. number pins package given device determined based needs 100% utilized FPGA. determining factor power handling abilities transient current impedance. Decoupling capacitor requirements track very closely since they based same factor. this reason, number pins each supply used indicator number capacitors needed that supply. supplies must considered: VCCINT, VCCAUX, VCCO, VREF. only necessary provide capacitor pins used. There need decouple VREF pins they used VREF. Conversely, VCCAUX VCCINT pins must always fully decoupled, i.e., they must always have capacitor pin. VCCO pro-rated according utilization.
Step Designing Generic Bypassing Network
number Xilinx test boards customer designs were analyzed discern some trends successful designs. 100% utilized designs with power supply noise order half maximum allowed power supply noise (VRIPPLE/2), generally approximately capacitor per-supply basis. generic bypassing network designed with this range capacitors mind. pro-rated number VCCO pins used. Given number discrete capacitors needed determined above, distribution capacitor values adding that total number must determined. cover broad range frequencies, broad range capacitor values must used. proportion high-frequency capacitors low-frequency capacitors important factor. objective parallel combination number values capacitors keep flat power supply impedance over frequencies from range range. Both large value (low frequency) small value (high frequency) capacitors needed. Small value capacitors tend have less impact total impedance profile, greater number small value capacitors needed yield same impedance level impact small number large value capacitors. keep impedance profile smooth free anti-resonance spikes, capacitor generally needed least every decade capacitor value range. typical ceramic capacitor range generally spans values from 0.001 exact value these capacitors critical. What critical having some capacitor value every order magnitude over this range. More values better, flatter impedance profile yielded. ratio capacitors giving relatively flat impedance where quantity capacitors roughly doubled every decade decrease size. other words,
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Design Verification
bottom three values network were 0.01 network might have capacitor, four capacitors, eight 0.01 capacitors. addition, low-frequency capacitance form tantalum, OS-CON, electrolytic capacitors needed. These large capacitors typically have higher than ceramic chip capacitors, making them effective over wider range frequencies. This also makes capacitors less likely contribute anti-resonance spikes. this reason, necessary maintain rule value decade. Generally, value 1000 range sufficient. percentages helpful calculating these ratios based total number capacitors. Table Table give these percentages classes supplies: VCCINT, VCCAUX, VCCO, VREF. Table 4-2: Capacitor Value Ratios Balanced Decoupling Network (VCCINT, VCCAUX, VCCO) Capacitor Value 1000 0.47 0.01 0.047 Quantity Percentage Capacitor Type Tantalum 0805 0603 0402
Table 4-3:
Capacitor Value Ratios Balanced Decoupling Network (VREF) Quantity Percentage Capacitor Type 0603 0402
Capacitor Value 0.47 0.01 0.047
every power supply except VREF, these ratios should roughly maintained. VREF supplies, values should distributed 50/50 ratio 0.47 capacitors 0.01 0.047 capacitors. Since primary function VREF decoupling capacitors reduce impedance VREF nodes thus reducing crosstalk coupling, very little low-frequency energy needed. Therefore, only capacitors 0.01 0.47 range necessary.
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Chapter Power Distribution System
Step Simulation
During simulation, generic decoupling network verified some cases refined. designer experiment with different values capacitors different packages achieve optimum power supply impedance profile constraints system. number levels design tools available from various vendors listed "EDA Tools Design Simulation," page simulation circuit essentially parallel combination decoupling capacitors with associated parasitics. simulator calculates aggregate impedance over pertinent range frequencies. equivalent circuit created analyzed SPICE (see "SPICE Simulation Examples," page example SPICE deck) tools listed "EDA Tools Design Simulation." more limited still effective approach plot impedance profile spreadsheet tool (for example, Microsoft Excel). Note that lumped simulation this type does reflect distributed properties Ground planes stackup. effects these planar structures usually begin manifest range, dependent geometries planes (for example, length width). These difficult predict without distributed model, such what offered tool like Speed2000, SIwave, Specctraquest Power Integrity, full-mesh SPICE simulation. this reason, unwise draw conclusions from results lumped simulation above MHz. using these tools simulate bypassing network, important have accurate parasitic values. Obtaining accurate self-parasitic data from capacitor vendor from in-house testing important. mounting parasitics lying path between bypass capacitor FPGA also need taken into account. These parasitics combined series give mounted capacitor parasitic resistance inductance. section "Mounting Inductance," page covers details mounting modeling. "Calculation Inductance," page lists equations parasitic inductance. more accurate inductance number particular geometry obtained using field solver such Ansoft's HFSS. following simulation, value mounting inductance added each capacitor's parasitic self-inductance come with LIS. This parameter reflects inductance small capacitor mountings board order mils thick. Thicker board stackups have higher associated inductance. Figure shows simple impedance plot from simulation parallel combination these capacitors, taking into account their parasitics approximate parasitics PCB. equivalent SPICE netlist included "SPICE Simulation Examples," page Table lists capacitor quantities, values, parasitic values used simulation. characteristics planes taken into account.
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Design Verification
Four Values Parallel Capacitors [ohms]
1.E+00
Impedance (ohms)
1.E-01
1.E-02
1.E-03 1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
Frequency [MHz]
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Figure 4-8:
Impedance Versus Frequency Plot
Table 4-4: Quantity
Values Used Impedance Plot Figure Symbol Package 0805 0603 0402 Capacitive Values 0.22 0.022 Parasitic Inductance (nH) Parasitic Resistance (ohms) 0.57 0.02 0.06 0.20
This collection capacitors good start. impedance below 0.033 from MHz, increases 0.11 MHz. Over this range there significant anti-resonance spikes. These capacitors used board design.
Step Building Design
this stage, laid with final capacitor networks verified simulation. board built. earlier sections capacitor placement land geometries detailed layout information.
Step Measuring Performance
performance measurement step, measurements made determine whether adequate devices serving. Determining whether bypassing network adequate given design relatively simple. measurement performed
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Chapter Power Distribution System
with high-bandwidth oscilloscope oscilloscope probe minimum), design running realistic test patterns.
Noise Magnitude Measurement
measurement taken either directly power pins device, across pair unused I/O, driven High driven Low. VCCINT VCCAUX only measured backside vias. VCCO also measured this way, more accurate results obtained measuring fixed signals unused I/Os same bank. When making noise measurement back-side board, necessary take into account parasitics vias path between measuring point FPGA, voltage drop occurring this path accounted oscilloscope measurement. Backside measurements also have potential pitfall. Many times, decoupling capacitors mounted directly underneath device, meaning that capacitor lands connect these vias directly with surface traces. These capacitors confound measurement, they like short circuit highfrequency current. make sure such capacitors short measurement, capacitors measurement site must removed. When measuring VCCO noise, measurement taken pair pins configured strong drivers logic logic This technique, when performed correctly, also show die-level noise. Measuring driven logic against driven logic shows degree rail collapse die. Measuring driven logic against ground shows amount ground bounce experiencing relative PDS. Since grounds common package levels device (excepting AGND MGTs, VREFN AVSS system monitor, ADCs), ground bounce measurement taken unused shows ground bounce supplies. Rail collapse measurements, other hand, only apply VCCO. make these measurements, oscilloscope should infinite persistence mode, acquire noise over long time period (many seconds minutes). design operates number different modes, utilizing different resources different amounts, these various conditions modes should operation while oscilloscope acquiring noise measurement. Noise measurements should made different VCC/GND pairs FPGA eliminate effects local noise phenomena. Figure shows instantaneous noise measurement taken VCCINT pins sample design. Figure 4-10 shows infinite persistence noise measurement same design. Since infinite persistence measurement catches noise events over long period, obviously yields more relevant results.
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Design Verification
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Figure 4-9: Instantaneous Measurement VCCO Supply, with Multiple Sending Patterns
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Figure 4-10:
Infinite Persistence Measurement Same Supply
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Chapter Power Distribution System
This measurement represents peak-to-peak noise. greater than equal maximum ripple voltage specified data sheet (10% VCC), then bypassing network adequate. maximum voltage ripple allowed this particular supply, with nominal value 1.5V this, 150mV. scope shots show noise range From this measurement, clear that decoupling network adequate. however, measurement showed noise greater than VCC, would inadequate. have working, robust design, changes should made PDS. greater number capacitors, different capacitance values, different numbers various decoupling capacitor values will bring noise down. Having necessary information improve decoupling network requires additional measurements. Specifically, measurement noise power spectrum necessary determine frequencies where noise resides. There many ways this. spectrum analyzer works well does oscilloscope with math functionality. Alternatively, long sequence time-domain data captured from oscilloscope converted frequency domain using MATLAB other software supporting FFT. also possible basic feel frequency content noise simply looking time-domain waveform measuring individual periodicities present noise.
Noise Spectrum Measurements
spectrum analyzer frequency-domain instrument. shows frequency content voltage signal inputs. When used measure inadequate PDS, user exact frequencies where inadequate. Excessive noise certain frequency indicates frequency where impedance high transient current demands device. Armed with this information, designer modify accommodate transient current specific frequency. This accomplished either adding capacitors with resonant frequencies close frequency noise lowering impedance critical frequency through other means. noise spectrum measurement should taken same place peak-to-peak noise measurement directly underneath device, pair unused driven High Low. spectrum analyzer takes measurements through cable, rather than through active probe like oscilloscope. best ways attach cable measurements through connector tapped into power ground planes vicinity device. most cases this available. Another attach cable measurement noise power planes remove decoupling capacitor vicinity device, solder center conductor shield cable directly capacitor lands. Alternatively, probe station used. most cases, distinct bands noise fixed frequencies seen. These correspond clock frequency harmonics. height each band represents relative power. majority energy usually contained tight bands around harmonics, with power falling frequency increases.
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Design Verification
Figure 4-11 shows example noise spectrum measurement. screenshot spectrum analyzer measurement power supply noise VCCO, with multiple sending patterns MHz.
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Figure 4-11:
Screenshot Spectrum Analyzer Measurement VCCO
noise bands correspond frequencies where FPGA demand current receiving from PDS. This could because there enough capacitance, because there enough capacitance parasitic inductance path separating capacitors from FPGA great. Whatever cause, impedance power supply this frequency high. Conversely, frequencies where there very little noise, impedance lower than needs solve these problems, bypassing network must modified. capacitor values, different quantities original values should chosen.
Step Optimum Bypassing Network Design (Optional)
cases where highly optimized needed, further measurements taken guide design carefully tailored decoupling network. network analyzer used measure impedance profile prototype PDS, giving output similar what discussed simulation section. network analyzer sweeps stimulus across range frequencies measures impedance each frequency. output impedance function frequency. Since spectrum analyzer gives output voltage function frequency, these measurements used together determine transient current function frequency.
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Chapter Power Distribution System
From Spectrum Analyzer From Network Analyzer Armed with understanding design's transient current requirements, designer make better choices. With maximum voltage ripple value from data sheet, value impedance needed frequencies determined. This yields target impedance function frequency. Given this, network capacitors designed accommodate transient current specific design. This six-step process lays closed-loop method designing verifying power distribution system. ensures adequate design.
Other Concerns Causes
this step-by-step method does yield design meeting required noise specifications, then other aspects system should analyzed possible changes.
Possibility Excessive Noise from Other Devices Board
When ground and/or power planes shared among many devices, often case, noise from inadequately decoupled device affect other devices. interfaces with inherently high transient current demands temporary periodic contention high-current drivers common cause; large microprocessors another. unacceptable amounts noise measured locally these devices, analysis should done local decoupling networks component.
Possibility Parasitic Inductance Planes, Vias, Connecting Traces
this case there enough capacitance bypassing network, much inductance path from capacitors FPGA. This could choice connecting trace solder land geometry, long path from capacitors FPGA, and/or current path power vias that traverse exceptionally thick stackup. case inadequate connecting trace capacitor land geometry, important keep mind loop inductance current path. vias bypass capacitor spaced millimeters from capacitor solder lands board, current loop area greater than needs (Figure 4-6a). Vias should placed directly against capacitor solder lands (Figure 4-6b). Never connect vias lands with section trace (Figure 4-6a). Other improvements geometry via-in-pad (where actually under solder land), shown, beside (where vias ends lands, rather astride them), Figure 4-6c. Double vias further improvement (Figure 4-6d). inductance path planes great, there parameters that changed; length electrical path, spreading inductance planes themselves. path length determined capacitor placement. Capacitors must placed close power/ground pairs device being bypassed. This especially important smallest capacitors network, since care been taken chose capacitors with parasitic inductance. There connecting low-inductance, high-frequency capacitor device through high-inductance path. Larger capacitors inherently have high parasitic self inductance allowing proximity device less important.
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Virtex-4 FPGA Designer's Guide UG072 (1.2) June 2008
Other Concerns Causes
spreading inductance planes controlled plane spacing dielectric constant material between them. section "Plane Inductance," page When boards exceptionally thick (greater than mils mm), vias have higher parasitic inductance. these cases, following changes design should considered. first move VCC/GND plane sandwiches close surface FPGA second place highest frequency capacitors surface. Both changes together reduce parasitic inductance relevant current path.
Possibility Signals Stronger Than Necessary
noise VCCO still high after making refinements PDS, interface power scaled back. This goes both outputs from FPGA inputs FPGA. some cases, excessive overshoot inputs FPGA reverse-bias clamp diodes IOBs. This large amounts noise into VCCO. this condition occurring, drive strength these interfaces should decreased, termination should used (both input output paths).
Possibility Signal Return Current Travelling Sub-Optimal Paths
Excessive noise caused signal return currents. every signal transmitted device into (and eventually into another device), there equal opposite current flowing from back into device's power/ground system. there low-impedance return current path available, less optimal, higher impedance path used. When this occurs, voltage changes induced PDS. This situation improved ensuring that every signal closely spaced fully intact return path. Various strategies could required including restricting signals only available routing layers, providing low-impedance paths currents travel between reference planes (decoupling capacitors specific locations PCB).
Virtex-4 FPGA Designer's Guide UG072 (1.2) June 2008
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Chapter Power Distribution System
Calculation Inductance
inductance major contributor parasitic inductance capacitor mounting. dimensions largely determine parasitic inductance. Equation 4-5, from Grover, used determine self-inductance single filled based length diameter. Dimensions inches nanohenries. 5.08 0.75 Equation
Example
calculate inductance going from bottom surface board surface board, board finished thickness length: board finished thickness mils, diameter mils. There 1000 mils inch. 0.062 0.003 5.08 0.75 0.062 5.08 0.062 0.75 0.003 5.08 0.062 3.67 1.15 This result self-inductance single via. self-inductance only part total inductance current loop part Since mutual inductance vias with opposing currents (power ground) effect total inductance, should taken into account when greater accuracy desired. mutual inductance closely spaced complementary vias lowers total inductance small amount.
SPICE Simulation Examples
This appendix demonstrates method used simulate decoupling capacitor networks SPICE. HSPICE techniques discussed here. Other variants SPICE dedicated simulation software also used. simulation referenced below purely illustrative purposes. Simulator details beyond scope this discussion left readers' investigation. HSPICE result included Figure 4-12. schematic representation included Figure 4-13. These capacitor networks represent capacitance parasitics 18-capacitor network. general capacitor array impedance calculation follows these steps: Formulate netlist L-C-R network. Understand where input node output node located. Apply stimulus input port. analysis L-C-R network. Measure input current well input voltage. Formulate V/I. Plot result using scale ease viewing.
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Virtex-4 FPGA Designer's Guide UG072 (1.2) June 2008
SPICE Simulation Examples
this approach, stimulus Analysis directive sweeps current waveform across prescribed frequency points. number frequency points decade commented appended HSPICE netlist. With current magnitude impedance calculated based V/I. Thus, main calculated variable voltage capacitor array positive node. other details complete SPICE decks: There bias resistor ground. There small input resistor connecting source L-C-R network (this optional).
Item necessary decrease simulation time. allows SPICE quickly calculate operating point circuit prior analysis. This accomplished providing SPICE path L-C-R network ground bias resistor). Item optional, convenient. provides component monitor input current L-CR network. viewing simulated impedance result HSPICE, .net directive executed order that HSPICE calculates direct plotting.
HSPICE Netlist
HSPICE netlist available Xilinx website:
HSPICE Output
Figure 4-12 shows HSPICE output: ZIN(MAG) using AWAVES graphical viewer.
ug072_4_12_080104
Figure 4-12: HSPICE Output
Virtex-4 FPGA Designer's Guide UG072 (1.2) June 2008
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Chapter Power Distribution System
Schematic Circuit
Figure 4-13 shows capacitor array with corresponding parasitic inductance resistance.
ug072_4_13_080104
Figure 4-13:
Schematic Circuit
Tools Design Simulation
Table lists some vendors tools design simulation. Table 4-5: Tools Design Simulation Tool SIwave Specctraquest Power Integrity Speed 2000 Star HSPICE UCADESR3.exe Vendor Ansoft Cadence Sigrity Synopsys UltraCAD Website http://www.ansoft.com http://www.cadence.com http://www.sigrity.com http://www.synopsys.com http://www.ultracad.com
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Virtex-4 FPGA Designer's Guide UG072 (1.2) June 2008
Appendix
References
UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide. UG070, Virtex-4 FPGA User Guide. Larry Smith, Decoupling Capacitor Calculations CMOS Circuits, Proceedings EPEP Conference, November 1984. Frederick Grover Ph.D., Inductance Calculations: Working Formulas Tables, Nostrand Company, Inc., Fourth Avenue, York, 1946.
Virtex-4 FPGA Designer's Guide UG072 (1.2) June 2008
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Appendix References
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Virtex-4 FPGA Designer's Guide UG072 (1.2) June 2008
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