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Virtex-4 FPGA User Guide
UG070 (v2.6) December 2008
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Revision History
following table shows revision history this document.
Date 08/02/04 09/10/04 Version Revision Initial Xilinx release. Printed Handbook version. Chapter "Clock Resources": Removed Table 1-6: "BUFGMUX_VIRTEX4 Attributes". Updated Table 1-1, Table 1-2, Table 1-5, Table 1-6. Revised Figure 1-2, Figure 1-5, Figure 1-6, Figure 1-7, Figure 1-9, Figure 1-10, Figure 1-13, Figure 1-14, Figure 1-16. Associated text around these tables figures were revised. Chapter "Digital Clock Managers (DCMs)", changes "FACTORY_JF Attribute" Table 2-6. Chapter "System Monitor": Changed Figure 9-4, Figure 9-5, Figure 9-7, Figure 9-8, Figure 9-9, Figure 9-10, Figure 9-21, Figure 9-25, Figure 9-26, Figure 9-27. Changes equation Temperature Sensor section. following tables changes: Table 9-3, Table 9-5, Table 9-6, Table 9-9, Table 911, Table 9-12, Table 9-14, Table 9-15. Changes entire System Monitor Calibration, System Monitor VHDL Verilog Design Example sections. 02/01/05 Chapter "Clock Resources", revised "Global Clock Buffers", "Clock Regions", "Clock Capable I/O" sections. Chapter "Block RAM," revised "Reset," page description Table 4-13. Chapter "SelectIO Resources," removed device configuration section. Virtex-4 Configuration Guide describes this information detail. Edited "SSTL (Stub-Series Terminated Logic)," page 281. Replaced LVDS_25_DCI with LVDCI_25 "Compatible example:," page 302. Added rule "DCI Virtex-4 FPGA Hardware," page 241. Added "Simultaneous Switching Output Limits," page 306. Removed Chapter System Monitor.
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UG070 (v2.6) December 2008
Date 04/11/05
Version
Revision Chapter Revised Table 1-1, page Figure 1-14, "BUFR Attributes Modes" section including Figure 1-21, page Chapter Revised FACTORY_JF value Table 2-6, page Added "Phase-Shift Overflow" section. Clarified global clock discussion "Global Clock Buffers", "Clock Regions", "Clock Capable I/O". Chapter Added "Built-in Block Error Correction Code" section. Revised Figure Figure 4-8, page 123. Chapter Revised Table Table 5-2, page 184. Chapter Revised Table 6-29, page 290. Chapter Revised "REFCLK Reference Clock" added Table 7-10, page 326. Chapter Added "ISERDES Latencies," page "OSERDES Latencies," page 394. Revised "Guidelines Using Bitslip Submodule" section.
09/12/05
Chapter Revised FACTORY_JF value Table 2-6, page LOCKED signal description updated Figure 2-20 Figure 2-21. Chapter Revised "Simultaneous Switching Output Limits" section. Chapter Added more information "Clock Enable Inputs CE2," page 369.
03/21/06
Chapter Updated description under Table 1-1. Updated Figure 1-21, page Chapter Changed Table 4-8, page added note. Updated discussions NO_CHANGE Mode Cascadable Block sections. Removed synchronous FIFO application example. Chapter Revised slice label Figure 5-30, page 224. Chapter Added "Xilinx DCI" section. Added IBUF "PULLUP/PULLDOWN/KEEPER IBUF, OBUFT, IOBUF" discussion. Added VCCO numbers +1.5V column Table 6-5, page 258. Corrected Figure 6-70, page 292. Added notes Table 6-38, page 299. Updated 3.3V Design Guidelines "Summary," page 306. Added "HSLVDCI (High-Speed Voltage Digitally Controlled Impedance)," page section. Added 1.2V Table 6-40, page 308, added link calculator text above table. Added HSLVDCI Table 6-42, page 310. Revised Virtex-4 Family) FF668 Table 6-43. Chapter Revised "Clock Enable Inputs CE2". Chapter "Temperature Sensing Diode": Added Virtex-4 temperature-sensing diode.
10/06/06
Chapter "SelectIO Logic Resources": Modified text section "REFCLK Reference Clock" deleted former Table 7-10.
UG070 (v2.6) December 2008
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Date 01/04/07
Version
Revision Chapter "Clock Resources": "I/O Clock Buffer BUFIO": Added same region" BUFIO ability drive BUFRs. "BUFG VHDL Verilog Templates": Corrected typo VHDL template. "Regional Clocks Clocks": Added reference PACE tool identifying clock regions. Chapter "Digital Clock Managers (DCMs)": "Status Flags": Corrected descriptions Clock Events "Input Clock Requirements": Clarified when output clocks deskewed. "Reset Input RST": Updated hold time after clock stabilization. "Frequency Synthesizer Characteristics": Added reference link macro monitoring LOCKED. Chapter "Block RAM": "Data Flow": Added paragraph clarifying ADDR setup/hold requirements. Table 4-11: Corrected typo ALMOST FULL. "RAMB16 Port Mapping Design Rules": Corrected logic level unused ADDR[A|B] pins High. "Synchronous Clocking": Clarified synchronous write/read timing. Deleted SIM_COLLISION_CHECK statements from templates. Chapter "SelectIO Resources": Figure 6-53: Corrected internal termination resistor designation. Table 6-1: Updated LVTTL voltage specifications. Table 6-31 following: Globally corrected OBUFGDS OBUFTDS. "Differential Termination Attribute": Corrected paragraph describing DIFF_TERM attribute. "Xilinx DCI": Added reference section "Driver with Termination VCCO/2 (Split Termination)." Figure 6-64: Corrected standard name DIFF_SSTL2_II. Table 6-38: Corrected standard name DIFF_HSTL_II_18_DCI. Chapter "SelectIO Logic Resources": "IDELAYCTRL Locations": Reworded description IDELAYCTRL locations clock regions. Table 7-6: Added "when Variable mode" function descriptions INC, ports. Table 7-9: Added Note TIDELAYRESOLUTION Added requirement wait clock cycles after increment decrement before sampling IDELAY. Figure 7-12: Modified show clock cycle wait time. Modified timing description match Figure 7-12. "IDELAY VHDL Verilog Instantiation Template": Changed port INC, from open zero (both Verilog VHDL). Deleted synthesis translate_off/synthesis translate_on statements from IDELAY instantiation templates.
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UG070 (v2.6) December 2008
Date 01/04/07 (cont'd)
Version (cont'd)
Revision Chapter "Advanced SelectIO Logic Resources": Table 8-1: REV: Added instruction connect GND. Table 8-2: Corrected BITSLIP_ENABLE value from "String" "Boolean". "Registered Outputs Q6": Added clarification in/out sequence. "High-Speed Clock Strobe-Based Memory Interfaces OCLK": Added instruction ground OCLK when INTERFACE_TYPE NETWORKING. "BITSLIP_ENABLE Attribute": Specified setting according setting INTERFACE_TYPE. "INTERFACE_TYPE Attribute": Added recommendation when ISERDES Memory Mode. Added Figure illustrate ISERDES internal connections Memory Mode. Added section "ISERDES Clocking Methods." "ISERDES Width Expansion": Added explanatory paragraph regarding master/slave ISERDES with differential/single-ended inputs. "Guidelines Expanding Serial-to-Parallel Converter Width": Corrected number master/slave input/output reversals. "Verilog Instantiation Template Width Expansion Feature": Corrected number errors template. "ISERDES Latencies": Deleted former Table most text this section replaced with statement relating latency INTERFACE_TYPE. Deleted synthesis translate_off/synthesis translate_on statements from ISERDES instantiation templates. "Data Parallel-to-Serial Converter": Added recommendation apply reset OSERDES prior use. "OSERDES Width Expansion": Added explanatory paragraph regarding master/slave OSERDES with differential/single-ended outputs. "OSERDES VHDL Template" Chapter Removed erroneous semicolon following TRISTATE_WIDTH. "ILOGIC Resources": Added sentence clarifying sharing between ILOGIC/ISERDES OLOGIC/OSERDES. Figure 7-1: Removed OFB/TFB inputs associated MUXes. Figure 8-2: Removed OFB/TFB inputs. "DIFF_SSTL2_II_DCI, DIFF_SSTL18_II_DCI Usage": Removed incorrect bidirectional link requirements reference on-chip differential termination. "DCI Virtex-4 FPGA Hardware": Modified point detailing when VRP/VRN reference resistors required. "PULLUP/PULLDOWN/KEEPER IBUF, OBUFT, IOBUF": Added paragraph recommending against using these circuits drive logic level board-level trace. "Frequency Synthesizer Characteristics": Updated information regarding setting AUTOCALIBRATE CONFIG STEPPING. Added section "FIFO16 Error Condition Work-Arounds" Chapter including VHDL/Verilog source files UG070.zip. Table 6-41: Added data FF676 device/package combinations.
03/15/07
UG070 (v2.6) December 2008
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Virtex-4 FPGA User Guide
Date 04/10/07
Version
Revision Added section "Cascading DCMs" Chapter Table 7-9: Deleted Note (1). Figure 7-12: Added assumption that IOBDELAY_VALUE text. Section "IDELAY Timing": Revised descriptions Clock Events Figure 7-12. Added section "Note Instability after Increment/Decrement Operation". Table 7-12: Revised description port. Chapter "Advanced SelectIO Logic Resources": ISERDES OSERDES sections extensively revised expanded with many figures tables. Figure associated text: Updated. Figure 2-20: Corrected reset requirement from periods Figure 2-22, associated text: Corrected number clock cycles Clock Event "Frequency Synthesizer Characteristics" Chapter Added note indicate need LOCKED monitoring macro recent step devices. "SelectIO Resources Introduction" Chapter Added note that differential VREF-dependent inputs powered VCCAUX. "DCI Virtex-4 FPGA Hardware" Chapter Removed erroneous reference SSTL3 standard. "Lower Capacitance Attributes" Chapter Added RSDS_25 list standards that have differential driver circuits. Added Note Table 6-40. Table 6-43: Included family devices added note Banks "Temperature Sensor Examples" Chapter Added information Texas Instruments temperature sensor.
08/10/07
04/10/08
Table 2-6, page Added CLK_FEEDBACK DCM_AUTOCALIBRATION attribute rows. Added descriptions CLKFX_DIVIDE CLKFX_MULTIPLY rows. "DCM_AUTOCALIBRATION Attribute," page section. Figure 2-9, page Figure 2-11, page Removed element from output. Under Figure 3-5, page 104: Clarified bullet regarding must before effect. Figure 4-11, page 142: Removed REGCEN. Table 6-40, page 308: Added LVCMOS15_16_fast, LVDCI_DV2_18, LVTTL24_fast. "REFCLK Reference Clock," page 342: Changed IDELAYCTRL_REF_PRECISION units MHz. Figure 7-21, page 355: Corrected OFFDDRB labeling. Figure 2-4, page Revised contents block. "System-Synchronous Setting (Default)," page Added text section describing cases when DESKEW_ADJUST parameter effect. "Asynchronous Clocking," page 119: Added results performing read write operation. Figure 6-6, page 238: Moved VREF inside FPGA. "DCI Virtex-4 FPGA Hardware," page 241: Added SSTL18_I_DCI list outputs that require reference resistors VRP/VRN. Figure 7-10, page 330: Updated figure title.
06/17/08
12/01/08
Virtex-4 FPGA User Guide
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UG070 (v2.6) December 2008
Table Contents
Revision History
Preface: About This Guide
Guide Contents Additional Documentation Additional Support Resources Conventions
Typographical Online Document
Chapter Clock Resources
Global Regional Clocks
Global Clocks Regional Clocks Clocks
Global Clocking Resources
Global Clock Inputs Global Clock Input Buffer Primitives Power Savings Disabling Global Clock Buffer Global Clock Buffers Global Clock Buffer Primitives Additional Models Clock Tree Nets GCLK Clock Regions Clock Capable Clock Buffer BUFIO BUFIO Primitive BUFIO Models Regional Clock Buffer BUFR BUFR Primitive BUFR Attributes Modes BUFR Models Regional Clock Nets BUFGCTRL VHDL Verilog Templates VHDL Template Verilog Template Declaring Constraints File BUFG VHDL Verilog Templates VHDL Template Verilog Template Declaring Constraints File BUFGCE BUFGCE_1 VHDL Verilog Templates VHDL Template Verilog Template
Regional Clocking Resources
VHDL Verilog Templates
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Declaring Constraints File BUFGMUX BUFGMUX_1 VHDL Verilog Templates VHDL Template Verilog Template Declaring Constraints File BUFGMUX_VIRTEX4 VHDL Verilog Templates VHDL Template Verilog Template Declaring Constraints File BUFIO VHDL Verilog Templates VHDL Template Verilog Template Declaring Constraints File BUFR VHDL Verilog Templates VHDL Template Verilog Template Declaring Constraints File
Chapter Digital Clock Managers (DCMs)
Summary Primitives.
DCM_BASE Primitive DCM_PS Primitive DCM_ADV Primitive
Ports
Clock Input Ports Source Clock Input CLKIN. Feedback Clock Input CLKFB Phase-Shift Clock Input PSCLK Dynamic Reconfiguration Clock Input DCLK Control Data Input Ports Reset Input Phase-Shift Increment/Decrement Input PSINCDEC Phase-Shift Enable Input PSEN Dynamic Reconfiguration Data Input DI[15:0] Dynamic Reconfiguration Address Input DADDR[6:0] Dynamic Reconfiguration Write Enable Input Dynamic Reconfiguration Enable Input Clock Output Ports Output Clock CLK0 Output Clock, Phase Shift CLK90 Output Clock, 180° Phase Shift CLK180 Output Clock, 270° Phase Shift CLK270 Output Clock CLK2X Output Clock, 180° Phase Shift CLK2X180 Frequency Divide Output Clock CLKDV Frequency-Synthesis Output Clock CLKFX Frequency-Synthesis Output Clock, 180° CLKFX180 Status Data Output Ports Locked Output LOCKED Phase-Shift Done Output PSDONE Status Dynamic Reconfiguration Data Output DO[15:0]
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Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
Dynamic Reconfiguration Ready Output DRDY
Attributes
CLK_FEEDBACK Attribute CLKDV_DIVIDE Attribute CLKFX_MULTIPLY CLKFX_DIVIDE Attributes CLKIN_DIVIDE_BY_2 Attribute CLKIN_PERIOD Attribute CLKOUT_PHASE_SHIFT Attribute DCM_AUTOCALIBRATION Attribute DCM_PERFORMANCE_MODE Attribute DESKEW_ADJUST Attribute DFS_FREQUENCY_MODE Attribute DLL_FREQUENCY_MODE Attribute DUTY_CYCLE_CORRECTION Attribute FACTORY_JF Attribute. PHASE_SHIFT Attribute STARTUP_WAIT Attribute Clock Deskew Clock Deskew Operation Input Clock Requirements Input Clock Changes. Output Clocks During Configuration Startup Deskew Adjust Characteristics Deskew Circuit Cascading DCMs Frequency Synthesis Frequency Synthesis Operation Frequency Synthesizer Characteristics Phase Shifting Phase-Shifting Operation Interaction PSEN, PSINCDEC, PSCLK, PSDONE Phase-Shift Overflow Phase-Shift Characteristics Dynamic Reconfiguration IBUFG BUFGCTRL BUFGCTRL from PMCD Standard Usage Board-Level Clock Generation Board Deskew with Internal Deskew Clock Switching Between DCMs
Design Guidelines
Connecting DCMs Other Clock Resources Virtex-4 Devices
Application Examples
VHDL Verilog Templates, Clocking Wizard Timing Models
Reset/Lock Fixed-Phase Shifting Variable-Phase Shifting Status Flags
Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
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Legacy Support
Chapter Phase-Matched Clock Dividers (PMCDs)
PMCD Summary PMCD Primitives, Ports, Attributes PMCD Usage Design Guidelines
Phase-Matched Divided Clocks Matched Clock Phase Reset (RST) Release (REL) Control Signals Connecting PMCD other Clock Resources IBUFG PMCD PMCD BUFGCTRL PMCD PMCD BUFGCTRL PMCD PMCD Single PMCD Parallel PMCDs IBUFG, BUFG, PMCD PMCD Further Division Clock Frequencies
Application Examples
VHDL Verilog Templates, Clocking Wizard
VHDL Template Verilog Template
Chapter Block
Block Summary Block Introduction Synchronous Dual-Port Single-Port RAMs
Data Flow Read Operation Write Operation Operating Modes WRITE_FIRST Transparent Mode (Default) READ_FIRST READ-BEFORE-WRITE Mode NO_CHANGE Mode Conflict Avoidance Asynchronous Clocking Synchronous Clocking Optional Output Registers Independent Read Write Port Width Selection Cascadable Block FIFO Support Byte-Wide Write Enable
Additional Block Features Virtex-4 Devices
Block Library Primitives Block Port Signals
Clock CLK[A|B] Enable EN[A|B] Write Enable WE[A|B] Register Enable REGCE[A|B]
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Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
Set/Reset SSR[A|B] Address ADDR[A|B]<14:#> Data-In Buses DI[A|B]<#:0> DIP[A|B]<#:0> Data-Out Buses DO[A|B]<#:0> DOP[A|B]<#:0> Cascade CASCADEIN[A|B] Cascade CASCADEOUT[A|B] Inverting Control Pins Unused Inputs
Block Address Mapping Block Attributes
Content Initialization INIT_xx Content Initialization INITP_xx Output Latches Initialization INIT (INIT_A INIT_B) Output Latches Synchronous Set/Reset SRVAL (SRVAL_A SRVAL_B) Optional Output Register On/Off Switch DO[A|B]_REG Clock Inversion Output Register Switch INVERT_CLK_DO[A|B]_REG Extended Mode Address Determinant RAM_EXTENSION_[A|B] Read Width READ_WIDTH_[A|B] Write Width WRITE_WIDTH_[A|B] Write Mode WRITE_MODE_[A|B] Block Location Constraints
Block Initialization VHDL Verilog Code Block VHDL Verilog Templates.
RAMB16 VHDL Template RAMB16 Verilog Template
Additional RAMB16 Primitive Design Considerations
Data Parity Buses DIP[A/B] DOP[A/B] Optional Output Registers Independent Read Write Port Width RAMB16 Port Mapping Design Rules Cascadable Block Byte-Write Enable
Additional Block Primitives
Instantiation Additional Block Primitives
Block Applications
Creating Larger Structures
Block Timing Model
Block Timing Parameters Block Timing Characteristics Clock Event Clock Event Clock Event Clock Event Block Timing Model
Built-in FIFO Support
EMPTY Latency
Top-Level View FIFO Architecture FIFO Primitive FIFO Port Descriptions
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FIFO Operations
Reset Operating Mode Standard Mode First Word Fall Through (FWFT) Mode Status Flags Empty Flag ALMOSTEMPTY Flag Read Error Flag Full Flag Write Error Flag ALMOSTFULL Flag
FIFO Attributes
FIFO ALMOSTEMPTY ALMOSTFULL Flag Offset Range
FIFO VHDL Verilog Templates
FIFO VHDL Template FIFO Verilog Template
FIFO Timing Models Parameters
FIFO Timing Characteristics Case Writing Empty FIFO Case Writing Full Almost Full FIFO Case Reading From Full FIFO Case Reading From Empty Almost Empty FIFO Case Resetting Flags
FIFO Applications
Cascading FIFOs Increase Depth Cascading FIFOs Increase Width
FIFO16 Error Condition Work-Arounds
FIFO16 Error Condition Solution Synchronous/Asynchronous Clock Work-Arounds Synchronous Clock Work-Around Asynchronous Clock Work-Around WRCLK Faster than RDCLK Design. RDCLK Faster than WRCLK Design. User-Programmable Flag Settings Composite FIFO Status Flags Resource Utilization Performance Expressed Maximum Read and/or Write Clock Frequency CORE Generator Tool Implementation. Software Updates Software Cores Solution Work-Around Using Third Fast Clock Design Description Notes: Timing Diagram Resource Utilization Performance Design Files Solution FIFO Flag Generator Using Gray Code. Design Description Notes: Resource Utilization
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Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
Performance Design Files
Solution Summary
Built-in Block Error Correction Code
Top-Level View Block Architecture Block Primitive Block Port Description Error Status Description Block Attribute Block VHDL Verilog Templates Block VHDL Template Block Verilog Template
Chapter Configurable Logic Blocks (CLBs)
Overview
Slice Description CLB/Slice Configurations Look-Up Table (LUT) Storage Elements. Distributed Memory (Available SLICEM only) Read Only Memory (ROM). Shift Registers (Available SLICEM only) Shift Register Data Flow Multiplexers Designing Large Multiplexers. Fast Lookahead Carry Logic Arithmetic Logic General Slice Timing Model Parameters Timing Parameters Timing Characteristics Slice Distributed Timing Model Parameters (Available SLICEM only) Distributed Timing Parameters Distributed Timing Characteristics Slice Timing Model Parameters (Available SLICEM only) Slice Timing Parameters Slice Timing Characteristics. Slice Carry-Chain Timing Model Parameters Slice Carry-Chain Timing Parameters. Slice Carry-Chain Timing Characteristics Distributed Primitives VHDL Verilog Instantiations Port Signals Clock WCLK Enable Address (A4, Data Data SPO, Inverting Control Pins Global Set/Reset
Slice Timing Models
Primitives Verilog/VHDL Examples
Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
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Attributes. Content Initialization INIT Initialization VHDL Verilog Codes Location Constraints Creating Larger Structures VHDL Verilog Templates Primitives Submodules Initialization VHDL Verilog Code Port Signals Clock CLK. Data Clock Enable (optional) Address Data Data (optional) Inverting Control Pins Global Set/Reset Attributes. Content Initialization INIT Location Constraints Fully Synchronous Shift Registers Static-Length Shift Registers VHDL Verilog Instantiation VHDL Verilog Templates Multiplexer Primitives Submodules Port Signals Data DATA_I Control SELECT_I Data DATA_O Multiplexer Verilog/VHDL Examples VHDL Verilog Instantiation VHDL Verilog Submodules
Shift Registers (SRLs) Primitives Verilog/VHDL Example
Multiplexer Primitives Verilog/VHDL Examples
Chapter SelectIO Resources
Tile Overview SelectIO Resources Introduction SelectIO Technology Resources General Guidelines
Virtex-4 FPGA Bank Rules 3.3V Support Reference Voltage (VREF) Pins Output Drive Source Voltage (VCCO) Pins Virtex-4 FPGA Digitally Controlled Impedance (DCI) Introduction Xilinx Controlled Impedance Driver (Source Termination) Controlled Impedance Driver with Half Impedance (Source Termination) Input Termination VCCO (Single Termination) Input Termination VCCO/2 (Split Termination) Driver with Termination VCCO (Single Termination) Driver with Termination VCCO (Split Termination)
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Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
Virtex-4 FPGA Hardware. Usage Examples
Virtex-4 FPGA SelectIO Primitives
IBUF IBUFG OBUF OBUFT IOBUF IBUFDS IBUFGDS OBUFDS OBUFTDS IOBUFDS Virtex-4 FPGA SelectIO Attributes/Constraints Location Constraints IOStandard Attribute Output Slew Rate Attributes Output Drive Strength Attributes Lower Capacitance Attributes PULLUP/PULLDOWN/KEEPER IBUF, OBUFT, IOBUF Differential Termination Attribute Virtex-4 FPGA Resource VHDL/Verilog Examples VHDL Template Verilog Template LVTTL (Low Voltage Transistor-Transistor Logic) LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor). LVDCI (Low Voltage Digitally Controlled Impedance) LVDCI_DV2 HSLVDCI (High-Speed Voltage Digitally Controlled Impedance) PCIX, PCI33, PCI66 (Peripheral Component Interface) (Gunning Transceiver Logic) GTL_DCI Usage GTLP (Gunning Transceiver Logic Plus) GTLP_DCI Usage HSTL (High-Speed Transceiver Logic) HSTL_ HSTL_ III, HSTL_ I_18, HSTL_ III_18 Usage HSTL_ I_DCI, HSTL_ III_DCI, HSTL_ I_DCI_18, HSTL_ III_DCI_18 Usage HSTL_ HSTL_ HSTL_ II_18, HSTL_ IV_18 Usage HSTL_ II_DCI, HSTL_ IV_DCI, HSTL_ II_DCI_18, HSTL_ IV_DCI_18 Usage DIFF_HSTL_ DIFF_HSTL_II_18 DIFF_HSTL_II_DCI, DIFF_HSTL_II_DCI_18 HSTL Class HSTL Class Complementary Single-Ended (CSE) Differential HSTL Class HSTL Class HSTL Class HSTL Class (1.8V) HSTL Class (1.8V) Complementary Single-Ended (CSE) Differential HSTL Class (1.8V) HSTL Class (1.8V) HSTL Class (1.8V) SSTL (Stub-Series Terminated Logic) SSTL2_I, SSTL18_I Usage SSTL2_I_DCI, SSTL18_I_DCI Usage
Specific Guidelines Virtex-4 FPGA Supported Standards
Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
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SSTL2_II, SSTL18_II Usage SSTL2_II_DCI, SSTL18_II_DCI Usage DIFF_SSTL2_II, DIFF_SSTL18_II Usage DIFF_SSTL2_II_DCI, DIFF_SSTL18_II_DCI Usage
SSTL2 Class (2.5V) SSTL2 Class (2.5V) Complementary Single-Ended (CSE) Differential SSTL2 Class (2.5V) SSTL18 Class (1.8V) SSTL18 Class (1.8V) Complementary Single-Ended (CSE) Differential SSTL Class (1.8V) Differential Termination: DIFF_TERM Attribute LVDS Extended LVDS (Low Voltage Differential Signaling) Transmitter Termination Receiver Termination HyperTransport Protocol (LDT) BLVDS (Bus LVDS) Differential LVPECL (Low-Voltage Positive Emitter-Coupled Logic) LVPECL Transceiver Termination
Standards Compatibility Standards Special Design Rules
Rules Combining Standards Same Bank 3.3V Design Guidelines Standard Design Rules. Mixing Techniques Summary Sparse-Chevron Packages Nominal Specifications Construction Signal Return Current Management Load Traces Power Distribution System Design Nominal Limit Table: Sparse Chevron Equivalent VCCO/GND Pairs: Sparse Chevron Nominal Limit Tables: Non-Sparse Chevron Equivalent VCCO/GND Pairs: Non-Sparse Chevron Actual Limits versus Nominal Limits Electrical Basis Noise Parasitic Factors Derating Method (PFDM) Weighted Average Calculation Calculation Full Device Full Device Example Full Device Calculator Other Assumptions LVDCI HSLVDCI Drivers Bank
Simultaneous Switching Output Limits
Chapter SelectIO Logic Resources
Introduction ILOGIC Resources
Combinatorial Input Path Input Overview (IDDR)
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Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
OPPOSITE_EDGE Mode SAME_EDGE Mode SAME_EDGE_PIPELINED Mode
Input Primitive (IDDR) IDDR VHDL Verilog Templates IDDR VHDL Template IDDR Verilog Template ILOGIC Timing Models ILOGIC Timing Characteristics ILOGIC Timing Characteristics, Input Delay Element (IDELAY) IDELAY Primitive IDELAY Ports IDELAY Attributes IDELAY Timing Note Instability after Increment/Decrement Operation IDELAY VHDL Verilog Instantiation Template IDELAYCTRL Overview IDELAYCTRL Primitive IDELAYCTRL Ports IDELAYCTRL Timing IDELAYCTRL Locations IDELAYCTRL Usage Design Guidelines
Combinatorial Output Data 3-State Control Path Output Overview (ODDR) OPPOSITE_EDGE Mode SAME_EDGE Mode Clock Forwarding Output Primitive (ODDR). ODDR VHDL Verilog Templates ODDR VHDL Template ODDR Verilog Template OLOGIC Timing Models. Timing Characteristics
OLOGIC Resources
Chapter Advanced SelectIO Logic Resources
Introduction Input Serial-to-Parallel Logic Resources (ISERDES).
ISERDES Primitive ISERDES Ports Combinatorial Output Registered Outputs Bitslip Operation BITSLIP Clock Enable Inputs High-Speed Clock Input Divided Clock Input CLKDIV Serial Input Data from High-Speed Clock Strobe-Based Memory Interfaces OCLK Reset Input ISERDES Attributes BITSLIP_ENABLE Attribute
Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
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DATA_RATE Attribute. DATA_WIDTH Attribute INTERFACE_TYPE Attribute IOBDELAY Attribute NUM_CE Attribute SERDES_MODE Attribute
ISERDES Clocking Methods ISERDES Width Expansion Guidelines Expanding Serial-to-Parallel Converter Width Verilog Instantiation Template Width Expansion Feature ISERDES Latencies ISERDES Timing Model Parameters Timing Characteristics ISERDES VHDL Verilog Instantiation Template. ISERDES VHDL Instantiation ISERDES Verilog Instantiation BITSLIP Submodule Bitslip Operation Bitslip Timing Model Parameters
Output Parallel-to-Serial Logic Resources (OSERDES)
Data Parallel-to-Serial Converter 3-State Parallel-to-Serial Conversion.
OSERDES Primitive OSERDES Ports Data Path Output 3-state Control Output High-Speed Clock Input Divided Clock Input CLKDIV Parallel Data Inputs Output Data Clock Enable Parallel 3-State Inputs 3-State Signal Clock Enable Reset Input OSERDES Attributes DATA_RATE_OQ Attribute DATA_RATE_TQ Attribute DATA_WIDTH Attribute SERDES_MODE Attribute TRISTATE_WIDTH Attribute OSERDES Width Expansion Guidelines Expanding Parallel-to-Serial Converter Width OSERDES Latencies OSERDES Timing Model Parameters Timing Characteristics Serialization Timing Characteristics Serialization Timing Characteristics 3-State Controller Serialization OSERDES VHDL Verilog Instantiation Templates OSERDES VHDL Template. OSERDES Verilog Template
Chapter Temperature Sensing Diode
Temperature-Sensing Diode (TDP/TDN)
Temperature Sensor Examples.
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Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
Maxim Remote/Local Temperature Sensors Texas Instruments Remote/Local Temperature Sensor National Semiconductor (LM83 LM86)
Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
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Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
Preface
About This Guide
This document describes Virtex®-4 FPGA architecture. Complete up-to-date documentation Virtex-4 family FPGAs available Xilinx® website http://www.xilinx.com/virtex4.
Guide Contents
Chapter "Clock Resources" Chapter "Digital Clock Managers (DCMs)" Chapter "Phase-Matched Clock Dividers (PMCDs)" Chapter "Block RAM" Chapter "Configurable Logic Blocks (CLBs)" Chapter "SelectIO Resources" Chapter "SelectIO Logic Resources" Chapter "Advanced SelectIO Logic Resources" Chapter "Temperature Sensing Diode"
Additional Documentation
following documents also available download http://www.xilinx.com/virtex4. DS112, Virtex-4 Family Overview features product selection Virtex-4 family outlined this overview. DS302, Virtex-4 Data Sheet: Switching Characteristics This data sheet contains Switching Characteristic specifications Virtex-4 family. UG073, XtremeDSP Virtex-4 FPGAs User Guide This guide describes XtremeDSPslice includes reference designs using DSP48 math functions various filters. UG071, Virtex-4 Configuration Guide This all-encompassing configuration guide includes chapters configuration interfaces (serial SelectMAP), bitstream encryption, Boundary-Scan JTAG configuration, reconfiguration techniques, readback through SelectMAP JTAG interfaces.
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Preface: About This Guide
UG072, Virtex-4 Designer's Guide This guide describes guidelines Virtex-4 family. covers SelectIOsignaling, RocketIOsignaling, power distribution systems, breakout, parts placement.
UG075, Virtex-4 Packaging Pinout Specification This specification includes tables device/package combinations maximum I/Os, definitions, pinout tables, pinout diagrams, mechanical drawings, thermal specifications.
UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide This guide describes RocketIO Multi-Gigabit Transceivers available Virtex-4 family.
UG074, Virtex-4 FPGA Embedded Tri-Mode Ethernet User Guide This guide describes Tri-mode Ethernet Media Access Controller available Virtex-4 family.
UG018, PowerPC Processor Block Reference Guide This guide describes PowerPC® processor block available Virtex-4 family.
Additional Support Resources
search database silicon software questions answers, create technical support case WebCase, Xilinx website http://www.xilinx.com/support.
Conventions
This document uses following conventions. example illustrates each convention.
Typographical
following typographical conventions used this document:
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Conventions
Convention
Meaning Variables syntax statement which must supply values
Example ngdbuild design_name Development System Reference Guide more information. wire drawn that overlaps symbol, nets connected. ngdbuild [option_name] design_name
Italic font
References other manuals
Emphasis text optional entry parameter. However, specifications, such bus[7:0], they required. list items from which must choose more Separates items list choices
Square brackets
Braces
lowpwr ={on|off} lowpwr ={on|off} Name QOUT' Name CLKIN' allow block block_name loc1 loc2 locn;
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Repetitive material that been omitted
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Online Document
following conventions used this document:
Convention Meaning Cross-reference link location current document Cross-reference link location another document Hyperlink website (URL) Example section "Additional Resources" details. Refer "Title Formats" Chapter details. Figure Virtex-II Platform FPGA User Guide. http://www.xilinx.com latest speed files.
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text Blue, underlined text
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Preface: About This Guide
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Chapter
Clock Resources
Global Regional Clocks
clocking purposes, each Virtex®-4 device divided into regions. number regions varies with device size, eight regions smallest device regions largest one.
Global Clocks
Each Virtex-4 device matched-skew global clock lines that clock sequential resources whole device (CLB, block RAM, DCMs, I/O), also drive logic signals. eight these global clock lines used region. Global clock lines only driven global clock buffer, also used clock enable circuit glitch-free multiplexer. select between clock sources, also switch away from failed clock source, feature Virtex-4 architecture. global clock buffer often driven Digital Clock Manager (DCM) eliminate clock distribution delay, adjust delay relative another clock. There more global clocks than DCMs, often drives more than global clock.
Regional Clocks Clocks
Each region "clock capable" regional clock inputs. Each input differentially single-endedly drive regional clocks clocks same region, also region above below (i.e., three adjacent regions). regional clock buffer programmed divide incoming clock rate integer number from This feature, conjunction with programmable serializer/deserializer (see Chapter "Advanced SelectIO Logic Resources") allows source-synchronous systems cross clock domains without using additional logic resources. third type clocking resource, clocks, very fast serve localized serializer/deserializer circuits (see Chapter "Advanced SelectIO Logic Resources"). more detail identify clock regions associated components, please PACE tool.
Global Clocking Resources
Global clocks dedicated network interconnect specifically designed reach clock inputs various resources FPGA. These networks designed have skew duty cycle distortion, power, increased jitter tolerance. They also designed support very high frequency signals.
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Chapter Clock Resources
Understanding signal path global clock expands understanding various global clock resources. global clocking resources network consist following paths components: Global Clock Inputs Global Clock Buffers Clock Tree Nets GCLK Clock Regions
Global Clock Inputs
Virtex-4 FPGAs contain specialized global clock input locations regular user I/Os used clock inputs. number clock inputs varies with device size. Smaller devices contain clock inputs, while larger devices have clock inputs. Table summarizes number clock inputs available different Virtex-4 devices. Table 1-1: Number Clock Inputs Device
Device XC4VLX15, XC4VLX25 XC4VSX25, XC4VSX35 XC4VFX12, XC4VFX20, XC4VFX40, XC4VFX60 XC4VLX40(1), XC4VLX60(1), XC4VLX80, XC4VLX100, XC4VLX160, XC4VLX200 XC4VSX55 XC4VFX100(2), XC4VFX140
Notes:
XC4VLX40 XC4VLX60 FF668 package only have clock input pins. XC4VFX100 FF1152 package only clock input pins.
Number Clock Inputs
Clock inputs configured standard, including differential standards. Each clock input either single-ended differential. clock inputs differential desired. When used outputs, global clock input pins configured output standard except LVDS output differential standards. Each global clock input supports single-ended output standard output differential standard.
Global Clock Input Buffer Primitives
primitives Table different configurations input clock input buffer. Table 1-2: Clock Buffer Primitives
Input Output Description Input clock buffer single-ended Input clock buffer differential
Primitive IBUFG IBUFGDS
These primitives work conjunction with Virtex-4 FPGA resource setting IOSTANDARD attribute desired standard. Refer Chapter "I/O Compatibility" Table 6-38 complete list possible standards.
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Global Clocking Resources
Power Savings Disabling Global Clock Buffer
Virtex-4 FPGA clock architecture provides straightforward means implementing clock gating purposes powering down portions design. Most designs contain several unused BUFGMUX resources. clock drive multiple BUFGMUX inputs, BUFGMUX outputs, which will synchronous with each other, used drive distinct regions logic. example, logic required always operating constrained clocking regions, then BUFGMUX outputs used drive those regions. Toggling enable other BUFGMUX then provides simple means stopping dynamic power consumption those regions logic available power savings. XPower tool used estimate power savings from such approach. difference calculated either toggling BUFGMUX enable setting frequency corresponding clock MHz.
Global Clock Buffers
There global clock buffers every Virtex-4 device. Each half (top/bottom) contains global clock buffers. global clock input directly connect from P-side differential input pair global clock buffer input same half, either bottom, device. Each differential global clock pair connect either differential single-ended clock PCB. using single-ended clock, then P-side pair must used because direct connection only exists this pin. naming conventions, refer Virtex-4 Packaging Pinout Specification. single-ended clock connected N-side differential pair results local route creates additional delay. single-ended clock connected differential pair then other side (N-side typically) used another single-ended clock pin. However, used user I/O. device with global clock pins connected differential single-ended board clocks. device with global clock pins connected clocks under these same conditions. Global clock buffers allow various clock/signal sources access global clock trees nets. possible sources input global clock buffers include: Global clock inputs Digital Clock Manager (DCM) outputs Phase-Matched Clock Divider (PMCD) outputs Rocket Multi-Gigabit Transceivers Other global clock buffer outputs General interconnect
global clock buffers only driven sources same half (top/bottom). global clock buffers drive clock regions Virtex-4 devices. primary/secondary rules from Virtex-II Virtex-II FPGAs apply. However, only eight different clocks driven single clock region. clock region CLBs) branch clock tree consisting eight rows eight rows down. clock region only spans halfway across device. clock buffers designed configured synchronous asynchronous "glitch free" multiplexer with clock inputs. Virtex-4 devices have more control pins provide wider range functionality more robust input switching. following
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Chapter Clock Resources
subsections detail various configurations, primitives, models Virtex-4 FPGA clock buffers.
Global Clock Buffer Primitives
primitives Table different configurations global clock buffers. Table 1-3: Global Clock Buffer Primitives
Input Output Control CE0, CE1, IGNORE0, IGNORE1,
Primitive BUFGCTRL BUFG BUFGCE BUFGCE_1 BUFGMUX BUFGMUX_1 BUFGMUX_VIRTEX4
Notes:
primitives derived from software preset BUFGCTRL.
BUFGCTRL
BUFGCTRL primitive shown Figure 1-1, switch between asynchronous clocks. other global clock buffer primitives derived from certain configurations BUFGCTRL. ISE® software tools manage configuration these primitives. BUFGCTRL four select lines, CE0, CE1. also additional control lines, IGNORE0 IGNORE1. These control lines used control input
BUFGCTRL IGNORE1
IGNORE0
UG070_1_01_031208
Figure 1-1:
BUFGCTRL Primitive
BUFGCTRL designed switch between clock inputs without possibility glitch. When presently selected clock transitions from High after
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Global Clocking Resources
change, output kept until other ("to-be-selected") clock transitioned from High Low. Then clock starts driving output.The default configuration BUFGCTRL falling edge sensitive held prior input switching. BUFGCTRL also rising edge sensitive held High prior input switching. some applications conditions previously described desirable. Asserting IGNORE pins bypasses BUFGCTRL from detecting conditions switching between clock inputs. other words, asserting IGNORE causes switch inputs instant select changes. IGNORE0 causes output switch away from input immediately when select changes, while IGNORE1 causes output switch away from input immediately when select changes. Selection input clock requires "select" pair CE0, CE1) asserted High. either asserted High, desired input selected. normal operation, both pairs (all four select lines) expected asserted High simultaneously. Typically only "select" pair used select line, while other tied High. truth table shown Table 1-4. Table 1-4:
Notes:
input refers valid input clock before this state achieved. other states, output becomes value INIT_OUT does toggle.
Truth Table Clock Resources
Input
Although both used select desired output, each these pins behaves slightly different. When using switch clocks, change clock selection faster than when using Violation setup/hold times pins causes glitch clock output. other hand, using pins allows user switch between clock inputs without regard setup/hold times. does result glitch. discussion "BUFGMUX_VIRTEX4". designed allow backward compatibility from Virtex-II Virtex-II FPGAs.
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Chapter Clock Resources
timing diagram Figure illustrates various clock switching conditions using BUFGCTRL primitives. Exact timing numbers best found using speed specification.
TBCCCK_CE
IGNORE0 IGNORE1
TBCCKO_O TBCCKO_O TBCCKO_O
Begin Begin
UG070_1_02_072907
Figure 1-2:
BUFGCTRL Timing Diagram
Before time event output uses input time TBCCCK_CE, before rising edge time event both deasserted Low. about same time, both asserted High. time TBCCKO_O, after time event output uses input This occurs after High transition (event followed High transition time event IGNORE1 asserted. time event asserted High while deasserted Low. TBCCKO_O, after time event output switched from without requiring High transition
Other capabilities BUFGCTRL are: Pre-selection inputs made after configuration before device operation. initial output after configuration selected either High Low. Clock selection using only tied High) change clock selection without waiting High transition previously selected clock.
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Global Clocking Resources
Table summarizes attributes BUFGCTRL primitive. Table 1-5: BUFGCTRL Attributes
Description Initializes BUFGCTRL output specified value after configuration. Sets positive negative edge behavior. Sets output level when changing clock selection. TRUE, BUFGCTRL output uses input after configuration(1). TRUE, BUFGCTRL output uses input after configuration(1). Possible Values (default),
Attribute Name INIT_OUT
PRESELECT_I0 PRESELECT_I1
Notes:
FALSE (default), TRUE FALSE (default), TRUE
Both PRESELECT attributes cannot TRUE same time. constraint available.
BUFG
BUFG simply clock buffer with clock input clock output. This primitive based BUFGCTRL with some pins connected logic High Low. Figure illustrates relationship BUFG BUFGCTRL. constraint available BUFG.
IGNORE1 BUFG
IGNORE0
UG070_1_03_031208
Figure 1-3:
BUFG BUFGCTRL
output follows input shown timing diagram Figure 1-4.
BUFG(I) BUFG(O) TBCCKO_O
UG070_1_04_071204
Figure 1-4:
BUFG Timing Diagram
BUFGCE BUFGCE_1
Unlike BUFG, BUFGCE clock buffer with clock input, clock output clock enable line. This primitive based BUFGCTRL with some pins connected logic High
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Chapter Clock Resources
Low. Figure illustrates relationship BUFGCE BUFGCTRL. constraint available BUFGCE BUFGCE_1.
BUFGCE BUFGCTRL IGNORE1
BUFGCE
IGNORE0
ug070_1_05_081904
Figure 1-5:
BUFGCE BUFGCTRL
switching condition BUFGCE similar BUFGCTRL. input prior incoming rising clock edge, following clock pulse does pass through clock buffer, output stays Low. level change during incoming clock High pulse effect until clock transitions Low. output stays when clock disabled. However, when clock being disabled completes clock High pulse. Since clock enable line uses BUFGCTRL, select signal must meet setup time requirement. Violating this setup time result glitch. Figure illustrates timing diagram BUFGCE.
BUFGCE(I) BUFGCE(CE) BUFGCE(O) TBCCKO_O
ug070_1_06_082504
TBCCCK_CE
Figure 1-6: BUFGCE Timing Diagram BUFGCE_1 similar BUFGCE, with exception switching condition. input prior incoming falling clock edge, following clock pulse does pass through clock buffer, output stays High. level change during incoming clock pulse effect until clock transitions High. output stays High when clock disabled. However, when clock being disabled completes clock pulse.
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Global Clocking Resources
Figure illustrates timing diagram BUFGCE_1.
BUFGCE_1(I) BUFGCE_1(CE) BUFGCE_1(O) TBCCKO_O
ug070_1_07_081904
TBCCCK_CE
Figure 1-7:
BUFGCE_1 Timing Diagram
BUFGMUX BUFGMUX_1
BUFGMUX clock buffer with clock inputs, clock output, select line. This primitive based BUFGCTRL with some pins connected logic High Low. Figure illustrates relationship BUFGMUX BUFGCTRL. constraint available BUFGMUX BUFGCTRL.
BUFGMUX IGNORE1
IGNORE0
ug070_1_08_071304
Figure 1-8:
BUFGMUX BUFGCTRL
Since BUFGMUX uses pins select pins, when using select, setup time requirement must met. Violating this setup time result glitch. Switching conditions BUFGMUX same pins BUFGCTRL. Figure illustrates timing diagram BUFGMUX.
TBCCCK_CE TBCCKO_O begin TBCCKO_O
Figure 1-9:
BUFGMUX Timing Diagram
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Chapter Clock Resources
Figure 1-9: current clock activated High. currently High, multiplexer waits deassert Low. Once Low, multiplexer output stays until transitions High Low. When transitions from High Low, output switches setup/hold times met, glitches short pulses appear output.
BUFGMUX_1 rising edge sensitive held High prior input switch. Figure 1-10 illustrates timing diagram BUFGMUX_1. constraint available BUFGMUX BUFGMUX_1.
TBCCCK_CE TBCCKO_O
UG070_1_10_082504
Figure 1-10: Figure 1-10: current clock activated High.
BUFGMUX_1 Timing Diagram
currently Low, multiplexer waits asserted High. Once High, multiplexer output stays High until transitions High. When transitions from High, output switches setup/hold times met, glitches short pulses appear output.
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Global Clocking Resources
BUFGMUX_VIRTEX4
BUFGMUX_VIRTEX4 clock buffer with clock inputs, clock output, select line. This primitive based BUFGCTRL with some pins connected logic High Low. Figure 1-11 illustrates relationship BUFGMUX_VIRTEX4 BUFGCTRL.
IGNORE1
BUFGMUX_VIRTEX4
IGNORE0
ug070_1_11_071304
Figure 1-11:
BUFGMUX_VIRTEX4 BUFGCTRL
BUFGMUX_VIRTEX4 uses pins select pins. switch anytime without causing glitch. setup/hold times determine whether output will pass extra pulse previously selected clock before switching clock. changes shown Figure 1-12, prior setup time TBCCCK_S before transitions from High Low, then output will pass extra pulse changes following hold time then output will pass extra pulse. violates setup/hold requirements, output might pass extra pulse, will glitch. case, output changes clock within three clock cycles slower clock. setup/hold requirements with respect falling clock edge (assuming INIT_OUT rising edge CE1. Switching conditions BUFGMUX_VIRTEX4 same BUFGCTRL. Figure 1-12 illustrates timing diagram BUFGMUX_VIRTEX4.
TBCCKO_O TBCCKO_O
ug070_1_12_080204
Figure 1-12:
BUFGMUX_VIRTEX4 Timing Diagram
Other capabilities BUFGMUX_VIRTEX4 primitive are: Pre-selection input after configuration. Initial output selected High after configuration.
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Chapter Clock Resources
Additional Models
Asynchronous Using BUFGCTRL
some cases application requires immediate switching between clock inputs bypassing edge sensitivity BUFGCTRL. example when clock inputs longer switching. this happens, clock output would have proper switching conditions because BUFGCTRL never detected clock edge. This case uses asynchronous mux. Figure 1-13 illustrates asynchronous with BUFGCTRL design example. Figure 1-14 shows asynchronous timing diagram.
IGNORE1
Asynchronous Design Example
IGNORE0
ug070_1_13_082704
Figure 1-13:
Asynchronous with BUFGCTRL Design Example
TBCCKO_O TBCCKO_O
Begin
UG070_1_14_033005
Figure 1-14: Figure 1-14: current clock from activated High.
Asynchronous Timing Diagram
Clock output immediately switches When Ignore signals asserted High, glitch protection disabled.
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Global Clocking Resources
BUFGMUX_VIRTEX4 with Clock Enable
BUFGMUX_VIRTEX4 with clock enable BUFGCTRL configuration allows user choose between incoming clock inputs. needed, clock enable used disable output. Figure 1-15 illustrates BUFGCTRL usage design example Figure 1-16 shows timing diagram.
BUFGMUX_VIRTEX4+CE Design Example IGNORE1
IGNORE0
ug070_1_15_071304
Figure 1-15:
BUFGMUX_VIRTEX4 with BUFGCTRL
TBCCCK_CE
TBCCKO_O TBCCKO_O
Begin Clock
UG070_1_16_082504
Figure 1-16: Figure 1-16:
BUFGMUX_VIRTEX4 with Timing Diagram
time event output uses input Before time event asserted High. time TBCCKO_O, after time event output uses input This occurs after High transition followed High transition completed. time TBCCCK_CE, before time event asserted Low. clock output switched kept after High transition completed.
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Chapter Clock Resources
Clock Tree Nets GCLK
Virtex-4 FPGA clock trees designed low-skew low-power operation. unused branch disconnected. clock trees also manage load/fanout when logic resources used. global clock lines buffers implemented differentially. This facilitates much better duty cycles common-mode noise rejection. Virtex-4 architecture, access global clock lines limited logic resources clock pins. global clock lines access other pins CLBs without using local interconnects. Applications requiring very fast signal connection large load/fanout benefit from this architecture.
Clock Regions
Virtex-4 devices improve clocking distribution clock regions. Each clock region have eight global clock domains. These eight global clocks driven combination global clock buffers. restrictions rules needed previous FPGA architectures longer applicable. Specifically, clock region limited four quadrants regardless die/device size. Instead, dimensions clock region fixed CLBs tall IOBs) spanning half (Figure 1-17). fixing dimensions clock region, larger Virtex-4 devices have more clock regions. result, Virtex-4 devices support many more multiple clock domains than previous FPGA architectures. Table shows number clock regions each Virtex-4 device. logic resources center column (DCMs, IOBs, etc.) located left clock regions. DCMs, used, utilize global clocks left regions feedback lines. four DCMs specific region. used same region, IDELAYCTRL uses another global clock that region. companion module PMCD, directly connected global clock, will also utilize global clocks same region.
XC4VLX15 Clock Regions
CLBs CLBs CLBs clock regions span half CLBs
XC4VLX100 Clock Regions
clock regions CLBs tall CLBs CLBs down) Center Column Logic Resources
UG070_1_17_071304
Figure 1-17:
Clock Regions
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Regional Clocking Resources
Table 1-6:
Device Family XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80
Virtex-4 FPGA Clock Regions
Number Clock Regions
XC4VLX100 XC4VLX160 XC4VLX200 Family XC4VSX25 XC4VSX35 XC4VSX55 Family XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140
Regional Clocking Resources
Regional clock networks clock networks independent global clock network. Unlike global clocks, span regional clock signal limited three clock regions. These networks especially useful source-synchronous interface designs. understand regional clocking works, important understand signal path regional clock signal. Virtex-4 FPGA regional clocking resources network consist following paths components: Clock Capable Clock Buffer BUFIO Regional Clock Buffer BUFR Regional Clock Nets
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Chapter Clock Resources
Clock Capable
typical clock region there clock capable pairs (there exceptions center column). Clock capable pairs regular pairs where LVDS output drivers have been removed reduce input capacitance. global clock inputs clock capable I/Os (i.e., they have LVDS output drivers). There four dedicated clock capable sites every bank. When used clock inputs, clock-capable pins drive BUFIO BUFR. They directly connect global clock buffers. When used single-ended clock pins, then described "Global Clock Buffers", P-side pair must used because direct connection only exists this pin.
Clock Buffer BUFIO
clock buffer (BUFIO) clock buffer available Virtex-4 devices. BUFIO drives dedicated clock within column, independent global clock resources. Thus, BUFIOs ideally suited source-synchronous data capture (forwarded/receiver clock distribution). BUFIOs only driven clock capable I/Os located same clock region. BUFIOs drive adjacent clock nets (for total three clock regions) well regional clock buffers (BUFR) same region. BUFIOs cannot drive logic resources (CLB, block RAM, etc.) because clock network only reaches column.
BUFIO Primitive
BUFIO simply clock clock buffer. There phase delay between input output. Figure 1-18 shows BUFIO. Table lists BUFIO ports. location constraint available BUFIO.
BUFIO
ug070_1_18_071304
Figure 1-18: Table 1-7:
BUFIO Primitive
BUFIO Port List Definitions
Type Output Input Width Definition Clock output port Clock input port
Port Name
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Regional Clocking Resources
BUFIO Models
Figure 1-19, BUFIO used drive logic using clock capable I/O. This implementation ideal source-synchronous applications where forwarded clock used capture incoming data.
Tile Tile Tile Tile Tile Tile Tile
Adjacent Region
Clock Capable
Tile BUFIO
Fabric Clock Capable
Tile
Tile Tile Tile Tile Tile Tile Tile
Adjacent Region
ug070_1_19_072204
Figure 1-19:
BUFIO Driving Logic Single Clock Region
Regional Clock Buffer BUFThe regional clock buffer (BUFR) another clock buffer available Virtex-4 devices. BUFRs drive clock signals dedicated clock within clock region, independent from global clock tree. Each BUFR drive regional clock nets region located, clock nets adjacent clock regions three clock regions).
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Chapter Clock Resources
Unlike BUFIOs, BUFRs drive logic logic resources (CLB, block RAM, etc.) existing adjacent clock regions. BUFRs driven either output from BUFIOs local interconnect. addition, BUFR capable generating divided clock outputs with respect clock input. divide values integer between eight. BUFRs ideal source-synchronous applications requiring clock domain crossing serial-to-parallel conversion. There BUFRs typical clock region (two regional clock networks). center column does have BUFRs.
BUFR Primitive
BUFR clock-in/clock-out buffer with capability divide input clock frequency.
CLug070_1_20_071204
Figure 1-20: Table 1-8:
BUFR Primitive
BUFR Port List Definitions
Type Output Input Input Width Definition Clock output port Clock enable port. Cannot used BYPASS mode. Asynchronous clear divide logic, sets output Low. Cannot used BYPASS mode. Clock input port
Port Name
Input
Additional Notes
When asserted/deasserted, output clock signal turns on/off four input clock cycles later. When global set/reset (GSR) signal High, BUFR does toggle, even held High. BUFR output toggles four clock cycles after signal deasserted.
BUFR Attributes Modes
Clock division BUFR controlled software through BUFR_DIVIDE attribute. Table lists possible values when using BUFR_DIVIDE attribute. Table 1-9: BUFR_DIVIDE Attribute
Description Defines whether output clock divided version input clock. Possible Values BYPASS (default)
Attribute Name BUFR_DIVIDE
Notes:
Location constraint available BUFR.
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Regional Clocking Resources
propagation delay through BUFR different BUFR_DIVIDE BUFR_DIVIDE BYPASS. When delay slightly more than BYPASS. other divisors have same delay BUFR_DIVIDE phase relationship between input clock output clock same possible divisions except BYPASS. timing relationship between inputs output BUFR when using BUFR_DIVIDE attribute illustrated Figure 1-21. this example, BUFR_DIVIDE attribute three. Sometime before this diagram asserted.
TBRDCK_CE
CLTBRCKO_O TBRDO_CLRO TBRCKO_O
UG070_1_21_030806
Figure 1-21:
BUFR Timing Diagrams with BUFR_DIVIDE Values
Figure 1-21: time TBRDCK_CE before clock event asserted High. Four clock cycles TBRCKO_O after asserted, output begins toggling divide three rate input TBRCKO_O other timing numbers best found speed specification. Note: duty cycle 50/50 division. pulse cycle longer. time event asserted. After TBRDO_CLRO from time event stops toggling. time event deasserted. time TBRCKO_O after clock event begins toggling again divided three rate
BUFR Models
BUFRs ideal source-synchronous applications requiring clock domain crossing serial-to-parallel conversion. Unlike BUFIOs, BUFRs capable clocking logic resources FPGAs other than IOBs. Figure 1-22 BUFR design example.
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Chapter Clock Resources
Adjacent Region
Tile Tile Tile Tile Tile Tile Tile CLBs CLBs CLBs CLBs CLBs CLBs CLBs CLBs Tile BUFIO BUFR Block Tile Block Tile
Clock Capable
Center Clock Capable
Tile CLBs CLBs CLBs CLBs CLBs CLBs CLBs CLBs Block Tile Block Tile
Tile Tile Tile Tile Tile Tile Tile
Adjacent Region
Figure 1-22: BUFR Driving Various Logic Resources
UG070_1_22_030708
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VHDL Verilog Templates
Regional Clock Nets
addition global clock trees nets, Virtex-4 devices contain regional clock nets. These clock trees also designed low-skew low-power operation. Unused branches disconnected. clock trees also manage load/fanout when logic resources used. Regional clock nets propagate throughout whole Virtex-4 device. Instead, they limited only clock region. clock region contains independent regional clock nets. access regional clock nets, BUFRs must instantiated. BUFR drive regional clocks adjacent clock regions (Figure 1-23). BUFRs bottom region only access adjacent region; below above respectively.
BUFRs
ug070_1_23_071404
Figure 1-23:
BUFR Driving Multiple Regions
VHDL Verilog Templates
VHDL Verilog code follows clocking resource primitives.
BUFGCTRL VHDL Verilog Templates
following examples illustrate instantiation BUFGCTRL module VHDL Verilog.
VHDL Template
-Example BUFGCTRL declaration component BUFGCTRL generic( INIT_OUT integer
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Chapter Clock Resources
PRESELECT_I0 boolean false; PRESELECT_I1 boolean false; port( std_ulogic; CE0: std_ulogic; CE1: std_ulogic; std_ulogic; std_ulogic; IGNORE0: std_ulogic; IGNORE1: std_ulogic; std_ulogic; std_ulogic component; -Example BUFGCTRL instantiation U_BUFGCTRL BUFGCTRL Port user_o, user_ce0, user_ce1, user_i0, user_i1, IGNORE0 user_ignore0, IGNORE1 user_ignore1, user_s0, user_s1 -Declaring constraints VHDL file attribute INIT_OUT integer; attribute PRESELECT_I0 boolean; attribute PRESELECT_I1 boolean; attribute string; attribute INIT_OUT U_BUFGCTRL: label attribute PRESELECT_I0 U_BUFGCTRL: label FALSE; attribute PRESELECT_I1 U_BUFGCTRL: label FALSE; attribute U_BUFGCTRL: label "BUFGCTRL_X#Y#"; -where valid integer locations BUFGCTRL
Verilog Template
//Example BUFGCTRL module declaration module BUFGCTRL CE0, CE1, IGNORE0, IGNORE1, S1); output input CE0; input CE1; input input input IGNORE0; input IGNORE1; input input parameter INIT_OUT parameter PRESELECT_I0 "FALSE"; parameter PRESELECT_I1 "FALSE";
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VHDL Verilog Templates
endmodule; //Example BUFGCTRL instantiation BUFGCTRL U_BUFGCTRL .O(user_o), .CE0(user_ce0), .CE1(user_ce1), .I0(user_i0), .I1(user_i1), .IGNORE0(user_ignore0), .IGNORE1(user_ignore1), .S0(user_s0), .S1(user_s1) Declaring constraints Verilog synthesis attribute INIT_OUT U_BUFGCTRL synthesis attribute PRESELECT_I0 U_BUFGCTRL FALSE; synthesis attribute PRESELECT_I1 U_BUFGCTRL FALSE; synthesis attribute U_BUFGCTRL "BUFGCTRL_X#Y#"; where valid integer locations BUFGCTRL
Declaring Constraints File
INST "U_BUFGCTRL" INIT_OUT INST "U_BUFGCTRL" PRESELECT_I0 FALSE; INST "U_BUFGCTRL" PRESELECT_I1 FALSE; INST "U_BUFGCTRL" BUFGCTRL_X#Y#; where valid integer locations BUFGCTRL
BUFG VHDL Verilog Templates
following examples illustrate instantiation BUFG module VHDL Verilog.
VHDL Template
-Example BUFG declaration component BUFG port( std_ulogic; std_ulogic component; -Example BUFG instantiation U_BUFG BUFG Port user_o, user_i -Declaring constraints VHDL file attribute string; attribute U_BUFG: label "BUFGCTRL_X#Y#"; -where valid integer locations BUFGCTRL
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Chapter Clock Resources
Verilog Template
//Example BUFG module declaration module BUFG output input endmodule; //Example BUFG instantiation BUFG U_BUFG .O(user_o), .I0(user_i) Declaring constraints Verilog synthesis attribute U_BUFG "BUFGCTRL_X#Y#"; where valid integer locations BUFGCTRL
Declaring Constraints File
INST "U_BUFG" BUFGCTRL_X#Y#; where valid integer locations BUFGCTRL
BUFGCE BUFGCE_1 VHDL Verilog Templates
following examples illustrate instantiation BUFGCE module VHDL Verilog. instantiation BUFGCE_1 exactly same BUFGCE with exception primitive name.
VHDL Template
-Example BUFGCE declaration component BUFGCE port( std_ulogic; std_ulogic; std_ulogic component; -Example BUFGCE instantiation U_BUFGCE BUFGCE Port user_o, user_ce, user_i -Declaring constraints VHDL file attribute string; attribute U_BUFGCE: label "BUFGCTRL_X#Y#"; -where valid integer locations BUFGCTRL
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VHDL Verilog Templates
Verilog Template
//Example BUFGCE module declaration module BUFGCE output input input endmodule; //Example BUFGCE instantiation BUFGCE U_BUFGCE .O(user_o), .CE0(user_ce), .I0(user_i) Declaring constraints Verilog synthesis attribute U_BUFGCE "BUFGCTRL_X#Y#"; where valid integer locations BUFGCTRL
Declaring Constraints File
INST "U_BUFGCE" BUFGCTRL_X#Y#; where valid integer locations BUFGCTRL
BUFGMUX BUFGMUX_1 VHDL Verilog Templates
following examples illustrate instantiation BUFGMUX module VHDL Verilog. instantiation BUFGMUX_1 exactly same BUFGMUX with exception primitive name.
VHDL Template
-Example BUFGMUX declaration component BUFGMUX port( std_ulogic; std_ulogic; std_ulogic; std_ulogic component; -Example BUFGMUX instantiation U_BUFGMUX BUFGMUX Port user_o, user_i0, user_i1, user_s -Declaring constraints VHDL file attribute string; attribute U_BUFGMUX: label "BUFGCTRL_X#Y#"; -where valid integer locations BUFGCTRL
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Chapter Clock Resources
Verilog Template
//Example BUFGMUX module declaration module BUFGMUX output input input input endmodule; //Example BUFGMUX instantiation BUFGMUX U_BUFGMUX .O(user_o), .I0(user_i0), .I1(user_i1), .S0(user_s) Declaring constraints Verilog synthesis attribute U_BUFGMUX "BUFGCTRL_X#Y#"; where valid integer locations BUFGCTRL
Declaring Constraints File
INST "U_BUFGMUX" BUFGCTRL_X#Y#; where valid integer locations BUFGCTRL
BUFGMUX_VIRTEX4 VHDL Verilog Templates
following examples illustrate instantiation BUFGMUX_VIRTEX4 module VHDL Verilog.
VHDL Template
-Example BUFGMUX_VIRTEX4 declaration component BUFGMUX_VIRTEX4 port( std_ulogic; std_ulogic; std_ulogic; std_ulogic component; -Example BUFGMUX_VIRTEX4 instantiation U_BUFGMUX_VIRTEX4 BUFGMUX_VIRTEX4 Port user_o, user_i0, user_i1, user_s
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-Declaring constraints VHDL file attribute attribute attribute attribute attribute attribute attribute attribute INIT_OUT integer; PRESELECT_I0 boolean; PRESELECT_I1 boolean; string; INIT_OUT U_BUFGMUX_VIRTEX4: label PRESELECT_I0 U_BUFGMUX_VIRTEX4: label FALSE; PRESELECT_I1 U_BUFGMUX_VIRTEX4: label FALSE; U_BUFGMUX_VIRTEX4: label "BUFGCTRL_X#Y#";
-where valid integer locations BUFGCTRL
Verilog Template
//Example BUFGMUX_VIRTEX4 module declaration module BUFGMUX_VIRTEX4 output input input input
parameter INIT_OUT 1'b0; parameter PRESELECT_I0 "TRUE"; parameter PRESELECT_I1 "FALSE"; endmodule; //Example BUFGCTRL instantiation BUFGMUX_VIRTEX4 U_BUFGMUX_VIRTEX4 .O(user_o), .I0(user_i0), .I1(user_i1), .S(user_s) Declaring constraints Verilog synthesis attribute INIT_OUT U_BUFGMUX_VIRTEX4 synthesis attribute PRESELECT_I0 U_BUFGMUX_VIRTEX4 FALSE; synthesis attribute PRESELECT_I1 U_BUFGMUX_VIRTEX4 FALSE; synthesis attribute U_BUFGMUX_VIRTEX4 "BUFGCTRL_X#Y#"; where valid integer locations BUFGCTRL
Declaring Constraints File
INST INST INST INST "U_BUFGMUX_VIRTEX4" "U_BUFGMUX_VIRTEX4" "U_BUFGMUX_VIRTEX4" "U_BUFGMUX_VIRTEX4" INIT_OUT PRESELECT_I0 FALSE; PRESELECT_I1 FALSE; BUFGCTRL_X#Y#;
where valid integer locations BUFGCTRL
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Chapter Clock Resources
BUFIO VHDL Verilog Templates
following examples illustrate instantiation BUFIO module VHDL Verilog.
VHDL Template
-Example BUFIO declaration component BUFIO port( std_ulogic; std_ulogic component; -Example BUFIO instantiation U_BUFIO BUFIO Port user_o, user_i -Declaring constraints VHDL file attribute string; attribute U_BUFIO: label "BUFIO_X#Y#"; -where valid integer locations BUFIO
Verilog Template
//Example BUFIO module declaration module BUFIO output input endmodule; //Example BUFIO instantiation BUFIO U_BUFIO .O(user_o), .I(user_i) Declaring constraints Verilog synthesis attribute U_BUFIO "BUFIO_X#Y#"; where valid integer locations BUFIO
Declaring Constraints File
INST "U_BUFIO" BUFIO_X#Y#; where valid integer locations BUFIO
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VHDL Verilog Templates
BUFR VHDL Verilog Templates
following examples illustrate instantiation BUFR module VHDL Verilog.
VHDL Template
-Example BUFR declaration component BUFR generic( BUFR_DIVIDE
string "BYPASS";
port( std_ulogic; std_ulogic; CLR: std_ulogic; std_ulogic component; -Example BUFR instantiation U_BUFR BUFR Port user_o, user_ce, user_clr, user_i -Declaring constraints VHDL file attribute attribute attribute attribute BUFR_DIVIDE string; string; INIT_OUT U_BUFR: label BYPASS; U_BUFR: label "BUFR_X#Y#";
-where valid integer locations
Verilog Template
//Example BUFR module declaration module BUFR CLR, output input input CLR; input parameter BUFR_DIVIDE "BYPASS"; endmodule; //Example BUFR instantiation BUFR U_BUFR .O(user_o), .CE(user_ce), .CLR(user_clr),
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Chapter Clock Resources
.I(user_i) Declaring constraints Verilog synthesis attribute BUFR_DIVIDE U_BUFR BYPASS; synthesis attribute U_BUFR "BUFR_X#Y#"; where valid integer locations
Declaring Constraints File
INST "U_BUFR" BUFR_DIVIDE=BYPASS; INST "U_BUFR" BUFR_X#Y#; where valid integer locations
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Chapter
Digital Clock Managers (DCMs)
Summary
Virtex®-4 FPGA Digital Clock Managers (DCMs) provide wide range powerful clock management features: Clock Deskew contains delay-locked loop (DLL) completely eliminate clock distribution delays, deskewing DCM's output clocks with respect input clock. contains delay elements (individual small buffers) control logic. incoming clock drives chain delay elements, thus output every delay element represents version incoming clock delayed different point. control logic contains phase detector delay-line selector. phase detector compares incoming clock signal (CLKIN) against feedback input (CLKFB) steers delay line selector, essentially adding delay output until CLKIN CLKFB coincide. Frequency Synthesis Separate outputs provide doubled frequency (CLK2X CLK2X180). Another output, CLKDV, provides frequency that specified fraction input frequency. other outputs, CLKFX CLKFX180, provide output frequency derived from input clock simultaneous frequency division multiplication. user specify integer multiplier divisor within range specified Timing Parameters section Virtex-4 Data Sheet. internal calculator determines appropriate selection, make output edge coincide with input clock whenever mathematically possible. example, multiply frequency 1.8, output rising edge coincident with input rising edge after every fifth input period, after every ninth output period. Phase Shifting allows coarse fine-grained phase shifting. coarse phase shifting uses 90°, 180°, 270° phases CLK0 make CLK90, CLK180, CLK270 clock outputs. 180° phase CLK2X CLKFX provide respective CLK2X180 CLKFX180 clock outputs. There also four modes fine-grained phase-shifting; fixed, variable-positive, variable-center, direct modes. Fine-grained phase shifting allows output clocks phase-shifted with respect CLKIN while maintaining relationship between coarse phase outputs. With fixed mode, fixed fraction phase shift defined during configuration multiples clock period divided 256. Using variable-positive variable-center modes phase dynamically repetitively moved forward backwards 1/256 clock period. With
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Chapter Digital Clock Managers (DCMs)
direct mode phase dynamically repetitively moved forward backwards value DCM_TAP. Timing Parameters section Virtex-4 Data Sheet. Dynamic Reconfiguration There connection change attributes without reconfiguring rest device. more information, Dynamic Reconfiguration chapter Virtex-4 Configuration Guide. DADDR[6:0], DI[15:0], DWE, DEN, DCLK inputs DO[15:0], DRDY outputs available dynamically reconfigure select functions. With dynamic reconfiguration, attributes changed select different phase shift, multiply divide from currently configured settings. Figure shows simplified view Virtex-4 FPGA center column resources including locations. Table summarizes availability DCMs each Virtex-4 device.
DCMs (Top Half) PMCDs (Top Half) I/Os BUFGCTRLs (Top Half) BUFGCTRLs (Bottom Half) I/Os PMCDs (Bottom Half) DCMs (Bottom Half)
UG070_2_01_030708
Virtex-4 FPGA Center Column
Figure 2-1:
Location
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Primitives
Table 2-1:
Available Resources
Device Available DCMs Site Names Bottom Half: DCM_ADV_X0Y0, DCM_ADV_X0Y1 Half: DCM_ADV_X0Y2, DCM_ADV_X0Y3 Bottom Half: DCM_ADV_X0Y0, DCM_ADV_X0Y1, DCM_ADV_X0Y2 Half: DCM_ADV_X0Y3, DCM_ADV_X0Y4, DCM_ADV_X0Y5, DCM_ADV_X0Y6, DCM_ADV_X0Y7 Bottom Half: DCM_ADV_X0Y0, DCM_ADV_X0Y1, DCM_ADV_X0Y2, DCM_ADV_X0Y3, DCM_ADV_X0Y4, DCM_ADV_X0Y5 Half: DCM_ADV_X0Y6, DCM_ADV_X0Y7, DCM_ADV_X0Y8, DCM_ADV_X0Y9, DCM_ADV_X0Y10, DCM_ADV_X0Y11
XC4VLX15 XC4VSX25 XC4VFX12, XC4VFX20 XC4VLX25, XC4VLX40, XC4VLX60 XC4VSX35, XC4VSX55 XC4VFX40
XC4VLX80, XC4VLX100, XC4VLX160, XC4VLX200 XC4VFX60, XC4VFX100
XC4VFX140
Bottom Half: DCM_ADV_X0Y0, DCM_ADV_X0Y1, DCM_ADV_X0Y2, DCM_ADV_X0Y3, DCM_ADV_X0Y4, DCM_ADV_X0Y5, DCM_ADV_X0Y6, DCM_ADV_X0Y7, DCM_ADV_X0Y8, DCM_ADV_X0Y9 Half: DCM_ADV_X0Y10, DCM_ADV_X0Y11 DCM_ADV_X0Y12, DCM_ADV_X0Y13 DCM_ADV_X0Y14, DCM_ADV_X0Y15 DCM_ADV_X0Y16, DCM_ADV_X0Y17 DCM_ADV_X0Y18, DCM_ADV_X0Y19
Primitives
Three primitives available: DCM_BASE, DCM_PS, DCM_ADV (see Figure 2-2).
DCM_BASE
CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 LOCKED
DCM_PS
CLKIN CLKFB CLK0 CLK90 CLK180 CLK270
DCM_ADV
CLKIN CLKFB CLK0 CLK90 CLK180 CLK270
PSINCDEC CLK2X PSEN CLK2X180 PSCLK CLKDV CLKFX CLKFX180 LOCKED PSDONE DO[15:0]
PSINCDEC CLK2X PSEN CLK2X180 PSCLK CLKDV DADDR[6:0] CLKFX DI[15:0] CLKFX180 LOCKED DCLK PSDONE DO[15:0] DRDY
UG070_2_02_080204
Figure 2-2:
Primitives
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Chapter Digital Clock Managers (DCMs)
DCM_BASE Primitive
DCM_BASE primitive accesses basic frequently used features simplifies user-interface ports. clock deskew, frequency synthesis, fixed-phase shifting features available with DCM_BASE. Table lists available ports DCM_BASE primitive. Table 2-2: DCM_BASE Primitive
Port Names CLKIN, CLKFB CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV, CLKFX, CLKFX180 LOCKED
Available Ports Clock Input Control Data Input Clock Output Status Data Output
DCM_PS Primitive
DCM_PS primitive accesses features ports available DCM_BASE plus additional ports used variable phase shifting feature. DCM_PS also following available features: clock deskew, frequency synthesis, fixed variable phase-shifting. Table lists available ports DCM_PS primitive. Table 2-3: DCM_PS Primitive
Port Names CLKIN, CLKFB, PSCLK RST, PSINCDEC, PSEN CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV, CLKFX, CLKFX180 LOCKED, PSDONE, DO[15:0]
Available Ports Clock Input Control Data Input Clock Output Status Data Output
DCM_ADV Primitive
DCM_ADV primitive access features ports available DCM_PS plus additional ports dynamic reconfiguration feature. superset other primitives. DCM_ADV uses features including clock deskew, frequency synthesis, fixed variable phase shifting, dynamic reconfiguration. Table lists available ports DCM_ADV primitive. Table 2-4: DCM_ADV Primitive
Port Names CLKIN, CLKFB, PSCLK, DCLK RST, PSINCDEC, PSEN, DADDR[6:0], DI[15:0], DWE, CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV, CLKFX, CLKFX180 LOCKED, PSDONE, DO[15:0], DRDY
Available Ports Clock Input Control Data Input Clock Output Status Data Output
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Ports
Ports
There four types ports available Virtex-4 architecture: Clock Input Ports Control Data Input Ports Clock Output Ports Status Data Output Ports
Clock Input Ports
Source Clock Input CLKIN
source clock (CLKIN) input provides source clock DCM. CLKIN frequency must fall ranges specified Virtex-4 Data Sheet. clock input signal comes from following buffers: IBUFG Global Clock Input Buffer compensates clock input path when IBUFG same edge (top bottom) device used. BUFGCTRL Internal Global Clock Buffer BUFGCTRL drive Virtex-4 device using dedicated global routing. BUFGCTRL drive CLKIN when used connect DCMs series. IBUF Input Buffer When IBUF drives CLKIN input, input skew compensated.
Feedback Clock Input CLKFB
feedback clock (CLKFB) input provides reference feedback signal delay-compensate clock outputs, align them with clock input. provide necessary feedback DCM, connect only CLK0 output CLKFB pin. When CLKFB connected, clock outputs deskewed CLKIN. When CLKFB connected, clock outputs deskewed CLKIN. However, relative phase relationship between output clocks preserved. During internal feedback configuration, CLK0 output connects global buffer same bottom half device. output global buffer connects CLKFB input same DCM. During external feedback configuration, following rules apply: forward clock, CLK0 must directly drive OBUF BUFGto-DDR configuration. External FPGA, forwarded clock signal must connected IBUFG (GCLK pin) IBUF driving CLKFB DCM. Both CLKFB should have identical buffers.
Figure Figure 2-10, "Application Examples," page illustrate clock forwarding with external feedback configuration. feedback clock input signal driven following buffers:
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Chapter Digital Clock Managers (DCMs)
IBUFG Global Clock Input Buffer This preferred source external feedback configuration. When IBUFG drives CLKFB same bottom half device, skew compensated deskew.
BUFGCTRL Internal Global Clock Buffer This internal feedback configuration. IBUF Input Buffer This external feedback configuration. When IBUF used, input skew compensated.
Phase-Shift Clock Input PSCLK
phase-shift clock (PSCLK) input provides source clock phase shift. PSCLK asynchronous phase frequency) CLKIN. phase-shift clock signal driven clock source (external internal), including: IBUF Input Buffer IBUFG Global Clock Input Buffer access dedicated routing, only IBUFGs same edge device (top bottom) used drive PSCLK input DCM. BUFGCTRL Internal Global Buffer Internal Clock internal clock using general purpose routing.
frequency range PSCLK defined PSCLK_FREQ_LF/HF (see Virtex-4 Data Sheet). This input must tied ground when CLKOUT_PHASE_SHIFT attribute NONE FIXED.
Dynamic Reconfiguration Clock Input DCLK
dynamic reconfiguration clock (DCLK) input provides source clock DCM's dynamic reconfiguration circuit. frequency DCLK asynchronous phase frequency) CLKIN. dynamic reconfiguration clock signal driven clock source (external internal), including: IBUF Input Buffer IBUFG Global Clock Input Buffer Only IBUFGs same edge device (top bottom) used drive CLKIN input DCM. BUFGCTRL Internal Global Buffer Internal Clock internal clock using general purpose routing.
frequency range DCLK described Virtex-4 Data Sheet. When dynamic reconfiguration used, this input must tied ground. dynamic reconfiguration chapter Virtex-4 Configuration Guide more information.
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Ports
Control Data Input Ports
Reset Input
reset (RST) input resets circuitry. signal active High asynchronous reset. Asserting signal asynchronously forces outputs (the LOCKED signal, status signals, output clocks) after some propagation delay. When reset asserted, last cycle clocks exhibit short pulse severely distorted duty-cycle, longer deskewed with respect another while deasserting Low. Deasserting signal starts locking process next CLKIN cycle. ensure proper reset locking process, signal must held until CLKIN CLKFB signals present stable least (The requirement CLKFB only applies when external feedback used.) time takes lock after reset specified Virtex-4 Data Sheet LOCK_DLL (for output) LOCK_FX (for output). These CLKFX outputs described "Clock Output Ports". locks faster higher frequencies. worse-case numbers specified Virtex-4 Data Sheet. designs, must held reset until CLKIN stable.
Phase-Shift Increment/Decrement Input PSINCDEC
phase-shift increment/decrement (PSINCDEC) input signal must synchronous with PSCLK. PSINCDEC input signal used increment decrement phaseshift factor when PSEN activated. result, output clocks shifted. PSINCDEC signal asserted High increment deasserted decrement. This input must tied ground when CLKOUT_PHASE_SHIFT attribute NONE FIXED.
Phase-Shift Enable Input PSEN
phase-shift enable (PSEN) input signal must synchronous with PSCLK. variable phase-shift operation initiated PSEN input signal. must activated period PSCLK. After PSEN initiated, phase change gradual with completion indicated High pulse PSDONE. There sporadic changes glitches output during phase transition. From time PSEN enabled until PSDONE flagged, output clock moves bit-by-bit from original phase shift target phase shift. phase shift complete when PSDONE flagged. PSEN must tied ground when CLKOUT_PHASE_SHIFT attribute NONE FIXED. Figure shows timing this input.
Dynamic Reconfiguration Data Input DI[15:0]
dynamic reconfiguration data (DI) input provides reconfiguration data dynamic reconfiguration. When used, bits must assigned zeros. Dynamic Reconfiguration chapter Virtex-4 Configuration Guide more information.
Dynamic Reconfiguration Address Input DADDR[6:0]
dynamic reconfiguration address (DADDR) input provides reconfiguration address dynamic reconfiguration. When used, bits must assigned zeros. output will reflect DCM's status. Dynamic Reconfiguration chapter Virtex-4 Configuration Guide more information.
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Chapter Digital Clock Managers (DCMs)
Dynamic Reconfiguration Write Enable Input
dynamic reconfiguration write enable (DWE) input provides write enable control signal write data into DADDR address. When used, must tied Low. Dynamic Reconfiguration chapter Virtex-4 Configuration Guide more information.
Dynamic Reconfiguration Enable Input
dynamic reconfiguration enable (DEN) input provides enable control signal access dynamic reconfiguration feature. When dynamic reconfiguration feature used, must tied Low. When tied Low, reflects status signals. Dynamic Reconfiguration chapter Virtex-4 Configuration Guide more information.
Clock Output Ports
provides nine clock outputs with specific frequency phase relationships. When CLKFB connected, clock outputs have fixed phase relationship CLKIN. When CLKFB connected, outputs phase aligned. However, phase relationship between output clocks preserved.
Output Clock CLK0
CLK0 output clock provides clock with same frequency DCM's effective CLKIN frequency. default, effective input clock frequency equal CLKIN frequency. CLKIN_DIVIDE_BY_2 attribute TRUE make effective CLKIN frequency actual CLKIN frequency. CLKIN_DIVIDE_BY_2 Attribute description provides further information. When CLKFB connected, CLK0 phase aligned CLKIN.
Output Clock, Phase Shift CLK90
CLK90 output clock provides clock with same frequency DCM's CLK0 only phase-shifted 90°.
Output Clock, 180° Phase Shift CLK180
CLK180 output clock provides clock with same frequency DCM's CLK0 only phase-shifted 180°.
Output Clock, 270° Phase Shift CLK270
CLK270 output clock provides clock with same frequency DCM's CLK0 only phase-shifted 270°.
Output Clock CLK2X
CLK2X output clock provides clock that phase aligned CLK0, with twice CLK0 frequency, with automatic 50/50 duty-cycle correction. Until locked, CLK2X output appears version input clock with 25/75 duty cycle. This behavior allows lock correct edge with respect source clock.
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Ports
Output Clock, 180° Phase Shift CLK2X180
CLK2X180 output clock provides clock with same frequency DCM's CLK2X only phase-shifted 180°.
Frequency Divide Output Clock CLKDV
CLKDV output clock provides clock that phase aligned CLK0 with frequency that fraction effective CLKIN frequency. fraction determined CLKDV_DIVIDE attribute. Refer CLKDV_DIVIDE Attribute more information.
Frequency-Synthesis Output Clock CLKFX
CLKFX output clock provides clock with following frequency definition: CLKFX frequency (M/D) effective CLKIN frequency this equation, multiplier (numerator) with value defined CLKFX_MULTIPLY attribute. divisor (denominator) with value defined CLKFX_DIVIDE attribute. Specifications well input output frequency ranges frequency synthesizer, provided Virtex-4 Data Sheet. rising edge CLKFX output phase aligned rising edges CLK0, CLK2X, CLKDV. When have common factor, alignment occurs only once every cycles CLK0.
Frequency-Synthesis Output Clock, 180° CLKFX180
CLKFX180 output clock provides clock with same frequency DCM's CLKFX only phase-shifted 180°.
Status Data Output Ports
Locked Output LOCKED
LOCKED output indicates whether clock outputs valid, i.e., outputs exhibit proper frequency phase. After reset, samples several thousand clock cycles achieve lock. After achieves lock, LOCKED signal asserted High. timing parameters section Virtex-4 Data Sheet provides estimates locking times. guarantee established system clock start-up cycle, delay completion device configuration process until after locked. STARTUP_WAIT attribute activates this feature. STARTUP_WAIT Attribute description provides further information. Until LOCKED signal asserted High, output clocks valid exhibit glitches, spikes, other spurious movement. particular, CLK2X output appears clock with 25/75 duty cycle.
Phase-Shift Done Output PSDONE
phase-shift done (PSDONE) output signal synchronous PSCLK. completion requested phase shift, PSDONE pulses High period PSCLK. This signal also indicates change phase shift initiated. PSDONE output signal valid phase-shift feature being used fixed mode.
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Chapter Digital Clock Managers (DCMs)
Status Dynamic Reconfiguration Data Output DO[15:0]
output provides status data output when using dynamic reconfiguration (Table 2-5). Further information using data output available Dynamic Reconfiguration chapter Virtex-4 Configuration Guide more information. dynamic reconfiguration port used, using DCM_BASE DCM_PS instead DCM_ADV strongly recommended. Table 2-5:
DO[0]
Status Mapping
Status Phase-shift overflow Description Asserted when phase-shifted beyond allowed phase-shift value when absolute delay range phase-shift delay line exceeded. Asserted when input clock stopped (CLKIN remains High more clock cycles). When CLKIN stopped, DO[1] CLKIN stopped status asserted within nine CLKIN cycles. When CLKIN restarted, CLK0 starts toggling DO[1] deasserted within nine clock cycles. Asserted when CLKFX stops. DO[2] CLKFX stopped status asserted within CLKIN cycles after CLKFX stopped. CLKFX will resume, DO[2] deasserted until reset. Asserted when feedback clock stopped (CLKFB remains High more clock cycles). DO[3] CLKFB stopped status asserted within CLKIN cycles after CLKFB stopped. CLKFB stopped deasserted within CLKIN cycles when CLKFB resumes after being stopped momentarily. occasionally skipped CLKFB will affect operation. However, stopping CLKFB long time result losing LOCKED. When LOCKED lost, needs reset resume operation.
DO[1]
CLKIN stopped
DO[2]
CLKFX stopped
DO[3]
CLKFB stopped
DO[15:4]
assigned
When LOCKED (during reset locking process), status signals deassert Low.
Dynamic Reconfiguration Ready Output DRDY
dynamic reconfiguration ready (DRDY) output provides response signal DCM's dynamic reconfiguration feature. Further information DRDY available dynamic reconfiguration section Virtex-4 Configuration Guide.
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Attributes
Attributes
handful attributes govern functionality. Table summarizes applicable attributes. This section provides detailed description each attribute. more information applying these attributes UCF, VHDL, Verilog code, refer Constraints Guide Table 2-6: Attributes
Description Determines type feedback applied CLKFB.
Controls CLKDV such that source clock divided This feature provides automatic duty cycle correction such that CLKDV output 50/50 duty cycle always low-frequency mode, well integer values division factor high-frequency mode. CLKFX_DIVIDE Sets divisor value CLKFX. CLKFX frequency equals effective CLKIN frequency multiplied M/D. Sets multiply CLKFX. CLKFX frequency equals effective CLKIN frequency multiplied M/D. Allows input clock frequency divided half when necessary meet input clock frequency requirements. Specifies source clock period help adjust optimum CLKFX/CLKFX180 outputs. Specifies phase-shift mode.
Attribute Name CLK_FEEDBACK
CLKDV_DIVIDE
Values String: "1X" "NONE"
Real: 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5,
Default Value
Integer:
CLKFX_MULTIPLY
Integer:
CLKIN_DIVIDE_BY_2
Boolean: FALSE TRUE
FALSE
CLKIN_PERIOD
Real
CLKOUT_PHASE_SHIFT
String: "NONE", "FIXED", "VARIABLE_POSITIVE", "VARIABLE_CENTER", "DIRECT"
NONE
Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
www.xilinx.com
Chapter Digital Clock Managers (DCMs)
Table 2-6:
Attributes (Continued)
Description When this attribute TRUE, protected from effects negative bias temperature instability (NBTI). This attribute cannot FALSE unless CLKIN CLKFB external feedback used) guaranteed never stop. macro also disabled user guarantee hold reset during clock stoppage. this attribute FALSE, reset requirement three clock cycles.
Allows selection between maximum frequency/ minimum jitter frequency/maximum phase-shift range. Affects amount delay feedback path, should used source-synchronous interfaces. Specifies frequency mode frequency synthesizer. Specifies frequency mode DLL. Controls outputs (CLK0, CLK90, CLK180, CLK270), exhibit 50/50 duty cycle. Leave this attribute default value. Controls update rate. Value depends DLL_FREQUENCY_MODE setting. Specifies phase-shift numerator. value range depends CLKOUT_PHASE_SHIFT clock frequency. When this attribute TRUE, configuration startup sequence waits specified cycle until locks.
Attribute Name DCM_AUTOCALIBRATION
Values
Boolean: TRUE FALSE
Default Value
TRUE
DCM_PERFORMANCE_MODE
String: "MAX_SPEED" "MAX_RANGE"
MAX_SPEED
DESKEW_ADJUST
String: "SYSTEM_SYNCHRONOUS" "SOURCE_SYNCHRONOUS" String: "LOW" "HIGH" String: "LOW" "HIGH" Boolean: TRUE FALSE
SYSTEM_ SYNCHRONOUS
DFS_FREQUENCY_MODE DLL_FREQUENCY_MODE DUTY_CYCLE_CORRECTION
TRUE
FACTORY_JF
BIT_VECTO
F0F0
PHASE_SHIFT
Integer: -255 1023 Boolean: FALSE TRUE
STARTUP_WAIT
FALSE
CLK_FEEDBACK Attribute
CLK_FEEDBACK attribute determines type feedback applied CLKFB. possible values NONE. default value When this attribute CLKFB must driven CLK0. When this attribute NONE, CLKFB must unconnected.
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Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
Attributes
CLKDV_DIVIDE Attribute
CLKDV_DIVIDE attribute controls CLKDV frequency. source clock frequency divided value this attribute. possible values CLKDV_DIVIDE are: 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, default value frequency mode, CLKDV_DIVIDE value produces CLKDV output with 50/50 duty-cycle. high frequency mode, CLKDV_DIVIDE value must integer value produce CLKDV output with 50/50 duty-cycle. non-integer CLKDV_DIVIDE values, CLKDV output duty cycle shown Table 2-7. Table 2-7: Non-Integer CLKDV_DIVIDE
CLKDV Duty Cycle High Frequency Mode (High Pulse/Low Pulse Value) 5/11 6/13 7/15
CLKDV_DIVIDE Value
CLKFX_MULTIPLY CLKFX_DIVIDE Attributes
CLKFX_MULTIPLY attribute sets multiply value CLKFX output. CLKFX_DIVIDE attribute sets divisor value CLKFX output. Both control CLKFX output making CLKFX frequency equal effective CLKIN (source clock) frequency multiplied M/D. possible values integer from possible values integer from default settings
CLKIN_DIVIDE_BY_2 Attribute
CLKIN_DIVIDE_BY_2 attribute used enable toggle flip-flop input clock path DCM. When FALSE, effective CLKIN frequency equals source clock frequency driving CLKIN input. When TRUE, CLKIN frequency divided before reaches rest DCM. Thus, sees half frequency applied CLKIN input operates based this frequency. example, clock drives CLKIN, CLKIN_DIVIDE_BY_2 TRUE; then effective CLKIN frequency MHz. Thus, CLK0 output CLK2X output MHz. effective CLKIN frequency must used evaluate operation specification derived from CLKIN frequency. possible values CLKIN_DIVIDE_BY_2 TRUE FALSE. default value FALSE.
CLKIN_PERIOD Attribute
CLKIN_PERIOD attribute specifies source clock period nanoseconds). default value
Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
www.xilinx.com
Chapter Digital Clock Managers (DCMs)
CLKOUT_PHASE_SHIFT Attribute
CLKOUT_PHASE_SHIFT attribute indicates mode phase shift applied outputs. possible values NONE, FIXED, VARIABLE_POSITIVE, VARIABLE_CENTER, DIRECT. default value NONE. When NONE, phase shift cannot performed phase-shift value effect outputs. When FIXED, outputs phase-shifted fixed phase from CLKIN. phase-shift value determined PHASE_SHIFT attribute. CLKOUT_PHASE_SHIFT attribute FIXED NONE, then PSEN, PSINCDEC, PSCLK inputs must tied ground. When VARIABLE_POSITIVE, outputs phase-shifted variable mode positive range with respect CLKIN. When VARIABLE_CENTER, outputs phase-shifted variable mode, positive negative range with respect CLKIN. VARIABLE_POSITIVE VARIABLE_CENTER, each phase-shift increment decrement) will increase decrease) phase shift period 1/256 CLKIN period. When DIRECT, output phase-shifted variable mode positive range with respect CLKIN. Each phase-shift increment/decrement will increase/decrease phase shift DCM_TAP (see Virtex-4 Data Sheet). starting phase VARIABLE_POSITIVE VARIABLE_CENTER modes determined phase-shift value. starting phase DIRECT mode always zero, regardless value specified PHASE_SHIFT attribute. Thus, PHASE_SHIFT attribute should zero when DIRECT mode used. non-zero phase-shift value DIRECT mode loaded using Dynamic Reconfiguration Ports Virtex-4 Configuration Guide.
DCM_AUTOCALIBRATION Attribute
autocalibration block protects from effects negative bias temperature instability (NBTI). This attribute cannot FALSE unless user guarantees that CLKIN CLKFB external feedback used) never stop. macro also disabled user guarantee that held reset when clocks stopped. this attribute FALSE, reset requirement three clock cycles.
DCM_PERFORMANCE_MODE Attribute
DCM_PERFORMANCE_MODE attribute allows choice optimizing either high frequency jitter frequency wide phase-shift range. attribute values MAX_SPEED MAX_RANGE. default value MAX_SPEED. When MAX_SPEED, optimized produce high frequency clocks with jitter. However, phase-shift range smaller than when MAX_RANGE selected. When MAX_RANGE, optimized produce frequency clocks with wider phase-shift range. DCM_PERFORMANCE_MODE affects following specifications: input output frequency range, phase-shift range, output jitter, DCM_TAP, CLKIN_CLKFB_PHASE, CLKOUT_PHASE, dutycycle precision. Virtex-4 Data Sheet specifies these values. most cases, DCM_PERFORMANCE_MODE attribute should MAX_SPEED (default). Consider changing MAX_RANGE only these situations: frequency needs below frequency limit MAX_SPEED setting. greater absolute phase-shift range required.
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Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
Attributes
DESKEW_ADJUST Attribute
DESKEW_ADJUST attribute affects amount delay feedback path. possible values SYSTEM_SYNCHRONOUS, SOURCE_SYNCHRONOUS, default value SYSTEM_SYNCHRONOUS. most designs, default value appropriate. source-synchronous design, this attribute SOURCE_SYNCHRONOUS. remaining values should only used after consulting with Xilinx. more information consult "Source-Synchronous Setting"section.
DFS_FREQUENCY_MODE Attribute
DFS_FREQUENCY_MODE attribute specifies frequency mode digital frequency synthesizer (DFS). possible values HIGH. default value LOW. frequency ranges both frequency modes specified Virtex-4 Data Sheet. DFS_FREQUENCY_MODE determines frequency range CLKIN, CLKFX, CLKFX180.
DLL_FREQUENCY_MODE Attribute
DLL_FREQUENCY_MODE attribute specifies either HIGH frequency mode delay-locked loop (DLL). default value LOW. frequency ranges both frequency modes specified Virtex-4 Data Sheet.
DUTY_CYCLE_CORRECTION Attribute
DUTY_CYCLE_CORRECTION attribute controls duty cycle correction clock outputs: CLK0, CLK90, CLK180, CLK270. possible values TRUE FALSE. default value TRUE. When TRUE, clock outputs duty cycle corrected within specified limits (see Virtex-4 Data Sheet details). strongly recommended always DUTY_CYCLE_CORRECTION attribute TRUE. Setting this attribute FALSE does necessarily produce output clocks with same duty cycle source clock.
FACTORY_JF Attribute
Factory_JF attribute affects DCMs jitter filter characteristics. This attribute controls update rate. Factory_JF must specific value depending DLL_FREQUENCY_MODE setting. default value F0F0 corresponding DLL_FREQUENCY_MODE (default). Factory_JF must manually F0F0 when DLL_FREQUENCY_MODE HIGH. ISE® software tool will issue warning FACTORY_JF stated.
PHASE_SHIFT Attribute
PHASE_SHIFT attribute determines amount phase shift applied outputs. This attribute used both fixed variable phase-shift mode. used with variable mode, attribute sets starting phase shift. When CLKOUT_PHASE_SHIFT VARIABLE_POSITIVE, PHASE_SHIFT value range 255. When CLKOUT_PHASE_SHIFT VARIABLE_CENTER FIXED, PHASE_SHIFT value range -255 255. When CLKOUT_PHASE_SHIFT DIRECT, PHASE_SHIFT value range 1023. default value
Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
www.xilinx.com
Chapter Digital Clock Managers (DCMs)
Refer "Phase Shifting," page information phase-shifting operation relationship with CLKOUT_PHASE_SHIFT PHASE_SHIFT attributes.
STARTUP_WAIT Attribute
STARTUP_WAIT attribute determines whether waits startup cycles lock. possible values this attribute TRUE FALSE. default value FALSE. When STARTUP_WAIT TRUE, LCK_cycle BitGen option used, then configuration startup sequence waits startup cycle specified LCK_cycle until locked.
Design Guidelines
This section provides detailed guidelines using Virtex-4 FPGA DCM.
Clock Deskew
Virtex-4 FPGA offers fully digital, dedicated, on-chip clock deskew. deskew feature provides zero propagation delay between source clock output clock, clock skew among output clock signals distributed throughout device, advanced clock domain control. deskew feature also functions clock mirror board-level clock serving multiple devices. This achieved driving CLK0 output off-chip board (and other devices board) then bringing clock back feedback clock. "Application Examples" section. Taking advantage deskew feature greatly simplifies improves system-level design involving high-fanout, high-performance clocks.
Clock Deskew Operation
deskew feature utilizes circuit DCM. simplest form, consists single variable delay line (containing individual small delay elements buffers) control logic. incoming clock drives delay line. output every delay element represents version incoming clock (CLKIN) delayed different point. clock distribution network routes clock internal registers clock feedback CLKFB pin. control logic contains phase detector delay-line selector. phase detector compares incoming clock signal (CLKIN) against feedback input (CLKFB) steers delay-line selector, essentially adding delay output until CLKIN CLKFB coincide, putting clocks 360° out-ofphase, (thus, phase). When edges from input clock line with edges from feedback clock, achieves lock. clocks have discernible difference. Thus, output clock compensates delay clock distribution network, effectively removing delay between source clock loads. size each intrinsic delay element DCM_TAP (see Characteristics table Virtex-4 Data Sheet). Figure illustrates simplified circuit.
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Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
Design Guidelines
CLKIN
Variable Delay Line
CLKOUT
Clock Distribution Network
Control CLKFB
UG070_2_03_060508
Figure 2-3:
Simplified Circuit
provide correct clock deskew, depends dedicated routing resources used clock source feedback input. additional delay element (see "Deskew Adjust") available compensate clock source feedback path. tools analyze routing around determine delay must inserted compensate clock source feedback path. Thus, using dedicated routing required achieve predictable deskew. nine output clocks deskewed when CLKFB used.
Input Clock Requirements
clock input driven either IBUFG/IBUFGDS, IBUF, BUFGMUX, BUFGCNTL. Since there dedicated routing between IBUF clock input, using IBUF causes additional input delay that compensated DCM. output clock signal essentially delayed version input clock signal. reflects instability input clock output waveform. input clock requirements specified Virtex-4 Data Sheet. Once locked, tolerate input clock period variations value specified CLKIN_PER_JITT_DLL_HF high frequencies) CLKIN_PER_JITT_DLL_LF frequencies). Larger jitter (period changes) cause lose lock, indicated LOCKED output deasserting. user must then reset DCM. cycle-to-cycle input jitter must kept less than CLKIN_CYC_JITT_DLL_LF frequencies CLKIN_CYC_JITT_DLL_HF high frequencies.
Input Clock Changes
Changing period input clock beyond maximum input period jitter specification requires manual reset DCM. Failure reset produces unreliable LOCKED signal output clock. possible temporarily stop input clock feedback clock with little impact deskew circuit, long CLKFX CLKFX180 used. input clock stopped CLKFX CLKFX180 used, CLKFX CLKFX180 outputs might stop toggling, DO[2] (CLKFX Stopped) asserted. must reset recover from this event. DO[2] CLKFX stopped status asserted CLKIN cycles after CLKFX stopped. CLKFX does resume DO[2] will deassert until reset. other case, clock should stopped more than minimize effect device cooling; otherwise, delays might change. clock should stopped during High phase, must restored with same input clock period/frequency. During this time, LOCKED stays High remains High when
Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
www.xilinx.com
Chapter Digital Clock Managers (DCMs)
clock restored. Thus, High LOCKED does necessarily mean that valid clock available. When stopping input clock (CLKIN remains High more clock cycles), nine more output clock cycles still generated delay line flushed. When output clock stops, CLKIN stopped (DO[1]) signal asserted. When clock restarted, output clock cycles generated eight clocks while delay line filled. Similarly, DO[1] signal deasserted once output clock generated. most common case three clocks. CLKIN restarted with phase relationship previous clock. frequency changed, requires reset. DO[1] forced whenever LOCKED Low. When locking process, DO[1] status held until LOCKED achieved.
Output Clocks
DCM's nine clock outputs used drive global clock network. fully-buffered global clock distribution network minimizes clock skew caused loading differences. monitoring sample output clock (CLK0), deskew circuit compensates delay routing network, effectively eliminating delay from external input port individual clock loads within device. outputs drive general interconnect; however, these connections suitable critical clock signals. recommended that clock signals should within global regional clock network. Refer Chapter "Clock Resources" more information using clock networks. Output connectivity carries some restrictions. clock outputs each drive OBUF, global clock buffer BUFGCTRL, they route directly clock input synchronous element. dedicated routing, clock outputs must drive BUFGCTRLs same bottom half device. BUFGCTRL same bottom half, local routing used might deskew properly. output clock signals until after activation LOCKED signal. Prior activation LOCKED signal, output clocks valid.
During Configuration Startup
During FPGA configuration, reset starts lock beginning startup sequence. requires both CLKIN CLKFB input clocks present stable when begins lock. device enters configuration startup sequence without input clock, with unstable input clock, then must reset after configuration with stable clock. following startup cycle dependencies note: default value LCK_cycle:NoWait. When this setting used, startup sequence does wait lock. WHen LCK_cycle other values, configuration startup remains specified startup cycle until locked. Before setting LCK_cycle option startup cycle BitGen, DCM's STARTUP_WAIT attribute must TRUE. startup sequence altered using BitGen option), place LCK_cycle (wait lock) before GTS_cycle (deassert GTS). Incorrect implementation will result locking incomplete configuration.
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Virtex-4 FPGA User Guide UG070 (v2.6) December 2008
Design Guidelines
Deskew Adjust
DESKEW_ADJUST attribute sets value configurable, variable-tap delay element control amount delay added feedback path (see Figure 2-4).
Data Input
VCCO
Into FPGA
Source IBUFG
CLKIN CLKFB Power Regulator VCCAUX CLK0
Feedback Delays System-Synchronous Default Setting Source-Synchronous Setting (Delay zero) VCCINT
UG070_2_04_060608
Figure 2-4:
Feedback Tap-Delay Elements
This delay element allows adjustment effective clock delay between clock source CLK0 guarantee non-positive hold times input flip-flop device. Adding more delay feedback path decreases effective delay actual clock path from FPGA clock input clock input flip-flop. Decreasing clock delay increases setup time represented input flip-flop, reduces positive hold times required. clock path delay includes delay through IBUFG, route, DCM, BUFG, clock-tree destination flip-flop. feedback delay equals clock-path delay, effective clock-path delay zero.
System-Synchronous Setting (Default)
default, feedback delay system-synchronous mode. primary timing requirements system-synchronous system non-positive hold times minimally positive hold times) minimal clock-to-out setup times. Faster clock-to-out setup times allow shorter system clock periods. Ideally, purpose zero-out clock delay produce faster clock-to-out non-positive hold times. systemsynchronous setting (default) DESKEW_ADJUST configures feedback delay element guarantee non-positive hold times input registers. exact delay number added feedback path device size dependent. This determined characterization. timing report, this included timing reduction input clock path represented TDCMINO parameter. shown Figure 2-4, feedback path includes delays default setting (red line). pin-to-pin timing parameters (with DCM) Virtex-4 Data Sheet reflects setup/hold clock-to-out times when system-synchronous mode.
Virte
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