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Virtex-II System Wake-Up Solutions
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Revision History
following table shows revision history this document.
Date 03/08/02 08/13/07 Version Initial Xilinx release. Updated format completed other minor edits. Removed obsolete products from System family. Replaced mature XC18V00 XC17V00 PROM families with Platform Flash PROM. Revision
UG028 (v1.1) August 2007
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Virtex-II System Wake-Up Solutions
Virtex-II System Wake-Up Solutions
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UG028 (v1.1) August 2007
Table Contents
Preface: About This Guide
Guide Contents Additional Resources Conventions
Typographical Online Document
Chapter Managing Hardware Software Data with Virtex-II Devices
Overview
System (CompactFlash) Solution Xilinx PROMs External Non-Volatile Memory
Chapter Basic Advanced Virtex-II Wake-Up Solutions
Basic Virtex-II Wake-Up Solution
Overview Basic System Architecture. Basic Solution Wake-Up Flow Basic Software Flow Overview Advanced System Architecture Advanced Solution Wake-Up Flow. Virtex-II JTAG Test Access Port (TAP) Advanced Software Flow
Advanced Virtex-II Wake-Up Solution
Virtex-II System Wake-Up Solutions UG028 (v1.1) August 2007
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Virtex-II System Wake-Up Solutions UG028 (v1.1) August 2007
Preface
About This Guide
VirtexTM-II Platform FPGA solution powerful system solution with numerous advanced features, including PowerPCprocessors RocketIOmulti-gigabit transceiver blocks. advanced features introduce options that need considered when selecting customized system wake-up solution. system wake-up process necessary bring Virtex-II devices operational stage system application typically consists steps, configuring FPGA logic booting PowerPC processor successful system operation. Virtex-II PowerPC (PPC) microprocessor initialized part system wake-up. This document briefly describes various options available system wakeup highlights most efficient solutions basic advanced systems.
Guide Contents
This manual contains following chapters: Chapter "Managing Hardware Software Data with Virtex-II Devices," gives overview different methods available configure Virtex-II devices. Chapter "Basic Advanced Virtex-II Wake-Up Solutions," describes wake-up setup used with other Xilinx FPGA families.
Additional Resources
find additional documentation, Xilinx website search Answer Database silicon, software, questions answers, create technical support WebCase, Xilinx website http://www.xilinx.com/support.
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Preface: About This Guide
Conventions
This document uses following conventions. example illustrates each convention.
Typographical
following typographical conventions used this document:
Convention Courier font Meaning Messages, prompts, program files that system displays Literal commands that enter syntactical statement Commands that select from menu Keyboard shortcuts Variables syntax statement which must supply values Italic font References other manuals Example speed grade:
Courier bold
ngdbuild design_name File Open Ctrl+C ngdbuild design_name Development System Reference Guide more information. wire drawn that overlaps symbol, nets connected. ngdbuild [option_name] design_name
Helvetica bold
Emphasis text optional entry parameter. However, specifications, such bus[7:0], they required. list items from which must choose more Separates items list choices
Square brackets
Braces
lowpwr ={on|off} lowpwr ={on|off} Name QOUT' Name CLKIN' allow block block_name loc1 loc2 locn;
Vertical
Vertical ellipsis Horizontal ellipsis
Repetitive material that been omitted
Repetitive material that been omitted
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Conventions
Online Document
following conventions used this document:
Convention Meaning Cross-reference link location current document Cross-reference link location another document Hyperlink website (URL) Example section "Additional Resources" details. Refer "Title Formats" Chapter details. Figure Virtex-II Platform FPGA User Guide. http://www.xilinx.com latest speed files.
Blue text
text Blue, underlined text
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Preface: About This Guide
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Virtex-II System Wake-Up Solutions UG028 (v1.1) August 2007
Chapter
Managing Hardware Software Data with Virtex-II Devices
Overview
This section gives overview different methods available configure VirtexTM-II device allow PowerPC(PPC) boot access memory code storage software execution. three system wake-up solutions Virtex-II Platform FPGAs are: System ACECF CompactFlash-based configuration management XILINX PROM Programmable Read-Only Memory External Non-volatile Memory Flash, Read-Only Memory, other equivalent solutions.
Table provides available solutions Virtex-II system wake-up. Table 1-1: Solutions Available Virtex-II System Wake-Up
Density
Solution
System CompactFlash
Mode Support
JTAG (IEEE 1149.1, IEEE 1532)
Configuration Speed
Mb/s
Technology
CompactFlashbased solution
Voltage Tolerance
Down 2.5V
Feature Support
Interface (PPC compatible) Configuration management multiple Design support Network reconfigurable Devices insystem, reprogrammable IEEE 1149.1 (JTAG)
Platform Flash PROM(2) (cascadable higher density) Master-Serial, Slave-SelectMAP Mb/s Flash 1.5V 3.3V
Notes:
XC2VP2 device which does contain configured same manner Virtex-II device with similar density. DS123, Platform Flash PROM Data Sheet, features specifications each family member.
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Chapter Managing Hardware Software Data with Virtex-II Devices
System (CompactFlash) Solution
System pre-engineered interface solution between CompactFlash one-inch Microdrive disk drive Virtex-II FPGA. features built-in microprocessor interface support configuration multiple devices, boards, bitstreams (multiple designs), well processor core initialization software storage. This drop-in configuration solution delivers dense, flexible, pre-engineered solution that reduces design time while supporting complex needs microprocessor-based solution. more information, see:
When System solution used with Virtex-II Platform FPGA, wakeup sequence follows: Configure Virtex-II FPGA logic from CompactFlash (CF) JTAG. Transfer boot code from CompactFlash block SelectRAM(block RAM) external (DRAM SRAM) JTAG. boots from block RAM. access CompactFlash memory port System Controller code storage software execution. also transfer software from CompactFlash block RAM, RAM, combination both faster execution.
Virtex-II
X-Ref Target Figure
System CompactFlash
Port
System Controller
JTAG Port Port
PPC405
BRAM
Logic
ug028_01_030802
Figure 1-1: System Solution Virtex-II Wake-Up
Xilinx PROMs
Xilinx PROMs provide ease-to-use, high-performance configuration solution. addition, Xilinx PROMs in-system programmable through standard IEEE 1149.1 (JTAG) port. When Xilinx Configuration PROM used with Virtex-II device (Figure 1-2), wake-up sequence follows: Configure FPGA portion Virtex-II device transfer boot code from PROM SelectMap Serial block RAM. block boots PPC.
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Virtex-II System Wake-Up Solutions UG028 (v1.1) August 2007
Overview
access external non-volatile memory, like standard Flash, code storage software execution. transfer software from external nonvolatile memory block RAM, RAM, combination both faster execution.
X-Ref Target Figure
Virtex-II
Xilinx PROM
PPC405
SelectMap/ Serial
BRAM
External Non-Volatile Memory
Logic
ug028_03_030102
Figure 1-2:
Xilinx PROM Solution Virtex-II System Wake-Up
External Non-Volatile Memory
External non-volatile memory used configure Virtex-II device including Flash-based memory (such standard Flash, cards, cards, etc.), well hard disk drives. Using external non-volatile memory requires controller configure Virtex-II device wake-up. controller design, refer following application notes: XAPP058, Xilinx In-System Programming Using Embedded Microcontroller XAPP079, Configuring Xilinx FPGAs Using XC9500 CPLD Parallel PROM XAPP424, Embedded JTAG Player XAPP502, Using Microprocessor Configure Xilinx FPGAs Slave Serial SelectMAP Mode
sequence wake-up Virtex-II device using external non-volatile memory follows: Configure FPGA portion Virtex-II device transfer boot code from external non-volatile memory either block RAM. Either block boots PPC.
access external non-volatile memory, non-volatile memory interface, code storage software execution. transfer software from external non-volatile memory block RAM, RAM, combination both faster execution.
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Chapter Managing Hardware Software Data with Virtex-II Devices
X-Ref Target Figure
Virtex-II Configuration Interface Controller Logic
Non-Volatile Memory
BRAM
Native Non-Volatile Memory Interface
PPC405
ug028_04_030802
Figure 1-3:
Non-Volatile Memory Solution Virtex-II Wake-Up
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Virtex-II System Wake-Up Solutions UG028 (v1.1) August 2007
Chapter
Basic Advanced Virtex-II Wake-Up Solutions
Basic Virtex-II Wake-Up Solution
Overview
first method described this section well-known setup used with other Xilinx FPGA families. setup requires very little external hardware minimal connections. only external device required this setup PROM storage device. PROM used store traditional configuration data VirtexTM-II device. level complexity that must addressed storage location Virtex-II PowerPCboot-code. this basic setup, Virtex-II FPGA block SelectRAM (also referred block RAM) utilized boot code storage. block contents loaded configuration data that stored PROM, thereby eliminating need additional external device store contents.
Basic System Architecture
Figure shows connections Xilinx PROM required Master Serial configuration mode. Figure also shows simplified block diagram Virtex-II device before configuration. this setup, both FPGA logic block load configuration from PROM boot-ups from block RAM.
X-Ref Target Figure
Xilinx PROM DATA OE/RESET
Master Serial Connections
Virtex-II CCLK DONE INIT FPGA Logic BRAM Embedded PPC405
ug028_05_022502
Notes:
Other modes also used similar manner with additional hardware connections. Refer appropriate Xilinx PROM data sheet guidelines required VCC/GND pull-up/pull-down optional connections
Figure 2-1: Virtex-II Basic System Wake-Up Solution
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Chapter Basic Advanced Virtex-II Wake-Up Solutions
This basic setup requires less hardware external connections, maximum storage space available boot-code software limited block RAM. Each available block contains Kbits. Table displays total amount block memory available each member Virtex-II family. Table 2-1: Sample Virtex-II Platform FPGA Block Microprocessor Cores
Device XC2VP4 XC2VP7 XC2VP20 XC2VP50
Notes:
XC2VP2 does contain cores, standard Virtex-II configuration solutions utilized. Kbits block available direct interfacing with Virtex-II PPC.
Columns
Cores
Total SelectRAM(1,2) Memory Blocks Kbits 1,584 3,888 Bits 516,096 811,008 1,622,016 3,981,312
Basic Solution Wake-Up Flow
Step Configuration Power-on Reset (POR) Step Startup Step Boot Wake-Up
Step
Configuration stage similar other Virtex FPGA families. During this stage, Virtex-II device powered completes three major phases: Clearing configuration memory Initialization Loading bitstream
Phase simply prepare device receive configuration data from PROM. FPGA's memory cleared mode settings sampled determine correct download mode. appropriate pins become active signify loading configuration data. loading bitstream defines functional operation internal blocks (for example function look-up tables (LUTs), flip-flops (FFs), multiplexers, buffers), (defining pull-up/pull-down, slew rate, etc.), their interconnections.
Step
Device startup transition stage from configuration mode normal programmed device operation. startup sequence performs following tasks: Release DONE Negate Global Tristate Signal (GTS) which activates I/Os Assert Global Write Enable (GWE) which allows RAMS flip-flops change state Assert End-Of-Startup (EOS) internal flag
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Basic Virtex-II Wake-Up Solution
Step
this stage, FPGA completed configuration starts execute code from reset vector.
Basic Software Flow
This section describes software flows necessary generate valid programming bitstream with Virtex-II boot code. also explains convert this bitstream into PROM file required this solution. flow through Xilinx software tools create valid bitstream Virtex-II device general same other Xilinx FPGA. standard flow takes design originating from schematic source code through design front-end tools create standard netlist. This netlist taken through Xilinx implementation tool suite physically map, then place route design into desired Virtex-II architecture. further details these software tools, refer on-line ISESoftware Manuals. deviation from most standard flow Xilinx FPGA families flow targeting Virtex-II device setup required allow execute code from block RAM. additional files utilized enable this functionality, block SelectRAM Memory file (.bmm) software code file (.elf). additional information creation usage these files, refer Embedded Development (EDK) User Guides.
X-Ref Target Figure
.bmm .elf (Memory File) (PPC code files) Source Code
Synthesis
Xilinx Software Implementation Tools
ug028_06_022802
Figure 2-2:
Xilinx Tool Software Flow Bitstream Generation with Block Initialization
last step this software flow creation PROM file programming PROM. PROM File created iMPACT software. merged bitstream created from Data2BRAM flow used input file iMPACT. user targets appropriate PROM density .mcs format create formatted PROM file target solution. detailed flow, refer on-line iMPACT Software Manual.
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Chapter Basic Advanced Virtex-II Wake-Up Solutions
Advanced Virtex-II Wake-Up Solution
Overview
second method discussed advanced users want take advantage configuration management auxiliary storage capabilities System CompactFlash (CF) solution. System manage eight separate designs Virtex-II device. default, design delivered power-up configure Virtex-II device boot PPC. command, System reconfigure Virtex-II FPGA with eight possible designs stored System controller microprocessor (MPU) port that provides access CompactFlash. Virtex-II connected System port access data standard file structure within System provides centralized solution system wake-up storage auxiliary application code data.
Advanced System Architecture
advanced system contains CompactFlash storage device, System CompactFlash controller, Virtex-II device, external RAM. System controller acts master controller CompactFlash device. power-up command, System controller extracts selected configuration file from CompactFlash delivers configuration data Virtex-II device JTAG Test Access Port (TAP). System configuration process includes delivery both FPGA fabric configuration bits initialization external with code data. below details configuration delivery scheme. optional port connection between Virtex-II device System controller gives access CompactFlash file structure reading writing additional application code data.
X-Ref Target Figure
JTAG Port
Virtex-II
CompactFLASH
Port
System Controller
FPGA Logic
Port
Embedded PPC405
External
ug028_08_022502
Figure 2-3:
Advanced System Wake-Up Solution
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Virtex-II System Wake-Up Solutions UG028 (v1.1) August 2007
Advanced Virtex-II Wake-Up Solution
Advanced Solution Wake-Up Flow
Virtex-II JTAG configuration flow designed support reconfiguration well initial configuration. Thus, Virtex-II wake-up flow begins with JTAG shutdown command sequence that disables active logic FPGA. FPGA configuration startup stages same Basic setup. However, extra stages required load code wake PPC.
Step JTAG Shutdown Command
Step FPGA Configuration
Step FPGA Startup
Step Loading
Step Boot Wake-Up
five stages wake-up flow accomplished through JTAG command sequences from System
Step
shutdown stage halts disables active logic FPGA. This stage prepares FPGA receive configuration data. case reconfiguration, this stage eliminates danger contention between configuration previously loaded configuration.
Step
configuration stage similar other Virtex FPGA families' configuration stages. During this stage, bitstream downloaded Virtex-II device. bitstream defines functional operation internal logic blocks, pins, interconnects internal peripheral devices, such external RAM.
Step
Startup transition stage from configuration mode normal programmed device operation. startup sequence performs following tasks: Releases DONE Negates Global Tristate Signal (GTS) which activates I/Os Asserts Global Write Enable (GWE) which allows RAMS flip-flops change state Assert End-Of-Startup (EOS) internal flag
completion this stage, FPGA fabric active including interconnects.
Step
software loading stage fills external with boot code data through control logic.
Step
boot stage consists setting program counter starting location boot code releasing into normal mode.
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Chapter Basic Advanced Virtex-II Wake-Up Solutions
Virtex-II JTAG Test Access Port (TAP)
JTAG Virtex-II device tightly integrated with FPGA configuration logic well control logic. JTAG FPGA configuration logic integration allows FPGA configured through JTAG TAP. JTAG control logic integration allows controlled through JTAG TAP. JTAG control memory initialization wake-up scheme. System instruct through JTAG write initial memory image. System also instruct start from specific code location through JTAG TAP.
Advanced Software Flow
single System configuration (.ace) file contains JTAG commands that necessary configure Virtex-II device wake advanced system. System configuration file created from sources: FPGA configuration bitstream (.bit) file code data (.elf) file. Embedded Development (EDK) User Guides descriptions flows that create .bit .elf files. Because target Virtex-II device JTAG scan chain with arbitrary number JTAG devices, System configuration file preparation process must understand JTAG scan chain layout. System solution delivers configuration code through serial JTAG vectors. These serial JTAG vectors saved intermediate facto standard Serial Vector Format (SVF) file.
X-Ref Target Figure
JTAG Chain Description File (.cdf)
Merged File iMPACT Software CompactFlash
Virtex-II Bitstream file (.bit)
Virtex-II Configuration (.svf) Serial Vector Format File (.svf)
SVF2ACE Translator
Virtex-II File (.elf)
ELF2SVF Translator
System File (.ace)
Memory (Code+Data) Initialization (.svf)
ug028_022802
Figure 2-4:
Advanced Virtex-II Software Flow
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Advanced Virtex-II Wake-Up Solution
Transformation .bit .elf files into unified .ace file requires three software steps:
Step
iMPACT software generates JTAG vectors delivering bitstream target Virtex-II within JTAG scan chain. result file with vectors shut down, configure, start FPGA logic. (See iMPACT Software Manual detailed instructions defining JTAG scan chain creating file program Virtex-II device.)
Step
ELF2SVF translates code data (.elf) file into JTAG instructions fill appropriate memory locations. addition, ELF2SVF translator appends JTAG instructions preset program counter starting location boot code into state with preset program counter value. resulting appended bitstream configuration file.
Step
Convert combined file into corresponding System CompactFlash (ACE) file. file copied CompactFlash unit system deployment (see DS080, System Data Sheet detailed instructions System CompactFlash operation file structure). target system, System controller executes file from CompactFlash configure wake PPC.
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