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Virtex-II Virtex-II FPGA User Guide
UG012 (v4.2) November 2007
Xilinx disclosing this user guide, manual, release note, and/or specification (the "Documentation") solely development designs operate with Xilinx hardware devices. reproduce, distribute, republish, download, display, post, transmit Documentation form means including, limited electronic, mechanical, photocopying, recording, otherwise, without prior written consent Xilinx. Xilinx expressly disclaims liability arising your Documentation. Xilinx reserves right, sole discretion, change Documentation without notice time. Xilinx assumes obligation correct errors contained Documentation, advise corrections updates. Xilinx expressly disclaims liability connection with technical support assistance that provided connection with Information. DOCUMENTATION DISCLOSED "AS-IS" WITH WARRANTY KIND. XILINX MAKES OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, STATUTORY, REGARDING DOCUMENTATION, INCLUDING WARRANTIES MERCHANTABILITY, FITNESS PARTICULAR PURPOSE, NONINFRINGEMENT THIRD-PARTY RIGHTS. EVENT WILL XILINX LIABLE CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, INCIDENTAL DAMAGES, INCLUDING LOSS DATA LOST PROFITS, ARISING FROM YOUR DOCUMENTATION. 2002-2007 Xilinx, Inc. rights reserved. XILINX, Xilinx logo, Brand Window, other designated brands included herein trademarks Xilinx, Inc. PowerPC trademark IBM, Inc. other trademarks property their respective owners.
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UG012 (v4.2) November 2007
Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
following table shows revision history this document. revision publications electronic only (PDF) unless otherwise noted. Version 01/31/02 10/14/02 12/04/02 01/23/03 (Print Edition.) Initial Xilinx release. (Print Edition.) Updated reprinted. Virtex-II family members packages. Revised support information. Added full support 3.3V standards PCI-X, LVTTL, LVCMOS33. Added wire-bond package FG676 XC2VP20, package diagram (Figure 5-66) pinout diagrams (Figure 5-11 through Figure 5-15). Revised Table 5-6. Removed pinout diagrams other references XC2VP40FF1517. Revised material added Figure section "Mixed Voltage Environments," page 298. Clariified explanation banks VCCO settings configuration operation section "Special VCCO Requirements during Configuration Readback," page 299. Table 3-37, Table 3-38: Corrected package type FG672 FF672, added package type FG676. Deleted (former) Table 3-3, Power-Up Timing Characteristics, replaced with hyperlink Data Sheet Module Deleted (former) Table 1-5, Multiplier Switching Characteristics, replaced with hyperlink Data Sheet Module Changed attribute CLOCK_FEEDBACK CLK_FEEDBACK. Clarifying text added section "Phase Shift Enable PSEN" Chapter Additional implementation rule added section "DCI Virtex-II Pro/Virtex-II Hardware" Chapter Corrections made command line, file, file command line equivalent section "Creating Keys" Chapter Added device-specific parameters step "Single Device Configuration Sequence" Chapter Section "Master SelectMAP Data Loading" Chapter Corrected maximum frequency SelectMAP configuration without BUSY handshaking MHz. Table 4-8: Corrected maximum SelectMAP frequency (FCC_SELECTMAP MHz. Appendix "BitGen PROMGen Switches Options": Updated commandline options correlate with development tools their documentation. Table 3-58: Added numerous LVDS primitives this table, including differential termination primitives. Added section "LVDS Input Examples." Changed Figure 3-119 show internal rather than external differential input termination. Various minor edits. Revision
04/11/03
UG012 (v4.2) November 2007
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Virtex-II Virtex-II FPGA User Guide
Version 06/30/03
Revision Corrected Location Constraints syntax, multiple instances. Added Figure 3-23, page associated explanatory text. Added code resetting after configuration section "External Feedback," page Modified Banking Rules section "DCI Virtex-II Pro/Virtex-II Hardware," page 236. Added reference Answer Record 13012 section "SSTL2_ I_DCI, SSTL2_II_DCI," page 238. Corrected command-line equivalent statements bitstream encryption files section "Creating Keys," page 270. Added section "SelectMAP ABORT Sequence ABORT Recovery," page 316, section "Master SelectMAP Programming Mode". Corrected shading property symbol key, diagrams, section "Pinout Diagrams," page 397. Numerous additional minor edits. Figure 3-59, page 158: Added missing connection between second Slice first Slice Figure 3-72, page 180: Corrected numbers inputs adder. Section "Routing with BlockRAM," page added. Table 3-36, page 202: Added parameters HSTL18 standards. Figure 3-90, page 215: Correct VREF from 0.75V 0.9V. Section "DCI Buffer Library Components," page 231, added IBUFG_LVDS components list. Section "Location Constraints," page 251: Added constraint locating register next register using different clock. Appendix "Choosing Battery VBATT" added, with linked reference section "VBATT," page 272. Page 292: added paragraph Introduction Configuration chapter specifying fixed voltage mode pins M0-M2, warning toggle these pins during after configuration. Table 4-2, page 292: Reduced configuration bitstream lengths devices bits. Section "Configuration Pins," page 296: Added warning constraints regarding application 3.3V signals dedicated configuration pins. Table 4-3, page 297: Corrected directionality BUSY/DOUT Output, INIT_B Input/Output. Updated with data from XAPP659. Former Table 4-6, Master/Slave Serial Mode Programming Switching, former Table 4-8, SelectMAP Write Timing Characteristics, removed. Virtex-II Virtex-II Data Sheet, Switching Characteristics these other timing parameter specifications. Table 4-6, page 302: Corrected FCC_SERIAL from MHz. Added footnote Figure 4-9, page 305, Figure 4-11, page 307, clarifying that DOUT transitions falling edge CCLK. Second paragraph below Figure 4-13, page 311: Corrected maximum no-handshake SelectMAP configuration speed from MHz. Section "Master SelectMAP Data Loading," page 311: Changed wording emphasize that RDWR_B toggled while CS_B still asserted, configuration abort will occur.
02/02/04
Virtex-II Virtex-II FPGA User Guide
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UG012 (v4.2) November 2007
Version 02/02/04 (cont'd) (cont'd)
Revision Section "Express-Style Loading," page 308: Added text clarify sequencing signals before, during, after data loading. Page 322: added text paragraph indicating that open-drain should pulled externally. Table 4-13, page 331: Updated "Total Bits" column with numbers. Figure 5-53, page 457; Figure 5-54, page 458; Figure 5-55, page 459; Figure 5-56, page 460: Corrected banking assignments pins AB12 AB31. shows these pins Banks respectively. Table 5-1, page Thermal Data Table 5-3: Changed Theta-JC 0.5°C/Watt packages. Section "Crosstalk," page 488: Clarified wording trace routing guidelines minimize crosstalk onto VREF lines. Section "Digital Clock Managers (DCMs)" Chapter Removed referrals CLK2X option implementing clock feedback loop DCM, including: Removed former Figures 3-25, 3-27, 3-39, which showed schematics CLK2X feedback implementation. Section "Attributes," page Removed section "Feedback Input" discussing CLK_FEEDBACK attribute, which used designate CLK2X feedback clock. Table 3-9, page 114: Removed CLK_FEEDBACK from table attributes. Section "VHDL Verilog Instantiation," page 115: Removed BUFG_ CLK2X_SUBM, BUFG_CLK2X_FB_SUBM, BUFG_PHASE_CLK2X_SUBM from list available submodules. Page 179: Added registered multiplier primitive table Table 3-26, schematic both multiplier primitives (Figure 3-71), explanatory text. Table 3-36, page 202: Added LVPECL_25 BLVDS_25 table. Table 3-38, page 206: Added referral XAPP689 managing ground bounce. Section "DCI Buffer Library Components," page 231: Removed LVDS_33_DCI LVDSEXT_33_DCI components from listing. Section "Creating Bidirectional LVDS Buffer," page 264, "Creating LVPECL Output Buffer," page 267: Added referral Table 3-36 guidelines. Section "Bitstream Encryption," page 269: Added referral Appendix "Choosing Battery VBATT." Section "Creating Keys" (end): Added material discussing initial value safeguard bitstream security. Table 4-3, page 297: Mode pins (M0, connected 3.3V unless through resistor. VBATT connected VCCAUX when bitstream encryption used. Section "Frame Length Register (FLR)," page 333: Added "minus word" description value loaded into this register. Former Table 4-3, Power-Up Timing Configuration Signals, removed. Virtex-II Platform FPGA Data Sheet, Switching Characteristics these other timing parameter specifications. Section "Test Access Port," page 321: Added mention implementation tool pull-up, pull-down, float options pins. Updated DS026 Appendix "Platform Flash Family PROMs" v5.0. Various edits deletions Glossary.
04/19/04
UG012 (v4.2) November 2007
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Version 04/19/04 (cont'd) (cont'd)
Revision Edits throughout synchronize/align User Guide with Data Sheet Table Updated DS026 Appendix "Platform Flash Family PROMs" v5.0. Various edits deletions Glossary. Edits throughout synchronize/align User Guide with Data Sheet Table
06/02/04
2.6.1
Table 4-3, page 297: Corrected BUSY/DOUT from "Input" "Output". Corrected INIT_B from "Input" "Input/Output". Removed redundant entries CCLK PROG_B. Revised throughout with updated tables, text, pinout diagrams, hyperlinks include devices, Virtex-II XC2VPX20 XC2VPX70, which feature RocketIO 10.3125 Gb/s MGT. Revised throughout with updated tables, text, package diagrams include Pb-free packaging options FGG256, FGG456, FGG676. Section "Frequency Synthesized Clock Output CLKFX," page 101: Added text indicating CLKFX phase alignment when CLKIN frequency below Mhz. Section "Phase Shift Characteristics," page 105: Added substantial detailed material related calculating controlling desired phase shift. Table 3-29, page 187: Added clarifying example Footnote regarding GTL/GTLP VCCO lower limit. Section "Daisy-Chain Configuration," page 303: Revised text clarify daisy-chain options strings different Xilinx FPGA devices. Section "RDWR_B," page 305: Revised text clarify status data when RDWR_B High Low. Table 4-16, page 331: Revised step give XC2VP2 code, step correct code from Corrected Footnote "data instruction". Chapter "Configuration": This chapter been expanded completely updated with material. Since most material newly written, specific changes this chapter recorded Revision History. Section "BUFG Exclusivity," page Corrected numbering exclusive buffer pairs. Figure 3-23, page Added note when reset DCM. Section "Fixed-Mode Phase Shifting Certain Virtex-II Devices," page 106: Added link Solution Record 13349. Table 3-9, page 114: From "Description" CLKIN_DIVIDE_BY_2, removed text specifying upper frequency limit using this attribute divide input clock Section "Embedded Multipliers," page 178: Deleted subsection Multipliers Single Primitive. Deleted references DUAL_MULT_* templates. Section "Output Drive Source Voltage (VCCO) Pins," page 199: Added text recommending that VCCO powered standards. Table 3-36, page 202: Corrected number SSOs following standards: GTL_DCI, GTLP_DCI, HSTLII_DCI, SSTL18_II, LVPECL_25, BLVDS_25. Added following standards: DIFF_HSTL_II, DIFF_HSTL_II_DCI, DIFF_HSTL_II_18, DIFF_HSTL_II_18_ DCI, DIFF_SSTL_II, DIFF_SSTL_II_DCI, DIFF_SSTL_II_18, DIFF_SSTL_II_18_ DCI. Section "DCI Virtex-II Pro/Virtex-II Hardware," page 236: Added step Added Figure 3-109, page 242.
08/05/04
03/07/05
Virtex-II Virtex-II FPGA User Guide
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UG012 (v4.2) November 2007
Version 03/07/05 (cont'd) (cont'd)
Revision Code template "DDR_input.v," page 253: Removed assign data_out just before "endmodule". Section "LVDS I/O," page 258: Replaced Table 3-58, "Available LVDS Primitives" with Table 3-58, "Available LVDS Standards". Section "Loading Encrypted Bitstreams," page 272: Corrected reference JTAG JSTART instruction JTAG JPROG_B. Added section "Temperature-Sensing Diode (DXP/DXN)," page 273. Corrected pinout diagram "FF672 Composite Pinout Diagram (XC2VP4)" (Figure 5-19, page 420). Previously, this figure shown composite pinout diagram FF672/XC2VP7 device. Section "Design Examples," page (Appendix Deleted text illustration that incorrectly suggested different battery voltage compliance requirements Virtex-II Virtex-II BBRAM power pin. Added section "Cascading DCMs," page "Feedback Clock Input CLKFB," page Added information regarding when CLK_FEEDBACK must NONE. "Reset Input RST," page and"Reset Input RST," page Corrected hold time from clock cycles. "Port Signals," page 108: Corrected paragraph regarding DUTY_CYCLE_CORRECTION attribute. "Data Flow," page 123: Added paragraph requiring block address setup/hold times port enabled, even data interest. Table 3-54 (LVCMOS15) Table 3-55, page (LVCMOS18): Updated voltage level definitions values. "Xilinx DCI," page 224: Added material clarifying effect outputs leaving VRN/VRP disconnected. "Xilinx DCI," page 224: Removed reference FreezeDCI. "DCI Virtex-II Pro/Virtex-II Hardware," page 236: Modified point detailing when VRP/VRN reference resistors required. "Location Constraints," page 251: Deleted last paragraph, incorrect. "Differential Termination LVDS Input Examples," page 260: Replaced VHDL Verilog instantiation examples. Chapter "Configuration": Corrected various typographical errors. "Device Startup," page 295: Added requirement 5-10 CCLK cycles after DONE released. Figure 4-5: Added pull-up resistor INIT_B signal. Deleted section "Using XC17V00 PROMs". Obsolete. Table 5-3: Added Pb-free package names. Corrected errors row/column headings. change values.) Figure 5-65, Figure 5-70: Replaced FG456/FGG456 FF1148/FFG1148 package drawings with updated versions.
03/28/07
UG012 (v4.2) November 2007
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Virtex-II Virtex-II FPGA User Guide
Version 11/05/07
Revision Added footnote regarding LVDS receiver differential termination standards Table 3-58 Table 3-59. Table 4-28: Corrected assignments MATCH_CYCLE LOCK_CYCLE. Table 4-16: Added Step "Configuration Memory Read Procedure (1149.1 JTAG)," page 374: Added steps 5(b) 5(c); corrected step 5(g) [formerly 5(e)]. Updated legal disclaimer. "Boundary-Scan Virtex-II Devices Using IEEE Standard 1149.1," page 321: Updated IEEE 1149.1 compliance statement.
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UG012 (v4.2) November 2007
Table Contents
Preface: About This Guide
Guide Contents Additional Resources Conventions
Typographical Online Document
Chapter Virtex-II Virtex-II FPGA Family
Next Logical Revolution Built Bandwidth Legacy Leadership Packets Everywhere Bridge, Anyone? Simplifying Complexity Time Money Flexibility Money Being Discrete
Chapter Timing Models
Summary Introduction Slice Timing Models
General Slice Timing Model Parameters Slice Distributed Timing Model Parameters Slice Timing Model Parameters
Block SelectRAM Timing Model Embedded Multiplier Timing Model Timing Models
Input Timing Model Parameters Output Timing Model Parameters. 3-State Timing Model Parameters
Pin-to-Pin Timing Models
Global Clock Input Output Global Clock Setup Hold.
Digital Clock Manager Timing Model
Operating Frequency Ranges Input Clock Tolerances Output Clock Precision Miscellaneous Timing Parameters
Additional Timing Models Other Publications: PPC405 Processor Block RocketIO/RocketIO Transceivers
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PPC405 Processor Block Timing Models RocketIO Transceiver Timing Models RocketIO Transceiver Timing Models
Chapter Design Considerations
Summary Introduction RocketIO RocketIO Transceivers Processor Block Global Clock Networks
Introduction Clock Distribution Resources Power Consumption Library Primitives Submodules Characteristics Location Constraints Secondary Clock Network VHDL Verilog Instantiation
Digital Clock Managers (DCMs).
Overview Clock De-Skew Legacy Support Frequency Synthesis Phase Shifting Waveforms
Block SelectRAMMemory
Introduction Synchronous Dual-Port Single-Port Characteristics Library Primitives VHDL Verilog Instantiation Port Signals Address Mapping Attributes. Initialization VHDL Verilog Codes Location Constraints Applications VHDL Verilog Templates Introduction Characteristics Library Primitives VHDL Verilog Instantiation Ports Signals Attributes. Initialization VHDL Verilog Codes Location Constraints Applications VHDL Verilog Templates
Distributed SelectRAM Memory
Look-Up Tables Shift Registers (SRLs)
Introduction
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Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
Shift Register Operations Characteristics Library Primitives Submodules Initialization VHDL Verilog Code Port Signals Attributes. Location Constraints Fully Synchronous Shift Registers Static-Length Shift Registers VHDL Verilog Instantiation Introduction Virtex-II Pro/Virtex-II Resources Wide-Input Multiplexers Characteristics Library Primitives Submodules Port Signals Applications VHDL Verilog Instantiation Introduction Virtex-II Pro/Virtex-II Resources VHDL Parameters Applications VHDL Verilog Instantiation Introduction Two's-Complement Signed Multiplier Library Primitives Submodules VHDL Verilog Instantiation Port Signals Location Constraints Routing with BlockRAM VHDL Verilog Templates Summary Introduction Fundamentals Overview Supported Standards Library Symbols Design Considerations Application Examples Introduction Xilinx Software Support Virtex-II Pro/Virtex-II Hardware Introduction Data Flow Characteristics Library Primitives
Large Multiplexers
Products (SOP) Logic
Embedded Multipliers
Single-Ended SelectIO-Ultra Resources
Digitally Controlled Impedance (DCI)
Double-Data-Rate (DDR)
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VHDL Verilog Instantiation Port Signals Initialization VHDL Verilog Location Constraints Applications VHDL Verilog Templates Introduction Creating LVDS Input/Clock Buffer Creating LVDS Output Buffer Creating LVDS Output 3-State Buffer Creating Bidirectional LVDS Buffer LDT. Implementation
LVDS
LVPECL I/O.
Introduction Creating LVPECL Input/Clock Buffer Creating LVPECL Output Buffer
Bitstream Encryption
What Triple Different. Classification Export Considerations Creating Keys Loading Keys Loading Encrypted Bitstreams VBATT Temperature-Sensing Diode (DXP/DXN) Introduction CORE Generator System CORE Generator Design Flow Core Types Xilinx Solutions Center CORE Generator Summary Virtex-II Pro/Virtex-II Cores Support
CORE Generator System
Chapter Configuration
Summary Introduction
Configuration Modes Configuration Process Flow Configuration Pins Mixed Voltage Environments System (CompactFlash) Solution Configuration PROMs Flash PROMs With CPLD Configuration Controller. Embedded Solutions PROM System Selection Guide
Configuration Solutions
Software Support Data Files
iMPACT
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Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
Programming Cables Boundary Scan Interconnect Testing Virtex-II Devices. In-System Programming Data Files
Serial Programming Modes
Master Serial Mode Slave Serial Mode
SelectMAP Programming Modes
Master SelectMAP Mode Slave SelectMAP Mode
SelectMAP ABORT Sequence ABORT Recovery
Triggering ABORT ABORT Status Word ABORT Recovery
Internal Configuration Access Port (ICAP) JTAG Boundary-Scan Programming Modes
Introduction Boundary-Scan Virtex-II Devices Using IEEE Standard 1149.1 Using Boundary Scan Virtex-II Devices Boundary-Scan Virtex-II Devices Using IEEE Standard 1532 Configuration Flows Using JTAG Configuration Memory: Columns Frames PPC405 Cores Configuration Memory Addressing Bitstream Packets Configuration Control Logic Configuration Partial Reconfiguration Preparing Design Readback Readback Command Sequences Readback Files Verifying Readback Data Readback Capture Using ChipScope
Configuration Details
Readback
Chapter Design Considerations
Summary Pinout Information
Introduction Definitions FG256/FGG256 Fine-Pitch Package
Pinout Diagrams
FG256/FGG256 Fine-Pitch Pinout Diagrams FG456/FGG456 Fine-Pitch Pinout Diagrams FG676/FGG676 Fine-Pitch Pinout Diagrams FF672 Flip-Chip Fine-Pitch Pinout Diagrams FF896 Flip-Chip Fine-Pitch Pinout Diagrams FF1152 Flip-Chip Fine-Pitch Pinout Diagrams FF1148 Flip-Chip Fine-Pitch Pinout Diagrams FF1517 Flip-Chip Fine-Pitch Pinout Diagrams
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FF1704 Flip-Chip Fine-Pitch Pinout Diagrams
Package Specifications
FG256/FGG256 Fine-Pitch Package (1.00 Pitch) FG456/FGG456 Fine-Pitch Package (1.00 Pitch) FG676/FGG676 Fine-Pitch Package (1.00mm pitch) FF672 Flip-Chip Fine-Pitch Package (1.00 Pitch) FF896 Flip-Chip Fine-Pitch Package (1.00 Pitch) FF1152 Flip-Chip Fine-Pitch Package (1.00 Pitch) FF1148 Flip-Chip Fine-Pitch Package (1.00 Pitch) FF1517 Flip-Chip Fine-Pitch Package (1.00 Pitch) FF1704 Flip-Chip Fine-Pitch Package (1.00 Pitch) FF1696 Flip-Chip Fine-Pitch Package (1.00 Pitch)
Flip-Chip Packages
Advantages Flip-Chip Technology
Thermal Data
Thermal Considerations Thermal Management Options
Printed Circuit Board Considerations
Layout Considerations Decoupling
Board Routability Guidelines
Board-Level Routing Challenges Board Routing Strategy
XPower IBIS Models
Using IBIS Models IBIS Generation. Advantages IBIS IBIS File Structure IBIS dV/dt Curves Ramp dV/dt Curves Xilinx IBIS Package Parasitic Modelling IBIS Simulations IBIS Simulators Xilinx IBIS Advantages ANSI/EIA IBIS Official Website
BSDL Boundary Scan Models
BSDL Files
Appendix BitGen PROMGen Switches Options
Using BitGen
BitGen Syntax BitGen Files BitGen Options
Using PROMGen
PROMGen Syntax PROMGen Files PROMGen Options Examples
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Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
Appendix Platform Flash Family PROMs
PROM Package Specifications
FS48 Package Specification VO48 Package Specification VO20 Package Specification
Appendix Choosing Battery VBATT
Battery Types Chemistry Choices
Primary Secondary Battery Cost Care Battery Summary
Design Examples
Case Case Case Case
Glossary. Index
Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
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Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
Preface
About This Guide
This document, Virtex-II Virtex-II FPGA User Guide, describes function operation VirtexTM-II Virtex-II devices, also includes information FPGA configuration techniques design considerations. comprises following main sections:
Guide Contents
Chapter "The Virtex-II Virtex-II FPGA Family" Chapter "Timing Models" Chapter "Design Considerations" Chapter "Configuration" Chapter "PCB Design Considerations" Appendix "BitGen PROMGen Switches Options" Appendix "Platform Flash Family PROMs" Appendix "Choosing Battery VBATT" Virtex-II Virtex-II Platform FPGAs: Complete Data Sheet
Virtex-II device specifications, refer Virtex-II Data Sheet:
following documents offer in-depth technical design information about RocketIO RocketIO multi-gigabit transceivers PowerPC processor, which covered this User Guide: RocketIO Transceiver User Guide RocketIO Transceiver User Guide PowerPC Processor Reference Guide PowerPC Processor Block Reference Guide
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Preface: About This Guide
Additional Resources
additional information, http://support.xilinx.com. following table lists some resources access from this website. also directly access these resources using provided URLs. Resource Data Sheets Description/URL Xilinx data sheets describe device-specific operating characteristics, architecture, pinouts/packaging. Xilinx user guides contain detailed, device-specific operating theory generic design examples various device functions. y=User+Guides Application Notes Xilinx application notes describe design techniques approaches general design well specific applications. Many application notes feature complete reference designs including source code. y=Application+Notes Xcell Journals Tech Tips This site contains quarterly journals Xilinx programmable logic users. this site latest news, design tips, patch information Xilinx design environment. Answers Database This database provides current listing solution records Xilinx software tools. Search this database using search function
User Guides
Conventions
This document uses following conventions. example illustrates each convention.
Typographical
following typographical conventions used this document: Convention Courier font Meaning Messages, prompts, program files that system displays Literal commands that enter syntactical statement Commands that select from menu Keyboard shortcuts Example speed grade:
Courier bold
ngdbuild design_name File Open Ctrl+C
Helvetica bold
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Conventions
Convention
Meaning Variables syntax statement which must supply values. angle brackets.)
Example
ngdbuild <design_name>
Italic font
References other manuals
Development System Reference Guide more information. wire drawn that overlaps symbol, nets connected. ngdbuild [option_name] design_name
Emphasis text optional entry parameter. However, specifications, such bus[7:0], they required. list items from which must choose more Separates items list choices
Square brackets
Braces
lowpwr ={on|off} lowpwr ={on|off} Name QOUT' Name CLKIN' allow block block_name loc1 loc2 locn;
Vertical
Vertical ellipsis Horizontal ellipsis
Repetitive material that been omitted
Repetitive material that been omitted
Online Document
following conventions used this document: Convention Meaning Cross-reference link location current document Cross-reference link location another document Hyperlink website (URL) Example section "Additional Resources" details. Refer "Title Formats" Chapter details. Figure Virtex-II Handbook. http://www.xilinx.com latest speed files.
Blue text
text Blue, underlined text
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Chapter
Virtex-II Virtex-II FPGA Family
Next Logical Revolution
Virtex-II ProTM/Virtex-II Platform FPGA solution most technically sophisticated silicon software product development history programmable logic industry. goal revolutionize system architecture "from ground up." achieve that objective, best circuit engineers system architects from IBM, Mindspeed, Xilinx co-developed world's most advanced Platform FPGA silicon product. Leading teams from embedded systems companies worked together with Xilinx software teams develop systems software solutions that enabled this system architecture paradigm. result first Platform FPGA solution capable implementing high performance system-on-a-chip designs previously exclusive domain custom ASICs, with flexibility development cost programmable logic. Virtex-II Pro/Virtex-II family marks first paradigm change from programmable logic programmable systems, with profound implications leading-edge system architectures networking applications, deeply embedded systems, digital signal processing systems. allows custom user-defined system architectures synthesized, next-generation connectivity standards seamlessly bridged, complex hardware software systems co-developed rapidly with insystem debug system speeds. Together, these capabilities usher next programmable logic revolution.
Built Bandwidth
Virtex-II Pro/Virtex-II family consists eleven members. nine Virtex-II devices contain four twenty RocketIOmulti-gigabit transceivers (MGTs), while Virtex-II devices contain eight twenty RocketIO MGTs. Each Xilinx RocketIO/RocketIO transceiver block contains complete user-configurable supporting circuitry that addresses real-life, system-level challenges. These include standard 8B/10B encode/decode (plus 64B/66B encode/decode RocketIO programmable signal integrity adjustments varying trace lengths materials, support synchronization multiple channels, programmable support channel control commands. addition, RocketIO RocketIO blocks first FPGAembedded transceivers reach baud rates 3.125 Gbps 10.3125 Gbps, respectively. Four RocketIO transceivers, employing sixteen traces, used support fullduplex Gbps channel RocketIO channel-bonding feature-or, single RocketIO transceiver implement same speed with just four traces. This equivalent traces typical LVTTL buses, traces high-speed, sourcesynchronous parallel LVDS bus. allows trace reduction over conventional parallel buses, resulting significant reductions complexity
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Chapter Virtex-II Virtex-II FPGA Family
system noise. RocketIO/RocketIO technology fulfills higher bandwidth system requirements than currently possible, with cost savings coming from faster time-tomarket, reduced printed circuit board (PCB) complexity, lower component count. Each larger devices incorporates small powerful IBM® PowerPC405 processor cores, each capable more than clock frequency Dhrystone MIPS. While processor cores occupy small area die, they provide tremendous system flexibility where they used. PowerPC cores fully embedded within FPGA fabric, where processor nodes controlled FPGA routing resources. This provides utmost architectural capability, where complex applications efficiently divided between high-speed logic implementation high-flexibility software implementations. example, packet processing application using only FPGA logic today high-speed packet routing augmented include slave high-performance processor exception handling in-system statistics monitoring. contrast, using separate processor externally requires hundreds additional interface pins, which degrades system performance significantly increases FPGA requirements overall board costs. Virtex-II Pro/Virtex-II products based most advanced FPGA fabric available: Virtex-IIarchitecture with IP-Immersiontechnology, which developed offer significant improvements engineering productivity, silicon efficiency, system flexibility. Unique features common Virtex-II Series-consisting Virtex-II Virtex-II families-include powerful SystemIOsystem connectivity solutions, digitally controlled impedance (DCI) technology, comprehensive clocking solutions, high-speed Active Interconnectrouting architecture, bitstream encryption. These features together constitute most complete Platform FPGA solution available, optimized high performance system-level applications. upward compatibility Virtex Series products ensures benefits engineering productivity, performance, design longevity, continuing cost reduction.
Legacy Leadership
Each Virtex families FPGAs been most successful programmable product family class, starting with introduction original Virtex family 1998. Virtex Virtex-E families were recognized industry highest technology products available when they were first introduced. Virtex-II family, which again achieved technology leadership density, performance, features, ushered Platform FPGAs-programmable devices with system-level capability performance implement systems functionality. Virtex-II family continues tradition technology leadership most sophisticated Platform FPGA yet, again breaking technology barrier benefit leading-edge system architects. Virtex-II Pro/Virtex-II family first FPGA family incorporate both serial transceiver technology hard processor core within general-purpose FPGA device. This significant high-bandwidth embedded processing applications such packet processing, where both high device bandwidth high performance processor cores needed together. Virtex-II Pro/Virtex-II devices industry's first FPGAs 0.13-micron process. nine-layer metal, all-copper, low-k process technology among most advanced semiconductor industry. combination advanced Active Interconnectarchitecture advanced process technology makes Virtex-II Pro/Virtex-II family highest performance FPGA world. RocketIO/RocketIO multi-gigabit MGTs highest performance, most complete embedded serial transceivers available. They user-configurable
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Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
Packets Everywhere
3.125 Gbps 10.3125 Gbps baud rate channel, which many times performance other embedded transceivers 1.25 Gbps. Each RocketIO/RocketIO transceiver provides complete common functionality available standard SerDes transceivers. contrast, "programmable ASSP" products with clock/data recovery (CDR) provide only most basic transceiver capability. PowerPC processor core used Virtex-II Pro/Virtex-II family highest performance embedded core available FPGAs. PowerPC architecture used many markets including communications, industrial control, test measurement systems, other performance-oriented markets. currently most popular processor architecture embedded applications.
Packets Everywhere
Virtex-II Pro/Virtex-II family provides powerful paradigm network processing where latency required, such storage area networks, wireless infrastructure, voice-over-IP networks. digital convergence phenomenon drives need packet routing based type priority. example, live voice video data packets require significantly lower latency than data file packets. data networking applications must handle higher bandwidth traffic well more complex types prioritized packets. many cases, Virtex-II Pro/Virtex-II devices offer higher overall performance than other solutions, including specialized network processors (NPs). Using Virtex-II architecture, most common packets quickly read routed using FPGA logic, without incurring lengthy software runtime needed NPs. FPGA logic interrupts PowerPC processor core only when processor instructions needed special packet types. example, packets stored into dual-port memory area accessible both FPGA logic PowerPC on-chip memory (OCM) port, allowing rapid change control packet disposition. using FPGA logic process most common packet types while processor core handles more specialized ones slave logic, Virtex-II architecture provide higher overall performance than NPs, well more sophisticated processing capabilities than FPGA logic alone.
Bridge, Anyone?
Powerful protocol bridges tying together disparate data stream formats well-suited Virtex-II Pro/Virtex-II solution. interface standards protocols include ExpressTM, Infiniband®, Gigabit Ethernet, XAUI/10 Gigabit Ethernet, RapidIOTM, HyperTransportTM. These must interface seamlessly another, well other standards such PCITM, Fibre Channel, Level Flexbus others. This presents significant challenge system developers because changing standards, scarcity off-the-shelf interface components, inflexibility available solutions. System designers have assemble their blend FPGAs, discrete physical transceivers, discrete communications processors solve their complex system challenges. Even newer "programmable ASSPs" (application-specific standard products) with built-in serial transceivers fall short, because they frequently require companion FPGAs supplement their logic capacity. Virtex-II solution, using powerful Xilinx SystemIOcapability fully integrate silicon, software, capabilities, provides most flexible pre-engineered protocol bridge solutions available fast timeto-market development cost.
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Chapter Virtex-II Virtex-II FPGA Family
Simplifying Complexity
Virtex-II Pro/Virtex-II solution offers powerful paradigm complex embedded systems found signal processing, industrial control, image processing, networking, communications, aeronautic applications. first time, complex embedded systems traditionally involving sophisticated hardware software developed concurrently, emulated actual hardware speed, debugged in-system, re-architected performance within weeks, rather than months years. addition, full systems remotely upgraded easily software-only upgrades performed today, using Compact Flash, CDROM, Internet, wireless transmission, other flexible means. Hardware design simplified using powerful development software large soft library assemble logic- processor-based platforms. Software development started earlier using actual device preconfigured sample platforms, without waiting system board developed. many cases, higher density Virtex-II components used early system development, whereby extra resources (including additional PowerPC processor cores) used easily emulate board-level components developed. This flexibility, obviously unavailable custom ASICs ASSPs, allows systems emulated speed, rather than simulated using software simulators 1000 times slower. In-system debugging further enhanced Xilinx ChipScope tool, which provides comprehensive logic analysis-from probing internal nodes full analysis with protocol adherence checks using external logic analyzer IEEE 1149.1 (JTAG) test access port. Using ChipScope result orders magnitude improvement engineering productivity. Complex systems optimally repartitioned between FPGA logic processor cores, allowing continuum possible trade-offs between speed logic flexibility software code. example, first implementation echo cancellation algorithm might all-software compiled code running PowerPC core, order allow system software development start. system further optimized, part algorithm could retargeted using Matlab Simulink into FPGA logic achieve significantly faster functionally identical system production release. another example, encryption application might implement Diffie-Hellman exchange algorithm, whereby exponentiation message management could optimally partitioned into FPGA logic embedded processor, respectively. this way, programmable systems paradigm offers tremendous flexibility allow system designers architects optimize trade-offs development time, system performance, system costs. significant that embedded systems enabled Virtex-II solutions "all-soft," that both logic software code controlled soft data file. Because this, cost design maintenance degree design reuse greatly enhanced. Whole system upgrades, including both hardware software, accomplished with unified soft file using System ACEconfiguration solutions, offering same cost ease software-only upgrades.
Time Money
Virtex-II Series, comprising both Virtex-II Virtex-II Pro/Virtex-II families, offers significantly faster time-to-market lower development costs than ASICs. Compared full-custom ASIC, Virtex-II solution eliminates need exhaustive verification during development, allows hardware-software debug system speeds rather than slow software simulation speeds. addition,
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Flexibility Money
Virtex-II Pro/Virtex-II features signal integrity, pre-engineered clocking capabilities, abundance soft cores, significantly reduce development time. Virtex-II Series offers significantly lower development costs than ASICs, lower tool costs, lower third-party costs, absence costs. Virtex-II Series also increases engineering productivity accelerating hardware availability software development increasing software debug speed. addition, availability powerful development tools enables straightforward retargeting other embedded processors into PowerPC platform. Compared other processor architectures, PowerPC core most cases allows higher performance more powerful capabilities, thus used accelerate preproduction performance-sensitive applications.
Flexibility Money
flexibility inherent Virtex-II Series allows system architects fine-tune their architectural partitioning after initial prototype developed. That each subsystem function freely implemented hardware only, software only, combination within hardware-software continuum, depending trade-off between performance complexity. example, wireless infrastructure system might initially implement rake filter function hardware, then change firmware implementation more software control necessary during later development. This repartitioning would impossible custom ASICs without significant time cost penalties. Virtex-II Series offers significantly more flexibility than fixed chip sets ASSPs, allowing user product differentiation future-proofing. design requirement that generally either ASSPs Virtex-II Platform FPGAs, initial design investment FPGA implementation higher. However, advantages Platform FPGA implementations include customizing functionality, ease design reuse, ability design bugs, differentiation user products, ownership control entire system. These important advantages highly competitive markets where ASSPs have standing errata lists unpredictable future availability. contrast, properly developed Platform FPGA designs soft designs that readily maintained reused needed. Therefore, FPGA methodologies provide system manufacturers with greater competitive advantage short term, greater ownership control over their products long term.
Being Discrete
Many high-bandwidth systems today large FPGAs together with discrete SerDes transceivers, discrete communications processors, other discrete components. Virtex-II Pro/Virtex-II family eliminate need many these external components, enhancing time-to-market performance, even providing system cost benefits many cases. Multi-chip solutions using FPGAs typically require over hundred pins interface each discrete quad 3.125 Gbps SerDes transceiver discrete microprocessor. result increased complexity accommodate hundreds traces, reduced system performance on-chip/off-chip connections, higher overall system costs. some cases, increased FPGA pin-count requirement force higher-density FPGA used, again increasing overall cost. these cases, Virtex-II Pro/Virtex-II devices integrate discrete components achieve faster system development, higher system performance, lower costs.
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Chapter Virtex-II Virtex-II FPGA Family
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Chapter
Timing Models
Summary
following topics covered this chapter: Slice Timing Models Block SelectRAM Timing Model Embedded Multiplier Timing Model Timing Models Pin-to-Pin Timing Models Digital Clock Manager Timing Model Additional Timing Models Other Publications: PPC405 Processor Block RocketIO/RocketIO Transceivers
Introduction
large size complexity Virtex-II Pro/Virtex-II FPGAs, understanding timing associated with various paths functional elements become difficult important problem. Although necessary understand various timing parameters order implement most designs using Xilinx software, thorough timing model assist advanced users analyzing critical paths planning speed-sensitive designs. Timing Model chapter broken into sections consisting three basic components: Functional Element Diagram basic architectural schematic illustrating pins connections. Timing Parameters Virtex-II Virtex-II Platform FPGA Data Sheet timing parameter definitions. Timing Diagram illustrates functional element timing parameters relative each other.
This chapter written with Xilinx Timing Analyzer software (TRCE) mind. names, parameter names, paths consistent with Post Route Timing PreRoute Static Timing reports. models this chapter conjunction with both Timing Analyzer software section switching characteristics Virtex-II Platform FPGA Data Sheet. Most timing parameters found section switching characteristics described this chapter.
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Chapter Timing Models
Slice Timing Models
three sections below describe timing parameters reported Data Sheet that associated with slices Configurable Logic Blocks (CLBs). sections correspond their respective (switching characteristics) sections data sheet: "General Slice Timing Model Parameters" (CLB Switching Characteristics) "Slice Distributed Timing Model Parameters" (CLB Distributed Switching Characteristics) "Slice Timing Model Parameters" (CLB Switching Characteristics)
General Slice Timing Model Parameters
Figure illustrates details Virtex-II Pro/Virtex-II slice. Note: Some elements Virtex-II Pro/Virtex-II slice have been omitted clarity. Only
elements relevant timing paths described this section shown.
FXINA FXINB MUXFX
inputs
FF/LAT
MUXF5 inputs
FF/LAT
SUG002_C3_017_030703
Figure 2-1:
Virtex-II Pro/Virtex-II General Slice
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Slice Timing Models
Timing Parameters
Table 2-1: General Slice Timing Parameters
Function Control Signal Description
Parameter
Combinatorial Delays TILO inputs outputs inputs output inputs output FXINA/FXINB inputs output Transparent Latch input XQ/YQ outputs Propagation delay from inputs slice, through look-up tables (LUTs), outputs slice. Propagation delay from inputs slice, through LUTs MUXF5 output slice. Propagation delay from inputs slice, through LUTs MUXF5 output slice. Propagation delay from FXINA/FXINB inputs, through MUXFX output slice. Incremental delay through transparent latch XQ/YQ outputs.
TIF5
TIF5X
TIFXY
TIFNCTL
Sequential Delays TCKO Clock (CLK) XQ/YQ outputs Latch Clock (CLK) XQ/YQ outputs Time after clock that data stable XQ/YQ outputs slice sequential elements (configured flip-flop). Time after clock that data stable XQ/YQ outputs slice sequential elements (configured latch).
TCKLO
Setup Hold Slice Sequential Elements
TxxCK Setup time (before clock edge) TCKxx Hold time (after clock edge) following descriptions setup times only.
TDICK/TCKDI
BX/BY inputs
Time before Clock (CLK) that data from inputs slice must stable D-input slice sequential elements (configured flip-flop). Time before Clock (CLK) that data from input slice must stable D-input slice sequential elements (configured flip-flop). Time before Clock (CLK) that data from input slice must stable D-input slice sequential elements (configured flip-flop). Time before Clock (CLK) that (Clock Enable) input slice must stable CE-input slice sequential elements (configured flip-flop).
TDYCK/TCKDY
input
TDXCK/TCKDX
input
TCECK/TCKCE
input
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Chapter Timing Models
Table 2-1:
General Slice Timing Parameters (Continued)
Function Control Signal Description Time before that (Set/Reset) (Rev) inputs slice must stable SR/Rev-inputs slice sequential elements (configured flip-flop). Synchronous set/reset only.
Parameter
TRCK/TCK
SR/BY inputs
Clock Set/Reset TRPW Minimum Pulse Width (Set/Reset) (Rev) pins. Propagation delay asynchronous Set/Reset slice sequential elements. From SR/BY inputs XQ/YQ outputs. Toggle Frequency Maximum Frequency that flip-flop clocked: 1/(TCH+TCL) Minimum Pulse Width, High. Minimum Pulse Width, Low.
FTOG
Timing Characteristics
Figure illustrates general timing characteristics Virtex-II Pro/Virtex-II slice.
TCECK TDYCK
(DATA)
TRCK TCKO TCKO
UG002_C3_018_101600
S(RESET)
(OUT)
Figure 2-2:
General Slice Timing Characteristics
time TCECK before Clock Event Clock-Enable signal becomes valid-high input slice register. time TDYCK before Clock Event data from input becomes valid-high input slice register reflected time TCKO after Clock Event time TRCK before Clock Event signal (configured synchronous reset this case) becomes valid-high, resetting slice register, this reflected time TCKO after Clock Event Note: most cases software uses DX/DY inputs route data slice registers when possible. This fastest path slice registers saves other slice routing resources.
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Slice Timing Models
Slice Distributed Timing Model Parameters
Figure illustrates details distributed implemented Virtex-II Pro/ Virtex-II slice. Note: Some elements Virtex-II Pro/Virtex-II slice have been omitted clarity. Only
elements relevant timing paths described this section shown.
MUXFX FXINA FXINB
ADDRESS
DATA_IN Address
SLICEWE[2:0]
WSGEN
MUXF5 ADDRESS
DATA_IN Address
(Write Enable)
UG002_C3_019_1204
Figure 2-3:
Virtex-II Pro/Virtex-II Slice Distributed
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Chapter Timing Models
Timing Parameters
Table 2-2:
Parameter
Slice Distributed Timing Parameters
Function Control Signal Description
Sequential Delays Slice Configured (Distributed RAM) outputs active) 16x1 mode outputs active) 32x1 mode Time after Clock (CLK) WRITE operation that data written distributed 16x1 mode) stable outputs slice. Time after Clock (CLK) WRITE operation that data written distributed 32x1 mode) stable outputs slice. Time after Clock (CLK) WRITE operation that data written distributed stable output slice.
TSHCKO16
TSHCKO32
TSHCKOF5
output active)
Setup Hold Slice Configured (Distributed RAM)
Setup time (before clock edge) Hold time (after clock edge) following descriptions setup times only.
TDS/TDH
BX/BY Data inputs (DI)
Time before clock that data must stable input slice (configured RAM), slice BX/BY inputs. Time before clock that address signals must stable inputs slice (configured RAM). Time before clock that Write Enable signal must stable input slice (configured RAM).
TAS/TAH
Address inputs
TWES/TWEH Clock TWPH TWPL
input (SR)
Minimum Pulse Width, High (for Distributed clock). Minimum Pulse Width, (for Distributed clock). Minimum clock period meet address write cycle time.
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Slice Timing Models
Timing Characteristics
Figure illustrates timing characteristics 16-bit distributed implemented Virtex-II Pro/Virtex-II slice (LUT configured RAM).
TWPH TWPL DATA_IN TWES DATA_OUT (X/Y Output) TILO TILO
TSHCK016 WRITE MEM(F) READ WRITE WRITE WRITE MEM(E) READ
UG002_C3_020_031301
Figure 2-4: Slice Distributed Timing Characteristics
Clock Event WRITE Operation
During WRITE operation, contents memory address ADDR inputs changed. data written this memory location reflected outputs synchronously. time TWES before Clock Event Write Enable signal (WE) becomes valid-high, enabling following WRITE operation. time before Clock Event address becomes valid inputs RAM. time before Clock Event DATA becomes valid input reflected output time TSHCKO16 after Clock Event
Clock Event READ Operation
READ operations asynchronous distributed RAM. long write-enable (WE) Low, address asserted time, contents that address reflected outputs after delay length TILO (propagation delay through LUT). Note that Address asserted after Clock Event that contents that location reflected output after delay length TILO.
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Chapter Timing Models
Slice Timing Model Parameters
Figure illustrates shift register implementation Virtex-II Pro/Virtex-II slice. Note: Note: Some elements Virtex-II Pro/Virtex-II slice have been omitted
clarity. Only elements relevant timing paths described this section shown.
Shift_In
MUXFX FXINA FXINB ADDRESS
MC15
(DATA_IN ADDRESS) WSGEN
MUXF5 Shift_In ADDRESS
MC15
(DATA_IN ADDRESS)
Shift_Out
UG002_C3_021_113000
Figure 2-5:
Virtex-II Pro/Virtex-II Slice
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Slice Timing Models
Timing Parameters
Table 2-3:
Parameter
Slice Timing Parameters
Function Control Signal Description
Sequential Delays Slice Configured (Select Shift Register) TREG outputs Time after Clock (CLK) WRITE operation that data written stable outputs slice. Time after Clock (CLK) WRITE operation that data written stable Shiftout XB/YB outputs slice. Time after Clock (CLK) WRITE operation that data written stable output slice.
TCKSH
Shiftout
TREGF5
output
Setup/Hold Slice Configured (Select Shift Register)
TxxS Setup time (before clock edge) TxxH= Hold time (after clock edge) following descriptions setup times only.
TSRLDS/ TSRLDH
BX/BY Data inputs (DI)
Time before clock that data must stable input slice (configured SRL), slice BX/BY inputs. Time before clock that Write Enable signal must stable input slice (configured SRL).
TWSS/TWSH Clock TSRPH TSRPL
input (WE)
Minimum Pulse Width, High (for clock). Minimum Pulse Width, (for clock).
Timing Characteristics
Figure illustrates timing characteristics 16-bit shift register implemented Virtex-II Pro/Virtex-II slice (LUT configured SRL).
TSRPH TSRPL
TWSS
Write Enable (SR)
TSRLDS
Shift_In (DI) Address Data
TREGXB
TREG TILO
TILO
(MC15)
UG002_C3_022_102700
Figure 2-6:
Slice Timing Characteristics
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Chapter Timing Models
Clock Event Shift_In
During WRITE (Shift_In) operation, single-bit content register address ADDR inputs changed, data shifted through SRL. data written this register reflected outputs synchronously, address unchanged during clock event. ADDR inputs changed during clock event, value data addressable output invalid. time TWSS before Clock Event Write Enable signal (SR) becomes valid-high, enabling WRITE operation that follows. time TSRLDS before Clock Event data becomes valid input reflected output after delay length TREG after Clock Event Note: Since address specified Clock Event data input reflected output, because written Register
Clock Event Shift_In
time TSRLDS before Clock Event data becomes valid input reflected output after delay length TREG after Clock Event Note: Since address still specified Clock Event data input reflected
output, because written Register
Clock Event Shift_In Addressable (Asynchronous) READ
READ operations asynchronous. address changed (between clock events), contents register that address reflected addressable output (X/Y outputs) after delay length TILO (propagation delay through LUT). time TSRLDS before Clock Event Data becomes valid input SRL, reflected output TREG time after Clock Event Notice that address changed (from some time after Clock Event value stored Register this time this example, this first data shifted in), reflected output after delay length TILO.
Clock Event (Most Significant Bit) Changes
time TREGXB after Clock Event first shifted into becomes valid (logical this case) output slice MC15 output (SRL).
Block SelectRAM Timing Model
Introduction
This section describes timing parameters associated with block SelectRAM (illustrated Figure 2-7) Virtex-II Pro/Virtex-II FPGA devices. This section intended used with section switching characteristics Virtex-II Platform FPGA Data Sheet Timing Analyzer (TRCE) report from Xilinx software. specific timing parameter values, refer switching characteristics section Virtex-II Platform FPGA Data Sheet.
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Block SelectRAM Timing Model
18-Kbit Block SelectRAM ADDR
DS031_10_102000
Figure 2-7:
Block SelectRAM Block Diagram
Timing Parameters
Table 2-4: Block SelectRAM Timing Parameters Function Control Signal Description
Parameter
Setup Hold Relative Clock (CLK)
TBxCK Setup time (before clock edge) TBCKx Hold time (after clock edge) following descriptions setup times only.
TBACK/TBCKA TBDCK/TBCKD TBECK/TBCKE
Address inputs Data inputs Enable Synchronous Set/Reset Write Enable
ADDR
Time before clock that address signals must stable ADDR inputs block RAM. Time before clock that data must stable inputs block RAM. Time before clock that enable signal must stable input block RAM. Time before clock that synchronous set/reset signal must stable input block RAM. Time before clock that write enable signal must stable input block RAM.
TBRCK/TBCK
TBWCK/TBCKW
Clock
TBCKO Clock Output Time after clock that output data stable outputs block RAM.
Clock
TBPWH TBPWL Clock Clock Minimum pulse width, high. Minimum pulse width, low.
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Chapter Timing Models
Timing Characteristics
timing diagram Figure describes single-port block Write-First mode. timing Read-First No-Change modes similar (see Chapter "Design Considerations").
TBPWH TBACK ADDR TBECK TBRCK TBWCK Disabled Read Write Read Reset Disabled TBDCK DDDD TBCKO (00) CCCC CCCC* BBBB (7E) AAAA 0101** 0000 TBPWL
Write Mode "WRITE_FIRST" SRVAL 0101
ug002_c3_002_100300
Figure 2-8:
Block SelectRAM Timing Characteristics
time block disabled; (enable) low.
Clock Event READ Operation
During read operation, contents memory address ADDR inputs unchanged. TBACK before Clock Event address becomes valid ADDR inputs block RAM. time TBECK before Clock Event Enable goes High input block RAM, enabling memory READ operation that follows. time TBCKO after Clock Event contents memory address become stable pins block RAM.
Clock Event WRITE Operation
During write operation, content memory location specified address ADDR inputs replaced value pins immediately reflected output latches WRITE-FIRST mode); (enable) high. time TBACK before Clock Event address becomes valid ADDR inputs block RAM. time TBDCK before Clock Event data CCCC becomes valid inputs block RAM. time TBWCK before Clock Event Write Enable becomes valid following block RAM. time TBCKO after Clock Event data CCCC becomes valid outputs block RAM.
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Block SelectRAM Timing Model
Clock Event (Synchronous Set/Reset) Operation
During operation, initialization parameter value SRVAL loaded into output latches block SelectRAM. operation does change contents memory independent ADDR inputs. time TBRCK before Clock Event synchronous set/reset signal becomes valid (High) input block RAM. time TBCKO after Clock Event SRVAL 0101 becomes valid outputs block RAM.
Clock Event Disable Operation
De-asserting enable signal disables write, read operation. disable operation does change contents memory values output latches. time TBECK before Clock Event enable signal becomes valid (Low) input block RAM. After Clock Event data outputs block unchanged.
Timing Model
Figure illustrates delay paths associated with implementation block SelectRAM. This example takes simplest paths chip (these paths vary greatly depending design). This timing model demonstrates where block SelectRAM timing parameters used.
FPGA
Block SelectRAM Data Address Write Enable Enable Synchronous Set/Reset [TIOPI NET] TBDCK [TIOPI NET] TBACK [TIOPI NET*] TBWCK [TIOPI NET] TBECK [TIOPI NET] TBRCK
ADDR
TBCKO [NET TIOOP]
Data
[TGI0O NET] BUFGMUX Clock [TIOPI NET]
ug002_c3_003_121701
Figure 2-9:
Block SelectRAM Timing Model
Varying interconnect delays TIOPI I-output delay TIOOP O-input delay TGI0O BUFGMUX delay
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Chapter Timing Models
Embedded Multiplier Timing Model
Introduction
This section explains timing parameters associated with embedded 18-bit 18-bit multipliers Virtex-II Pro/Virtex-II FPGAs (see Figure 2-10). propagation delays through embedded multiplier differ based size multiplier function implemented. longest delay through multiplier highest order output (P35). Therefore, 18-bit 18-bit signed multiplier implemented, worst-case delay this function longest delay associated with embedded multiplier block. smaller (LSB) multipliers used, shorter delays realized. This section intended used conjunction with section switching characteristics Virtex-II Platform FPGA Data Sheet Timing Analyzer (TRCE) report from Xilinx software. specific timing parameter values, refer Virtex-II Platform FPGA Data Sheet.
Multiplier Block A[17:0]
MULT B[17:0]
P[35:0]
DS031_40_100400
Figure 2-10:
Embedded 18-bit 18-bit Multiplier Block
Timing Parameters
Worst-Case Propagation Delays
TMULT timing parameter reported Timing Analyzer software. These values correspond propagation delay through multiplier specific output multiplier block. shortest delay longest These parameters found table entitled "Multiplier Switching Characteristics" Module Virtex-II Platform FPGA Data Sheet. delay-to-pin ratio essentially linear (see Figure 2-11). This implies that smaller multiply functions faster than larger ones. This true long inputs used.
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Embedded Multiplier Timing Model
Delay
Figure 2-11:
UG002_C3_023_092500
Pin-to-Delay Ratio Curve
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Chapter Timing Models
Timing Characteristics
Figure 2-12 illustrates result (outputs) 4-bit 4-bit unsigned multiply implemented embedded multiplier block.
Time input [3.0] input [3.0]
1111
1111
TMULT (P0) TMULT (P1) TMULT (P2) TMULT (P3) TMULT (P4) TMULT (P5) TMULT (P6) TMULT (P7)
UG002_C3_024_101300
Figure 2-12:
Embedded Multiplier Block Timing Diagram
time 4-bit numbers multiplied become valid A[0.3], B[0.3] inputs embedded multiplier. result appears output pins P[0.7] staggered fashion. First, becomes valid time TMULT(P0), followed each subsequent output pin, until becomes valid time TMULT (P7). this case, delay this multiply function should correspond that other words, result valid until output pins become valid.
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Timing Models
Timing Models
following three sections describe timing parameters associated with Virtex-II Pro/Virtex-II IOB. These three sections are: "IOB Input Timing Model Parameters" "IOB Output Timing Model Parameters" "IOB 3-State Timing Model Parameters"
These sections intended used conjunction with section switching characteristics Data Sheet Timing Analyzer (TRCE) report from Xilinx software. specific timing parameter values, refer Data Sheet.
Note Standard Adjustments:
"IOB Input Output Switching Characteristics Standard Adjustments" tables Module Data Sheet delay adders (+/-) added timing parameter values associated with Global Clock (see "Pin-to-Pin Timing Models," page 55), standard other than LVCMOS_25 used. values specified Data Sheet parameters covered this section specified LVCMOS_25 another standard used, these delays change. However, there several exceptions. following parameters associated with going high-impedance (3-State buffer OFF) should adjusted: TIOTHZ TIOTLPHZ TGTS TIOCKHZ TIOSRHZ
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Chapter Timing Models
Input Timing Model Parameters Figure 2-13 illustrates inputs.
LATCH ICLK1
LATCH ICLK2
UG002_C3_004_101300
Figure 2-13:
Virtex-II Pro/Virtex-II Inputs
Timing Parameters
Table 2-5: Input Timing Parameters
Function Control Signal Description
Parameter Propagation Delays TIOPI TIOPID
Propagation delay from output with delay adder. Propagation delay from output with delay adder. Propagation delay from output transparent latch with delay adder. Propagation delay from output transparent latch with delay adder.
TIOPLI
TIOPLID
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Timing Models
Table 2-5:
Input Timing Parameters
Function Control Signal Description
Parameter
Setup Hold With Respect Clock Input Register
TxxCK Setup time (before clock edge) TxxCKxx Hold time (after clock edge) following descriptions setup times only.
TIOPICK/TIOICKP
input with delay
Time before clock that input signal from must stable input Input Register, with delay. Time before clock that input signal from must stable input Input Register, with delay. Time before clock that Clock Enable signal must stable input Input Register. Time before clock that Set/Reset signal must stable input Input Register.
TIOPICKD/TIOICKPD
input with delay
TIOICECK/TIOCKICE
input
TIOSRCKI Clock TIOCKIQ Set/Reset Delays TIOSRIQ
input (IFF, synchronous)
Clock (CLK) (IQ) output
Time after clock that output data stable output Input Register.
Input (asynchronous)
Time after Set/Reset signal toggled that output input register (IQ) reflects signal. Time after Global Set/Reset toggled that output input register (IQ) reflects reset.
TGSRQ
output
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Chapter Timing Models
Timing Characteristics
Figure 2-14 illustrates input register timing.
TIOPICK TIOICECK TIOSRCKI (reset) TIOCKIQ TIOCKIQ
UG002_c3_005_112700
Figure 2-14:
Input Register Timing Characteristics
Clock Event
time TIOICECK before Clock Event input clock enable signal becomes validhigh input input register, enabling input register incoming data. time TIOPICK before Clock Event input signal becomes valid-high input input register reflected output input register time TIOCKIQ after Clock Event
Clock Event
time TIOSRCKI before Clock Event signal (configured synchronous reset this case) becomes valid-high resetting input register reflected output time TIOCKIQ after Clock Event
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Timing Models
Timing Characteristics, DDFigure 2-15 illustrates input register timing.
ICLK1 ICLK2 TIOPICK TIOICECK TIOSRCK (reset) TIOCKIQ TIOCKIQ TIOPICK
TIOCKIQ TIOCKIQ
UG002_c3_006_112700
Figure 2-15: Input Register Timing Characteristics
Clock Event
time TIOICECK before Clock Event input clock enable signal becomes validhigh input both input registers, enabling them incoming data. Since signals common both registers, care must taken toggle these signals between rising edges ICLK1 ICLK2 well meeting register setup-time relative both clocks. time TIOPICK before Clock Event (rising edge ICLK1) input signal becomes valid-high input both registers reflected output inputregister time TIOCKIQ after Clock Event
Clock Event
time TIOPICK before Clock Event (rising edge ICLK2) input signal becomes valid-low input both registers reflected output input-register time TIOCKIQ after Clock Event change this case).
Clock Event
time TIOSRCKI before Clock Event signal (configured synchronous reset this case) becomes valid-high resetting input-register (IQ1) time TIOCKIQ after Clock Event input-register (IQ2) time TIOCKIQ after Clock Event
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Chapter Timing Models
Output Timing Model Parameters
Figure 2-16 illustrates outputs.
LATCH OTCLK1 Shared registers LATCH Attribute INIT1 INIT0 SRHIGH SRLOW Attribute INIT1 INIT0 SRHIGH SRLOW
3-State Control
OTCLK2
Reset Type SYNC ASYNC
UG002_C3_007_101300
Figure 2-16:
Virtex-II Pro/Virtex-II Output
Timing Parameters
Table 2-6: Output Timing Parameters
Function Control Signal Description
Parameter Propagation Delays TIOOP TIOOLP
Propagation delay from input pad. Propagation delay from input transparent latch.
Setup Hold With Respect Clock Output Register
TxxCK Setup time (before clock edge) TxxCKxx Hold time (after clock edge) following descriptions setup times only.
TIOOCK/TIOCKO
input
Time before clock that data must stable input Output Register. Time before clock that Clock Enable signal must stable input Output Register.
TIOOCECK/TIOCKOCE
input
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Timing Models
Table 2-6:
Output Timing Parameters
Function Control Signal Description Time before clock that Set/Reset signal must stable input Output Register.
Parameter
TIOSRCKO/TIOCKOSR Clock TIOCKP Set/Reset Delays TIOSRP
input (OFF)
Clock (CLK)
Time after clock that output data stable pad.
Input (asynchronous)
Time after Set/Reset input toggled that reflects reset. Time after Global Set/Reset toggled that reflects reset.
TIOGSRQ
Timing Characteristics
Figure 2-17 illustrates output register timing.
TIOOCK TIOOCECK TIOSRCKO (reset) TIOCKP
UG002_C3_008_112700
Figure 2-17:
Output Register Timing Characteristics
Clock Event
time TIOOCECK before Clock Event output clock enable signal becomes validhigh input output register, enabling output register incoming data. time TIOOCK before Clock Event output signal becomes valid-high input output register reflected time TIOCKP after Clock Event
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Chapter Timing Models
Clock Event
time TIOSRCKO before Clock Event signal (configured synchronous reset this case) becomes valid-high, resetting output register reflected time TIOCKP after Clock Event
Timing Characteristics, DDFigure 2-18 illustrates output register timing.
OTCLK1
OTCLK2 TIOOCK TIOOCK TIOOCECK TIOSRCKO TIOCKP TIOCKP
UG002_c3_009_112700
Figure 2-18:
Output Register Timing Characteristics
Clock Event
time TIOOCECK before Clock Event output clock enable signal becomes validhigh input both output registers, enabling them incoming data. Since signal common both registers, care must taken toggle this signal between rising edges OTCLK1 OTCLK2 well meeting register setup-time relative both clocks. time TIOOCK before Clock Event (rising edge OTCLK1), output signal becomes valid-high input output register reflected time TIOCKP after Clock Event
Clock Event
time TIOOCK before Clock Event (rising edge OTCLK2), output signal becomes valid-high input output register reflected time TIOCKP after Clock Event change this case).
Clock Event
time TIOSRCKO before Clock Event signal (configured synchronous reset this case) becomes valid-high, resetting output-register (reflected time
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Timing Models
TIOCKP after Clock Event change this case) output-register (reflected time TIOCKP after Clock Event change this case).
3-State Timing Model Parameters
Figure 2-19 illustrates 3-state timing
Attribute INIT1 INIT0 SRHIGH SRLOW
LATCH OTCLK1 Shared registers LATCH OTCLK2
Attribute INIT1 INIT0 SRHIGH SRLOW
Reset Type SYNC ASYNC
UG002_C3_010_120600
Figure 2-19:
Virtex-II Pro/Virtex-II 3-State
Timing Parameters
Table 2-7: 3-State Timing Parameters
Function Control Signal Description
Parameter Propagation Delays TIOTHZ
Time after input toggled that goes high-impedance. Time after input toggled that goes from high-impedance valid data. Time after input transparent latch toggled that goes high-impedance.
TIOTON
TIOTLPHZ
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Chapter Timing Models
Table 2-7:
3-State Timing Parameters (Continued)
Function Control Signal Description Time after input transparent latch toggled that goes from high-impedance valid data. Time after Global 3-state signal asserted that goes high-impedance.
Parameter
TIOTLPON
TGTS Setup Hold With Respect Clock 3-State Register
TxxCK Setup time (before clock edge) TxxCKxx Hold time (after clock edge)
following descriptions setup times only.
TIOTCK/TIOCKT
input
Time before clock that signal must stable input 3-state Register. Time before clock that clock enable signal must stable input 3-state Register. Time before clock that set/reset signal.
TIOTCECK/TIOCKTCE
input
TIOSRCKT/TIOCKTSR Clock TIOCKHZ
input (TFF)
Clock (CLK) High-Z Clock (CLK) valid data
Time after clock that goes high-impedance. Time after clock that goes from high-impedance valid data.
TIOCKON Set/Reset Delays TIOSRHZ
Input High-Z (asynchronous)
Time after signal toggled that goes high-impedance. Time after signal toggled that goes from high-impedance valid data.
TIOSRON
Input valid data (asynchronous)
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Timing Models
Timing Characteristics
Figure 2-20 illustrates 3-state register timing.
TIOTCK TIOTCECK TIOSRCKT TIOCKHZ DATA TIOCKON DATA DATA
UG002_c3_011_101300
Figure 2-20:
3-State Register Timing Characteristics
Clock Event
time TIOTCECK before Clock Event 3-state clock enable signal becomes validhigh input 3-state register, enabling 3-state register incoming data. time TIOTCK before Clock Event 3-state signal becomes valid-high input 3-state register, returning high-impedance time TIOCKHZ after Clock Event
Clock Event
time TIOSRCKT before Clock Event signal (configured synchronous reset this case) becomes valid-high, resetting 3-state register returning valid data time TIOSRON after Clock Event
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Chapter Timing Models
Timing Characteristics, DDFigure 2-21 illustrates 3-state register timing.
OTCLK1
OTCLK2 TIOTCK TIOTCK TIOTCECK TIOSRCKT TIOCKHZ DATA TIOCKON DATA TIOSRON DATA
UG002_c3_012_101300
Figure 2-21:
3-State Register Timing Characteristics
Clock Event
time TIOTCECK before Clock Event 3-state clock enable signal becomes valid-high input both 3-state registers, enabling them incoming data. Since signal common both registers, care must taken toggle this signal between rising edges OTCLK1 OTCLK2 well meeting register setup-time relative both clocks.
Clock Event
time TIOTCK before Clock Event (rising edge OTCLK2), 3-state signal becomes valid-high input 3-state register switching highimpedance time TIOCKHZ after Clock Event
Clock Event
time TIOTCK before Clock Event (rising edge OTCLK1), 3-state signal becomes valid-high input 3-state register keeping high-impedance another half clock cycle (half period OTCLK1
Clock Event
time TIOTCK before Clock Event (rising edge OTCLK2), 3-state signal becomes valid-low input 3-state register switching valid data time TIOCKON after Clock Event This repeated 3-state signal following clock event maintaining valid data until Clock Event
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Pin-to-Pin Timing Models
Clock Event
time TIOTCK before Clock Event (rising edge OTCLK2), 3-state signal becomes valid-high input 3-state register switching highimpedance time TIOCKHZ after Clock Event
Clock Event
time TIOSRCKT before Clock Event (rising edge OTCLK1), signal (configured synchronous reset this case) becomes valid-high input 3-state Register returning valid data time TIOSRON after Clock Event
Pin-to-Pin Timing Models
This section explains delays timing parameters associated with Global Clock network DCM. These delays true pin-to-pin delays relative Global Clock output input with without DCM. This section consists parts: "Global Clock Input Output" "Global Clock Setup Hold"
former describes delay from Global Clock (with without DCM) output Output flip-flop. latter describes set-up time Input flipflop from input relative Global Clock (with without DCM). values reported switching characteristics section Virtex-II Platform FPGA Data Sheet LVCMOS_25 standards. different standards, adjust these values with those shown "IOB Switching Characteristics Standard Adjustments" tables. This section intended used conjunction with section switching characteristics Virtex-II Platform FPGA Data Sheet Timing Analyzer (TRCE) report from Xilinx software. specific timing parameter values, refer Virtex-II Platform FPGA Data Sheet.
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Chapter Timing Models
Global Clock Input Output
Figure 2-22 illustrates paths associated with timing parameters defined this section. Note that they differ only their DCM.
Global Clock
BUFGMUX Data Output Register Output Data
Output Register Output
BUFGMUX
Global Clock
UG002_C3_013_101300
Figure 2-22: Global Clock Input Output Model
Timing Parameters
Table 2-8: Global Clock Input Output Timing Parameters
Description Time after Global Clock (pin), using DCM, that output data from Output flip-flop stable output pin. Time after Global Clock (pin), without DCM, that output data from Output flip-flop stable output pin.
Parameter TICKOFDLL TICKOF
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Pin-to-Pin Timing Models
Timing Characteristics
waveforms depicted Figure 2-23 demonstrate relation Global Clock pin, output data, timing parameters.
Global Clock DCM) D-input Output Register TICKOF Output
Global Clock (With DCM) D-input Output Register TICKOFDLL Output
UG002_C3_015_101300
Figure 2-23: Global Clock Input Output Timing Characteristics
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Chapter Timing Models
Global Clock Setup Hold
Figure 2-24 illustrates paths associated with timing parameters defined this section. Note, they differ only their DCM.
Global Clock
BUFGMUX Input
Input
BUFGMUX
Global Clock
UG002_C3_014_101300
Figure 2-24:
Global Clock Setup Hold Model
Timing Parameters
Setup Hold Input Registers Relative Global Clock (pin):
TPSDLL TPHDLL Time before Global Clock (pin), with DCM, that input signal must stable D-input input register. TPSFD TPHFD Time before Global Clock (pin), without DCM, that input signal must stable D-input input register. Note: TPSFD Setup time (before clock edge) TPHFD Hold time (after clock edge). previous descriptions setup times only.
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Pin-to-Pin Timing Models
Timing Characteristics
waveforms depicted Figure 2-25 demonstrate relation Global Clock pin, input data, timing parameters.
Global Clock DCM) Input TPSFD TPHFD
Global Clock (With DCM) Input TPSDLL TPHDLL
UG002_C3_016_101300
Figure 2-25:
Global Clock Setup Hold Timing Characteristics
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Chapter Timing Models
Digital Clock Manager Timing Model
This section describes timing parameters associated with Digital Clock Manager (DCM), which reported Virtex-II Platform FPGA Data Sheet. Note that these parameters used Timing Analyzer software production timing reports; they measured values fully characterized silicon. specific timing parameter values, refer Virtex-II Platform FPGA Data Sheet. This section discusses following: Operating Frequency Ranges: minimum maximum frequencies supported clock inputs outputs. Input Clock Tolerances: Input clock period (pulse widths), jitter, drift requirements proper function clock inputs. Output Clock Precision: Output clock period jitter, phase offsets, duty cycle clock outputs (worst case). Miscellaneous Timing Parameters: lock times, delay shifting range.
detailed description input clock tolerance, jitter, phase offset waveforms this section.
Operating Frequency Ranges
Figure 2-26 illustrates functional block corresponding timing parameters clock inputs outputs.
CLKIN (CLKIN_FREQ_(DLL FX)_(LF HF)) CLKFB CLK0 CLKOUT_FREQ_1X_(LF CLK90 CLKOUT_FREQ_1X_LF CLK180 CLKOUT_FREQ_1X_(LF CLK270 CLKOUT_FREQ_1X_LF CLK2X CLKOUT_FREQ_2X_LF CLK2X180 CLKOUT_FREQ_2X_LF CLKDV CLKOUT_FREQ_DV_(LF CLKFX CLKOUT_FREQ_FX_(LF CLKFX180 CLKOUT_FREQ_FX_(LF PSDONE
PSINCDEC PSEN PSCLK_FREQ_(LF DSSEN
LOCKED STATUS
ug002_c1_004_112800
Figure 2-26: Functional Block: Operating Frequency Ranges
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Digital Clock Manager Timing Model
Timing Parameters
Table 2-9: Operating Frequency Range Parameters
Parameter Frequency Mode CLKOUT_FREQ_1X_LF minimum maximum frequency CLK0, CLK90, CLK180, CLK270 outputs lowfrequency mode. minimum maximum frequency CLK2X CLK2X180 outputs low-frequency mode. minimum maximum frequency CLKDV output low-frequency mode. minimum maximum frequency CLKFX CLKFX180 outputs low-frequency mode. minimum maximum frequency CLKIN input low-frequency mode when using delay-locked loop (DLL) outputs. minimum maximum frequency CLKIN input low-frequency mode when using outputs. minimum maximum frequency PSCLK input low-frequency mode. Description
CLKOUT_FREQ_2X_LF CLKOUT_FREQ_DV_LF CLKOUT_FREQ_FX_LF CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
PSCLK_FREQ_LF High Frequency Mode CLKOUT_FREQ_1X_HF CLKOUT_FREQ_DV_HF CLKOUT_FREQ_FX_HF CLKIN_FREQ_DLL_HF
minimum maximum frequency CLK0, CLK180 outputs high-frequency mode. minimum maximum frequency CLKDV output high-frequency mode. minimum maximum frequency CLKFX CLKFX180 outputs high-frequency mode. minimum maximum frequency CLKIN input high-frequency mode when using outputs. minimum maximum frequency CLKIN input high-frequency mode when using outputs. minimum maximum frequency PSCLK input high-frequency mode.
CLKIN_FREQ_FX_HF
PSCLK_FREQ_HF
Notes:
Delay-locked loop (DLL) outputs include: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV. outputs include: CLKFX CLKFX180
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Chapter Timing Models
Input Clock Tolerances
Timing Parameters
Table 2-10: Input Clock Tolerance Parameters
Parameter PSCLK_PULSE Description minimum pulse width (HIGH LOW) that PSCLK input have over range frequencies. minimum pulse width (HIGH LOW) that CLKIN input have over range frequencies. Also applies PSCLK. maximum allowed variation delay (across environmental changes) feedback clock path when routed externally board-level de-skew.
CLKIN_PULSE
CLKFB_DELAY_VAR_EXT
Frequency Mode CLKIN_CYC_JITT_DLL_LF maximum cycle-to-cycle jitter CLKIN input have when using outputs lowfrequency mode. maximum cycle-to-cycle jitter CLKIN input have when using outputs lowfrequency mode. maximum period jitter CLKIN input have when using outputs low-frequency mode. maximum period jitter CLKIN input have when using outputs low-frequency mode.
CLKIN_CYC_JITT_FX_LF
CLKIN_PER_JITT_DLL_LF
CLKIN_PER_JITT_FX_LF
High Frequency Mode CLKIN_CYC_JITT_DLL_HF maximum cycle-to-cycle jitter CLKIN input have when using outputs highfrequency mode. maximum cycle-to-cycle jitter CLKIN input have when using outputs highfrequency mode. maximum period jitter CLKIN input have when using outputs high-frequency mode. maximum period jitter CLKIN input have when using outputs high-frequency mode.
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_DLL_HF
CLKIN_PER_JITT_FX_HF
Notes:
frequencies applicable CLKIN_PULSE range from >400 MHz. These frequencies also apply PSCLK_PULSE. Since PSCLK less than MHz, pulse width under this condition specified PSCLK only.
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Digital Clock Manager Timing Model
Output Clock Precision
Timing Parameters
Table 2-11: Output Clock Precision Parameters
Parameter CLKOUT_PER_JITT_0 CLKOUT_PER_JITT_90 CLKOUT_PER_JITT_180 CLKOUT_PER_JITT_270 CLKOUT_PER_JITT_2X CLKOUT_PER_JITT_DV1 CLKOUT_PER_JITT_DV2 CLKOUT_PER_JITT_FX CLKIN_CLKFB_PHASE CLKOUT_PHASE CLKOUT_DUTY_CYCLE_DLL CLKOUT_DUTY_CYCLE_FX Description maximum period jitter CLK0 output clock from (worst case). maximum period jitter CLK90 output clock from (worst case). maximum period jitter CLK180 output clock from (worst case). maximum period jitter CLK270 output clock from (worst case). maximum period jitter CLK2X CLK2X180 output clocks from (worst case). maximum period jitter CLKDV (integer division) output clock from (worst case). maximum period jitter CLKDV (non-integer division) output clock from (worst case). maximum period jitter output clocks from (worst case). Maximum phase offset between CLKIN CLKFB inputs DCM. Maximum phase offset between clock outputs. duty-cycle precision outputs. duty-cycle precision outputs.
Miscellaneous Timing Parameters
Table 2-12: Miscellaneous Timing Parameters
Parameter LOCK_DLL LOCK_FX LOCK_DLL_FINE_SHIFT FINE_SHIFT_RANGE DCM_TAP Description Time required lock over range clock frequencies when using outputs. Time required lock when using outputs. Additional lock time when performing fine phase shifting. Absolute range fine phase shifting. Resolution delay line.
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Chapter Timing Models
waveforms Figure 2-27 demonstrate relationship between clock tolerance, jitter, phase.
Period Tolerance: allowed input clock period change nanoseconds.
TCLKIN
TCLKIN Input Clock Jitter
Output Jitter: difference between ideal reference clock edge actual design.
Phase Offset Maximum Phase Difference
Ideal Period Actual Period Jitter Maximum Phase Difference Phase Offset
ds022_24_112800
Figure 2-27:
Output jitter period jitter measured output clocks, excluding input clock jitter. Phase offset between CLKIN CLKFB worst-case fixed time difference between rising edges CLKIN CLKFB, excluding output jitter input clock jitter. Phase offset between clock outputs worst-case fixed time difference between rising edges outputs, excluding output jitter input clock jitter. Maximum phase difference between CLKIN CLKFB output jitter phase offset between CLKIN CLKFB, greatest difference between CLKIN CLKFB rising edges alone (excluding input clock jitter). Maximum phase difference between clock outputs output jitter phase offset between clock outputs, greatest difference between output rising edges alone (excluding input clock jitter).
Jitter
Jitter, Phase, Tolerance Timing Waveforms
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Additional Timing Models Other Publications: PPC405 Processor Block
Additional Timing Models Other Publications: PPC405 Processor Block RocketIO/RocketIO Transceivers
their length complexity, timing models PPC405 Processor Block RocketIO/RocketIO Multi-Gigabit Transceivers included this User Guide. They found publications described below, which cover detail operation implementation these Virtex-II Pro/Virtex-II components:
PPC405 Processor Block Timing Models
Timing models PPC405 Processor Block found PowerPC Processor Block Reference Guide. most current version this guide available website intended used conjunction with Module Virtex-II Pro/Virtex-II Data Sheet Timing Analyzer (TRCE) report from Xilinx software. specific timing parameter values, refer data sheet.
RocketIO Transceiver Timing Models
Timing models RocketIO Transceiver found RocketIO Transceiver User Guide, UG024. most current version this volume available Xilinx website
RocketIO Transceiver Timing Models
Timing models RocketIO Transceiver found RocketIO Transceiver User Guide, UG035. most current version this volume available Xilinx website
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Chapter Timing Models
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Chapter
Design Considerations
Summary
This chapter covers following topics: RocketIO RocketIO Transceivers Processor Block Global Clock Networks Digital Clock Managers (DCMs) Block SelectRAMMemory Distributed SelectRAM Memory Look-Up Tables Shift Registers (SRLs) Large Multiplexers Products (SOP) Logic Embedded Multipliers Single-Ended SelectIO-Ultra Resources Digitally Controlled Impedance (DCI) Double-Data-Rate (DDR) LVDS LVPECL Bitstream Encryption CORE Generator System
Introduction
This chapter describes take advantage many special features Virtex-II /Virtex-II architecture achieve maximum density performance. many cases, functions described automatically generated using Xilinx CORE Generatortool. This noted throughout chapter, following sections specifically: Block SelectRAMMemory Distributed SelectRAM Memory Look-Up Tables Shift Registers (SRLs) Large Multiplexers Embedded Multipliers
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Chapter Design Considerations
RocketIO RocketIO Transceivers
Virtex-II Pro/Virtex-II devices provide twenty multi-gigabit transceivers capable various high-speed serial standards such Gigabit Ethernet, FiberChannel, Infiniband, XAUI. addition, channel-bonding feature aggregates multiple channels allowing even higher data transfer rate. most up-to-date information RocketIO RocketIO transceiver features, design examples, power considerations, board layout suggestions, refer most current revision RocketIO Transceiver User Guide RocketIO Transceiver User Guide Xilinx website
Processor Block
additional user manuals detail hardware software design aspects processor block. PowerPC Processor Block Reference Guide provides information input/output signals, timing relationships between signals, mechanisms software control interface operation. PowerPC Processor User Manual serves stand-alone reference application system programmers PPC405 processor core. most up-to-date information PPC405 processor core, refer current revisions these manuals Xilinx website
Global Clock Networks
Introduction
Virtex-II Pro/Virtex-II devices support very high frequency designs thus require low-skew advanced clock distribution. With device density million system gates, numerous global clocks necessary most designs. Therefore, provide uniform portable solution (soft-IP), Virtex-II Pro/Virtex-II devices from XC2VP2 XC2VP100 have global clock buffers support global clock domains. eight these clocks used quadrant device synchronous logic elements (that registers, 18Kb block RAM, pipeline multipliers) IOBs. software tools place route these global clocks automatically. design uses between clocks, must partitioned into quadrants, with clocks quadrant. more than clocks required, backbone horizontal vertical long lines routing resources) used additional clock network. addition clock distribution, clock buffers also "glitch-free" synchronous multiplexers. These multiplexers capable switching between asynchronous synchronous) clocks time. particular phase relations between clocks needed. clock multiplexers also configured global clock buffer with clock enable. clock stopped High clock buffer output.
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Global Clock Networks
Clock Distribution Resources
various resources available manage distribute clocks include: Sixteen clock pads that used regular user I/Os used clock inputs. sixteen clock pads configured standard, including differential standards (for example, LVDS). Sixteen "IBUFG" elements that represent clock inputs VHDL Verilog designs. Eight "IBUFGDS" elements (that attributes LVPECL_25, LVDS_25, LDT_25, ULVDS_25) that represent differential clock input pairs VHDL Verilog design. Each IBUFGDS replaces IBUFG elements. Four twelve Digital Clock Managers (DCMs), depending device size, deskew generate clocks. more information DCMs, "Digital Clock Managers (DCMs)," page Sixteen "BUFGMUX" elements that consist sixteen global clock buffers (BUFG), global clock buffers with clock enable (BUFGCE), global clock multiplexers (BUFGMUX).
Figure illustrates placement these clock resources Virtex-II Pro/Virtex-II devices (the XC2VP20/XC2VPX20 through XC2VP70/XC2VPX70) that have eight DCMs.
GCLK Pads User I/Os IBUFG BUFGMUX IBUFG User I/Os
BRAM Multiplier
BRAM Multiplier
BRAM Multiplier Clock Domains
BRAM Multiplier
BRAM Multiplier
BRAM Multiplier
BRAM Multiplier
BRAM Multiplier
BUFGMUX IBUFG User I/Os GCLK Pads IBUFG
User I/Os
UG002_C2_092_120100
Figure 3-1:
Clock Resources Virtex-II Pro/Virtex-II Devices
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Chapter Design Considerations
simple scheme distribute external clock device implement clock with IBUFG input buffer connected BUFG global buffer, shown Figure Figure 3-3. primary (GCLKP) secondary (GCLKS) clock pads have relationship with P-side N-side differential clock inputs. banks GCLKP corresponds N-side, GCLKS corresponds P-side differential clock input. banks this correspondence reversed.
IBUFG BUFG
GCLK
Clock Distribution
Clock Input IBUFGDS GCLKS GCLKP (Bank Scheme) Clock Distribution BUFG
Differential Clock Input
UG002_C2_105_080601
Figure 3-2:
Simple Clock Distribution (Bank Scheme)
IBUFG BUFG
GCLK
Clock Distribution
Clock Input
IBUFGDS GCLKP GCLKS
BUFG
Clock Distribution
Differential Clock Input
(Bank Scheme)
UG002_C2_084_080601
Figure 3-3:
Simple Clock Distribution (Bank Scheme)
Major synthesis tools automatically infer IBUFG BUFG when corresponding input signal used clock VHDL Verilog code. high frequency adapted (frequency, phase, forth) clock distribution with skew implemented using between output IBUFG input BUFG, shown Figure 3-4. "Digital Clock Managers (DCMs)," page provides details about DCMs their use.
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Global Clock Networks
IBUFG BUFG
GCLK
CLKIN CLKFB
CLK0
Clock Distribution
UG002_C2_085_050503
Figure 3-4: Clock Distribution with Clock distribution from internal sources also possible with BUFG only with DCM, shown Figure 3-5.
BUFG
Logic
Clock Distribution
BUFG
Logic CLKIN CLKFB CLKO
Clock Distribution
UG002_C2_086_050503
Figure 3-5:
Internal Logic Driving Clock Distribution
Global Clock Inputs
clock buffer inputs either clock pads (refer Virtex-II Virtex-II Platform FPGA Data Sheet), outputs DCM, local interconnect. Each clock buffer synchronous "glitch-free" multiplexer with clock inputs select input. Internal logic alternatively regular IOB) feed clock inputs. internal external signal drive select input clock enable input. possible inputs driving global clock buffer multiplexer summarized Table 3-1.
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Chapter Design Considerations
Table 3-1:
Inputs Driving Global Clock Buffers DCMs
Destination Source BUFG(I) BUFGCE(I)
Dedicated same quadrant(1) Same edge (top bottom)(2) General interconnect General interconnect
BUFGCE (CE)
General interconnect General interconnect
BUFGMUX
Dedicated same quadrant(1) Same edge (top bottom)(2) General interconnect General interconnect General interconnect
BUFGMUX
General interconnect General interconnect
(CLKIN)
Same edge General interconnect(3) General interconnect(3) General interconnect(3) Global clock Global clock
External Clock IBUFG(O) Clock Outputs Internal Logic User IBUF(O) (not IBUFG) BUFG(O) BUFGMUX(O)
Notes:
IBUFGs quadrant have dedicated connection specific BUFG. Others would require general interconnect hooked Same edge (top bottom) enables dedicated routing resources. input skew compensated.
BUFG (BUFGCE, BUFGMUX) outputs available quadrant boundaries. output global clock buffer routed non-clock pins.
Primary Secondary Global Multiplexers
Each global clock buffer self-synchronizing circuit called clock multiplexer. global clock buffers multiplexers divided follows: Eight primary clock multiplexers Eight secondary clock multiplexers
hardware difference exists between primary secondary clock multiplexer. However, some restrictions apply primary/secondary multiplexers, because they share input connections, well access quadrant. Each Virtex-II Pro/Virtex-II device divided into four quadrants: North-West, South-West, North-East, South-East. Each quadrant primary secondary clock multiplexers. clock multiplexers indexed with primary secondary each index, alternating bottom (i.e., clock multiplexer "0P" bottom facing clock multiplexer "0S" top). each device, eight top/bottom clock multiplexers divided into four primary four secondary, indexed shown Figure 3-6.
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Global Clock Networks
BUFGMUX
BUFGMUX
UG002_C2_087_113000
Figure 3-6:
Primary Secondary Clock Multiplexer Locations
Primary/Secondary: Rule
Considering "facing" clock multiplexers (BUFG#P BUFG#S), other these clock outputs enter quadrant chip drive clock within that quadrant, shown Figure 3-7. Note that clock multiplexers "xP" "xS" compete quadrant access. example, BUFG0P output cannot used same quadrant BUFG0S.
UG002_C2_088_113000
Figure 3-7:
Facing BUFG#P BUFG#S Connections
Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
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Chapter Design Considerations
Primary/Secondary: Rule
BUFGCE BUFGMUX configuration, shared inputs have considered. adjacent clock multiplexers share inputs, shown Figure 3-8. clock multiplexer "1P" "0S" have common I0/I1 I1/I0 inputs.
BUFGMUX
BUFGMUX
UG002_C2_089_113000
Figure 3-8:
Clock Multiplexer Pair Sharing Clock Multiplexer Inputs
Table lists clock multiplexer pairs Virtex-II Pro/Virtex-II device. primary multiplexer inputs I1/I0 common with corresponding secondary multiplexer inputs I0/I1 (i.e., Primary input common with secondary input, primary input common with secondary input). Table 3-2: Clock Multiplexer Pairs
Primary I1/I0 Secondary I0/I1 Table 3-3:
Bottom Clock Multiplexer Pairs
Primary I1/I0 Secondary I0/I1
Primary/Secondary Usage
eight global clocks, safe eight primary global multiplexers (1P, bottom). Because shared inputs, maximum eight independent global clock multiplexers used design, shown Figure 3-9.
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Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
Global Clock Networks
GCLK7P
GCLK5P
GCLK3P
GCLK1P
IBUFG/IBUFGDS
clocks
clocks
clocks clocks clocks
IBUFG/IBUFGDS
GCLK6P
GCLK4P
GCLK2P
GCLK0P
UG002_C2_090_113000
Figure 3-9:
Eight Global Clocks Design
Clocks
four clock pins (IBUFG) quadrant feed DCMs same edge device. clock-to-out setup times identical DCMs. four clock outputs used drive clock multiplexer same edge (top bottom), shown Figure 3-10.
BUFG Exclusivity
Each restriction number BUFGs drive (top bottom) edge. Pairs buffers with shared dedicated routing resources exist such that only buffer from each dedicated pair driven single DCM. exclusive pairs each edge are: 0:4, 1:5, 2:6, 3:7.
Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
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Chapter Design Considerations
GCLK7P
GCLK6S
GCLK5P
GCLK4S
GCLK3P
GCLK2S
GCLK1P
GCLK0S
IBUFG
IBUFG
BUFGMUX
BUFGMUX
UG002_C2_091_080601
Figure 3-10:
Clocks
Clock Output
clock distribution based eight clock trees quadrant. Each clock multiplexer output driving global clock net. Virtex-II Pro/Virtex-II device eight dedicated low-skew clock nets. device divided into four quadrants (NW, with eight global clocks available quadrant. Eight clock buffers middle edge eight middle bottom edge. these clock buffer outputs used quadrant, maximum eight clocks quadrant, illustrated Figure 3-11, provided there primary secondary conflict.
BUFGMUX
BUFGMUX
Clocks
Clocks
BUFGMUX
BUFGMUX
DS031_45_120200
Figure 3-11: Clock Buffer Outputs Quadrant
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Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
Global Clock Networks
Designs with more than eight clocks must floorplanned manually automatically, distributing clocks each quadrant. example, design with clocks floorplanned shown Figure 3-12.
CLK_
CLK_C CLK_B CLK_F CLK_P clocks CLK_K CLK_D clocks CLK_O CLK_N CLK_B CLK_E CLK_A CLK_I CLK_H
Clocks CLK_A CLK_G CLK_A
CLK_H CLK_M
CLK_C CLK_J
CLK_L CLK_N clocks clocks CLK_P
CLK_
UG002_C2_079_120200
Figure 3-12:
16-Clock Floorplan
Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
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Chapter Design Considerations
clock nets clock buffers this example associated shown Table 3-4. Table 3-4: Clock Association With Clock Buffers
Clock (top edge) BUFG Clock (bottom edge) BUFG Quadrant Quadrant Quadrant Quadrant
CLK_A CLK_I CLK_A CLK_A CLK_I CLK_A
CLK_B CLK_J CLK_B CLK_B CLK_J
CLK_C CLK_K CLK_C CLK_C CLK_K
CLK_D CLK_L CLK_L CLK_D
CLK_E CLK_M CLK_M CLK_E
CLK_F CLK_N CLK_F CLK_N CLK_N
CLK_G CLK_O CLK_G CLK_O
CLK_H CLK_P CLK_P CLK_H CLK_H CLK_P
CLK_A used three quadrants, other clocks used quadrants, regardless position clock buffers (multiplexers), long they competing access same quadrant. That CLK_A (BUFG7P) cannot used same quadrant with CLK_I (BUFG7S). Refer "Primary/Secondary: Rule page 73.) other words, buffers with same index cannot used same quadrant. Each register, block RAM, registered multiplier, register (IOB) connected eight clock nets available particular quadrant. Note that global clock (primary buffer) used four quadrants, corresponding secondary buffer available.
Power Consumption
Clock trees have been designed skew low-power operation. unused branch disconnected, shown Figure 3-13.
BUFGMUX
Clocks
BUFGMUX
ug002_c2_093_113000
Figure 3-13:
Low-Power Clock Network
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Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
Global Clock Networks
Also available reduce overall power consumption BUFGCE feature, dynamically driving clock tree only when corresponding module used, BUFGMUX feature, switching from high-frequency clock low-frequency clock. frequency synthesizer capability generate high) frequency clock from single source clock, illustrated Figure 3-14. (See "Digital Clock Managers (DCMs)," page 89.)
BUFGMUX CLKIN CLKFB (÷10) CLKDV BUFG
UG002_C2_094_121101
CLK0
Clock Tree
Figure 3-14:
Dynamic Power Reduction Scheme
Library Primitives Submodules
primitives Table available with input, output, control pins listed. Table 3-5: Clock Primitives Input Output Control
Primitive IBUFG IBUFGDS BUFG BUFGMUX BUFGMUX_1
Refer "Single-Ended SelectIO-Ultra Resources," page list attributes available IBUFG Refer "LVDS I/O," page list attributes available IBUFGDS. submodules Table available with input, output, control pins listed. Table 3-6: Clock Submodules Input Output Control
Submodule BUFGCE BUFGCE_1
Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
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Chapter Design Considerations
Primitive Functions
IBUFG
IBUFG input clock buffer with clock input clock output.
IBUFGDS
IBUFGDS differential input clock buffer with clock inputs (positive negative polarity) clock output.
BUFG
Virtex-II Pro/Virtex-II devices have global clock buffers (each which used BUFG, BUFGMUX, BUFGCE). BUFG global clock buffer with clock input clock output, driving lowskew clock distribution network. output follows input, shown Figure 3-15.
BUFG(I) BUFG(O)
UG002_C2_099_120100
Figure 3-15:
BUFG Waveforms
BUFGMUX BUFGMUX_1
BUFGMUX (see Figure 3-16) switch between unrelated, even asynchronous clocks. Basically, selects input, High selects input. Switching from clock other done such that output High time never shorter than shortest High time either input clock. long presently selected clock High, level change effect. (For BUFGMUX_1, long presently selected clock Low, level change effect.) BUFGMUX preferred circuit rising edge clocks, while BUFGMUX_1 preferred falling edge clocks.
BUFGMUX
DS083-2_63_121701
Figure 3-16:
Virtex-II Pro/Virtex-II BUFGMUX BUFGMUX_1 Function
Operation BUFGMUX Circuit
presently selected clock while changes, goes after changed, output kept until other ("to-be-selected") clock made transition from High Low. that instant, clock starts driving output. clock inputs asynchronous with regard each other, input change time, except short setup time prior rising edge presently
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Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
Global Clock Networks
selected clock; that prior rising edge BUFGMUX output Violating this setup time requirement result undefined runt pulse output. Figure 3-17 shows switch-over from CLK0 CLK1.
Wait Switch CLK1
DS083-2_46_121701
Figure 3-17: current clock CLK0. activated High.
BUFGMUX Waveform Diagram
CLK0 currently High, multiplexer waits CLK0 Low. Once CLK0 Low, multiplexer output stays until CLK1 transitions High Low. When CLK1 transitions from High Low, output switches CLK1. glitches short pulses appear output.
Operation BUFGMUX_1 Circuit
presently selected clock High while changes, goes High after changed, output kept High until other ("to-be-selected") clock made transition from High. that instant, clock starts driving output. clock inputs asynchronous with regard each other, input change time, except short setup time prior falling edge presently selected clock; that prior falling edge BUFGMUX output Violating this setup time requirement result undefined runt pulse output. Figure 3-18 shows switch-over from CLK0 CLK1.
Wait High CLK0 CLK1
DS083-2_46a_121701
Figure 3-18:
BUFGMUX_1 Waveform Diagram
Virtex-II Virtex-II FPGA User Guide UG012 (v4.2) November 2007
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Chapter Design Considerations
current clock CLK0. activated High. CLK0 currently Low, multiplexer waits CLK0 High. Once CLK0 High, multiplexer output stays High until CLK1 transitions High. When CLK1 transitions from High, output switches CLK1. glitches short pulses appear output.
Submodules
BUFGCE BUFGCE_1
BUFGCE BUFGCE_1 submodules based BUFGMUX BUFGMUX_1, respectively. BUFGCE BUFGCE_1 global clock buffers incorporating smart enable function that avoids output glitches runt pulses. select signal must meet setup time clock. BUFGCE preferred circuit clocking rising edge, while BUFGCE_1 preferred when clocking falling edge.
Operation BUFGCE Circuit
input (see Figure 3-19) active (High) prior incoming rising clock edge, this Low-to-High-to-Low clock pulse passes through clock buffer. level change during incoming clock High time effect.
BUFGCE
DS031_62_101200
Figure 3-19:
Virtex-II Pro/Virtex-II BUFGCE BUFGCE_1 Function
input inactive (Low) prior incoming rising clock edge, following clock pulse does pass through clock buffer, output stays Low. level change during incoming clock High time effect. must change during short setup window just prior rising clock edge BUFGCE_1 input Violating this s
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