DS160 (v1.2) June 2009 Advance Product Specification Spartan®-6 f

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DS160 (v1.2) June 2009 Advance Product Specification Spartan®-6 f

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Spartan-6 Family Overview
DS160 (v1.2) June 2009 Advance Product Specification
Spartan®-6 family provides leading system integration capabilities with lowest total cost high-volume applications. thirteen-member family delivers expanded densities ranging from 3,400 148,000 logic cells, with half power consumption previous Spartan families faster, more comprehensive connectivity. Built mature low-power copper process technology that delivers optimal balance cost, power, performance, Spartan-6 family offers new, more efficient, dual-register 6-input look-up table (LUT) logic rich selection built-in system-level blocks. These include block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIOtechnology, power-optimized highspeed serial transceiver blocks, Expresscompatible Endpoint blocks, advanced system-level power management modes, autodetect configuration options, enhanced security with Device protection. These features provide low-cost programmable alternative custom ASIC products with unprecedented ease-of-use. Spartan-6 FPGAs offer best solution highvolume logic designs, consumer-oriented designs, cost-sensitive embedded applications. Spartan-6 FPGAs programmable silicon foundation Targeted Design Platforms that deliver integrated software hardware components enable designers focus innovation soon their development cycle begins.
Summary Spartan-6 FPGA Features
Spartan-6 Family: Spartan-6 FPGA: Logic optimized Spartan-6 FPGA: High-speed serial connectivity Designed cost Multiple efficient integrated blocks Optimized selection standards Staggered pads High volume plastic wire-bonded packages static dynamic power process optimized cost power Hibernate power-down mode zero power Suspend mode maintains state configuration with multi-pin wake-up, control enhancement Lower-power 1.0V core voltage FPGAs, only) High performance 1.2V core voltage FPGAs, speed grades) Multi-voltage, multi-standard SelectIO banks 1050 Mb/s data transfer rate differential Selectable output drive, 3.3V 1.2V standards protocols Low-cost HSTL SSTL memory interfaces swap compliance Adjustable slew rates improve signal integrity High-speed serial transceivers FPGAs 3.125 Gb/s High speed interfaces including: Serial ATA, Aurora, Ethernet, Express, OBSAI, CPRI, EPON, GPON, DisplayPort, XAUI Integrated Endpoint block Express designs (LXT) cost PCI® technology support compatible with bit, specification Efficient DSP48A1 slices High-performance arithmetic signal processing Fast multiplier 48-bit accumulator Pipelining cascading capability Pre-adder assist filter applications Integrated Memory Controller blocks DDR, DDR2, DDR3, LPDDR support Data rates Mb/s (12.8 Gb/s peak bandwidth) Multi-port structure with independent FIFO reduce design timing issues Abundant logic resources with increased logic capacity Optional shift register distributed support Efficient 6-input LUTs improve performance minimize power with dual flip-flops pipeline centric applications Block with wide range granularity Efficient block Fast block with byte write enable blocks that optionally programmed independent block RAMs Clock Management Tile (CMT) enhanced performance noise, flexible clocking Digital Clock Managers (DCMs) eliminate clock skew duty cycle distortion Phase-Locked Loops (PLLs) low-jitter clocking Frequency synthesis with simultaneous multiplication, division, phase shifting Sixteen low-skew global clock networks Simplified configuration, supports low-cost standards 2-pin auto-detect configuration Broad third-party Flash support Feature rich Xilinx Platform Flash with JTAG MultiBoot support remote upgrade with multiple bitstreams, using watchdog protection Enhanced security design protection Unique Device identifier design authentication bitstream encryption larger devices Faster embedded processing with enhanced, cost, MicroBlazesoft processor Industry-leading reference designs
2009 Xilinx, Inc. XILINX, Xilinx logo, Virtex, Spartan, ISE, other designated brands included herein trademarks Xilinx United States other countries. PCI, PCIe Express trademarks PCI-SIG used under license. other trademarks property their respective owners.
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Spartan-6 Family Overview
Spartan-6 FPGA Feature Summary
Table Spartan-6 FPGA Feature Summary Device
Configurable Logic Blocks (CLBs) Device Logic Cells(1) Slices(2) Flip-Flops Distributed (Kb) DSP48A1 Slices(3) Block Blocks Kb(4) Memory Endpoint Maximum Total CMTs(5) Controller Blocks User Blocks Express Transceivers Banks (Kb)
XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX45 XC6SLX75 XC6SLX100 XC6SLX150 XC6SLX25T XC6SLX45T XC6SLX75T XC6SLX100T XC6SLX150T
3,840 9,152 14,579 24,051 43,661 74,637 101,261 147,443 24,051 43,661 74,637 101,261 147,443
1,430 2,278 3,750 6,822 11,662 15,822 23,038 3,750 6,822 11,662 15,822 23,038
4,800 11,440 18,224 30,064 54,576 93,296 126,576 184,304 30,064 54,576 93,296 126,576 184,304
1,355 1,355
2,088 3,096 4,824 4,824 2,088 3,096 4,824 4,824
Notes:
Spartan-6 FPGA logic cell ratings reflect increased logic cell capability offered 6-input architecture. Each Spartan-6 FPGA slice contains four LUTs eight flip-flops. Each DSP48A1 slice contains multiplier, adder, accumulator. Block RAMs fundamentally size. Each block also used independent blocks. Each contains DCMs PLL.
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Spartan-6 Family Overview
Spartan-6 FPGA Device-Package Combinations Available I/Os
Spartan-6 FPGA package combinations with available I/Os transceivers package shown Table transceivers, pinouts compatible. Table Spartan-6 Device-Package Combinations Maximum Available I/Os
Package CPG196(1) Size (mm) Pitch (mm) Device XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX45 XC6SLX75 XC6SLX100 XC6SLX150 XC6SLX25T XC6SLX45T XC6SLX75T XC6SLX100T XC6SLX150T
User
TQG144(1)
User
CSG225(2)
User
FT(G)256(3)
User
CSG324
GTPs User
FG(G)484(3,4)
GTPs User
CSG484(4)
GTPs User
FG(G)676(3)
GTPs User
FG(G)900(3)
GTPs User
Notes: There memory controller devices these packages. Memory controller block support XC6SLX9 XC6SLX16 devices. There memory controller XC6SLX4. These devices available both Pb-free (additional packages standard ordering options. These packages support four memory controllers XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, XC6SLX150T devices.
Configuration
Spartan-6 FPGAs store customized configuration data SRAM-type internal latches. number configuration bits between depending device size independent specific user-design implementation, unless compression mode used. configuration storage volatile must reloaded whenever FPGA powered This storage also reloaded time pulling PROGRAM_B Low. Several methods data formats loading configuration available. Bit-serial configurations either master serial mode, where FPGA generates configuration clock (CCLK) signal, slave serial mode, where external configuration data source also clocks FPGA. byte-wide configurations, master SelectMAP mode generates CCLK signal while slave SelectMAP mode receives CCLK signal 16-bit-wide transfer. master serial mode, beginning bitstream optionally switch clocking source external clock, which faster more precise than internal clock. available JTAG pins boundary-scan protocols load bit-serial configuration data.
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Spartan-6 Family Overview bitstream configuration information generated ISEsoftware using program called BitGen. configuration process typically executes following sequence: Detects power-up (power-on reset) PROGRAM_B when Low. Clears whole configuration memory. Samples mode pins determine configuration mode: master slave, bit-serial parallel. Loads configuration data starting with bus-width detection pattern followed synchronization word, checks proper device code, ends with cyclic redundancy check (CRC) complete bitstream. Starts user-defined sequence events: releasing internal reset preset) flip-flops, optionally waiting DCMs and/or PLLs lock, activating output drivers, transitioning DONE High.
Spartan-6 FPGAs support MultiBoot configuration, where more FPGA configuration bitstreams stored single configuration source. FPGA application controls which configuration load next when load Spartan-6 FPGAs also include unique, factory-programmed Device identifier useful tracking purposes, anticloning designs, protection. largest devices, bitstreams copy protected using encryption.
Dynamic Reconfiguration Port
dynamic reconfiguration port (DRP) gives system designer easy access configuration bits status registers transceivers. behaves like memory-mapped registers, access modify block-specific configuration bits well status control registers.
Readback
Most configuration data read back without affecting system's operation.
CLBs, Slices, LUTs
Each configurable logic block (CLB) Spartan-6 FPGAs consists slices, arranged side-by-side part vertical columns. There three types slices Spartan-6 architecture: SLICEM, SLICEL, SLICEX. Each slice contains four LUTs, eight flip-flops, miscellaneous logic. LUTs general-purpose combinatorial sequential logic support. Synthesis tools take advantage these highly efficient logic, arithmetic, memory features. Expert designers also instantiate them.
SLICEM
quarter (25%) Spartan-6 slices SLICEMs. Each four SLICEM LUTs configured either 6-input with output, dual 5-input LUTs with identical 5-bit addresses independent outputs. These LUTs also used distributed 64-bit with bits times bits LUT, single 32-bit shift register (SRL32), 16-bit shift registers (SRL16s) with addressable length. Each output registered flip-flop within CLB. arithmetic operations, high-speed carry chain propagates carry signals upwards column slices.
SLICEL
quarter (25%) Spartan-6 slices SLICELs, which contain features SLICEM except memory/shift register function.
SLICEX
half (50%) Spartan-6 slices SLICEXs. SLICEXs have same structure SLICELs except arithmetic carry option wide multiplexers.
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Spartan-6 Family Overview
Clock Management
Each Spartan-6 FPGA CMTs, each consisting DCMs PLL, which used individually concatenated.
provides four phases input frequency (CLKIN): shifted 90°, 180°, 270° (CLK0, CLK90, CLK180, CLK270). also provides doubled frequency CLK2X complement CLK2X180. CLKDV output provides fractional clock frequency that phase-aligned CLK0. fraction programmable every integer from well 1.5, 2.5, 7.5. CLKIN optionally divided zero-delay clock buffer when clock signal drives CLKIN, while CLK0 output back CLKFB input. Frequency Synthesis Independent basic functionality, frequency synthesis outputs CLKFX CLKFX180 programmed generate output frequency that input frequency (FIN) multiplied simultaneously divided where integer from integer from Phase Shifting With CLK0 connected CLKFB, nine outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV, CLKFX, CLKFX180) shifted common amount, defined integer multiple fixed delay. fixed delay value (fraction input period) established configuration also incremented decremented dynamically. Spread-Spectrum Input accept track typical spread-spectrum clock inputs, provided they abide input clock specifications listed Spartan-6 data sheet.
PLLs
serve frequency synthesizer wider range frequencies jitter filter incoming clocks conjunction with DCMs. heart voltage-controlled oscillator (VCO) with frequency range 1000 MHz, thus spanning more than octave. Three sets programmable frequency dividers adapt required application. pre-divider (programmable configuration) reduces input frequency feeds input traditional phase comparator. feedback divider (programmable configuration) acts multiplier because divides output frequency before feeding other input phase comparator. must chosen appropriately keep within controllable frequency range. eight equally spaced outputs (0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°). Each selected drive output dividers, (each programmable configuration divide integer from 128).
Clock Distribution
Each Spartan-6 FPGA provides abundant clock lines address different clocking requirements high fanout, short propagation delay, extremely skew.
Global Clock Lines
each Spartan-6 FPGA, global-clock lines have highest fanout reach every flip-flop clock. Global clock lines must driven global clock buffers, which also perform glitchless clock multiplexing clock enable function. Global clocks often driven from CMTs, which completely eliminate basic clock distribution delay.
Clocks
clocks especially fast serve only localized input output delay circuits serializer/deserializer (SERDES) circuits, described Logic section.
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Spartan-6 Family Overview
Block
Every Spartan-6 FPGA between dual-port block RAMs, each storing Kbits. Each block completely independent ports that share only stored data.
Synchronous Operation
Each memory access, whether read write, controlled clock. inputs, data, address, clock enables, write enables registered. data output always latched, retaining data until next operation. optional output data pipeline register allows higher clock rates cost extra cycle latency. During write operation dual-port mode, data output reflect either previously stored data, newly written data, remain unchanged.
Programmable Data Width
Each port configured 16), 32). x18, configurations include parity bits. ports have different aspect ratios. Each block divided into completely independent block RAMs that each configured aspect ratio from block RAMs, only simple dual-port mode provide data widths bits. this mode, port dedicated read operation other port dedicated write operation. full freedom port data width values retained, there read output during write. dual-port data width limitation.
Memory Controller Block
Most Spartan-6 devices include dedicated memory controller blocks (MCBs), each targeting single-chip DRAM (either DDR, DDR2, DDR3, LPDDR), supporting access rates Mb/s. dedicated routing predefined FPGA I/Os. used, these I/Os available general purpose FPGA I/Os. memory controller offers complete multi-port arbitrated interface logic inside Spartan-6 FPGA. Commands pushed, data pushed pulled from independent built-in FIFOs, using conventional FIFO control signals. multi-port memory controller configured many ways. internal 32-, 64-, 128-bit data interface provides simple reliable interface MCB. connected 16-bit external DRAM. MCB, many applications, provides faster DRAM interface compared traditional internal data buses, which wider clocked lower frequency. FPGA logic interface flexibly configured irrespective physical memory device.
Digital Signal Processing-DSP48A1 Slice
applications many binary multipliers accumulators, best implemented dedicated slices. Spartan-6 FPGAs have many dedicated, full-custom, low-power slices, combining high speed with small size, while retaining system design flexibility. Each DSP48A1 slice consists dedicated two's complement multiplier 48-bit accumulator, both capable operating MHz. DSP48A1 slice provides extensive pipelining extension capabilities that enhance speed efficiency many applications, even beyond digital signal processing, such wide dynamic shifters, memory address generators, wide multiplexers, memory-mapped register files. accumulator also used synchronous up/down counter. multiplier perform barrel shifting.
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Spartan-6 Family Overview
Input/Output
number pins varies from 570, depending device package size. Each configurable comply with large number standards, using 3.3V. Spartan-6 FPGA SelectIO Resources User Guide describes compatibilities various options. With exception supply pins dedicated configuration pins, other package pins have same capabilities, constrained only certain banking rules. user bidirectional; there input-only pins. pins organized banks, with four banks smaller devices banks larger devices. Each bank several common VCCO output supply-voltage pins, which also powers certain input buffers. Some single-ended input buffers require externally applied reference voltage (VREF). There several dual-purpose VREF-I/O pins each bank. given bank, when standard calls VREF voltage, each VREF that bank must connected same voltage rail used pin.
Electrical Characteristics
Single-ended outputs conventional CMOS push/pull output structure, driving High towards VCCO towards ground, into high-Z state. Many features available system designer optionally invoke each their design, such weak internal pull-up pull-down resistors, strong internal split-termination input resistors, adjustable output drive-strengths slew-rates, differential termination resistors. Spartan-6 FPGA SelectIO Resources User Guide more details available options each standard.
Logic
Input Output Delay
This section describes available logic resources connected interfaces. inputs outputs configured either combinatorial registered. Double data rate (DDR) supported inputs outputs. input output individually delayed increments ~100 each. This implemented IODELAY2. identical delay value available either data input output. bidirectional data line, transfer from input output delay automatic. number delay steps configuration also incremented decremented while use. Because these delays vary with supply voltage, process, temperature, optional calibration mechanism built into each IODELAY2: simple system synchronous case, data input delay value that guarantees zero data hold time inserted automatically, without user intervention. source synchronous designs where more accuracy required, calibration mechanism (optionally) determine dynamically many taps needed delay data full clock cycle, then programs IODELAY2 with that value, thus centering clock middle data eye. special mode available only differential inputs, which uses phase-detector mechanism determine whether incoming data signal being accurately sampled middle eye. results from phase-detector logic used either increment decrement input delay, time, ensure error-free operation very high rates.
ISERDES OSERDES
Many applications combine high-speed bit-serial with slower parallel operation inside device. This requires serializer deserializer (SerDes) inside structure. Each input access deserializer (serial-to-parallel converter) with programmable parallel width bits. Where differential inputs used, serializers cascaded provide parallel widths bits. Each output access serializer (parallel-to-serial converter) with programmable parallel width bits. serializers cascaded when differential driver used give access widths bits. When distributing double data rate clock, SerDes data actually clocked in/out single data rate eliminate possibility errors duty cycle distortion. This faster single data rate clock either derived frequency multiplication PLL, doubled locally each differentiating both clock edges when incoming clock uses double data rate.
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Low-Power Gigabit Transceiver
Ultra-fast data transmission between ICs, over backplane, over longer distances becoming increasingly popular important. requires specialized dedicated on-chip circuitry differential capable coping with signal integrity issues these high data rates. Spartan-6 devices have gigabit transceiver circuits. Each transceiver combined transmitter receiver capable operating data rate between Mb/s 3.125 Gb/s. transmitter receiver independent circuits that separate PLLs multiply reference frequency input certain programmable numbers between become bit-serial data clock. Each transceiver large number user-definable features parameters. these defined during device configuration, many also modified during operation.
Transmitter
transmitter fundamentally parallel-to-serial converter with conversion ratio transmitter output drives board with single-channel differential current-mode logic (CML) output signal. TXOUTCLK appropriately divided serial data clock used directly register parallel data coming from internal logic. incoming parallel data through small FIFO optionally modified with 8B/10B algorithm guarantee sufficient number transitions. bit-serial output signal drives package pins with complementary signals. This output signal pair programmable signal swing well programmable preemphasis compensate board losses other interconnect characteristics.
Receiver
receiver fundamentally serial-to-parallel converter, changing incoming serial differential signal into parallel stream words, each bits wide. receiver takes incoming differential data stream, feeds through programmable equalizer compensate board other interconnect characteristics), uses FREF input initiate clock recognition. There need separate clock line. data pattern uses non-return-to-zero (NRZ) encoding optionally guarantees sufficient data transitions using 8B/10B encoding scheme. Parallel data then transferred into FPGA logic using RXUSRCLK clock. serial-to-parallel conversion ratio
Integrated Endpoint Blocks Express Designs
Express standard packet-based, point-to-point serial interface standard. differential signal transmission uses embedded clock, which eliminates clock-to-data skew problems traditional wide parallel buses. Express Base Specification defines rate Gb/s lane, direction (transmit receive). When using 8B/10B encoding, this supports data rate Gb/s lane. Spartan-6 devices include integrated Endpoint block Express technology that compliant with Express Base Specification Revision 1.1. This block highly configurable system design requirements operates compliant single lane Endpoint. integrated Endpoint block interfaces transceivers serialization/deserialization, block RAMs data buffering. Combined, these elements implement physical layer, data link layer, transaction layer protocol. Xilinx provides light-weight (<100 LUT), configurable, ease-of-use LogiCOREwrapper that ties various building blocks (the integrated Endpoint block Express technology, transceivers, block RAM, clocking resources) into compliant Endpoint solution. system designer control over many configurable parameters: maximum payload size, reference clock frequency, base address register decoding filtering.
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Spartan-6 Family Overview
Spartan-6 FPGA Ordering Information
Spartan-6 FPGA ordering information shown Figure applies packages including Pb-Free.
X-Ref Target Figure
Example: XC6SLX100T-2FGG676C
Device Type Speed Grade (-L1(1), -3(2))
Note: ordering code lower power version. devices offered this version. Spartan-6 FPGA data sheet more information. speed grades available devices.
Temperature Range: Commercial +85°C) Industrial -40°C +100°C) Number Pins Pb-Free Package Type
DS160_01_061909
Figure Spartan-6 FPGA Ordering Information
Revision History
following table shows revision history this document:
Date
02/02/09 05/05/09
Version
Initial Xilinx release.
Description Revisions
Updated simplified Designed cost, Multi-voltage, multi-standard SelectIO banks, Integrated Memory Controller blocks sections page Clarified support page only specification. Revised number logic cells, slices, maximum user I/O, added number flip-flops Table Table revised user counts, removed XC6SLX25 CSG225 package XC6SLX45T FGG676 package, added XC6SLX9 FT(G)256 package XC6SLX45 CSG324 package, added notes. Clerical edits following sections: Dynamic Reconfiguration Port, Readback, CLBs, Slices, LUTs, Frequency Synthesis, PLLs, Programmable Data Width, Memory Controller Block. Clarified range, VREF banks, electrical characteristics Input/Output section. Updated device/package combinations Table Table including adding XC6SLX75 XC6SLX75T devices. Added ordering information FPGA documentation sections. Removed partial reconfiguration discussion from Readback section.
06/24/09
Notice Disclaimer
XILINX HARDWARE FPGA CPLD DEVICES REFERRED HEREIN ("PRODUCTS") SUBJECT TERMS CONDITIONS XILINX LIMITED WARRANTY WHICH VIEWED THIS LIMITED WARRANTY DOES EXTEND PRODUCTS APPLICATION ENVIRONMENT THAT WITHIN SPECIFICATIONS STATED XILINX DATA SHEET. SPECIFICATIONS SUBJECT CHANGE WITHOUT NOTICE. PRODUCTS DESIGNED INTENDED FAIL-SAFE APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH LIFE-SUPPORT SAFETY DEVICES SYSTEMS, OTHER APPLICATION THAT INVOKES POTENTIAL RISKS DEATH, PERSONAL INJURY, PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). PRODUCTS CRITICAL APPLICATIONS SOLE RISK CUSTOMER, SUBJECT APPLICABLE LAWS REGULATIONS.
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Spartan-6 Family Overview
Spartan-6 FPGA Documentation
Complete up-to-date documentation Spartan-6 family FPGAs available Xilinx website addition most recent Spartan-6 Family Overview, following files also available download: Spartan-6 FPGA Data Sheet: Switching Characteristics (DS162) This data sheet contains Switching Characteristic specifications Spartan-6 family. Spartan-6 FPGA Packaging Pinout Specifications (UG385) These specifications includes tables device/package combinations maximum I/Os, definitions, pinout tables, pinout diagrams, mechanical drawings, thermal specifications. Spartan-6 FPGA Configuration Guide (UG380) This all-encompassing configuration guide includes chapters configuration interfaces (serial parallel), multi-bitstream management, bitstream encryption, boundary-scan JTAG configuration, reconfiguration techniques. Spartan-6 FPGA SelectIO Resources User Guide (UG381) This guide describes SelectIOresources available Spartan-6 devices. Spartan-6 FPGA Clocking Resources User Guide (UG382) This guide describes clocking resources available Spartan-6 devices, including DCMs PLLs. Spartan-6 FPGA Block Resources User Guide (UG383) This guide describes Spartan-6 device block capabilities. Spartan-6 FPGA Configurable Logic Blocks User Guide (UG384) This guide describes capabilities configurable logic blocks (CLB) available Spartan-6 devices. Spartan-6 FPGA Transceivers User Guide (UG386) This guide describes transceivers available Spartan-6 FPGAs. Spartan-6 FPGA DSP48A1 Slice User Guide (UG389) This guide describes architecture DSP48A1 slice Spartan-6 FPGAs provides configuration examples. Spartan-6 FPGA Memory Controller User Guide (UG388) This guide describes Spartan-6 FPGA memory controller block, dedicated, embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 FPGAs most popular memory standards. Spartan-6 FPGA Design Guide (UG393) This guide provides information design Spartan-6 devices, with focus strategies making design decisions interface level.
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DS160 (v1.2) June 2009 Advance Product Specification Spartan®-6 f

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