Author: Martin Kellermann XAPP756 (v1.0) November 2004 Summa
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Transmitting Data Between LVDS RocketIO Devices
Author: Martin Kellermann
XAPP756 (v1.0) November 2004
Summary
serial transfer data between devices board cards backplane using LVDS differential standard well established. Existing cards need able interface newer technologies. This application note discusses possible ways interconnect standard LVDS transceivers with Current Mode Logic (CML) technology used Xilinx RocketIOmulti-gigabit transceivers (MGTs) through coupling coupling.
Introduction
This application note discusses transmission between LVDS-based CML-based interfaces. Analog example simulations show principal interoperability between those kinds devices. Additionally, design transmitting data from LVDS using Xilinx technology available.
AC-Coupled Data Transmission
data transmission between transceivers where differential voltage matches common mode voltage does not, coupling usually used. This accomplished putting capacitor series into signal path. Because galvanic connection exists between sender receiver, transmitted signal must DC-balanced, meaning number transmitted ones zeros must equal over time. 8B10B coding scheme used many high-speed transmission protocols guarantees this balance avoids charging discharging transmission line. Choosing correct value coupling depends maximum length occurring chosen protocol data-dependent jitter caused discharge effects. Generally, capacitor appropriate lengths consecutive non-changing bits data rates several Mbits/sec. good explanation calculations necessary choosing correct value capacitor, refer Maxim's application note HFAN-1.1: "Choosing AC-Coupling Capacitors".
DC-Coupled Data Transmission
data transmission between devices that fully electrically compliant (the common mode voltage differential voltage match), DC-coupled transmission preferable. this case, transceivers directly connected without galvanic interruption. DC-coupled transmission work, following requirements must met: LVDS driver must differential termination. LVDS receiver must have common mode voltage typically 1.25V voltage swing between
Termination Voltage LVDS Transmitter
receiver RocketIO simplified circuit shown Figure Each differential transmission lines internally terminated adjustable terminator against termination voltage VTRX (typically 1.8V). Leaving VTRX unconnected
2004 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, further disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice. NOTICE DISCLAIMER: Xilinx providing this design, code, information is." providing design, code, information possible implementation this feature, application, standard, Xilinx makes representation that this implementation free from claims infringement. responsible obtaining rights require your implementation. Xilinx expressly disclaims warranty whatsoever with respect adequacy implementation, including limited warranties representations that this implementation free from claims infringement implied warranties merchantability fitness particular purpose.
XAPP756 (v1.0) November 2004
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DC-Coupled Data Transmission FPGA results resistance between (150 with termination). setting termination RocketIO transceiver attribute TERMINATION_IMP=50 leaving VTRX unconnected generates necessary termination LVDS driver.
VTRX
X756_01_101304
Figure Simplified Input Circuit
Common Mode Voltage LVDS Receiver
output driver simplified circuit shown Figure VTTX typically 2.5V generates common mode voltage approximately 1.5V. common mode voltage lowered standard LVDS level decreasing voltage VTTX. Through HSPICE simulation, value 1.8V VTTX determined suitable.
VTTX
Output Driver
X756_02_101304
Figure Simplified Output Circuit
HSPICE Simulation RocketIO Transceiver LVDS (DC-Coupled)
suggested circuits DC-coupled transmission simulated with setup shown Figure Figure rerun simulation yourself, need download HSPICE models RocketIO driver LVDS pins from SPICE suite. appropriate wrappers topologies located simulation directory xapp756.zip. transmission line, wide stripline chosen. HSPICE model this found signal integrity SPICE Suite. RocketIO transceiver LVDS transmission, distance assumed between LVDS pins FPGA termination resistor.
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XAPP756 (v1.0) November 2004
DC-Coupled Data Transmission
V(term)
RocketIO
LVDS
X756_03_101304
Figure Topology DC-Coupled Transmission (CML LVDS)
Several simulations have been performed this setup using HSPICE 2003.03. first simulation uses pulse response find worst-case pattern swing with pre-emphasis. placing cursors resulting waveform overlaying, worst-case pattern 110100000000010 been found, which creates worst-case diagram (see Figure
X756_04_100104
Figure Stimulus Pulse Response
X756_05_100104
Figure Result Pulse Response LVDS Receiver
worst-case diagram, pulses must overlap minimize interior eye. find necessary pattern achieve this, pulse response added multiple times onto itself that initial pulse minimized. Shifting pulse period right brings logic level pulse into middle reflection's ditch. Shifting response another does decrease size center. pulse shifted multiple times until significant response seen anymore. during shifting initial logic level pulse falls into ditches caused reflections, added pattern, otherwise added.
XAPP756 (v1.0) November 2004
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DC-Coupled Data Transmission Applying this method results pattern 110100000000010, which transmitted into line. This pattern closes from bottom. also close from top, pattern inverted transmitted afterwards, leading diagram shown Figure
X756_06_101304
Figure Worst-Case Diagram Given System
Even though worst case, pattern still properly received shown Figure
X756_07_100104
Figure Worst-Case Pattern after RocketIO Transceiver
Virtex-II Prodevices also feature differential internal termination LVDS. Using this feature simplifies traces from layout perspective also improves impedance matching with less impedance discontinuities. Simulating system shown Figure results improved receiving device.
V(term)
RocketIO
LVDS
X756_08_101304
Figure Topology DC-Coupled Transmission (CML LVDS_DT)
pulse response resulting diagram LVDS_DT example shown Figure Figure respectively.
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XAPP756 (v1.0) November 2004
DC-Coupled Data Transmission
X756_09_100104
Figure Pulse Response Example LVDS_DT
X756_10_101404
Figure Resulting Diagram
Comparing results clearly shows advantage internal LVDS_DT (differential termination) systems like this. Similar simulations have been performed LVDS driving RocketIO transceiver. this simulation termination inside RocketIO transceiver. Hence there external components. topology shown Figure simpler fewer impedance discontinuities that decrease signal quality.
V(term), open
LVDS
RocketIO
X756_11_101304
Figure Topology DC-Coupled Transmission (LVDS CML)
XAPP756 (v1.0) November 2004
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DC-Coupled Data Transmission result pulse response (Figure LVDS topology shows benefit internal termination. reflections occur anymore.
X756_12_100104
Figure Pulse Response Example LVDS Circuit
Looking positions when reflection occurs, resulting pattern worst-case pattern 100000000000011, which results edges transmitted signal right reflections. This pattern changed 100000100000011 more edges datastream. resulting shown Figure Comparing diagram with external termination Figure shows improvement quality.
X756_13_101304
Figure Resulting Worst-Case Diagram
data received correctly, shown Figure
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XAPP756 (v1.0) November 2004
Conclusion
X756_14_100104
Figure Resulting Worst-Case Pattern after LVDS Transceiver
Conclusion
discussed circuits allow DC-coupled transmission data between LVDS circuits used Virtex-II devices speeds down Mbits/sec. designs described appendices have been created prove concept hardware. target boards those designs ML321 Evaluation Board RocketIO design XLVDSPro Demonstration Board LVDS.
Appendix LVDS Design
LVDS design consists main parts, data generation serialization. Data generation runs slower system clock generates 8-bit wide PRBS pattern. This pattern goes into 8B10B encoder, generated with CORE Generatorsystem. Every clock cycles, comma character inserted into this PRBS pattern encoded character. 10-bit output encoder into second main block, LVDS_10:1 block, then transmitted FPGA.
PRBS CLK_64M
8B10B CLK_64M LVDS_10:1 TX_LVDS
CLK_64M
COMMACNT
CLK_64M CLK_320M
CLK_320M_ext CLKGEN
CLK_320M CLK_64M
X756_15_102004
Figure Block Diagram LVDS System
10:1 serializer takes 10-bit wide data system clock, splits data into 5-bit sections, transfers this data into domain. 3-bit counter each path generates select signal MUX. This built three stages: first stage LUTs, MUXF5 between those LUTs, MUXF6 fifth bit. Figure shows block diagram this serializer.
XAPP756 (v1.0) November 2004
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Appendix RocketIO Design
CNT5 CLK_320M CLK_64M CLK_320M CLK_320M CLK_320M CNT5 CLK_320M
X756_16_101304
CLK_320M DDR-FF
TX_LVDS
CLK_320M
Figure Block Diagram 10:1 Serializer
Appendix RocketIO Design
RocketIO design (see Figure simple feasibility design. works recovered clock side using digital clock manager (DCM). production designs, advised directly RXRECCLK with DCM, either clean with external have protocol that utilizes clock correction.
RX_LVDS RXDATA RXCHARISK RXCHARISCOMMA RXREALIGN ALIGN_ENABLE RXUSRCLK2
PRBS Checker
RXUSRCLK2
Alignment Control
CLK_64M
TXUSRCLK/2
CLKGEN
RXRECCLK
RXUSRCLK/2
X756_17_101304
Figure RocketIO Block Diagram
design checks detected commas received datastream. Once comma detected, state machine checks three additional commas that words apart. soon those commas found, link considered aligned incoming data checked against errors. errors found, counter incremented displays value board. side very similar LVDS design. PRBS generator comma-count logic identical. However, 8B10B encoding serialization, dedicated functions RocketIO transceiver used. Because receiving SelectIO inputs have capability recovering clock embedded datastream, additional RocketIO transceiver used transmit constant pattern source-synchronous clock.
www.xilinx.com XAPP756 (v1.0) November 2004
Appendix LVDS Design
Appendix LVDS Design
LVDS inputs receive data correctly source-synchronous clock must initially aligned into middle incoming data eye. reference design XAPP268 used this function. When clock-data alignment finished, data deserialized circuit shown Figure Initially data split into path data received positive clock edge second negative clock edge. Only positive path shown simplicity. one-shot encoded enable circles pulse clock-cycle length that enables flip-flops serial-parallel conversion. This converted data stored flip-flops. Every five clock cycles either five bottom flip-flops read out, controlled second oneshot encoded read enable.
W_CE_P[9:0] D_R[9:5] R_CE_P[9]
RX_LVDS
DDR-FF
CLK_320M CLK_320M_180
D_R[4:0]
R_CE_P[4] R_CE_P[9:0]
X756_18_102004
Figure LVDS Deserializer
Writing reading takes place opposite halves this serial-in, parallel-out (SIPO) circuit, hence data corruption happen. read data MUXed together then presented rest design. After deserializer, data comma-aligned then checked design.
Appendix Hardware Configuration
boards used LVDS RocketIO transmission listed below: LVDS Transmission Xilinx XLVDSPro demonstration board with XC2VP20-FF896 Transmission Xilinx ML321 evaluation board with Virtex-II XC2VP7-FF672 designs were done VHDL, simulated with Modelsim 5.8D, synthesized using XST, implemented using 6.2i SP3. Table Table provide design sizes LVDS transceiver transceiver, respectively.
XAPP756 (v1.0) November 2004
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References
Table LVDS Transceiver (XC2VP20)
Parameter Occupied slices MULT18X18s GCLKs DCMs Total Number 9,280 Percent
Table Transceiver (XC2VP7)
Parameter Occupied slices GCLKs DCMs Total Number 4,928 Percent
reference design uses standard connectors. uses cable manufactured Florida Technology. voltages reference are: DC-coupled
VTRX open VTTX 1.8V VTRX 1.8V VTTX 2.5V
AC-coupled
References
following documents provide additional information relevant this application note: Xilinx XAPP230: "The LVDS Standard" Xilinx XAPP268: "Active Phase Alignment" Xilinx UG024: RocketIO Transceiver User Guide HFAN-1.1: "Choosing AC-Coupling Capacitors"
Revision History
following table shows revision history this document. Date 11/04/04 Version Initial Xilinx release. Revision
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XAPP756 (v1.0) November 2004
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