3.3V Design Guidelines Author: Simon XAPP653 (v3.1.1) 2008

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3.3V Design Guidelines Author: Simon XAPP653 (v3.1.1) 2008

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Application Note: Virtex-5, Virtex-4, Virtex-II Families
3.3V Design Guidelines
Author: Simon
XAPP653 (v3.1.1) 2008
Summary
This application note describes 3.3V PCIsolution Virtex®-5, Virtex-4, Virtex-II families. 3.3V design guidelines Spartan®-3 Generation families, refer XAPP457. 3.3V regulator reference design described this application note verified work with Virtex family pins, operating 3.3V standard.
Compliance
Compliance Specification requires clamp diodes withstand -3.5V 7.1V voltages undershoot overshoot tests, respectively. only exception clock pin. Figure shows compliance test setup requirements. This figure extracted from Compliance Specification.
Overvoltage Waveform Voltage Source Impedance (min) +7.1V 7.1V, p-to-p (minimum)
3.3V Supply
(max)
Evaluation Setup
Input Buffer
62.5 MHz)
+3.6V 7.1V, p-to-p (minimum) -3.5V
Undervoltage Waveform Voltage Source Impedance
x653_01_041607
Figure Overshoot/Undershoot Compliance Test Requirements
2002-2008 Xilinx, Inc. XILINX, Xilinx logo, Virtex, Spartan, other designated brands included herein trademarks Xilinx United States other countries. trademark PCI-SIG used under license. other trademarks property their respective owners.
XAPP653 (v3.1.1) 2008
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Compliance
Virtex-5 Virtex-II Devices
meet compliance requirement, Xilinx recommends regulating Virtex-5 Virtex-II FPGA VCCO 3.0V (the minimum VCCO compliance requirement) extend lower absolute maximum limit. lower absolute maximum limit derived from this equation: UndershootMAX VCCO GOSMAX where GOSMAX (maximum gate oxide stress) constant 4.05V. upper absolute maximum limit derived from Equation OvershootMAX Ground GOSMAX Hence, maximum overshoot 4.05V, regardless VCCO level. When VCCO 3.75V (the absolute maximum supply voltage Xilinx® FPGAs), UndershootMAX becomes -0.3V. When VCCO lowered 3.0V, UndershootMAX extended -1.05V, based Equation this case, ground clamp diode turns approximately -0.6V, clamping voltage before reaches absolute maximum limit. However, voltage across diode increases more current passes through determine exact voltage across ground clamp diode, Equation GND) where: diode current source voltage diode voltage drop ground source voltage impedance Because unknown, value assumed. corresponding compared against IBIS models validate assumption. Based undershoot test conditions, 3.5V assumption that 0.9V, applied Equation follows: (0.9) result implies diode current when 0.9V. Since closely corresponds ground clamp diode characteristics found published IBIS models (Table page assumption valid. other words, when 3.5V source voltage applied Virtex-5 Virtex-II FPGA through resistor, ground diode clamps 0.9V. Similar Equation current going through power clamp diode during overshoot test calculated follows: VCCO) Based overshoot test conditions, 7.1V assumption that 1.0V, applied Equation result implies diode current when 1.0V. Since corresponds power clamp diode characteristics found published IBIS models (refer Table page
XAPP653 (v3.1.1) 2008 www.xilinx.com
Equation
Equation
Equation
Voltage Regulation
assumption valid. other words, when 7.1V source voltage applied Virtex-5 Virtex-II FPGA through resistor, power diode clamps 4.0V. summary, ground power clamp diodes meet undershoot overshoot compliance requirements (assuming VCCO 3.0V) because following: ground clamp diode limits voltage -0.9V before reaching lower absolute maximum limit -1.05V. power clamp diode limits voltage 4.0V before reaching upper absolute maximum limit 4.05V.
Virtex-4 Devices
stated data sheet Virtex-4 family, when more than I/Os used, Virtex-4 device absolute maximum limit 4.05V, absolute minimum limit -0.95V. this case, described previous section, regulating VCCO 3.0V applies. However, these limits relaxed when fewer I/Os used. such cases, maximum VCCO 3.35V commercial grade 3.25V industrial grade devices.
Additional Information
additional information, UG072, Virtex-4 Designer's Guide, UG203, Virtex-5 Designer's Guide, XAPP659, Virtex-II Virtex-II 3.3V Design Guidelines.
Voltage Regulation
Regulator Reference Design
reference design schematic shown Figure provides solution regulating VCCO 3.0V. offers electrical compliance standard Virtex-5, Virtex-4, Virtex-II FPGA designs. This low-cost solution uses minimal board space been verified.
from 5.0V LT1763CS8
VOUT
VCCO Pins Bank Connected
Virtex-5, Virtex-4, Virtex-II FPGA
26.1
Size: 1206
38.3
Size: 1206
Tantalum
Size:
3.3V
X653_02_050108
Figure Reference Design Schematic
Regulator Implementation
highlighted elements Figure (U1, comprise regulator implementation typical FPGA layout. This configuration supplies VOUT tightly regulated 3.0V 3.3V VCCO banks. LT1763CS8 regulator covers industrial operating temperature range since regulator junction temperature range -40°C +125°C. reference design provides fully compliant electrical interface Virtex-5, Virtex-4, Virtex-II devices. Depending performance requirements, PCI33 PCI66 standard I/Os connecting should used.
XAPP653 (v3.1.1) 2008
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Appendix
Voltage Regulator Layout FPGA
Provide Low-Impedance Path VOUT VCCO banks
3.3V Signals
x653_03_022205
Figure Layout Area Example Linear Technology LT1763CS8 Devices Linear Technology manufactures noise, dropout, micropower LT1763 series regulators. These devices capable supplying output current with dropout voltage Internal protection circuitry includes reverse battery protection, current limiting, thermal limiting, reverse current protection. LT1763CS8 regulator used this application adjustable device with 1.22V reference voltage. regulator details from Linear Technology, data sheet Linear Technology website following URL: http://www.linear.com. Solution Cost total cost solution shown Figure estimated less than $2.00 1000-piece quantities. This estimate includes LT1763CS8 regulator, resistors, capacitor.
Appendix
Table Table show voltage-current characteristics Virtex-II FPGA protection diodes under different temperature voltage conditions. This data, along with additional information about drive capability, located IBIS models. Table Virtex-II FPGA Ground Clamp Diode Characteristics External Voltage -3.3000 -3.2000 -3.1000 -3.0000 -2.9000 -2.8000 -2.7000 -2.6000 -2.5000 (typ) -4.9900 -4.7610 -4.5320 -4.3030 -4.0740 -3.8450 -3.6160 -3.3870 -3.1580 (min) -4.5330 -4.3320 -4.1310 -3.9300 -3.7280 -3.5270 -3.3260 -3.1260 -2.9250 (max) -4.9880 -4.7580 -4.5280 -4.2980 -4.0680 -3.8380 -3.6080 -3.3780 -3.1480 Unit Measure
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Appendix Table Virtex-II FPGA Ground Clamp Diode Characteristics (Continued) External Voltage -2.4000 -2.3000 -2.2000 -2.1000 -2.0000 -1.9000 -1.8000 -1.7000 -1.6000 -1.5000 -1.4000 -1.3000 -1.2000 -1.1000 -1.0000 -0.9000 -0.8000 -0.7000 -0.6000 -0.5000 -0.4000 -0.3000 -0.2000 -0.1000 0.0000
Notes:
Typical conditions 25°C, 3.3V. Minimum conditions 100°C, 3.0V. Maximum conditions 0°C, 3.45V.
(typ) -2.9290 -2.7010 -2.4720 -2.2450 -2.0190 -1.7940 -1.5720 -1.3530 -1.1380 -0.9302 -0.7315 -0.5469 -0.3813 -0.2385 -0.1281 -70.5400 -47.3200 -30.4600 -16.4200 -6.2200 -1.2320 -0.1076 -4.5180 -0.1127 -6.6770
(min) -2.7260 -2.5260 -2.3280 -2.1300 -1.9330 -1.7380 -1.5440 -1.3520 -1.1620 -0.9775 -0.7977 -0.6261 -0.4659 -0.3210 -0.1957 -99.1700 -46.2500 -25.8900 -14.3600 -6.2200 -1.6750 -0.2328 -18.5600 -1.0300 -66.9100
(max) -2.9180 -2.6890 -2.4590 -2.2310 -2.0040 -1.7790 -1.5550 -1.3350 -1.1190 -0.9107 -0.7115 -0.5270 -0.3625 -0.2240 -0.1294 -89.4300 -65.7900 -44.8300 -26.3200 -11.6000 -2.8860 -0.3018 -13.8700 -0.3010 -13.2700
Unit Measure
Table Virtex-II FPGA Power Clamp Diode Characteristics External Voltage 3.3000 3.2000 3.1000 3.0000 2.9000 2.8000 2.7000 2.6000
XAPP653 (v3.1.1) 2008
(typ) 4.2620 4.0700 3.8770 3.6850 3.4930 3.3010 3.1090 2.9170
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(min) 3.4560 3.3060 3.1560 3.0050 2.8560 2.7060 2.5560 2.4070
(max) 4.4610 4.2590 4.0570 3.8550 3.6530 3.4510 3.2490 3.0470
Unit Measure
Appendix Table Virtex-II FPGA Power Clamp Diode Characteristics (Continued) External Voltage 2.5000 2.4000 2.3000 2.2000 2.1000 2.0000 1.9000 1.8000 1.7000 1.6000 1.5000 1.4000 1.3000 1.2000 1.1000 1.0000 0.9000 0.8000 0.7000 0.6000 0.5000 0.4000 0.3000 0.2000 0.1000 0.0000
Notes:
Typical conditions 25°C, 3.3V. Minimum conditions 100°C, 3.0V. Maximum conditions 0°C, 3.45V.
(typ) 2.7260 2.5340 2.3430 2.1520 1.9610 1.7700 1.5800 1.3890 1.2010 1.0150 0.8339 0.6584 0.4927 0.3397 0.2032 94.8800 39.6900 23.3600 14.3400 7.3070 2.4360 0.3499 21.9300 0.8963 0.0760 0.0429
(min) 2.2580 2.1090 1.9600 1.8120 1.6650 1.5170 1.3710 1.2250 1.0800 0.9373 0.7954 0.6558 0.5195 0.3884 0.2656 156.7000 73.0000 29.6200 15.0000 7.8690 3.1010 0.6618 70.4200 5.2470 0.5476 0.2878
(max) 2.8460 2.6450 2.4440 2.2430 2.0420 1.8420 1.6420 1.4430 1.2470 1.0530 0.8634 0.6793 0.5034 0.3393 0.1932 87.4000 46.4600 31.4500 20.0800 10.7500 3.9780 0.6555 39.3900 1.7000 0.4264 0.3536
Unit Measure
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Revision History
Revision History
following table shows revision history this document. Date 06/17/02 02/06/03 04/14/03 01/09/04 05/19/04 03/07/05 03/09/05 05/03/07 Version 1.3.1 2.0.1 Initial Xilinx release. Added "PCI Compliance" section. Added standard suggestions connecting bus. Added references Spartan-3 FPGA family. Replaced "PCI Compliance" section with more detailed information. Added "Appendix". Removed statement about alternate solutions from "Regulator Implementation" section. Updated application note include Virtex-4 devices. Corrected author's name. Expanded include Virtex-4, Virtex-5, Spartan-3, Spartan-3E devices. Modified information Compliance Specification requirement "PCI Compliance" section. Restructured document headings, resized figures, reformatted tables Appendix. Throughout: Removed references Spartan-3 Generation devices. Refer XAPP457 Spartan-3 Generation 3.3V information. Figure Changed regulator output capacitor from Figure page Added capacitor regulator. Repagination. Revision
07/09/07
05/05/08 05/12/08
3.1.1
Notice Disclaimer
Xilinx disclosing this Application Note "AS-IS" with warranty kind. This Application Note possible implementation this feature, application, standard, subject change without further notice from Xilinx. responsible obtaining rights require connection with your implementation this Application Note. XILINX MAKES REPRESENTATIONS WARRANTIES, WHETHER EXPRESS IMPLIED, STATUTORY OTHERWISE, INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES MERCHANTABILITY, NONINFRINGEMENT, FITNESS PARTICULAR PURPOSE. EVENT WILL XILINX LIABLE LOSS DATA, LOST PROFITS, SPECIAL, INCIDENTAL, CONSEQUENTIAL, INDIRECT DAMAGES ARISING FROM YOUR THIS APPLICATION NOTE.
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3.3V Design Guidelines Author: Simon XAPP653 (v3.1.1) 2008

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