Power Distribution System (PDS) Design: Using Bypass/Decoupling Capaci
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Application Note: Virtex-II Series
Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors
Author: Mark Alexander
XAPP623 (v2.1) February 2005
Summary
This application note specifies build power distribution systems Virtexdevices. also covers basic principles power distribution systems bypass decoupling capacitors. step-by-step process described where power distribution system designed verified. final section discusses additional sources power supply noise provides resolutions.
Introduction
FPGA designers faced with unique task when comes designing power distribution systems (PDS). Most other large, dense (such large microprocessors) come with very specific bypass capacitor requirements. Since these devices only designed implement specific tasks their hard silicon, their power supply demands fixed only fluctuate within certain range. FPGAs share this property. Since FPGAs implement almost infinite number applications undetermined frequencies multiple clock domains, very complicated predict what their transient current demands will Since exact transient current behavior cannot known FPGA design, only choice when designing first version FPGA with conservative worstcase design. Transient current demands digital devices cause ground bounce, bane highspeed digital designs. low-noise high-power situations, power supply decoupling network must tailored very closely these transient current needs, otherwise ground bounce power supply noise will exceed limits device. transient currents FPGA different from design design. This application note provides comprehensive method designing bypassing network suit individual needs specific FPGA design. first step this process examine utilization FPGA rough idea transient current requirements. Next, conservative decoupling network designed these requirements. third step refine network through simulation modification capacitor numbers values. fourth step, full design built fifth step measured. Measurements made consisting oscilloscope possibly spectrum analyzer readings power supply noise. Depending measured results, further iterations through part selection simulation steps could necessary optimize specific application. sixth optional step also given cases where perfectly optimized needed.
Basic Decoupling Network Principles
Before starting into design flow, important understand basic electrical principles involved. This section discusses purpose properties components. also describes important aspects discrete capacitor placement mounting well geometry stackup recommendations. purpose provide power devices system. Each device system only power requirements operation, also requirement
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Basic Decoupling Network Principles cleanliness that power. Most digital devices, including Xilinx FPGAs, have requirement that supplies, must fluctuate more than above below nominal value. this document used generically refer FPGA power supplies: VCCINT, VCCO, VCCAUX, VREF. Multi-gigabit transceiver (MGT) analog supplies (AVCCAUXTX, AVCCAUXRX, VTTX, VTRX) covered here. specific instructions these supplies, RocketIOTransceiver User Guide (Reference #1). This requirement specifies maximum amount noise present power supply, often referred "ripple voltage." device requirements state that must within nominal voltage, that means peak peak voltage ripple must more than nominal VCC. This assumes that nominal exactly nominal value given datasheet. this case, then VRIPPLE must adjusted value correspondingly less than 10%. power consumed digital device varies over time, this variance occurs frequency scales. frequency variance power consumption usually result devices large portions devices being enabled disabled. This occur time scales from milliseconds days. High frequency variance power consumption result individual switching events inside device, this happens scale clock frequency first harmonics clock frequency. Since voltage level device fixed, changing power demands manifested changing current demand. must accommodate these variances current draw with little change power supply voltage possible. When current draw device changes, power distribution system cannot respond that change instantaneously. short time before responds, voltage device changes. This where power supply noise appears. There main causes this corresponding major components PDS. first major component voltage regulator. observes output voltage adjusts amount current being supplied keep voltage constant. Most common voltage regulators make this adjustment order milliseconds microseconds. They effective maintaining output voltage events frequencies from hundred kilohertz (depending regulator). transient events that occur frequencies above this range, there time before voltage regulator respond level demand. example, current demand device increases matter nanoseconds, voltage device sags some amount until voltage regulator adjust new, higher level current must provide. This might take from microseconds milliseconds, during which time voltage sags. second major component bypass decoupling capacitors. this application note, words "bypass" "decoupling" used interchangeably. Their function local energy storage device. They cannot provide power, only small amount energy stored them (the voltage regulator present provide power). function this local energy storage respond very quickly changing current demands. capacitors effective maintaining power supply voltage frequencies from hundreds kilohertz hundreds megahertz milliseconds nanoseconds range. Decoupling capacitors events occurring above below this range. example, current demand device increases picoseconds, voltage device sags some amount until capacitors supply extra charge device. current demand device changes maintains this level number milliseconds, voltage regulator circuit, operating parallel with bypass capacitors, effectively takes over them, changing output supply this current.
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Basic Decoupling Network Principles Figure shows major components PDS: power supply, decoupling capacitors, active device being powered this case, FPGA).
FPGA
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Figure Simplified Circuit
Figure shows further simplified circuit, showing reactive components decomposed frequency-dependent resistor.
ltransient VRIPPLE
FPGA
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Figure Further Simplified Circuit
What Role Inductance?
There property capacitors current paths that retards changes current flow. This reason capacitors cannot respond instantaneously transient currents, changes that occur frequencies higher than their effective range. This property called inductance. Inductance thought momentum charge. Where charge moving some rate through conductor, this implies some amount current. level current change, charge must move different rate. Because there momentum (stored magnetic field energy) associated with this charge, takes some amount time charge slow down speed greater inductance, greater resistance change, longer takes current level change. purpose accommodate whatever current demands device(s) could have, respond changes that demand quickly possible. When these demands met, voltage across device's power supply changes. This observed noise. Since inductance retards abilities bypass capacitors quickly respond changing current demands, should minimized. Figure shows inductances between FPGA device capacitors, between capacitors voltage regulator. These inductances arise parasitics capacitors themselves current paths PCB. important that each these minimized.
Capacitor Parasitic Inductance
capacitor's various properties, capacitance value often considered most important. However domain design, property parasitic inductance (ESL Equivalent Series Inductance) same greater importance. factor that influences parasitic inductance more than other dimensions package. Very simply, physically small capacitors tend have lower parasitic inductance
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Basic Decoupling Network Principles than physically large capacitors. Just short wire less inductance than long wire, short capacitor less inductance than long capacitor. Likewise, wide wire less inductance than narrow wire, does capacitor have less inductance than narrow capacitor. these reasons, when choosing decoupling capacitors, smallest package should chosen given value. Similarly, given package size (essentially fixed inductance value), highest capacitance value available that package should chosen. Surface-mount chip capacitors smallest capacitors available, making them good choice discrete bypass capacitors. values from down very small values such 0.001 type capacitors usually used. These have parasitic inductance, acceptable temperature characteristic. larger values, such 1000 tantalum capacitors used. These have parasitic inductance relatively high equivalent series resistance (ESR), giving them low-quality factor consequently very wide range effective frequencies. They also provide comparatively high capacitance value small package size, thus reducing board real-estate costs. cases where tantalum capacitors available, low-inductance electrolytic capacitors used. Other technologies with similar characteristics also available. real capacitor characteristics only capacitance also inductance resistance. Figure shows parasitic model real capacitor. real capacitor should treated circuit.
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Figure Parasitics Real, Non-Ideal Capacitor
Figure shows impedance characteristic real capacitor. Overlaid this plot curves corresponding capacitor's capacitance parasitic inductance (ESL). These curves combine form total impedance characteristic circuit formed parasitics capacitor.
Total Impedance Characteristic
Inductive Contribution (ESL)
Impedance
Capacitive Contribution
Frequency
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Figure Contribution Parasitics Total Impedance Characteristics
capacitive value increased, capacitive curve moves down left. parasitic inductance decreased, inductive curve moves down right. Since parasitic
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Basic Decoupling Network Principles
inductance capacitors given package essentially fixed, inductance curve remains fixed. different capacitor values selected that same package, capacitive curve moves down relative fixed inductance curve. only decrease total impedance capacitor given package increase value capacitor. only move parasitic inductance curve down (and consequently lower total impedance characteristic), connect additional capacitors parallel.
Inductance from Current Paths
parasitic inductance current paths have distinct sources: capacitor mounting, power ground planes PCB. Mounting Inductance this context, mounting refers capacitor's solder land PCB, trace any) between land via, itself. vias, traces, pads capacitor mounting contribute anywhere from inductance depending specific geometry. Since inductance current path proportional area loop current traverses, important minimize size this loop. loop consists path through power plane, through via, through connecting trace land, through capacitor, through other land connecting trace, down through other via, into other plane, shown Figure
0402 Capacitor Body Surface Trace
Solderable Terminal Capacitor Solder Land
Power Ground planes
Mounted Capacitor Current Loop
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Figure Cutaway View with Capacitor Mounting
shortening connecting traces, area this loop minimized inductance reduced. Similarly, reducing length through which current flows, loop area minimized inductance reduced.
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Basic Decoupling Network Principles
0402 Land Pattern, vias, long traces,
0402 Land Pattern, vias, 0.8nH
0402 Land Pattern, side vias, 0.6nH 0402 Land Pattern, double side vias, 0.4nH
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Figure Example Capacitor Land Mounting Geometries
existence and/or length connecting trace impact parasitic inductance mounting. Wherever possible, there should connecting trace (Figure should butt against land itself (Figure 6b). Additionally, connecting trace should made wide possible. Further improvements made mounting placing vias side capacitor lands (Figure 6c), doubling number vias (Figure 6d). Currently, very manufacturing processes allow via-in-pad geometries, this another good option. technique using multiple vias land important when using ultra-low inductance capacitors, such reverse aspect ratio capacitors (AVX's LICC). Many times effort squeeze more parts into small area, layout engineers share vias among multiple capacitors. This technique should used under circumstances. capacitor mounting (lands, traces vias) typically contributes about same amount more inductance than capacitor's parasitic inductance. second capacitor connected into vias existing capacitor, only improves very small amount. better reduce total number capacitors maintain one-to-one ratio lands vias. Plane Inductance power ground planes have some amount inductance associated with them. geometry these planes determines their inductance. Since power ground planes definition planar structure, current does just flow through them direction. tends spread travels from point another, accordance with property similar skin effect. this reason, inductance planes described "spreading inductance," specified units henries square. square dimensionless, shape section plane, size, that determines inductance. Spreading inductance acts like other inductance resist changes amount current conductor. this case, conductor power plane planes. This quantity should reduced much possible, since retards ability capacitors respond transient currents device. Since shape plane typically something designer little control over, only controllable factor spreading inductance value.
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Basic Decoupling Network Principles
This primarily determined thickness dielectric separating power plane from associated ground plane. high-frequency power distribution systems type discussed here, power ground planes work pairs. Their inductances exist independently each other. spacing (and dielectric constant material) between power ground planes determines spreading inductance pair. closer spacing (the thinner dielectric), lower spreading inductance. Table gives approximate values spreading inductance different thicknesses dielectric (Reference #2).
Table Capacitance Spreading Inductance Values Various Thicknesses Power-Ground Plane Sandwiches
Dielectric Thickness (mil, microns) Inductance (pH/square) Capacitance (pF/in2, pF/cm2) 225, 450, 900,
Since closer spacing results decreased spreading inductance, best, wherever possible, place planes directly adjacent planes stackup. Facing planes sometimes referred "sandwiches." While sandwiches necessary past previous technologies, speeds involved sheer amount power required fast, dense devices demands Besides offering low-inductance current path, power-ground sandwiches also offer some high-frequency decoupling capacitance. plane area increases separation between power ground planes decreases, value this capacitance increases. same time, since parasitic inductance this capacitance decreasing, effective frequency band center frequency increases. Capacitance square inch also given Table This capacitance alone usually enough give power-ground sandwiches compelling advantage. However, when viewed bonus spreading inductance, advantage most designers gladly take. Stackup Layer Order placement Ground planes stackup (determined layer order) significant impact parasitic inductances power current paths. this reason, designers need consider layer order early stages design cycle, putting highpriority supplies half stackup low-priority supplies bottom half stackup. Power supplies with high transient current should have their associated planes close surface (FPGA side) stackup decrease distance vertical direction that currents travel through vias before reaching associated planes. mentioned previous section, every plane should have plane adjacent stackup reduce spreading inductance. Since high-frequency currents couple tightly skin effect, plane adjacent given plane tends carry majority current complementary that plane. this reason, adjacent planes considered pair. plane pairs reside half stackup, because manufacturing constraints typically require stackup symmetrical about center with respect dielectric thicknesses etched copper areas. designer must determine which plane pairs have high priority carry high-frequency energy, which pairs have priority carry lower frequency energy.
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Basic Decoupling Network Principles
Capacitor Effective Frequency
Every capacitor narrow frequency band where most effective decoupling capacitor. Outside this band, does have some contribution general much smaller. frequency bands some capacitors wider than others. capacitor determines quality factor capacitor, which determines width effective frequency band. Tantalum capacitors generally have very wide effective band, while chip capacitors, with their lower ESR, generally have very narrow effective band. effective frequency band corresponds capacitor's resonant frequency. While ideal capacitor only capacitive characteristic, real non-ideal capacitors also have parasitic inductance parasitic resistance ESR. These parasitics series form circuit (Figure resonant frequency associated with that circuit resonant frequency capacitor. determine resonant frequency circuit, following equation used:
Equation
Alternatively, frequency sweep SPICE simulation circuit could performed, frequency where minimum impedance value occurs would resonant frequency. important distinguish between capacitor's self-resonant frequency effective resonant frequency mounted capacitor when part system. This simply difference between taking into account only capacitor's parasitic inductance, taking into account parasitic inductance well that vias, planes, connecting traces lying between FPGA. self-resonant frequency capacitor RSELF (the value reported capacitor datasheet), considerably higher than effective mounted resonant frequency system, FRIS. Since mounted capacitor's performance what important, mounted resonant frequency that used when evaluating capacitor part larger PDS. main contributors mounted parasitic inductance capacitor's parasitic inductance, inductance lands connecting traces, inductance vias, power plane inductance. Vias traverse full board stackup their device when capacitors mounted underside board. These vias contribute something range 1,500 board with finished thickness mils; vias thicker boards have higher inductance. Because there these paths series with each capacitor, twice this value should added capacitor's parasitic inductance. This quantity, parasitic inductance capacitor mounting, designated LMOUNT. determine total parasitic inductance capacitor in-system, LIS, capacitor's parasitic inductance LSELF added parasitic inductance mounting, LMOUNT: LSELF LMOUNT
Example
Ceramic Chip capacitor (AVX capacitor data used here) 0.01 LSELF FRSELF LMOUNT
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Basic Decoupling Network Principles determine effective in-system parasitic inductance (LIS), parasitics: LSELF +LMOUNT +0.8 Plugging values from example:
FRIS: Mounted Capacitor Resonant Frequency: Since decoupling capacitor only effective narrow band frequencies around resonant frequency, important that resonant frequency taken into account when choosing collection capacitors build decoupling network.
Capacitor Anti-Resonance
common problem associated with capacitors FPGA anti-resonant spikes aggregate impedance. These spikes caused combinations energy storage devices (such discrete capacitors, parasitic inductances, power ground planes). inter-plane capacitance power ground planes especially with high-quality factor, crossover point between high-frequency discrete capacitors this plane capacitance might exhibit high-impedance anti-resonance peak. FPGA high transient current demand this frequency (acting stimulus), large noise voltage results. improved only bringing down impedance anti-resonant spike. mitigate this problem, either characteristics highfrequency discrete capacitors characteristics Ground planes must changed.
Capacitor Placement
Capacitors need close device perform decoupling function. There basic reasons this requirement. First, increased spacing between device decoupling capacitor increases distance travelled current power ground planes, hence, inductance current path between device capacitor. Since inductance this path (the loop followed current goes from side capacitor pin[s] FPGA, from pin[s] FPGA side capacitor[s]), proportional loop area, decreasing inductance matter decreasing loop area. Shortening distance between device decoupling capacitor(s) reduces inductance resulting less impeded transient current flow. Because dimensions PCBs, this reason tends less important with regard placement than second reason. second reason deals with phase relationship between FPGA noise source mounted capacitor. Their phase relationship determines capacitor's effectiveness. capacitor effective providing transient current certain frequency (for instance, optimum frequency that capacitor), must within fraction wavelength associated with that frequency. placement capacitor determines length transmission line interconnect this case, power ground plane pair) between capacitor FPGA. propagation delay this interconnect relevant factor.
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Basic Decoupling Network Principles Noise from FPGA falls into certain frequency bands, different sizes decoupling capacitors take care different frequency bands. this reason, capacitor placement determined based effective frequency each capacitor. When FPGA initiates change current demand, causes small local disturbance voltage point power ground planes). decoupling capacitor counteract this, capacitor first voltage difference. There finite time delay between start disturbance FPGA power pins start capacitor's view disturbance. This time delay equal distance from FPGA power pins capacitor, divided propagation speed current through dielectric (the substrate where power planes embedded). There another delay same duration compensation current from capacitor reach FPGA. Therefore, transient current demand FPGA, there round-trip delay capacitor before relief seen FPGA. placement distances greater than quarter wavelength some frequency, energy transferred FPGA negligible. decreasing distances less than quarter wavelength, energy transferred FPGA increases 100% zero distance. Efficient energy transfer from capacitor FPGA requires placement capacitor fraction quarter wavelength FPGA power pins. This fraction should small because capacitor also effective frequencies slightly above resonant frequency, where corresponding wavelength shorter. practical applications, tenth quarter wavelength good target. This leads placing capacitor within fortieth wavelength power pins decoupling. wavelength corresponds FRIS, capacitor's mounted resonant frequency.
Example
0.001 Ceramic Chip capacitor, 0402 package 125.8 0.001 Equation calculates TRIS, mounted period resonance, from FRIS 7.95 Equation 125.8 Equation computes wavelength based TRIS propagation velocity dielectric.
Wavelength PROP
Equation
where PROP
-inch
7.95 47.9 inches PROP
PLACE
Equation
47.9 inches PLACE 1.20 inches
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Basic Decoupling Network Principles
this example, effective frequency, equal resonant frequency, determined Equation This effective frequency determined 125.8 MHz. reciprocal this taken give resonant period, 7.95 using Equation Using propagation speed current (approximately inch), wavelength associated with this capacitor computed approximately inches using Equation computed Equation fortieth this inches. Therefore target placement radius (RPLACE) capacitors this size within inches (3.0 power ground pins they decoupling. other capacitor sizes follow same manner. radius inches terribly difficult achieve current technology. does require placing capacitors directly underneath device opposite side PCB. acceptable capacitors mounted around periphery device, provided target radius maintained. 0.001 capacitors among smallest decoupling network, placement radii less than inch unnecessary. larger capacitors, target placement radius expands quickly resonant frequency goes down. capacitor, example, placed anywhere board, target radius inches much bigger than most PCBs (corresponding resonant frequency 1.56 MHz).
Example Capacitor Layout
Figure example bottom-side artwork showing capacitor layout. Black fill hatch represents plated copper, represents vias, blue represents silkscreen labels, purple represents package outlines. FPGA footprint seen regular array dots upper portion figure center. absence vias cross pattern center device indicates that solder lands surface their associated vias escape toward corners.
package outline
silkscreen label
plated copper
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Figure Example Layout showing Capacitor Placement Bottom Surface
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Design Verification this example, many high-frequency 0402 decoupling capacitors placed within footprint FPGA opposite side board (C150, C117). There also handful 0603 decoupling capacitors termination resistors (C307, R274). Larger capacitors placed outside footprint FPGA, moving farther away from FPGA with increasing size (C247, C288). Traces connecting capacitor lands vias kept short possible. Also large-package capacitors with large separation between solder lands (C42, C224), vias inserted between solder lands reduce parasitic inductance mounting. necessary place high-frequency capacitors within footprint FPGA. perfectly acceptable place capacitors around periphery device, provided planes have Ground plane adjacent them, separated dielectric less than mils thickness. Also, cases where Ground plane pairs half stackup (closer device), advantageous place capacitors surface board, around periphery device. cases where large numbers external termination resistors used, placement termination resistors takes priority over decoupling capacitors. Moving away from device concentric rings, termination resistors should closest device, followed smallest-value decoupling capacitors, then followed larger-value decoupling capacitors.
Design Verification
Having discussed basic operating principles power distribution systems, this section introduces step-by-step process designing verifying PDS.
Step Determining Critical Parameters FPGA
designing first iteration decoupling capacitor network, basic objective have capacitor used device. Therefore, effective number pins each supply must determined. Very designs 100% various resources FPGA. FPGA package inside very carefully sized meet needs fully utilized without being overly conservative. number pins package given device determined based needs 100% utilized FPGA. determining factor power handling abilities transient current impedance. Decoupling capacitor requirements track very closely since they based same factor. this reason, number pins each supply used indicator number capacitors needed that supply. supplies must considered: VCCINT, VCCAUX, VCCO, VREF. only necessary provide capacitor pins used. There need decouple VREF pins they used VREF. Conversely, VCCAUX VCCINT pins must always fully decoupled, i.e., they must always have capacitor pin. VCCO prorated according utilization.
Pro-rating VCCO Pins
number VCCO pins used device determined based Simultaneously Switching Output (SSO) restrictions given device documentation (data sheet user guide). budget calculated per-bank basis using these restrictions. utilization resources bank determines percentage budget used. This percentage effectively represents percentage VCCO pins used device.
Examples: Using XC2V3000 FF1152
Single bank full device examples provided. Single Bank Example hypothetical design, Bank outputs Each configured 3.3V LVCMOS Fast driver.
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Design Verification
limit 3.3V LVCMOS Fast drivers table datasheet VCC/GND pair. There VCCO pins bank this device. Therefore, limit this type driver bank. This bank uses outputs. Therefore percentage total bank budget that used Bank Percentage Used Used/Limit 80/130 Full Device Example this example, utilization I/Os device listed Table well perbank limits each standard (Table computed from number VCC/GND pair limits Virtex-II Platform FPGA User Guide (Reference #3).
Table Utilization Each Bank Full Device Example
Bank Number Bank Bank Bank Bank Bank Voltage 3.3V 3.3V 1.5V 1.5V 1.8V Utilization Bank 1.8V Bank 1.8V Bank 1.8V Standard LVCMOS_12F LVCMOS_12F LVDCI LVDCI HSTL_1 LVCMOS_12F HSTL_1 LVCMOS_12F HSTL_1 LVCMOS_12F HSTL_1 LVCMOS_12F
Table Limits Standards Full Device Example
Standard 3.3V LVCMOS_12F 1.5V LVDCI 1.8V HSTL_1 1.8V LVCMOS_12F Limit Bank
budget banks computed single-bank example. Banks however, have standards them. these banks, budget computed each standard separately, then combined. Banks 1.8V HSTL_1: used used/limit 32/260 1.8V LVCMOS_12F: used used/limit 45/117 Total budget each bank:
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Design Verification Table summarizes budgets each bank device.
Table Budgets Each Bank Full Device Example
Bank Number Bank Bank Bank Bank Bank Bank Bank Bank Budget
number VCCO pins used bank (Table simply number VCCO pins bank times percentage budget used.
Table Number VCCO Pins Used
Bank Number Bank Bank Bank Bank Bank Bank Bank Bank Calculated pins pins pins pins pins pins pins pins Number Pins Used pins pins pins pins pins pins pins pins
Step Designing Generic Bypassing Network
number Xilinx test boards customer designs were analyzed discern some trends successful designs. 100% utilized designs with power supply noise order half maximum allowed power supply noise (VRIPPLE/2), generally approximately capacitor per-supply basis. generic bypassing network designed with this range capacitors mind. pro-rated number VCCO pins used. Given number discrete capacitors needed determined above, distribution capacitor values adding that total number must determined. cover broad range frequencies, broad range capacitor values must used. proportion high-frequency capacitors low-frequency capacitors important factor. objective parallel combination number values capacitors keep flat power supply impedance over frequencies from range range. Both large value (low frequency) small value (high frequency) capacitors needed. Small value capacitors tend have less impact total impedance profile, greater number small value capacitors needed yield same impedance level impact small number large value capacitors. keep impedance profile smooth free anti-resonance spikes, capacitor generally needed least every decade capacitor value range. typical ceramic
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Design Verification capacitor range generally spans values from 0.001 exact value these capacitors critical. What critical having some capacitor value every order magnitude over this range. More values better, flatter impedance profile yielded.
ratio capacitors giving relatively flat impedance where quantity capacitors roughly doubled every decade decrease size. other words, bottom three values network were 0.01 network might have capacitor, four capacitors, eight 0.01 capacitors. addition, low-frequency capacitance form tantalum, OS-CON, electrolytic capacitors needed. These large capacitors typically have higher than ceramic chip capacitors, making them effective over wider range frequencies. This also makes capacitors less likely contribute anti-resonance spikes. this reason, necessary maintain rule value decade. Generally, value 1000 range sufficient. percentages helpful calculating these ratios based total number capacitors (Table
Table Capacitor Value Percentages Balanced Decoupling Network
Capacitor Value 1000 0.47 0.01 0.047 Quantity Percentage Capacitor Type Tantalum 0805 0603 0402
every power supply except VREF, these ratios should roughly maintained. VREF supplies, values should distributed 50/50 ratio 0.47 capacitors 0.01 0.047 capacitors. Since primary function VREF decoupling capacitors reduce impedance VREF nodes thus reducing crosstalk coupling, very little low-frequency energy needed. Therefore, only capacitors 0.01 0.47 range necessary.
1.5V Supply Example
this example, 1.5V supply Virtex-II device supplies VCCO banks VCCINT. There VCCINT pins this device. Banks were previously calculated pins each. Adding VCCINT pins four VCCO pins Banks equals pins. Therefore, there should capacitors total 1.5V supply. Table shows quantity each value capacitor determined.
Table Calculation Capacitor Quantities 1.5V Supply Example
Capacitor Value 0.47 0.047 Calculated pins 1.92 pins 6.72 pins 12.6 pins 26.4 Quantity Capacitors
This calculation gives first-pass estimate capacitors necessary 1.5V supply. Changes made exact number capacitors accommodate different values make supply more symmetric (e.g., using eight capacitors instead seven more standard layout). Capacitor values also modified according specific constraints design (e.g., pre-existing capacitors). This process capacitor selection must repeated each supply.
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Design Verification
Step Simulation
During simulation, generic decoupling network verified some cases refined. designer experiment with different values capacitors different packages achieve optimum power supply impedance profile constraints system. number levels design tools available from various vendors listed Appendix Tools Design Simulation. simulation circuit essentially parallel combination decoupling capacitors with associated parasitics. simulator calculates aggregate impedance over pertinent range frequencies. equivalent circuit created analyzed SPICE (see Appendix SPICE Simulation Examples example SPICE deck) tools listed Appendix Tools Design Simulation. more limited still effective approach plot impedance profile spreadsheet tool (for example, Microsoft Excel). Note that lumped simulation this type does reflect distributed properties Ground planes stackup. effects these planar structures usually begin manifest range, dependent geometries planes (for example, length width). These difficult predict without distributed model, such what offered tool like Speed2000, SIwave, Specctraquest Power Integrity, full-mesh SPICE simulation. this reason, unwise draw conclusions from results lumped simulation above MHz. using these tools simulate bypassing network, important have accurate parasitic values. Obtaining accurate self-parasitic data from capacitor vendor from inhouse testing important. mounting parasitics lying path between bypass capacitor FPGA also need taken into account. These parasitics combined series give mounted capacitor parasitic resistance inductance. section Mounting Inductance covers details mounting modeling. Appendix Calculation Inductance lists equations parasitic inductance. more accurate inductance number particular geometry obtained using field solver such Ansoft's HFSS. following simulation, value mounting inductance added each capacitor's parasitic self-inductance come with LIS. This parameter reflects inductance small capacitor mountings board order mils thick. Thicker board stackups have higher associated inductance. Figure shows simple impedance plot from simulation parallel combination these capacitors, taking into account their parasitics approximate parasitics PCB. equivalent SPICE netlist included Appendix SPICE Simulation Examples. Table lists capacitor quantities, values, parasitic values used simulation. characteristics planes taken into account.
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Design Verification
Four Values Parallel Capacitors [ohms]
1.E+00
Impedance (ohms)
1.E-01
1.E-02
1.E-03 1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
Frequency [MHz]
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Figure Impedance Versus Frequency Plot Table Values Used Impedance Plot Figure
Quantity Symbol Package 0805 0603 0402 Capacitive Values (µF) 0.22 0.022 Parasitic Inductance (nH) Parasitic Resistance (ohms) 0.57 0.02 0.06 0.20
This collection capacitors good start. impedance below 0.033 from MHz, increases 0.11 MHz. Over this range there significant antiresonance spikes. These capacitors used board design.
Step Building Design
this stage, laid with final capacitor networks verified simulation. board built. earlier sections capacitor placement land geometries detailed layout information.
Step Measuring Performance
performance measurement step, measurements made determine whether adequate devices serving. Determining whether bypassing network adequate given design relatively simple. measurement performed with highbandwidth oscilloscope oscilloscope probe minimum), design running realistic test patterns.
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Design Verification Noise Magnitude Measurement measurement taken either directly power pins device, across pair unused I/O, driven High driven Low. VCCINT VCCAUX only measured backside vias. VCCO also measured this way, more accurate results obtained measuring fixed signals unused I/Os same bank. When making noise measurement back-side board, necessary take into account parasitics vias path between measuring point FPGA, voltage drop occurring this path accounted oscilloscope measurement. Backside measurements also have potential pitfall. Many times, decoupling capacitors mounted directly underneath device, meaning that capacitor lands connect these vias directly with surface traces. These capacitors confound measurement, they like short circuit high-frequency current. make sure such capacitors short measurement, capacitors measurement site must removed. When measuring VCCO noise, measurement taken pair pins configured strong drivers logic logic This technique, when performed correctly, also show die-level noise. Measuring driven logic against driven logic shows degree rail collapse die. Measuring driven logic against ground shows amount ground bounce experiencing relative PDS. Since grounds common package levels device (excepting AGND MGTs), ground bounce measurement taken unused shows ground bounce supplies. Rail collapse measurements, other hand, only apply VCCO. make these measurements, oscilloscope should infinite persistence mode, acquire noise over long time period (many seconds minutes). design operates number different modes, utilizing different resources different amounts, these various conditions modes should operation while oscilloscope acquiring noise measurement. Noise measurements should made different VCC/GND pairs FPGA eliminate effects local noise phenomena. Figure shows instantaneous noise measurement taken VCCINT pins sample design. Figure shows infinite persistence noise measurement same design. Since infinite persistence measurement catches noise events over long period, obviously yields more relevant results.
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Design Verification
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Figure Instantaneous Measurement VCCO Supply, with Multiple Sending Patterns
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Figure Infinite Persistence Measurement Same Supply
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Design Verification This measurement represents peak-to-peak noise. greater than equal maximum ripple voltage specified datasheet (10% VCC), then bypassing network adequate. maximum voltage ripple allowed this particular supply, with nominal value 1.5V this, 150mV. scope shots show noise range From this measurement, clear that decoupling network adequate. however, measurement showed noise greater than VCC, would inadequate. have working, robust design, changes should made PDS. greater number capacitors, different capacitance values, different numbers various decoupling capacitor values will bring noise down. Having necessary information improve decoupling network requires additional measurements. Specifically, measurement noise power spectrum necessary determine frequencies where noise resides. There many ways this. spectrum analyzer works well does oscilloscope with math functionality. Alternatively, long sequence time-domain data captured from oscilloscope converted frequency domain using MATLAB other software supporting FFT. also possible basic feel frequency content noise simply looking timedomain waveform measuring individual periodicities present noise. Noise Spectrum Measurements spectrum analyzer frequency-domain instrument. shows frequency content voltage signal inputs. When used measure inadequate PDS, user exact frequencies where inadequate. Excessive noise certain frequency indicates frequency where impedance high transient current demands device. Armed with this information, designer modify accommodate transient current specific frequency. This accomplished either adding capacitors with resonant frequencies close frequency noise lowering impedance critical frequency through other means. noise spectrum measurement should taken same place peak-to-peak noise measurement directly underneath device, pair unused driven High Low. spectrum analyzer takes measurements through cable, rather than through active probe like oscilloscope. best ways attach cable measurements through connector tapped into power ground planes vicinity device. most cases this available. Another attach cable measurement noise power planes remove decoupling capacitor vicinity device, solder center conductor shield cable directly capacitor lands. Alternatively, probe station used. most cases, distinct bands noise fixed frequencies seen. These correspond clock frequency harmonics. height each band represents relative power. majority energy usually contained tight bands around harmonics, with power falling frequency increases.
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Design Verification Figure shows example noise spectrum measurement. screenshot spectrum analyzer measurement power supply noise VCCO, with multiple sending patterns MHz.
Figure Screenshot Spectrum Analyzer Measurement VCCO
noise bands correspond frequencies where FPGA demand current receiving from PDS. This could because there enough capacitance, because there enough capacitance parasitic inductance path separating capacitors from FPGA great. Whatever cause, impedance power supply this frequency high. Conversely, frequencies where there very little noise, impedance lower than needs solve these problems, bypassing network must modified. capacitor values, different quantities original values should chosen.
Step Optimum Bypassing Network Design (Optional)
cases where highly optimized needed, further measurements taken guide design carefully tailored decoupling network. network analyzer used measure impedance profile prototype PDS, giving output similar what discussed simulation section. network analyzer sweeps stimulus across range frequencies measures impedance each frequency. output impedance function frequency. Since spectrum analyzer gives output voltage function frequency, these measurements used together determine transient current function frequency.
From Spectrum Analyzer From Network Analyzer
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Other Concerns Causes Armed with understanding design's transient current requirements, designer make better choices. With maximum voltage ripple value from datasheet, value impedance needed frequencies determined. This yields target impedance function frequency. Given this, network capacitors designed accommodate transient current specific design. This six-step process lays closed-loop method designing verifying power distribution system. ensures adequate design.
Other Concerns Causes
this step-by-step method does yield design meeting required noise specifications, then other aspects system should analyzed possible changes.
Possibility Excessive Noise from Other Devices Board
When ground and/or power planes shared among many devices, often case, noise from inadequately decoupled device affect other devices. interfaces with inherently high transient current demands temporary periodic contention highcurrent drivers common cause; large microprocessors another. unacceptable amounts noise measured locally these devices, analysis should done local decoupling networks component.
Possibility Parasitic Inductance Planes, Vias, Connecting Traces
this case there enough capacitance bypassing network, much inductance path from capacitors FPGA. This could choice connecting trace solder land geometry, long path from capacitors FPGA, and/or current path power vias that traverse exceptionally thick stackup. case inadequate connecting trace capacitor land geometry, important keep mind loop inductance current path. vias bypass capacitor spaced millimeters from capacitor solder lands board, current loop area greater than needs (Figure 6a). Vias should placed directly against capacitor solder lands (Figure 6b). Never connect vias lands with section trace (Figure 6a). Other improvements geometry via-in-pad (where actually under solder land), shown, beside (where vias ends lands, rather astride them), Figure Double vias further improvement (Figure 6d). inductance path planes great, there parameters that changed; length electrical path, spreading inductance planes themselves. path length determined capacitor placement. Capacitors must placed close power/ground pairs device being bypassed. This especially important smallest capacitors network, since care been taken chose capacitors with parasitic inductance. There connecting low-inductance, high-frequency capacitor device through high-inductance path. Larger capacitors inherently have high parasitic self inductance allowing proximity device less important. spreading inductance planes controlled plane spacing dielectric constant material between them. section "Plane Inductance". When boards exceptionally thick (greater than mils mm), vias have higher parasitic inductance. these cases, following changes design should considered. first move VCC/GND plane sandwiches close surface FPGA second place highest frequency capacitors surface. Both changes together reduce parasitic inductance relevant current path.
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Conclusion
Possibility Signals Stronger Than Necessary
noise VCCO still high after making refinements PDS, interface power scaled back. This goes both outputs from FPGA inputs FPGA. some cases, excessive overshoot inputs FPGA reverse-bias clamp diodes IOBs. This large amounts noise into VCCO. this condition occurring, drive strength these interfaces should decreased, termination should used (both input output paths).
Possibility Signal Return Current Travelling Sub-Optimal Paths
Excessive noise caused signal return currents. every signal transmitted device into (and eventually into another device), there equal opposite current flowing from back into device's power/ground system. there low-impedance return current path available, less optimal, higher impedance path used. When this occurs, voltage changes induced PDS. This situation improved ensuring that every signal closely spaced fully intact return path. Various strategies could required including restricting signals only available routing layers, providing low-impedance paths currents travel between reference planes (decoupling capacitors specific locations PCB).
Conclusion
This application note overview important principles power distribution systems, followed step-by-step process designing PDS. This iterative method design, where designer first creates generic network, simulates refines then measures then refines again based measured results described. When this method fails give acceptable result, other possible contributors problem explored. Through this method, problems resolved.
References
Xilinx, Inc., RocketIO Transceiver User Guide, UG024 Larry Smith "Decoupling Capacitor Calculations CMOS Circuits," Proceedings EPEP Conference, November 1984 Xilinx, Inc., Virtex-II Platform FPGA User Guide UG002 Frederick Grover Ph.D. "Inductance Calculations: Working Formulas Tables", Nostrand Company, Inc. Fourth Avenue York 1946
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Appendix Glossary
Appendix Glossary
Land: section exposed metal surface where surface-mount devices soldered Network Analyzer: instrument used measure frequency-domain characteristics electrical networks. electrical characteristics power distribution systems often measured using network analyzer. Oscilloscope: instrument used show time-domain voltage signal. Power supply noise signal measured when establishing magnitude noise voltage power supply. Sandwich: pair planes stackup separated only dielectric material, signal layer in-between. most cases, these planes ground potential other plane carries power. Also known buried capacitance. Spectrum Analyzer: instrument used measure frequency content signal. Power supply noise signal measured when establishing characteristics power distribution system. Stackup: series layers often referred stackup. Multi-layered boards comprised alternating layers signal routing plane metal dielectric material. dielectric material also serves structural substrate. Via: vertical connection PCB, usually formed drilling hole through plating walls this hole with conductive material. Vias make electrical connections between different layers PCB. Vias represent impedance discontinuities when they signal path, represent additional parasitic inductance when they power distribution path (both undesirable). parasitic inductance formula shown Appendix Calculation Inductance. Voltage Ripple: Power supply noise often referred voltage ripple. maximum voltage ripple corresponds maximum amount power supply variation allowed part's absolute maximum ratings.
Appendix Calculation Inductance
inductance major contributor parasitic inductance capacitor mounting. dimensions largely determine parasitic inductance. Equation from Grover (Reference #4), used determine self-inductance single filled based length diameter. Dimensions inches nanohenries. 5.08 0.75 Example Equation
calculate inductance going from bottom surface board surface board, board finished thickness length: board finished thickness mils, diameter mils. There 1000 mils inch. 0.062 0.003 5.08 0.75 0.062 5.08 0.062 0.75 0.003 5.08 0.062 3.67 1.15
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Appendix SPICE Simulation Examples
This result self-inductance single via. self-inductance only part total inductance current loop part Since mutual inductance vias with opposing currents (power ground) effect total inductance, should taken into account when greater accuracy desired. mutual inductance closely spaced complementary vias lowers total inductance small amount.
Appendix SPICE Simulation Examples
This appendix demonstrates method used simulate decoupling capacitor networks SPICE. HSPICE techniques discussed here. Other variants SPICE dedicated simulation software also used. simulation referenced below purely illustrative purposes. Simulator details beyond scope this discussion left readers' investigation. HSPICE result included Figure schematic representation included Figure These capacitor networks represent capacitance parasitics 18-capacitor network. general capacitor array impedance calculation follows these steps: Formulate netlist L-C-R network Understand where input node output node located Apply stimulus input port analysis L-C-R network Measure input current well input voltage Formulate Plot result using scale ease viewing this approach, stimulus Analysis directive sweeps current waveform across prescribed frequency points. number frequency points decade commented appended HSPICE netlist. With current magnitude impedance calculated based V/I. Thus, main calculated variable voltage capacitor array positive node. other details complete SPICE decks: There bias resistor ground There small input resistor connecting source L-C-R network (this optional) Item necessary decrease simulation time. allows SPICE quickly calculate operating point circuit prior analysis. This accomplished providing SPICE path L-C-R network ground bias resistor). Item optional, convenient. provides component monitor input current L-C-R network. viewing simulated impedance result HSPICE, .net directive executed order that HSPICE calculates direct plotting.
HSPICE Netlist
HSPICE Netlist available Xilinx site:
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Appendix SPICE Simulation Examples
HSPICE Output
Figure shows HSPICE output: ZIN(MAG) using AWAVES graphical viewer.
Figure HSPICE Output
Schematic Circuit
Figure shows capacitor array with corresponding parasitic inductance resistance.
Figure Schematic Circuit
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Appendix Tools Design Simulation
Appendix Tools Design Simulation
Table lists some vendors tools design simulation.
Table Tools Design Simulation
Tool SIwave Specctraquest Power Integrity Speed 2000 Star HSPICE UCADESR3.exe Vendor Ansoft Cadence Sigrity Synopsys UltraCAD Website http://www.ansoft.com http://www.cadence.com http://www.sigrity.com http://www.synopsys.com http://www.ultracad.com
Revision History
following table shows revision history this document. Date 08/08/02 04/21/03 06/11/03 04/05/04 Version Initial Xilinx release. Updated smaller file size. Minor text changes clarity. Replaced Figure Figure Figure Added sections called "PCB Stackup Layer Order", "Capacitor Anti-Resonance", "Example Capacitor Layout" (the Figure part "Example Capacitor Layout" section). Removed references PSPICE. Made additional text changes clarity. Revised denominator FRIS equation shown page under "Capacitor Effective Frequency." Revision
02/28/05
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