Table Contents1. 7.1. 7.2. GENERAL DESCRIPTION FEATURES PARAMETERS BAL
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PRELIMINARY W971GG6JB BANKS DDR2 SDRAM
Table Contents1. 7.1. 7.2. GENERAL DESCRIPTION FEATURES PARAMETERS BALL CONFIGURATION BALL DESCRIPTION.7 BLOCK DIAGRAM FUNCTIONAL DESCRIPTION.9 Power-up Initialization Sequence Mode Register Extended Mode Registers Operation 7.2.1. 7.2.2. 7.2.2.1. 7.2.2.2. 7.2.2.3. 7.2.2.4. 7.2.3. 7.2.3.1. 7.2.3.2. 7.2.3.3. 7.2.4. 7.2.5. 7.2.5.1. 7.3. 7.3.1. 7.3.2. 7.3.3. 7.3.4. 7.3.5. 7.3.6. 7.3.7. 7.3.8. 7.3.9. 7.3.10. 7.3.11. 7.4. 7.4.1. Mode Register Command (MRS).10 Extend Mode Register Commands (EMRS) Extend Mode Register Command (1), (1).11 Enable/Disable.12 Extend Mode Register Command (2), (2).13 Extend Mode Register Command (3), (3).14 Off-Chip Driver (OCD) Impedance Adjustment Extended Mode Register Impedance Adjustment Impedance Adjust.16 Drive Mode On-Die Termination (ODT).18 related timings command update delay.18 Bank Activate Command.20 Read Command.20 Write Command Burst Read with Auto-precharge Command.21 Burst Write with Auto-precharge Command.21 Precharge Command Self Refresh Entry Command Self Refresh Exit Command.21 Refresh Command No-Operation Command Device Deselect Command.23 Posted
Command Function.20
Read Write access modes
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PRELIMINARY W971GG6JB
7.4.1.1. 7.4.2. 7.4.3. 7.4.4. 7.4.5. 7.5. 7.6. Examples posted operation.23 Burst mode operation.24 Burst read mode operation.25 Burst write mode operation Write data mask
Burst Interrupt Precharge operation.27 7.6.1. 7.6.2. Burst read operation followed precharge.27 Burst write operation followed precharge Burst read with Auto-precharge Burst write with Auto-precharge
7.7.
Auto-precharge operation 7.7.1. 7.7.2.
7.8. 7.9.
Refresh Operation.29 Power Down Mode.29 7.9.1. 7.9.2. Power Down Entry Power Down Exit.30 Input clock frequency change during precharge power down.30 OPERATION MODE Command Truth Table Clock Enable (CKE) Truth Table Synchronous Transitions Data Mask (DM) Truth Table.32 Function Truth Table Simplified Stated Diagram.36 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Operating Temperature Condition.37 Recommended Operating Conditions Electrical Characteristics Input Logic Level.38 Input Logic Level Capacitance Leakage Output Buffer Characteristics Characteristics 9.9.1. Characteristics -18/-25/-3 speed grades.40 Measurement Test Parameters Characteristics.43 9.11.1. 9.11.2. Characteristics Operating Condition speed grade Characteristics Operating Condition -25/-3 speed grade
7.10. 8.1. 8.2. 8.3. 8.4. 8.5. 9.1. 9.2. 9.3. 9.4. 9.5. 9.6. 9.7. 9.8. 9.9. 9.10. 9.11.
9.12 9.13 9.14.
Input Test Conditions Differential Input/Output Logic Levels Overshoot Undershoot Specification 9.14.1. Overshoot Undershoot Specification Address Control Pins:
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PRELIMINARY W971GG6JB
9.14.2. 10.1. 10.2. 10.3. 10.4. 10.5. 10.6. 10.7. 10.8. 10.9. 10.10. 10.11. 10.12. 10.13. 10.14. 10.15. 10.16. 10.17. 10.18. 10.19. 10.20. 10.21. 10.22. 10.23. Overshoot Undershoot Specification Clock, Data, Strobe Mask pin: Command Input Timing Timing Signals Timing Active/Standby Mode Timing Power Down Mode Timing mode switch entering power down mode Timing mode switch exiting power down mode.59 Data output (read) timing.60 Burst read operation: RL=5 (AL=2, CL=3, BL=4).60 Data input (write) timing.61 Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4).61 Seamless burst read operation: Seamless burst write operation: 4).62 Burst read interrupt timing: (CL=3, AL=0, BL=8).63 Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) Write operation with Data Mask: WL=3, AL=0, BL=4) Burst read operation followed precharge: RL=4 (AL=1, CL=3, BL=4, tRTP 2clks).65 Burst read operation followed precharge: RL=4 (AL=1, CL=3, BL=8, tRTP Burst read operation followed precharge: RL=5 (AL=2, CL=3, BL=4, tRTP Burst read operation followed precharge: RL=6 (AL=2, CL=4, BL=4, tRTP
TIMING WAVEFORMS
Burst read operation followed precharge: RL=4 (AL=0, CL=4, BL=8, tRTP>2clks) Burst write operation followed precharge: (RL-1) Burst write operation followed precharge: (RL-1) Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP 2clks).68
10.24. Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP>2clks) 10.25. Burst read with Auto-precharge followed activation same bank (tRC Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP 2clks) 10.26. Burst read with Auto-precharge followed activation same bank (tRP Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP 2clks) 10.27. 10.28. 10.29. 10.30. 10.31. 10.32. Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3.70 Burst write with Auto-precharge tRP): WL=4, WR=2, BL=4, tRP=3 Self Refresh Timing Active Power Down Mode Entry Exit Timing.72 Precharged Power Down Mode Entry Exit Timing.72 Clock frequency change precharge Power Down mode PACKAGE SPECIFICATION Package Outline WBGA-84 (8x12.5 ).74 REVISION HISTORY
Publication Release Date:Feb. 2009 Revision
2clks).65 2clks).66 2clks).66
PRELIMINARY W971GG6JB
GENERAL DESCRIPTION
W971GG6JB bits DDR2 SDRAM, organized 8,388,608 words banks bits. This device achieves high speed transfer rates 1066Mb/sec/pin (DDR2-1066) general applications. W971GG6JB sorted into following speed grades: -18, compliant DDR2-1066/CL7 specification, compliant DDR2-800/CL6 specification, compliant DDR2-667/CL5 specification. control address inputs synchronized with pair externally supplied differential clocks. Inputs latched cross point differential clocks (CLK rising falling). I/Os synchronized with single ended differential DQS- pair source synchronous fashion.
FEATURES
Power Supply: VDD, VDDQ Double Data Rate architecture: data transfers clock cycle Latency: Burst Length: Bi-directional, differential data strobes (DQS transmitted received with data Edge-aligned with Read data center-aligned with Write data aligns transitions with clock Differential clock inputs (CLK Data masks (DM) write data Commands entered each positive edge, data data mask referenced both edges Posted programmable additive latency supported make command data efficiency Read Latency Additive Latency plus Latency Off-Chip-Driver impedance adjustment (OCD) On-Die-Termination (ODT) better signal quality Auto-precharge operation read write bursts Auto Refresh Self Refresh modes Precharged Power Down Active Power Down Write Data Mask Write Latency Read Latency Interface: SSTL_18 Packaged WBGA Ball (8X12.5 using Lead free materials with RoHS compliant
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PRELIMINARY W971GG6JB
PARAMETERS
SPEED GRADE SYM. Bin(CL-tRCD-tRP) PARAMETER Min. Max. Min. Max. tCK(avg) DDR2-1066 7-7-7 1.875 1.875nS 3.75 13.125 13.125 53.125 DDR2-800 6-6-6 3.75 DDR2-667 5-5-5 3.75
Average clock period
Min. Max.
Min. Max.
tRCD tRAS IDD0 IDD1 IDD2Q IDD4R IDD4W IDD5B IDD6 Active Read/Write Command Delay Time Precharge Active Command Period Active Ref/Active Command Period Active Precharge Command Period Operating current Operation current (Single bank) Precharge quiet standby current Operating burst read current Operating burst write current Burst refresh current Self refresh current
Min. Max. Min. Min. Min. Min. Max. Max. Max. Max. Max. Max. Max.
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PRELIMINARY W971GG6JB
BALL CONFIGURATION
VSSQ UDQS VDDQ UDQS VSSQ DQ15 VDDQ VDDQ DQ10 VSSQ DQ13 VSSQ LDQS VDDQ LDQS VSSQ
DQ14 VSSQ VDDQ VDDQ DQ12 VSSQ DQ11 VSSQ
VDDQ VDDQ VSSQ
VDDQ VDDQ VSSQ
VDDL VREF
A10/AP
VSSDL
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PRELIMINARY W971GG6JB
BALL DESCRIPTION
BALL NUMBER
M8,M3,M7,N2,N8,N3 ,N7,P2,P8,P3,M2,P7
SYMBOL
FUNCTION
DESCRIPTION
Provide address active commands, column address Auto-precharge Read/Write commands select location memory array respective bank. address: A0-A12. Column address: A0-A9. (A10 used Auto-precharge) BA0-BA2 define which bank ACTIVE, READ, WRITE PRECHARGE command being applied. Bi-directional data bus. (registered HIGH) enables termination resistance internal DDR2 SDRAM. Data Strobe Lower Byte: Output with read data, input with write data source synchronous operation. Edge-aligned with read data, center-aligned with write data. LDQS corresponds data DQ0-DQ7. LDQS only used when differential data strobe mode enabled control (1)[A10 EMRS command]. Data Strobe Upper Byte: Output with read data, input with write data source synchronous operation. Edge-aligned with read data, center-aligned with write data. UDQS corresponds data DQ8-DQ15. UDQS only used when differential data strobe mode enabled control (1)[A10 EMRS command]. commands masked when registered
A0-A12
Address
L2,L3,L1 G8,G2,H7,H3,H1,H9 ,F1,F9,C8,C2,D7,D3, D1,D9,B1,B9
BA0-BA2 DQ0-DQ15
Bank Select Data Input Output Termination Control
LDQS, F7,E8 LDQS Data Strobe
UDQS, B7,A8 UDQS Data Strobe
Chip Select
HIGH. provides external bank selection systems with multiple ranks. considered part command code.
K7,L7,K3
Command Inputs
(along with define command being entered. input mask signal write data. Input data masked when sampled high coincident with that input data during Write access. sampled both edges DQS. Although pins input only, loading matches loading. differential clock inputs. address control input signals sampled crossing positive edge negative edge Output (read) data referenced crossings (both directions crossing). (registered HIGH) activates (registered LOW) deactivates clocking circuitry DDR2 SDRAM. VREF reference voltage inputs. Power Supply: 1.8V 0.1V. Ground. Power Supply: 1.8V 0.1V. Ground. Isolated device improved noise immunity. connection Ground. Power Supply: 1.8V 0.1V.
B3,F3
Input Data Mask
J8,K8
CLK,
Differential Clock Inputs
A1,E1,J9,M9,R1 A3,E3,J3,N1,P9 A9,C1,C3,C7,C9,E9, G1,G3,G7,G9 A7,B2,B8,D2,D8,E7, F2,F8,H2,H8 A2,E2,L1,R3,R7,R8
VREF VDDQ VSSQ VSSDL VDDL
Clock Enable Reference Voltage Power Supply Ground Power Supply Ground Connection Ground Power Supply
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
BLOCK DIAGRAM
Publication Release Date:Feb. 2009 Revision
DECODER DECODER DECODER DECODER
DECODER DECODER DECODER DECODER
PRELIMINARY W971GG6JB
FUNCTIONAL DESCRIPTION
7.1. Power-up Initialization Sequence
DDR2 SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. following sequence required Power-up Initialization. Apply power attempt maintain below VDDQ state (all other inputs undefined.) Either following sequence required Power-up. voltage ramp time must greater than from when ramps from min; during voltage ramp, |VDD -VDDQ| volts. VDD, VDDL VDDQ driven from single power converter output limited 0.95V VREF tracks VDDQ/2 VDDQ VREF must times Voltage levels I/Os outputs must less than VDDQ during voltage ramp time avoid DRAM latch-up. During ramping supply voltages, VDDL VDDQ must maintained applicable both levels until ramping supply voltages complete. Apply VDD/VDDL before same time VDDQ Apply VDDQ before same time VREF tracks VDDQ/2 VDDQ VREF must times. Start Clock maintain stable condition (min.). After stable power clock (CLK, apply Deselect take HIGH. Wait minimum then issue precharge command. Deselect applied during period. Issue EMRS command (2). issue EMRS command (2), provide BA0, HIGH BA1, BA2.) Issue EMRS command (3). issue EMRS command (3), provide HIGH BA1, BA2.) Issue EMRS enable DLL. issue Enable command, provide HIGH BA1, BA2. A9=A8=A7=LOW must used when issuing this command.) Issue Mode Register command reset. issue Reset command, provide HIGH BA2.) Issue precharge command. Issue more Auto Refresh commands. Issue command with initialize device operation. (i.e. program operating parameters without resetting DLL.) least clocks after step execute Calibration (Off Chip Driver impedance adjustment). calibration used, EMRS Calibration Default (A9=A8=A7=HIGH) followed EMRS exit Calibration Mode (A9=A8=A7=LOW) must issued with other operating parameters EMR(1). DDR2 SDRAM ready normal operation.
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
Notes:
guarantee off, VREF must valid level must applied pin. VREF must within with respect VDDQ/2 during supply ramp time. VDD/VDDL voltage ramp time must greater than from when ramps from min. VDDQ voltage ramp time from when achieved when VDDQ achieved VDDQ must greater than
Command
EMRS
ERMS
ERMS
400nS
tMRD Enable Reset
tMRD
tRFC
tRFC Cycle
tMRD
Follow Flow chart
tOIT CAL. Mode Exit
Default
7.2. Mode Register Extended Mode Registers Operation
application flexibility, burst length, burst type, Latency, reset function, write recovery time (WR) user defined variables must programmed with Mode Register (MRS) command. Additionally, disable function, driver impedance, additive Latency, Termination), single-ended strobe (off chip driver impedance adjustment) also user defined variables must programmed with Extended Mode Register (EMRS) command. Contents Mode Register (MR) Extended Mode Registers (1), altered re-executing EMRS Commands. Even user chooses modify only subset (1), variables, variables within addressed register must redefined when EMRS commands issued. MRS, EMRS Reset affect array contents, which mean re-initialization including those executed time after power-up without affecting array contents.
7.2.1.
Mode Register Command (MRS)
"L", "L", "L", "L", "L", "L", "L", Register Data) mode register stores data controlling various operating modes DDR2 SDRAM. programs Latency, burst length, burst sequence, test mode, reset, Write Recovery (WR) various vendor specific options make DDR2 SDRAM useful various applications. default value Mode Register after power-up defined, therefore Mode Register must programmed during initialization proper operation. DDR2 SDRAM should bank precharge state with already HIGH prior writing into mode register. mode register command cycle time (tMRD) required complete write operation mode register. mode register contents changed using same command clock cycle requirements during normal operation long banks precharge state. Publication Release Date:Feb. 2009 Revision
Figure
Initialization sequence after power-up
PRELIMINARY W971GG6JB
mode register divided into various fields depending functionality. Burst length defined A[2:0] with options burst lengths. burst length decodes compatible with SDRAM. Burst address sequence type defined Latency defined A[6:4]. DDR2 does support half clock latency mode. used test mode. used reset. must normal operation. Write recovery time defined A[11:9]. Refer table specific codes.
Address Field
Latency
Burst Length
Mode Register
Reset
Mode Normal Test
Burst Type Sequential Interleave
Burst Length
DDR2-667 (-3)
DDR2-800 (-25)
mode Active power down exit time Fast exit (use tXARD) Slow exit (use tXARDS)
Write recovery Auto-precharge Reserved
Latency Latency Reserved Reserved Reserved
DDR2-1066 (-18)
DDR2-667 (-3)
DDR2-800 (-25)
Note: (write recovery Auto-precharge) determined tCK(avg) determined tCK(avg) min. WR[cycles] tWR[nS] tCK(avg)[nS] where stands round mode register must programmed this value. This also used with determine tDAL.
7.2.2.
Extend Mode Register Commands (EMRS)
7.2.2.1. Extend Mode Register Command (1),
"L", "L", "L", "L", "H", Register data) extended mode register stores data enabling disabling DLL, output driver strength, additive latency, ODT, disable, program. default value extended mode register defined, therefore extended mode register must programmed during initialization proper operation. DDR2 SDRAM should bank precharge with already high prior writing into extended mode register (1). mode register command cycle time (tMRD) must satisfied complete write operation extended mode register (1). Extended mode register contents changed using same command clock cycle requirements during normal operation long banks precharge state. used enable disable. used enabling reduced strength output driver. A[5:3] determines additive latency, A[9:7] used control, used disable. used setting.
Figure
Mode Register (MRS)
Publication Release Date:Feb. 2009 Revision
DDR2-1066 (-18)
PRELIMINARY W971GG6JB
7.2.2.2. Enable/Disable must enabled normal operation. enable required during power-up initialization, upon returning normal operation after having disabled. automatically disabled when entering Self Refresh operation automatically re-enabled reset upon exit Self Refresh operation. time enabled (and subsequently reset), clock cycles must occur before Read command issued allow time internal clock synchronized with external clock. Failing wait synchronization occur result violation tDQSCK parameters
Address Field
Qoff
program
Additive Latency
O.I.C
Extended Mode Register
mode
(nominal) Disabled ohm*2
Enable Enable Disable
Additive Latency Latency Reserved
DDR2-/667/800 (-3/-25)
Qoff (Optional)*5 Output buffer enabled Output buffer disabled Enable Disable Strobe Function Matrix (DQS Enable) (Enable) (Disable) Hi-z
Output Driver Impedance Control Output driver impedance control Normal Reduced Driver size 100%
Notes: default RDQS disabled Optional DDR2-667. When Adjust mode issued, from previously value must applied. After setting default, calibration mode needs exited setting A9-A7 000. Refer section 7.2.3 detailed information.
Output disabled DQs, LDQS, LDQS UDQS, UDQS This feature used conjunction with DIMM measurements when IDDQ desired included.
Figure
Publication Release Date:Feb. 2009 Revision
DDR2-1066 (-18)
Driver impedance adjustment Calibration Program calibration mode exit; matain setting Drive Drive Adjust mode*3 Calibration default*4
PRELIMINARY W971GG6JB
7.2.2.3. Extend Mode Register Command (2),
"L", "L", "L", "L", "L", "H", Register data) extended mode register controls refresh related features. default value extended mode register defined, therefore extended mode register must programmed during initialization proper operation. DDR2 SDRAM should bank precharge state with already high prior writing into extended mode register (2). mode register command cycle time (tMRD) must satisfied complete write operation extended mode register (2). Mode register contents changed using same command clock cycle requirements during normal operation long banks precharge state.
Address Field
SELF
Extended Mode Register
High Temperature Self Refresh Rate Enable Disable Enable (Optional)
Note: rest bits reserved future bits except BA0, must programmed when setting extended mode register during initialization. When DRAM operated TCASE extended Self Refresh rate must enabled setting before Self Refresh mode entered.
Figure
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PRELIMINARY W971GG6JB
7.2.2.4. Extend Mode Register Command (3),
"L", "L", "L", "L", "H", "H", "L", Register data) function defined extended mode register (3). default value defined, therefore must programmed during initialization proper operation.
Note: bits EMR(3) except reserved future must when programming EMR(3).
Figure
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PRELIMINARY W971GG6JB
7.2.3. Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature flow chart Figure example sequence. Every calibration mode command should followed "OCD calibration mode exit" before other command being issued. should before entering impedance adjustment Termination (ODT) should carefully controlled depending system environment.
shoud programmed before entering impedance adjustment should carefully controlled depending system environment
Start EMRS: calibration mode exit
EMRS: Drive(1) &DQS High;
EMRS: Drive(0) &DQS Low; High
Test
Need Calibration
Test Need Calibration
EMRS: calibration mode exit
EMRS: calibration mode exit
EMRS: Enter Adjust Mode
EMRS: Enter Adjust Mode
BL=4 code input Inc,
BL=4 code input Inc,
EMRS: calibration mode exit
EMRS: calibration mode exit EMRS: calibration mode exit
Figure
Impedance Adjustment Flow Chart
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
7.2.3.1. Extended Mode Register Impedance Adjustment
impedance adjustment done using following EMRS mode. drive mode outputs driven DDR2 SDRAM. Drive mode, signals driven HIGH signals driven LOW. Drive mode, signals driven signals driven HIGH. adjust mode, operation code data must used. case calibration default, output driver characteristics have nominal impedance value Ohms during nominal temperature voltage conditions. applies only normal full strength output drive setting defined reduced strength set, default driver characteristics applicable. When calibration adjust mode used, default output driver characteristics applicable. After calibration completed driver strength default, subsequent EMRS commands intended adjust characteristics must specify A[9:7] '000' order maintain default calibrated value.
7.2.3.2. Impedance Adjust
adjust output driver impedance, controllers must issue ADJUST EMRS command along with burst code DDR2 SDRAM table this operation, Burst Length command before activating controllers must drive burst code same time. table means bits time time forth. driver output impedance adjusted DDR2 SDRAM simultaneously after calibration, DQS's given DDR2 SDRAM will adjusted same driver strength setting. maximum step count adjustment when limit reached, further increment decrement code effect. default setting step within step range. When Adjust mode command issued, from previously value must applied.
burst code inputs Other Combinations
Table
Table
Drive Mode Program
Operation calibration mode exit
Drive HIGH Drive HIGH Adjust mode calibration default
Adjust Mode Program Operation Pull-up driver strength Pull-down driver strength operation) operation) Increase step Decrease step Increase step Decrease step Increase step Increase step Decrease step Increase step Increase step Decrease step Decrease step Decrease step Reserved
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PRELIMINARY W971GG6JB
proper operation adjust mode, clocks tDS/tDH should shown Figure input data pattern adjustment, fixed order affected burst type (i.e., sequential interleave).
EMRS(1) EMRS
EMRS
DQS_in
DQ_in
adjust mode
calibration mode exit
7.2.3.3. Drive Mode
Drive mode, both Drive Drive (0), used controllers measure DDR2 SDRAM Driver impedance. this mode, outputs driven tOIT after "enter drive mode" command output drivers turned-off tOIT after "OCD calibration mode exit" command shown Figure
EMRS tOIT
high Drive (1), high Drive high Drive
Drive
Enter Drive mode
Figure
Figure
Adjust Mode
EMRS tOIT HI-Z
calibration mode exit
Drive Mode
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PRELIMINARY W971GG6JB
7.2.4. On-Die Termination (ODT)
On-Die Termination (ODT) feature DDR2 components that allows DRAM turn on/off termination resistance each UDQS/ UDQS LDQS/ LDQS signal control pin. UDQS LDQS terminated only when enabled address feature designed improve signal integrity memory channel allowing DRAM controller independently turn on/off termination resistance DRAM devices. function used active standby modes. turned supported Self Refresh mode. (Example timing waveforms refer 10.3, 10.4 Timing Active/Standby/Power Down Mode 10.5, 10.6 timing mode switch entering/exiting power down mode diagram Chapter
VDDQ VDDQ VDDQ
Rval1 DRAM Input Buffer Rval1
Rval2
Rval3 Input
Rval2
Rval3
VSSQ
VSSQ
VSSQ
Switch (sw1, sw2, sw3) enabled pin. Selection among sw1, sw2, determined "Rtt (nominal)" (1). Termination included DQs, DQS, pins.
7.2.5.
related timings
7.2.5.1. command update delay During normal operation value effective termination resistance changed with EMRS command. update setting done between tMOD,min tMOD,max, must remain HIGH entire duration tMOD window proper operation. timings shown following timing diagram.
Figure
Functional Representation
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PRELIMINARY W971GG6JB
EMRS
tMOD,max tAOFD tMOD,min
setting
Updating
setting
EMRS command directed EMR(1), which updates information EMR(1)[A6,A2], i.e. (Nominal). setting this diagram Register setting, what measured from outside.
However, prevent impedance glitch channel, following conditions must met. tAOFD must before issuing EMRS command. must remain entire duration tMOD window, until tMOD,max met. ready normal operation with setting, signal raised again turned ODT. Following timing diagram shows proper update procedure.
tAOFD tMOD,max tAOND
setting
EMRS command directed EMR(1), which updates information EMR(1)[A6,A2], i.e. (Nominal). setting this diagram what measured from outside.
Figure
update delay timing tMOD, measured from outside Publication Release Date:Feb. 2009 Revision
Figure
update delay timing tMOD
EMRS
setting
PRELIMINARY W971GG6JB
7.3. Command Function
7.3.1. Bank Activate Command
="L", ="L", ="H", ="H", BA0, BA1, BA2=Bank, address) Bank Activate command must applied before Read Write operation executed. Immediately after bank active command, DDR2 SDRAM accept read write command following clock cycle. Read/Write command issued bank that satisfied tRCDmin specification, then additive latency must programmed into device delay when Read/Write command internally issued device. additive latency value must chosen assure tRCDmin satisfied. Additive latencies supported. Once bank been activated must precharged before another Bank Activate command applied same bank. bank active precharge times defined tRAS tRP, respectively. minimum time interval between successive Bank Activate commands same bank determined cycle time device (tRC). minimum time interval between Bank Activate commands tRRD. order ensure that components with internal memory banks exceed instantaneous current supplying capability, certain restrictions operation banks must observed. There rules. restricting number sequential commands that issued another allowing more time precharge Precharge command. rules follows: Sequential Bank Activation Restriction: more than banks activated rolling tFAW window. Converting clocks done dividing tFAW[nS] tCK(avg)[ns], rounding next integer value. example rolling window, (tFAW tCK(avg) clocks, activate command issued clock more than three further activate commands issued between clock N+9. Precharge Allowance: Precharge command equal tnRP nCK, where tnRP tCK(avg) value single bank precharge.
Tn+1
Tn+2
Tn+3
Address
Bank Addr.
Bank Col. Addr.
Bank Addr.
delay time(tCCD) tRCD Additive Latency delay(AL)
delay time( tRRD) Command Bank Activate Bank Post Read
Bank Activate
7.3.2.
Read Command
="L", ="H", ="L", ="H", BA0, BA1, BA2=Bank, A10="L", A9=Column Address) READ command used initiate burst read access active row. value BA0, BA1, inputs selects bank, address inputs determine starting column address.
Figure
Bank activate command cycle: tRCD tRRD tCCD
Cycle time
tRC)
Publication Release Date:Feb. 2009 Revision
Bank Active
Internal delay
tRCDmin) Bank Col. Addr. Bank Addr. Bank Addr. Bank Addr.
Read Begins
Bank Post Read
Bank Precharge
Bank Precharge
Bank Activate
tRAS)
Bank Precharge time
tRP)
PRELIMINARY W971GG6JB
address input determines whether Auto-precharge used. Auto-precharge selected, being accessed will precharged READ burst; Auto-precharge selected, will remain open subsequent accesses.
7.3.3.
Write Command
="L", ="H", ="L", ="L", BA0, BA1, BA2=Bank, A10="L", A9=Column Address) WRITE command used initiate burst write access active row. value BA0, BA1, inputs selects bank, address inputs determine starting column address. address input determines whether Auto-precharge used. Auto-precharge selected, being accessed will precharged WRITE burst; Auto-precharge selected, will remain open subsequent accesses.
7.3.4.
Burst Read with Auto-precharge Command
="L", ="H", ="L", ="H", BA0, BA1, BA2=Bank, A10="H", A9=Column Address) HIGH when Read Command issued, Read with Auto-precharge function engaged. DDR2 SDRAM starts Auto-precharge operation rising edge which BL/2) cycles later than read with command tRAS(min) tRTP(min) satisfied.
7.3.5.
Burst Write with Auto-precharge Command
="L", ="H", ="L", ="L", BA0, BA1, BA2=Bank, A10="H", A9=Column Address) HIGH when Write Command issued, Write with Auto-precharge function engaged. DDR2 SDRAM automatically begins precharge operation after completion burst write plus write recovery time (WR) programmed mode register.
7.3.6.
Precharge Command
="L", ="L", ="H", ="L", BA0, BA1, BA2=Don't Care, A10="H", A12=Don't Care) Precharge command precharge banks simultaneously. Then banks switched idle state.
7.3.7.
Self Refresh Entry Command
="L", ="L", ="L", ="H", CKE="L", BA0, BA1, BA2, A12=Don't Care) Self Refresh command used retain data, even rest system powered down. When Self Refresh mode, DDR2 SDRAM retains data without external clocking. DDR2 SDRAM device built-in timer accommodate Self Refresh operation. must turned before issuing Self Refresh command, either driving using EMRS command. Once command registered, must held keep device Self Refresh mode. automatically disabled upon entering Self Refresh automatically enabled upon exiting Self Refresh. When DDR2 SDRAM entered Self Refresh mode, external signals except CKE, "Don't Care". clock internally disabled during self refresh operation save power. user change external clock frequency halt external clock clock after Self Refresh entry registered; however, clock must restarted stable before device exit self refresh operation.
7.3.8.
Self Refresh Exit Command
(CKE="H", ="H" CKE="H", ="L", ="H", ="H", ="H", BA0, BA1, BA2, A12=Don't Care)
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procedure exiting Self Refresh requires sequence commands. First, clock must stable prior going back HIGH. Once Self Refresh Exit registered, delay least tXSNR must satisfied before valid command issued device allow internal refresh progress. must remain HIGH entire Self Refresh exit period tXSRD proper operation except self refresh re-entry. Upon exit from Self Refresh, DDR2 SDRAM back into Self Refresh mode after waiting least tXSNR period issuing refresh command (refresh period tRFC). Deselect commands must registered each positive clock edge during Self Refresh exit interval tXSNR. should turned during tXSRD. Self Refresh mode introduces possibility that internally timed refresh event missed when raised exit from Self Refresh mode. Upon exit from Self Refresh, DDR2 SDRAM requires minimum extra auto refresh command before back into Self Refresh mode.
7.3.9.
Refresh Command
="L", ="L", ="L", ="H", CKE="H", BA0, BA1, BA2, A12=Don't Care) Refresh used during normal operation DDR2 SDRAM. This command persistent, must issued each time refresh required. refresh addressing generated internal refresh controller. This makes address bits "Don't Care" during Auto Refresh command. DDR2 SDRAM requires Auto Refresh cycles average periodic interval tREFI (max.). When refresh cycle completed, banks DDR2 SDRAM will precharged (idle) state. delay between auto refresh command (REF) next activate command subsequent auto refresh command must greater than equal auto refresh cycle time (tRFC). allow improved efficiency scheduling switching between tasks, some flexibility absolute refresh interval provided. maximum eight Refresh commands posted given DDR2 SDRAM, meaning that maximum absolute interval between Refresh command next Refresh command tREFI.
CLK/CLK
"HIGH"
Precharge
Figure
Refresh command Publication Release Date:Feb. 2009 Revision
tRFC
tRFC
PRELIMINARY W971GG6JB
7.3.10. No-Operation Command
"L", "H", "H", "H", CKE, BA0, BA1, BA2, Don't Care) No-Operation command simply performs operation (same command Device Deselect).
7.3.11. Device Deselect Command
"H", CKE, BA0, BA1, BA2, Don't Care) Device Deselect command disables command decoder that Address inputs ignored. This command similar No-Operation command.
7.4. Read Write access modes
DDR2 SDRAM provides fast column access operation. single Read Write Command will initiate serial read write operation successive clock cycles. boundary burst cycle strictly restricted specific segments page length. page length 2048 divided into uniquely addressable boundary segments depending burst length, burst, burst respectively. 4-bit 8-bit burst operation will occur entirely within groups beginning with column address supplied device during Read Write Command (CA0-CA9, CA11). second, third fourth access will also occur within this group segment. However, burst order function starting address, burst sequence. burst access must interrupt previous burst operation case setting. However, case setting, cases interrupt burst access allowed, reads interrupted read, other writes interrupted write with burst boundary respectively. minimum delay defined tCCD, minimum clocks read write cycles.
7.4.1.
Posted
Posted operation supported make command data efficient sustainable bandwidths DDR2 SDRAM. this operation, DDR2 SDRAM allows read write command issued immediately after bank activate command time during
-delay time, tRCD, period). command held time Additive Latency (AL) before issued inside device. Read Latency (RL) controlled Latency (CL). Therefore user chooses issue Read/Write command before tRCDmin, then (greater than must written into (1). Write Latency (WL) always defined (Read Latency where Read Latency defined Additive Latency plus Latency CL). Read Write operations using allow seamless bursts. (Example timing waveforms refer 10.11 10.12 seamless burst read/write operation diagram Chapter
7.4.1.1. Examples posted operation
Examples read followed write same bank where where shown Figures respectively.
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/CLK
Active A-Bank
Read A-Bank
Write A-Bank
WL=RL-1=4 AL=2 DQS/DQS tRCD RL=AL+CL=5
Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3
CL=3
where
CLK/CLK
Active A-Bank
DQS/DQS tRCD RL=AL+CL=3
Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3
where
7.4.2.
Burst mode operation
Burst mode operation used provide constant flow data memory locations (write cycle), from memory locations (read cycle). parameters that define burst mode will operate burst sequence burst length. DDR2 SDRAM supports burst modes only. burst mode, full interleave address ordering supported, however, sequential address ordering nibble based ease implementation. burst length programmable defined A[2:0]. burst type, either sequential interleaved, programmable defined [A3]. Seamless burst read write operations supported. Unlike DDR1 devices, interruption burst read writes cycle during mode operation prohibited. However case mode, interruption burst read write operation limited cases, reads interrupted read, writes interrupted write. (Example timing waveforms refer 10.13 10.14 Burst read write interrupt timing diagram Chapter
Figure
Figure
Example Read followed write same bank,
AL=0
Read A-Bank Write A-Bank
WL=RL-1=2 CL=3
Example Read followed write same bank,
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Therefore Burst Stop command supported DDR2 SDRAM devices.
Burst Length
Starting Address
7.4.3.
Burst read mode operation
Burst Read initiated with READ command. address inputs determine starting column address burst. delay from start command when data from first cell appears outputs equal value read latency (RL). data strobe output (DQS) driven clock cycle before valid data (DQ) driven onto data bus. first burst synchronized with rising edge data strobe (DQS). Each subsequent data-out appears phase with signal source synchronous manner. equal additive latency (AL) plus Latency (CL). defined Mode Register (MRS). defined Extended Mode Register (1). (Example timing waveforms refer 10.7 10.8 Data output (read) timing Burst read operation diagram Chapter
7.4.4.
Burst write mode operation
Burst Write initiated with WRITE command. address inputs determine starting column address burst. Write Latency (WL) defined Read Latency (RL) minus equal -1); number clocks delay that required from time write command registered clock edge associated first strobe. data strobe signal (DQS) should driven (preamble) nominally half clock prior first data burst cycle must applied pins first rising edge following preamble. tDQSS specification must satisfied each positive transition associated clock edge during write cycles. subsequent burst data issued successive edges until burst length completed, which burst. When burst finished, additional data supplied pins will ignored. Signal ignored after burst write operation complete. time from completion burst write bank precharge write recovery time (WR). (Example timing waveforms refer 10.9 10.10 Data input (write) timing Burst write operation diagram Chapter
Table
Burst Length Sequence
Sequential Addressing (decimal) Interleave Addressing (decimal)
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7.4.5. Write data mask
write data mask (DM) each data bits (DQ) will supported DDR2 SDRAM, consistent with implementation DDR1 SDRAM. identical timings write operations data bits, though used unidirectional manner, internally loaded identically data bits insure matched system timing. used during read cycles. (Example timing waveform refer 10.15 Write operation with Data Mask diagram Chapter
7.5. Burst Interrupt
Read Write burst interruption prohibited burst length only allowed burst length under following conditions: Read burst only interrupted another Read command. Read burst interruption Write Precharge Command prohibited. Write burst only interrupted another Write command. Write burst interruption Read Precharge Command prohibited. Read burst interrupt must occur exactly clocks after previous Read command. other Read burst interrupt timings prohibited. Write burst interrupt must occur exactly clocks after previous Write command. other Write burst interrupt timings prohibited. Read Write burst interruption allowed bank inside DDR2 SDRAM. Read Write burst with Auto-precharge enabled allowed interrupt. Read burst interruption allowed Read with Auto-precharge command. Write burst interruption allowed Write with Auto-precharge command. command timings referenced burst length mode register. They referenced actual burst. example below: Minimum Read Precharge timing BL/2 where burst length mode register actual burst (which shorter because interrupt). Minimum Write Precharge timing tWR, where starts with rising clock after un-interrupted burst from actual burst end.
(Example timing waveforms refer 10.13 10.14 Burst read write interrupt timing diagram Chapter
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7.6. Precharge operation
Precharge Command used precharge close bank that been activated. Precharge Command used precharge each bank independently banks simultaneously. Three address bits A10, used define which bank precharge when command issued. Table Bank selection precharge address bits HIGH HIGH HIGH HIGH HIGH Don't Care
7.6.1.
Burst read operation followed precharge
Minimum Read Precharge command spacing same bank BL/2 max(RTP, clks
earliest possible precharge, precharge command issued rising edge which "Additive Latency (AL) BL/2 max(RTP, clocks" after Read command. bank active (command) issued same bank after precharge time (tRP). precharge command cannot issued until tRAS satisfied. minimum Read Precharge spacing also satisfy minimum analog time from rising clock edge that initiates last 4-bit prefetch Read Precharge command. This time called tRTP (Read Precharge). this time from actual read after Read command) Precharge command. this time from clocks after Read Precharge command. (Example timing waveforms refer 10.16 10.20 Burst read operation followed precharge diagram Chapter
7.6.2.
Burst write operation followed precharge
Minimum Write Precharge Command spacing same bank BL/2 clks
write cycles, delay must satisfied from completion last burst write cycle until Precharge Command issued. This delay known write recovery time (tWR) referenced from completion burst write precharge command. Precharge command should issued prior delay. (Example timing waveforms refer 10.21 10.22 Burst write operation followed precharge diagram Chapter
7.7. Auto-precharge operation
Before active bank opened, active bank must precharged using either Precharge command Auto-precharge function. When Read Write command given DDR2 SDRAM, timing accepts extra address, column address A10, allow active bank automatically begin precharge earliest possible moment during burst read write cycle. when READ WRITE command issued, then normal Read Write burst operation executed bank remains active completion burst sequence.
HIGH HIGH HIGH HIGH Don't Care
HIGH HIGH HIGH HIGH Don't Care
Precharge Bank(s) Bank only Bank only Bank only Bank only Bank only Bank only Bank only Bank only Banks
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HIGH when Read Write command issued, then Auto-precharge function engaged. During Auto-precharge, Read command will execute normal with exception that active bank will begin precharge rising edge which Latency (CL) clock cycles before read burst. Auto-precharge also implemented during Write commands. precharge operation engaged Auto-precharge command will begin until last data burst write sequence properly stored memory array. This feature allows precharge operation partially completely hidden during burst read cycles (dependent upon Latency) thus improving system performance random data access. lockout circuit internally delays Precharge operation until array restore operation been completed (tRAS satisfied) that Auto-precharge command issued with read write command.
7.7.1.
Burst read with Auto-precharge
HIGH when Read Command issued, Read with Auto-precharge function engaged. DDR2 SDRAM starts Auto-precharge operation rising edge which BL/2) cycles later from Read with command tRAS(min) tRTP(min) satisfied. (Example timing waveform refer 10.23 Burst read operation with Auto-precharge diagram Chapter tRAS(min) satisfied edge, start point Auto-precharge operation will delayed until tRAS(min) satisfied. tRTP(min) satisfied edge, start point Auto-precharge operation will delayed until tRTP(min) satisfied. case internal precharge pushed tRTP, starts point where tRTP ends (not next rising clock edge after this event). minimum time from Read with Autoprecharge next Activate command becomes (tRTP tRP) (Example timing waveform refer 10.24 Burst read operation with Auto-precharge diagram Chapter 10.), time from Read with Auto-precharge next Activate command (tRTP tRP) where stands "rounded next integer". event internal precharge does start earlier than clocks after last 4-bit prefetch. bank active command issued same bank following conditions satisfied simultaneously. precharge time (tRP) been satisfied from clock which Auto-precharge begins. cycle time (tRC) from previous bank activation been satisfied. (Example timing waveforms refer 10.25 10.26 Burst read with Auto-precharge followed activation same bank (tRC Limit) (tRP Limit) diagram Chapter
7.7.2.
Burst write with Auto-precharge
HIGH when Write Command issued, Write with Auto-Precharge function engaged. DDR2 SDRAM automatically begins precharge operation after completion burst write plus write recovery time (WR) programmed mode register. bank undergoing Autoprecharge from completion write burst reactivated following conditions satisfied. data-in bank activate delay time tRP) been satisfied. cycle time (tRC) from previous bank activation been satisfied. (Example timing waveforms refer 10.27 10.28 Burst write with Auto-precharge (tRC Limit) tRP) diagram Chapter
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From Command Read
Command Precharge same Bank Read) Precharge
Read w/AP
Precharge same Bank Read w/AP) Precharge
Write
Precharge same Bank Write) Precharge
Write w/AP
Precharge same Bank Write w/AP) Precharge
Precharge
Precharge same Bank Precharge) Precharge
Precharge
Precharge Precharge
Notes: RTP[cycles] tRTP[nS] tCK(avg)[nS] where stands round given bank, precharge period should counted from latest precharge command, either bank precharge precharge all, issued that bank. precharge period satisfied after tRPall tCK) depending latest precharge command issued that bank.
7.8. Refresh Operation
DDR2 SDRAM requires refresh rows rolling interval. necessary refresh generated ways: explicit Auto Refresh commands internally timed Self Refresh mode. Self Refresh mode enters issuing Self Refresh command (CKE asserted "LOW") while banks idle state. device Self Refresh mode long held "LOW". case 8192 burst Auto Refresh commands, 8192 burst Auto Refresh commands must performed within before entering after exiting Self Refresh mode. case distributed Auto Refresh commands, distributed auto refresh commands must issued every last distributed Auto Refresh commands must performed within before entering self refresh mode. After exiting from Self Refresh mode, refresh operation must performed within Self Refresh mode, input/output buffers disable, resulting lower power dissipation (except buffer). (Example timing waveform refer 10.29 Self Refresh diagram Chapter
7.9. Power Down Mode
Power-down synchronously entered when registered LOW, along with Deselect command. allowed while mode register extended mode register command time, read write operation progress. allowed while other operation such activation, Precharge Auto-precharge Auto Refresh progress, power down specification will applied until finishing those operations. should locked state when power-down entered. Otherwise should reset after exiting power-down mode proper read operation.
Table
Precharge Auto-precharge clarifications
Minimum Delay between "From Command" Command" BL/2 max(RTP, BL/2 max(RTP, BL/2 max(RTP, BL/2 max(RTP, BL/2 BL/2 BL/2 BL/2 Unit clks clks clks clks clks clks clks clks clks clks clks clks Notes
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7.9.1. Power Down Entry
types Power Down Mode performed device: Precharge Power Down Mode Active Power Down Mode. power down occurs when banks idle, this mode referred Precharge Power Down; power down occurs when there active bank, this mode referred Active Power Down. Entering power down deactivates input output buffers, excluding CLK, CKE. Also disabled upon entering Precharge Power Down slow exit Active Power Down, kept enabled during fast exit Active Power Down. power down mode, stable clock signal must maintained inputs DDR2 SDRAM, should valid state other input signals "Don't Care". must maintained until tCKE been satisfied. Maximum power down duration limited refresh requirements device, which allows maximum tREFI maximum posting utilized immediately before entering power down. (Example timing waveforms refer 10.30 10.31 Active Precharged Power Down Mode Entry Exit diagram Chapter
7.9.2.
Power Down Exit
power-down state synchronously exited when registered HIGH (along with Deselect command). high must maintained until tCKE been satisfied. valid, executable command applied with power-down exit latency, tXP, tXARD, tXARDS, after goes HIGH. Power-down exit latency defined Characteristics table this data sheet.
7.10. Input clock frequency change during precharge power down
DDR2 SDRAM input clock frequency changed under following condition: DDR2 SDRAM precharged power down mode. must turned must logic level. minimum clocks must waited after goes before clock frequency change. SDRAM input clock frequency allowed change only within minimum maximum operating frequency specified particular speed grade. During input clock frequency change, must held stable levels. Once input clock frequency changed, stable clocks must provided DRAM before precharge power down exited must RESET command after precharge power down exit. Depending clock frequency additional EMRS command need issued appropriately etc. During re-lock period, must remain off. After lock time, DRAM ready operate with clock frequency. (Example timing waveform refer 10.32 Clock frequency change precharge Power Down mode diagram Chapter
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OPERATION MODE
8.1. Command Truth Table
COMMAND
Bank Activate Single Bank Precharge Precharge Banks Write Write with Autoprecharge Read Read with Autoprecharge (Extended) Mode Register Operation Device Deselect Refresh Self Refresh Entry Self Refresh Exit Power Down Mode Entry Power Down Mode Exit Notes: DDR2 SDRAM commands defined states rising edge clock.
Bank addresses [2:0] determine which bank operated upon. (E)MRS selects (Extended) Mode Register. Burst reads writes terminated interrupted. Burst Interrupt Chapter details. VREF must maintained during Self Refresh operation. Self Refresh Exit asynchronous. Power Down does perform refresh operations. duration Power Down Mode therefore limited refresh requirements outlined Chapter 7.9.
Previous Current Cycle Cycle
A9-A0
NOTES 1,2,3 1,2,3 1,2,3 1,2,3
Address Column Column Column Column Column Column Column Column
Code
1,4,5
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8.2. Clock Enable (CKE) Truth Table Synchronous Transitions
CURRENT STATE2 Previous Cycle (N-1)
Power Down Self Refresh Bank(s) Active Banks Idle REFRESH DESELECT DESELECT DESELECT Self Refresh Exit Active Power Down Entry Precharge Power Down Entry Self Refresh Entry DESELECT Power Down Exit Maintain Power Down
COMMAND Current Cycle
ACTION
NOTES
Maintain Power Down
Refer Command Truth Table
Notes: logic state clock edge (N-1) state previous clock edge. Current state state DDR2 SDRAM immediately prior clock edge COMMAND command registered clock edge ACTION result COMMAND (N). states sequences shown illegal reserved unless explicitly described elsewhere this document. Self Refresh Exit DESELECT commands must issued every clock edge occurring during tXSNR period. Read commands issued only after tXSRD (200 clocks) satisfied. Self Refresh mode only entered from Banks Idle state. Must legal command defined Command Truth Table. Valid commands Power Down Entry Exit DESELECT only. Valid commands Self Refresh Exit DESELECT only. Power Down Self Refresh entered while Read Write operations, (Extended) Mode Register operations Precharge operations progress. Chapter "Power Down Mode" Chapter 7.3.7/7.3.8 "Self Refresh Entry/Exit Command" detailed list restrictions. tCKEmin clocks means must registered three consecutive positive clock edges. must remain valid input level entire time takes achieve clocks registration. Thus, after transition, transition from valid level during time period tIH. state does affect states described this table. function available during Self Refresh. section 7.2.4. Power Down does perform refresh operations. duration Power Down Mode therefore limited refresh requirements outlined Chapter 7.9. must maintained HIGH while SDRAM calibration mode. means "don't care (including floating around VREF)" Self Refresh Power Down. However must driven high Power Down function enabled (Bit (1)). VREF must maintained during Self Refresh operation.
8.3. Data Mask (DM) Truth Table
FUNCTION
Write enable Write inhibit
Valid
NOTE
Note: Used mask write data, provided coincident with corresponding data.
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8.4. Function Truth Table
CURRENT STATE
Idle Banks Active Read Write
ADDRESS
Op-Code Op-Code Op-Code Op-Code
COMMAND
READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS
ACTION
Power down Power down ILLEGAL ILLEGAL activating Precharge/ Precharge banks Auto Refresh Self Refresh Mode/Extended register accessing Begin read Begin write ILLEGAL Precharge/ Precharge banks ILLEGAL ILLEGAL Continue burst Continue burst Burst interrupt ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst Continue burst ILLEGAL Burst interrupt ILLEGAL ILLEGAL ILLEGAL ILLEGAL
NOTES
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Function Truth Table, continued
CURRENT STATE
ADDRESS
Op-Code Op-Code Op-Code Op-Code
COMMAND
READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS
ACTION
Continue burst Continue burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst Continue burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after NOP-> Idle after ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after ILLEGAL ILLEGAL NOP-> active after tRCD NOP-> active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
NOTES
Read with Autoprecharge
Write with Autoprecharge
Precharge
Activating
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Function Truth Table, continued
CURRENT STATE
ADDRESS
Op-Code Op-Code Op-Code Op-Code
COMMAND
READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS
ACTION
NOP-> Bank active after NOP-> Bank active after ILLEGAL write ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Precharge after NOP-> Precharge after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after NOP-> Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after tMRD NOP-> Idle after tMRD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
NOTES
Write Recovering
Write Recovering with Autoprecharge
Refreshing
Mode Register Accessing
Notes:
This command issued other banks, depending state banks. banks must "IDLE". Read Write burst interruption prohibited burst length only allowed burst length Burst read/write only interrupted another read/write with burst boundary. other case read/write interrupt allowed. Remark: High level, level, High level (Don't Care), Valid data.
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8.5. Simplified Stated Diagram
calibration
Initialization Sequence
CKEL
Self Refreshing SELF Setting MR,EMR (E)MRS Idle banks Precharged CKEL CKEH CKEL Precharge Power Down CKEL CKEH Refreshing
Activating CKEL CKEL
Autoomatic Sequence Command Sequence
Active Power Down CKEH CKEL
Bank Active Write Write WRITA READA Read Write Read Read CKEL LOW, enter Power Down CKEH HIGH, exit Power Down CKEH HIGH, exit Self Refresh Activate WRITA Write with Auto-precharge READA Read (with Auto-precharge PREA Precharge (E)MRS (Extended) Mode Register SELF Enter Self Refresh Refresh
Writing
Reading
WRITA READA WRITA Writing with Auto-precharge PRE, PREA PRE, PREA PRE, PREA
READA
Reading with Auto-precharge
Precharging
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ELECTRICAL CHARACTERISTICS
9.1. Absolute Maximum Ratings
PARAMETER
Voltage relative Voltage VDDQ relative Voltage VDDL relative Voltage relative Storage Temperature
Notes:
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. When VDDQ VDDL less than 500mV; VREF equal less than 300mV. Storage temperature case surface temperature center/top side DRAM.
SYMBOL
VDDQ VDDL VIN, VOUT TSTG
RATING
-1.0 -0.5 -0.5 -0.5
UNIT
NOTES
9.2. Operating Temperature Condition
PARAMETER
Operating Temperature
Notes:
Operating Temperature case surface temperature center/top side DRAM. Supporting 85°C with full JEDEC specifications. Supporting being able extend with doubling Auto Refresh commands frequency period tREFI enter Self Refresh mode this high temperature range (2).
SYMBOL
TOPR
RATING
UNIT
NOTES
9.3. Recommended Operating Conditions
SYM.
VDDL VDDQ VREF
Notes:
There specific device supply voltage requirement SSTL_18 compliance. However under conditions VDDQ must than equal VDD. value VREF selected user provide optimum noise margin system. Typically value VREF expected about VDDQ transmitting device VREF expected track variations VDDQ. Peak peak noise VREF exceed +/-2 VREF(dc). transmitting device must track VREF receiving device. VDDQ tracks with VDD, VDDL tracks with VDD. parameters measured with VDD, VDDQ VDDDL tied together.
Supply Voltage Supply Voltage Supply Voltage Output Input Reference Voltage Termination Voltage (System)
TCASE
-18/-25/-3, VDD, VDDQ 1.8V 0.1V)
PARAMETER
MIN.
0.49 VDDQ VREF 0.04
TYP.
VDDQ VREF
MAX.
0.51 VDDQ VREF 0.04
UNIT
NOTES
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9.4. Electrical Characteristics
PARAMETER/CONDITION
effective impedance value EMRS(A6,A2)=0,1; effective impedance value EMRS(A6,A2)=1,0; effective impedance value EMRS(A6,A2)=1,1; Deviation with respect VDDQ/2
Rtt2(eff) Rtt3(eff)
Notes:
Test condition measurements. Optional DDR2-667.
Measurement Definition Rtt(eff): Apply (ac) (ac) test separately, then measure current I(VIH (ac)) I(VIL (ac)) respectively. (ac), (ac), VDDQ values defined SSTL_18.
Rtt(eff) (VIH(ac) VIL(ac)) /(I(VIHac) I(VILac))
Measurement Definition Measure voltage (VM) test (midpoint) with load.
VDDQ) 100%
9.5. Input Logic Level
PARAMETER
input logic HIGH input logic
9.6. Input Logic Level
PARAMETER
input logic HIGH input logic
TCASE
TCASE
-18/-25/-3, VDD, VDDQ 1.8V 0.1V)
SYM.
VIH(dc) VIL(dc)
MIN.
VREF 0.125 -0.3
MAX.
VDDQ VREF 0.125
-18/-25/-3, VDD, VDDQ 1.8V 0.1V)
SYM.
(ac) (ac)
MIN.
VREF 0.200
-25/-3 MAX.
VREF 0.200
MIN.
VREF 0.200 VSSQ VPEAK
MAX.
VDDQ VPEAK VREF 0.200
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TCASE
-18/-25/-3, VDD, VDDQ 1.8V 0.1V)
SYM.
Rtt1(eff)
MIN.
NOM.
MAX.
UNIT
NOTES
UNIT
UNIT
PRELIMINARY W971GG6JB
9.7. Capacitance
SYM.
CDCK CDIO
PARAMETER
Input Capacitance Input Capacitance delta input Capacitance, other input-only pins Input Capacitance delta, other input-only pins Input/output Capacitance, LDM, UDM, LDQS,
MIN.
MAX.
0.25 0.25
UNIT
LDQS UDQS, UDQS
Input/output Capacitance delta, LDM, UDM, LDQS, LDQS UDQS, UDQS
9.8. Leakage Output Buffer Characteristics
SYM.
PARAMETER
Input Leakage Current VDD)
MIN.
MAX.
UNIT
NOTES
IOH(dc) IOL(dc)
Notes:
Minimum Required Output Pull-up Maximum Required Output Pull-down Output Minimum Source Current Output Minimum Sink Current
other pins under test LDQS, LDQS UDQS, UDQS disabled turned off. VDDQ VOUT 1.42 (VOUT VDDQ)/IOH must less than values VOUT between VDDQ VDDQ 0.28V. VDDQ VOUT 0.28V. VOUT/IOL must less than values VOUT between 0.28V. values IOH(dc) IOL(dc) based conditions given Notes They used test drive current capability ensure VIHmin plus noise margin VILmax minus noise margin delivered SSTL_18 receiver.
Output Leakage Current (Output disabled, VOUT VDDQ)
0.603 -13.4 13.4
0.603
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9.9. Characteristics
9.9.1. Characteristics -18/-25/-3 speed grades
SYM. CONDITIONS MAX.
Operating Current Bank Active-Precharge tCK(IDD), tRC(IDD), tRAS tRASmin(IDD);
MAX.
UNIT MAX. NOTES
IDD0
IDD1
HIGH, HIGH between valid commands; Address control inputs SWITCHING; Databus inputs SWITCHING. Operating Current Bank Active-ReadPrecharge IOUT CL(IDD), tCK(IDD), tRC(IDD), tRAS tRASmin(IDD), tRCD tRCD(IDD); HIGH, HIGH between valid commands; Address control inputs SWITCHING; Data inputs SWITCHING. Precharge Power-Down Current banks idle; tCK(IDD); LOW; Other control address inputs STABLE; Data inputs FLOATING. Precharge Standby Current banks idle; tCK(IDD); HIGH, HIGH; Other control address inputs SWITCHING; Data inputs SWITCHING. Precharge Quiet Standby Current banks idle; tCK(IDD); HIGH, HIGH; Other control address inputs STABLE; Data inputs FLOATING. Active Power-Down Current Fast Exit banks open; MRS(12) tCK(IDD); LOW; Other control address inputs Slow Exit STABLE; MRS(12) Data inputs FLOATING. Active Standby Current banks open; tCK(IDD); tRAS tRASmax(IDD), tRP(IDD); HIGH, HIGH between valid commands; Other control address inputs SWITCHING; Data inputs SWITCHING.
1,2,3,4,5,
1,2,3,4,5,
IDD2P
1,2,3,4,5,
IDD2N
1,2,3,4,5,
IDD2Q
1,2,3,4,5,
1,2,3,4,5,
IDD3P
IDD3N
1,2,3,4,5,
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
Operating Burst Read Current banks open, Continuous burst reads, IOUT CL(IDD), tCK(IDD); tRAS tRASmax(IDD), tRP(IDD);
HIGH, HIGH between valid commands; Address inputs SWITCHING; Data inputs SWITCHING. Operating Burst Write Current banks open, Continuous burst writes; CL(IDD), tCK(IDD); tRAS tRASmax(IDD), tRP(IDD); HIGH, HIGH between valid commands; Address inputs SWITCHING; Data inputs SWITCHING. Burst Refresh Current tCK(IDD); Refresh command every tRFC(IDD) interval; HIGH, HIGH between valid commands; Other control address inputs SWITCHING; Data inputs SWITCHING. Self Refresh Current external clock off, Other control address inputs FLOATING; Data inputs FLOATING. Operating Bank Interleave Read Current bank interleaving reads, IOUT 0mA; CL(IDD), tRCD(IDD) tCK(IDD); tCK(IDD), tRC(IDD), tRRD tRRD(IDD), tRCD tRCD(IDD); HIGH, HIGH between valid commands; Address inputs STABLE during deselects; Data inputs SWITCHING.
IDD4R
1,2,3,4,5,
IDD4W
1,2,3,4,5,
IDD5B
1,2,3,4,5,
IDD6
1,2,3,4,5,
IDD7
Notes:
0.1V; VDDQ 0.1V. specifications tested after device properly initialized. Input slew rate specified Parametric Test Condition. parameters specified with disabled.
Data consists LDM, UDM, LDQS, LDQS UDQS UDQS Definitions (ac) (max) HIGH STABLE inputs stable HIGH level FLOATING inputs VREF VDDQ/2 SWITCHING inputs changing between HIGH every other clock cycle (once clocks) address control signals, inputs changing between HIGH every other data transfer (once clock) signals including masks strobes.
1,2,3,4,5,
(ac) (min)
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
9.10. Measurement Test Parameters
SPEED GRADE Bin(CL-tRCD-tRP)
CL(IDD) tCK(IDD) tRCD(IDD) tRP(IDD) tRC(IDD) tRASmin(IDD) tRASmax(IDD) tRRD(IDD)-2KB tFAW(IDD)-2KB tRFC(IDD)
DDR2-1066 (-18) 7-7-7
1.875 13.125 13.125 53.125 70000 127.5
DDR2-800 (-25) 6-6-6
70000 127.5
DDR2-667 (-3) 5-5-5
70000 127.5
UNIT
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
9.11. Characteristics
9.11.1. Characteristics Operating Condition speed grade
SPEED GRADE SYM. Bin(CL-tRCD-tRP) PARAMETER
tRCD tRAS tRFC tREFI tCCD Active Read/Write Command Delay Time Precharge Active Command Period Active Ref/Active Command Period Active Precharge Command Period Auto Refresh Active/Auto Refresh command period Average periodic refresh Interval
DDR2-1066 (-18) 7-7-7 MIN.
13.125 13.125 53.125 127.5
UNIT25 MAX.
70000
NOTES
4,23
85°C
TCASE
command delay
tCK(avg) CL=4 tCK(avg) Average clock period tCK(avg) CL=5 tCK(avg) CL=6 tCK(avg) CL=7 tCH(avg) tCL(avg) tDQSCK tDQSQ tCKE tRRD tFAW tDAL tWTR tRTP (base) (base) tIPW tDQSS tDSS tDSH tDQSH tDQSL Average clock high pulse width Average clock pulse width output access time from CLK/ output access time from DQS-DQ skew associated signals minimum high pulse width Active active command period page size Four Activate Window page size Write recovery time Auto-precharge write recovery precharge time Internal Write Read command delay Internal Read Precharge command delay Address control input setup time Address control input hold time Address control input pulse width each input latching rising transitions associated clock edges falling edge setup time falling edge hold time from input high pulse width input pulse width
TCASE
85°C 95°C
3.75 1.875 1.875 0.48 0.48 -350 -325
tCK(avg) tCK(avg)
0.52 0.52
30,31 30,31 30,31 30,31 30,31 30,31 8,23 9,23 4,23 10,26 11,26
tnRP -0.25 0.35 0.35
0.25
tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg)
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
Characteristics Operating Condition speed grade, continued
SPEED GRADE SYM. Bin(CL-tRCD-tRP) PARAMETER
tWPRE tWPST tRPRE tRPST tDS(base) tDH(base) tDIPW tLZ(DQS) tLZ(DQ) tQHS tXSNR tXSRD tXARD tXARDS tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tMRD tMOD tOIT tDELAY Write preamble Write postamble Read preamble Read postamble input setup time input hold time input pulse width each input Data-out high-impedance time from CLK/ DQS/ -low-impedance time from CLK/ low-impedance time from CLK/ Clock half pulse width Data hold skew factor DQ/DQS output hold time from Exit Self Refresh non-Read command Exit Self Refresh Read command Exit precharge power down command Exit active power down Read command Exit active power down Read command (slow exit, lower power) turn-on delay turn-on turn-on (Power Down mode) turn-off delay turn-off turn-off (Power Down mode) power down Entry Latency Power Down Exit Latency Mode Register command cycle time command update delay Drive mode output delay Minimum time clocks remain after asynchronously drops
DDR2-1066 (-18) 7-7-7 MIN.
0.35 0.35
UNITS25 MAX.
tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg)
NOTES
14,36 14,37 16,27,29 17,27,29
tAC,max tAC,max tAC,max
tAC,min tAC,min Min. (tCH(abs), tCL(abs))
15,35 15,35 15,35
tQHS tRFC tAC,min tAC,min tAC,min tAC,min tIS+tCK(avg)+tIH
tAC,max 2.575 tCK(avg) tAC,max+1 tAC,max tCK(avg) tAC,max
18,19 20,35
21,39 21,38,39
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
9.11.2. Characteristics Operating Condition -25/-3 speed grade
SPEED GRADE SYM. Bin(CL-tRCD-tRP) PARAMETER
tRCD tRAS tRFC tREFI tCCD Active Read/Write Command Delay Time Precharge Active Command Period Active Ref/Active Command Period Active Precharge Command Period Auto Refresh Active/Auto Refresh command period Average periodic refresh Interval
DDR2-800 (-25)
DDR2-667 (-3)
6-6-6 MIN.
127.5
5-5-5 MAX.
UNITS25 NOTES MAX.
4,23
MIN.
127.5
70000
70000
85°C
TCASE
command delay
tCK(avg) CL=3 tCK(avg) Average clock period tCK(avg) CL=4 tCK(avg) CL=5 tCK(avg) CL=6 tCH(avg) tCL(avg) tDQSCK tDQSQ tCKE tRRD tFAW tDAL tWTR tRTP (base) (base) tIPW tDQSS tDSS tDSH tDQSH tDQSL Average clock high pulse width Average clock pulse width output access time from CLK/ output access time from DQS-DQ skew associated signals minimum high pulse width Active active command period page size Four Activate Window page size Write recovery time
Auto-precharge write recovery precharge time tnRP Internal Write Read command delay Internal Read Precharge command delay Address control input setup time Address control input hold time Address control input pulse width each input latching rising transitions associated clock edges falling edge setup time falling edge hold time from input high pulse width input pulse width -0.25 0.35 0.35
TCASE
85°C 95°C
3.75 0.48 0.48 -400 -350
3.75
tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg)
0.52 0.52
30,31 30,31 30,31 30,31 30,31 30,31 8,23 9,23 4,23 10,26 11,26
0.48 0.48 -450 -400
0.52 0.52
tnRP -0.25 0.35 0.35
0.25
0.25
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
Characteristics Operating Condition -25/-3 speed grades, continued
SPEED GRADE SYM.
tWPRE tWPST tRPRE tRPST
DDR2-800 (-25)
DDR2-667 (-3)
Bin(CL-tRCD-tRP) PARAMETER
Write preamble Write postamble Read preamble Read postamble
6-6-6 MIN.
0.35 0.35
5-5-5 MAX.
UNITS25 NOTES MAX.
tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) 15,35 14,36 14,37 16,27,29 17,27,29
MIN.
0.35 0.35
tDS(base) input setup time tDH(base) input hold time tDIPW input pulse width each input Data-out high-impedance time from CLK/ DQS/ -low-impedance time from CLK/ tLZ(DQ) tQHS tXSNR tXSRD tXARD tXARDS tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tMRD tMOD tOIT tDELAY low-impedance time from CLK/ Clock half pulse width Data hold skew factor DQ/DQS output hold time from Exit Self Refresh non-Read command Exit Self Refresh Read command Exit precharge power down command Exit active power down Read command Exit active power down Read command (slow exit, lower power) turn-on delay turn-on turn-on (Power Down mode) turn-off delay turn-off turn-off (Power Down mode) power down Entry Latency Power Down Exit Latency Mode Register command cycle time command update delay Drive mode output delay Minimum time clocks remain after asynchronously drops
tAC,max
tAC,max
tLZ(DQS)
tAC,min tAC,min Min. (tCH(abs), tCL(abs))
tAC,max tAC,max
tAC,min tAC,min Min. (tCH(abs), tCL(abs))
tAC,max tAC,max
15,35 15,35
tQHS tRFC tAC,min tAC,min tAC,min tAC,min tIS+tCK(avg)+
tQHS tRFC tAC,min
tAC,max
tAC,max
18,19 20,35
tCK(avg) tCK(avg) tAC,min tAC,max tAC,max tAC,max tAC,min tAC,max
21,39 21,38,39
tCK(avg) tCK(avg) tAC,min tAC,max tAC,max
tIS+tCK(avg)+
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
Notes:
voltages referenced VSS. Tests timing, IDD, electrical characteristics conducted nominal reference/supply voltage levels, related specifications device operation guaranteed full voltage range specified. disabled measurements that ODT-specific. timing reference load:
VDDQ
Output
Timing reference point
VDDQ/2
Figure timing reference load
This minimum requirement. Minimum read precharge timing provided that tRTP tRAS(min) have been satisfied. refresh timing violated, data corruption occur data must re-written with valid data before valid READ executed. This optional feature. detailed information, please refer "operating temperature condition" chapter this data sheet. tCKE clocks means must registered three consecutive positive clock edges. must remain valid input level entire time takes achieve clocks registration. Thus, after transition, transition from valid level during time period tIH. minimum clocks *nCK) required irrespective operating frequency. tWTR least clocks nCK) independent operation frequency. Input waveform timing referenced from input signal crossing VIH(ac) level rising signal VIL(ac) falling signal applied device under test. Figure Input waveform timing referenced from input signal crossing VIL(dc) level rising signal VIH(dc) falling signal applied device under test. Figure
VDDQ VIH(ac) VIH(dc) VREF(dc) VIL(dc) VIL(ac)
Figure Differential input waveform timing
maximum limit tWPST parameter device limit. device operates with greater value this parameter, system performance (bus turnaround) will degrades accordingly.
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
tDQSQ: Consists data skew output pattern effects, p-channel n-channel variation output drivers well output Slew Rate mismatch between associated given cycle. tRPST point tRPRE begin point referenced specific voltage level specify when device output longer driving (tRPST), begins driving (tRPRE). Figure shows method calculate these points when device longer driving (tRPST), begins driving (tRPRE) measuring signal different voltages. actual voltage measurement points critical long calculation consistent. transitions occur same access time valid data transitions. These parameters referenced specific voltage level which specifies when device output longer driving (tHZ), begins driving (tLZ). Figure shows method calculate point when device longer driving (tHZ), begins driving (tLZ) measuring signal different voltages. actual voltage measurement points critical long calculation consistent. tLZ(DQ) refers DQ's tLZ(DQS) refers (UDQS, LDQS, UDQS LDQS each treated single-ended signal.
tRPST point
tRPRE begin point
tHZ,tRPST point
tLZ,tRPRE begin point
Figure Method calculating transitions endpoints
Input waveform timing with differential data strobe enabled MR[bit10]=0, referenced from input signal crossing VIH(ac) level differential data strobe crosspoint rising signal, from input signal crossing VIL(ac) level differential data strobe crosspoint falling signal applied device under test. DQS, signals must monotonic between Vil(dc)max Vih(dc)min. Figure Input waveform timing with differential data strobe enabled MR[bit10]=0, referenced from differential data strobe crosspoint input signal crossing VIH(dc) level falling signal from differential data strobe crosspoint input signal crossing VIL(dc) level rising signal applied device under test. DQS, signals must monotonic between Vil(dc)max Vih(dc)min. Figure
VDDQ VIH(ac) VIH(dc) VREF(dc) VIL(dc) VIL(ac)
Figure Differential input waveform timing
User choose which active power down exit timing (bit 12). tXARD expected used fast active power down exit timing. tXARDS expected used slow active power down exit timing.
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
Additive Latency. turn time when device leaves high impedance resistance begins turn turn time when resistance fully Both measure from tAOND, which interpreted differently speed bin. DDR2-667/800/1066, tAOND clock cycles after clock edge that registered first HIGH counting actual input clock edges. turn time when device starts turn resistance. turn time when high impedance. Both measured from tAOFD. DDR2-667/800: This interpreted differently speed bin. tCK(avg) assumed, tAOFD after second trailing clock edge counting from clock edge that registered first counting actual input clock edges. DDR2-1066: This interpreted tCK(avg) [nS] after second trailing clock edge counting from clock edge that registered first counting actual input clock edges. tAOFD 0.9375 [nS] 1.875 [nS]) after second trailing clock edge counting from clock edge that registered first counting actual input clock edges. clock frequency allowed change during Self Refresh mode precharge power-down mode. case clock frequency change during precharge power-down, specific procedure required described Chapter 7.10. these parameters, DDR2 SDRAM device characterized verified support tnPARAM RU{tPARAM tCK(avg)}, which clock cycles, assuming input clock jitter specifications satisfied. Examples: device will support tnRP RU{tRP tCK(avg)}, which clock cycles, input clock jitter specifications met. This means: DDR2-667 5-5-5, which 15nS, device will support tnRP RU{tRP tCK(avg)} i.e. long input clock jitter specifications met, Precharge command Active command Tm+5 valid even (Tm+5 less than 15nS input clock jitter. DDR2-1066 7-7-7, which 13.125 device will support tnRP RU{tRP tCK(avg)} i.e. long input clock jitter specifications met, Precharge command Active command Tm+7 valid even (Tm+7 less than 13.125 input clock jitter. tDAL [nCK] [nCK] tnRP [nCK] {tRP [pS] tCK(avg) [pS] where value programmed mode register stands round Example: DDR2-1066 7-7-7 tCK(avg) 1.875 with programmed nCK, tDAL RU{13.125 1.875 [nCK] [nCK] [nCK]. units, `tCK(avg)' `nCK', introduced DDR2-667, DDR2-800 DDR2-1066. Unit `tCK(avg)' represents actual tCK(avg) input clock under operation. Unit `nCK' represents clock cycle input clock, counting actual clock edges. Examples: DDR2-667/800: [nCK] means; Power Down exit registered Active command registered Tm+2, even (Tm+2 tCK(avg) tERR(2per),min. DDR2-1066: [nCK] means; Power Down exit registered Active command registered Tm+3, even (Tm+3 tCK(avg) tERR(3per),min. These parameters measured from command/address signal (CKE, ODT, BA0, etc.) transition edge respective clock signal (CLK/ crossing. spec values affected amount clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), setup hold relative clock signal crossing that latches command/address. That these parameters should whether clock jitter present not. violated, data corruption occur data must re-written with valid data before valid READ executed. These parameters measured from data strobe signal ((L/U)DQS/ crossing respective clock signal (CLK/ crossing. spec values affected amount clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), these relative clock signal crossing. That these parameters should whether clock jitter present not. These parameters measured from data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge respective data strobe signal ((L/U)DQS/ crossing.
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
Input clock jitter spec parameter. These parameters ones table below referred 'input clock jitter spec parameters'. jitter specified random jitter meeting Gaussian distribution.
Input clock-Jitter specifications parameters DDR2-667, DDR2-800 DDR2-1066
PARAMETER
Clock period jitter Clock period jitter during locking period Cycle cycle clock period Cycle cycle clock period jitter during locking period Cumulative error across cycles Cumulative error across cycles Cumulative error across cycles Cumulative error across cycles Cumulative error across cycles, inclusive Cumulative error across cycles, inclusive Duty cycle jitter
SYMBOL
tJIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6-10per) tERR(10-50per) tJIT(duty)
DDR2-667 MIN.
-125 -100 -250 -200 -175 -225 -250 -250 -350 -450 -125
DDR2-800 MIN.
-100 -200 -160 -150 -175 -200 -200 -300 -450 -100
DDR2-1066 MIN.
-180 -160 -132 -157 -175 -188 -250 -425
MAX.
MAX.
MAX.
UNIT
Definitions: tCK(avg) tCK(avg) calculated average clock period across consecutive cycle window.
tCK(avg)
where
tCH(avg) tCL(avg) tCH(avg) defined average HIGH pulse width, calculated across consecutive HIGH pulses.
tCH(avg) tCK(avg))
where
tCL(avg) defined average pulse width, calculated across consecutive pulses.
tCL(avg) tCK(avg))
where
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
tJIT(duty) tJIT(duty) defined cumulative jitter jitter. jitter largest deviation single from tCH(avg). jitter largest deviation single from tCL(avg).
tJIT(duty) Min/max {tJIT(CH), tJIT(CL)} where, tJIT(CH) {tCHi- tCH(avg) where 200} tJIT(CL) {tCLi- tCL(avg) where 200}
tJIT(per), tJIT(per,lck) tJIT(per) defined largest deviation single from tCK(avg).
tJIT(per) Min/max {tCKi- tCK(avg) where 200}
tJIT(per) defines single period jitter when already locked. tJIT(per,lck) uses same definition single period jitter, during locking period only. tJIT(per) tJIT(per,lck) guaranteed through final production testing.
tJIT(cc), tJIT(cc,lck) tJIT(cc) defined difference clock period between consecutive clock cycles:
tJIT(cc) |tCKi+1 tCKi|
tJIT(cc) defines cycle cycle jitter when already locked. tJIT(cc,lck) uses same definition cycle cycle jitter, during locking period only. tJIT(cc) tJIT(cc,lck) guaranteed through final production testing.
tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) tERR (11-50per) tERR defined cumulative error across multiple consecutive cycles from tCK(avg).
tERR(nper) tCK(avg)
Where tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6 10per) tERR(11 50per)
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
These parameters specified their average values, however understood that following relationship between average timing absolute instantaneous timing holds times. (Min SPEC values used calculations table below.)
PARAMETER
Absolute clock period Absolute clock HIGH pulse width
SYMBOL
tCK(abs) tCH(abs)
tCK(avg),min tJIT(per),min tCH(avg),min tCK(avg),min tJIT(duty),min tCL(avg),min tCK(avg),min tJIT(duty),min
tCK(avg),max tJIT(per),max tCH(avg),max tCK(avg),max tJIT(duty),max tCL(avg),max tCK(avg),max tJIT(duty),max
UNIT
Absolute clock pulse width
tCL(abs)
Examples: DDR2-667, tCH(abs),min 0.48 3000 1315 DDR2-1066, tCH(abs),min 0.48 1875 minimum absolute half period actual input clock. input parameter input specification parameter. used conjunction with tQHS derive DRAM output timing tQH. value used calculation determined following equation; tCH(abs), tCL(abs) where, tCH(abs) minimum actual instantaneous clock HIGH time; tCL(abs) minimum actual instantaneous clock time; tQHS accounts for: pulse duration distortion on-chip clock circuits, which represents well actual input transferred output; worst case push-out transition followed worst case pull-in next transition, both which independent each other, data skew, output pattern effects, p-channel nchannel variation output drivers tQHS, where: minimum absolute half period actual input clock; tQHS specification value under column. {The less half-pulse width distortion present, larger value larger valid data will be.} Examples: system provides 1315 into DDR2-667 SDRAM, DRAM provides minimum. system provides 1420 into DDR2-667 SDRAM, DRAM provides 1080 minimum. system provides into DDR2-1066 SDRAM, DRAM provides minimum. system provides into DDR2-1066 SDRAM, DRAM provides minimum. When device operated with input clock jitter, this parameter needs derated actual tERR(6-10per) input clock. (output deratings relative SDRAM input clock.) Examples: measured jitter into DDR2-667 SDRAM tERR(6-10per),min tERR(6-10per),max then tDQSCK,min(derated) tDQSCK,min tERR(6-10per),max tDQSCK,max(derated) tDQSCK,max tERR(6-10per),min Similarly, tLZ(DQ) DDR2-667 derates tLZ(DQ),min(derated) 1193 tLZ(DQ),max(derated) (Caution min/max usage!) measured jitter into DDR2-1066 SDRAM tERR(6-10per),min tERR(6-10per),max then tDQSCK,min(derated) tDQSCK,min tERR(6-10per),max tDQSCK,max(derated) tDQSCK,max tERR(6-10per),min Similarly, tLZ(DQ) DDR2-1066 derates tLZ(DQ),min(derated) tLZ(DQ),max(derated) (Caution min/max usage!)
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
When device operated with input clock jitter, this parameter needs derated actual tJIT(per) input clock. (output deratings relative SDRAM input clock.) Examples: measured jitter into DDR2-667 SDRAM tJIT(per),min tJIT(per),max then tRPRE,min(derated) tRPRE,min tJIT(per),min tCK(avg) 2178 tRPRE,max(derated) tRPRE,max tJIT(per),max tCK(avg) 2843 (Caution min/max usage!) measured jitter into DDR2-1066 SDRAM tJIT(per),min tJIT(per),max then tRPRE,min(derated) tRPRE,min tJIT(per),min tCK(avg) 1615.5 tRPRE,max(derated) tRPRE,max tJIT(per),max tCK(avg) 2125.5 (Caution min/max usage!) When device operated with input clock jitter, this parameter needs derated actual tJIT(duty) input clock. (output deratings relative SDRAM input clock.) Examples: measured jitter into DDR2-667 SDRAM tJIT(duty),min tJIT(duty),max then tRPST,min(derated) tRPST,min tJIT(duty),min tCK(avg) tRPST,max(derated) tRPST,max tJIT(duty),max tCK(avg) 1592 (Caution min/max usage!) measured jitter into DDR2-1066 SDRAM tJIT(duty),min tJIT(duty),max then tRPST,min(derated) tRPST,min tJIT(duty),min tCK(avg) tRPST,max(derated) tRPST,max tJIT(duty),max tCK(avg) 1188 (Caution min/max usage!) When device operated with input clock jitter, this parameter needs derated -tJIT(duty),max tERR(610per),max tJIT(duty),min tERR(6-10per),min actual input clock. (output deratings relative SDRAM input clock.) Examples: measured jitter into DDR2-667 SDRAM tERR(6-10per),min tERR(6-10per),max tJIT(duty),min tJIT(duty),max then tAOF,min(derated) tAOF,min tJIT(duty),max tERR(6-10per),max tAOF,max(derated) tAOF,max tJIT(duty),min tERR(6-10per),min 1050 1428 (Caution min/max usage!) measured jitter into DDR2-1066 SDRAM tERR(6-10per),min tERR(6-10per),max tJIT(duty),min tJIT(duty),max then tAOF,min(derated) tAOF,min tJIT(duty),max tERR(6-10per),max tAOF,max(derated) tAOF,max tJIT(duty),min tERR(6-10per),min 1218 (Caution min/max usage!) tAOFD DDR2-667/800/1066, clock assumes tCH(avg), average input clock HIGH pulse width relative tCK(avg). tAOF,min tAOF,max should each derated same amount actual amount tCH(avg) offset present DRAM input with respect 0.5. Example: input clock worst case tCH(avg) 0.48, tAOF,min should derated subtracting 0.02 tCK(avg) from whereas input clock worst case tCH(avg) 0.52, tAOF,max should derated adding 0.02 tCK(avg) Therefore, have; tAOF,min(derated) tAC,min [0.5 Min(0.5, tCH(avg),min)] tCK(avg) tAOF,max(derated) tAC,max [Max(0.5, tCH(avg),max) 0.5] tCK(avg) tAOF,min(derated) Min(tAC,min, tAC,min [0.5 tCH(avg),min] tCK(avg)) tAOF,max(derated) Max(tAC,max, tAC,max [tCH(avg),max 0.5] tCK(avg)) where tCH(avg),min tCH(avg),max minimum maximum tCH(avg) actually measured DRAM input balls. Note that these deratings addition tAOF derating input clock jitter, i.e. tJIT(duty) tERR(6-10per). However values used equations shown above from timing parameter table derated. Thus final derated values tAOF are; tAOF,min(derated_final) tAOF,min(derated) tJIT(duty),max tERR(6-10per),max tAOF,max(derated_final) tAOF,max(derated) tJIT(duty),min tERR(6-10per),min
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
9.12 Input Test Conditions
CONDITION
Input reference voltage Input signal maximum peak peak swing Input signal minimum slew rate
Notes:
Input waveform timing referenced input signal crossing through VIH/IL(ac) level applied device under test. input signal minimum slew rate maintained over range from VREF VIH(ac) rising edges range from VREF VIL(ac) falling edges shown below figure. timings referenced with input waveforms switching from VIL(ac) VIH(ac) positive transitions VIH(ac) VIL(ac) negative transitions
9.13 Differential Input/Output Logic Levels
PARAMETER
differential input voltage differential cross point input voltage differential cross point output voltage
Notes:
(ac) specifies input differential voltage |VTR -VCP required switching, where true input signal (such CLK, LDQS UDQS) complementary input signal (such LDQS UDQS minimum value equal (ac) (ac). typical value (ac) expected about VDDQ transmitting device (ac) expected track variations VDDQ. (ac) indicates voltage which differential input signals must cross. typical value (ac) expected about VDDQ transmitting device (ac) expected track variations VDDQ. (ac) indicates voltage which differential output signals must cross.
VSWING(MAX)
Falling Slew
Rising Slew
Figure
input test signal Differential signal levels waveform
VREF VIL(ac)
TCASE
-18/-25/-3, VDD, VDDQ 1.8V 0.1V)
TCASE
-18/-25/-3, VDD, VDDQ 1.8V 0.1V)
SYMBOL
VALUE
UNIT
NOTES
VREF VSWING(MAX) SLEW
VDDQ
V/nS
SYM.
MIN.
VDDQ 0.175 VDDQ 0.125
MAX.
VDDQ VDDQ 0.175 VDDQ 0.125
UNIT
NOTES
(ac) (ac) (ac)
VDDQ VIH(ac) VIH(dc) VREF VIL(dc) VIL(ac) VIH(ac) VREF
VSSQ Crossing point VDDQ
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
9.14. Overshoot Undershoot Specification
9.14.1. Overshoot Undershoot Specification Address Control Pins:
Applies A0-A12, BA0-BA2, /CS, /RAS, /CAS, /WE, CKE,
PARAMETER
0.66 0.66
UNIT
Maximum peak amplitude allowed overshoot area Maximum peak amplitude allowed undershoot area Maximum overshoot area above Maximum undershoot area below
V-nS V-nS
9.14.2. Overshoot Undershoot Specification Clock, Data, Strobe Mask pin:
Applies LDQS, /LDQS, UDQS, /UDQS, LDM, UDM, CLK, /CLK
PARAMETER
0.19 0.19
0.23 0.23
0.23 0.23
UNIT
Maximum peak amplitude allowed overshoot area Maximum peak amplitude allowed undershoot area Maximum overshoot area above VDDQ Maximum undershoot area below VSSQ
V-nS V-nS
Maximum Amplitude Overshoot Area
VDD/VDDQ Volts VSS/VSSQ
Maximum Amplitude Time (nS)
Undershoot Area
Figure
overshoot undershoot definition
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
TIMING WAVEFORMS
10.1. Command Input Timing
A0~A12 BA0,1
Refer Command Truth Table
10.2. Timing Signals
VIH(AC) VIL(AC)
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
10.3. Timing Active/Standby Mode
VIH(ac)
tAOND
VIL(ac)
tAOFD Internal Term Res. tAON(min) tAON(max)
tAOF(min) tAOF(max)
10.4. Timing Power Down Mode
VIH(ac)
VIL(ac)
tAOFPD(max) tAOFPD(min) Internal Term Res. tAONPD(min) tAONPD(max)
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
10.5. Timing mode switch entering power down mode
tANPD Entering Slow Exit Active Power Down Precharge Power Down
IL(ac)
Internal
Term Res.
tAOFD
Active Standby ings applied
IL(ac)
Internal
Term Res.
FPD(max)
Power Down ings applied
Internal
Term Res.
Active Standby ings applied
Internal
Term Res.
AONPD(m
Power Down ings applied
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
10.6. Timing mode switch exiting power down mode
AXPD
IH(ac)
Exiting from Slow Active Power Down Precharge Power Down Active Standby ings applied Internal
Term Res.
Power Down ings applied Internal
Term Res.
(ac)
AOFPD(m
IH(ac)
Active Standby ings applied
Internal
Term Res.
(ac)
tAON
Power Down ings applied
Internal
Term Res.
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
10.7. Data output (read) timing
tRPRE tRPST tDQSQmax tDQSQmax
10.8. Burst read operation: RL=5 (AL=2, CL=3, BL=4)
CLK/CLK
Posted READ
tDQSCK
DQS, DQ's
Dout Dout Dout Dout
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
10.9. Data input (write) timing
tDQSH tWPRE
VIH(ac) VIL(ac)
tDQSL
tWPST
VIH(dc) VIL(dc)
DMin
VIH(ac) DMin VIL(ac)
DMin
VIH(dc) DMin VIL(dc)
10.10. Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4)
Posted WRITE
Completion Burst Write
Precharge
Case with tDQSS(max)
tDQSS
tDSS tDQSS
tDSS
Case with tDQSS(min)
tDQSS tDSH
tDQSS tDSH
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
10.11. Seamless burst read operation:
CLK/CLK
Post READ
Post READ
DQS, DQ's DOUT DOUT DOUT DOUT DOUT DOUT DOUT
Note:
seamless burst read operation supported enabling read command every other clock operation, every clock operation. This operation allowed regardless same different banks long banks activated.
10.12. Seamless burst write operation:
CLK/CLK
Post WRITE
Post WRITE
DQS,
DQ's
Note:
seamless burst write operation supported enabling write command every other clock operation, every four clocks operation. This operation allowed regardless same different banks long banks activated.
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
10.13. Burst read interrupt timing: (CL=3, AL=0, BL=8)
CLK/CLK
READ
READ
DQS,
DQ's
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
10.14. Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8)
CLK/CLK
Write
Write
DQS,
DQ's
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
10.15. Write operation with Data Mask: WL=3, AL=0, BL=4)
CMDMAND rite
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
10.16. Burst read operation followed precharge: RL=4 (AL=1, CL=3, BL=4, tRTP 2clks)
CLK/CLK
AL+BL/2 clks
DQS,
DQ's tRAS tRTP
Dout Dout Dout Dout
10.17. Burst read operation followed precharge: RL=4 (AL=1, CL=3, BL=8, tRTP 2clks)
CLK/CLK
Post READ
BL/2 clks
Precharge
DQS,
DQ's
Dout Dout A1Dout A2Dout Dout Dout Dout A6Dout
tRTP
first 4-bit prefetch
second 4-bit prefetch
Post READ
Precharge
Bank Activate
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
10.18. Burst read operation followed precharge: RL=5 (AL=2, CL=3, BL=4, tRTP 2clks)
CLK/CLK
BL/2 clks
DQS,
DQ's tRAS
Dout Dout Dout Dout
tRTP
10.19. Burst read operation followed precharge: RL=6 (AL=2, CL=4, BL=4, tRTP 2clks)
CLK/CLK
Post READA
BL/2 clks
Precharge
DQS,
DQ's tRAS tRTP
Publication Release Date:Feb. 2009 Revision
Post READ
Precharge
Bank Activate
Bank Activate
Dout Dout Dout Dout
PRELIMINARY W971GG6JB
10.20. Burst read operation followed precharge: RL=4 (AL=0, CL=4, BL=8, tRTP>2clks)
CLK/CLK
Post READ
Precharge
Bank Activate
BL/2 max(RTP, clks
DQS,
DQ's tRAS tRTP
Dout Dout Dout Dout Dout
first 4-bit prefetch
second 4-bit prefetch
10.21. Burst write operation followed precharge: (RL-1)
CLK/CLK
Post WRITE
Completion Burst Write
DQS,
DQ's
Publication Release Date:Feb. 2009 Revision
Dout Dout Dout
Precharge
PRELIMINARY W971GG6JB
10.22. Burst write operation followed precharge: (RL-1)
CLK/CLK
Posted WRITE
Precharge
Completion Burst Write
DQS, DQ's
CLK/CLK
Post READA
BL/2 clks
Bank Activate
DQS,
DQ's
Dout Dout A1Dout A2Dout Dout Dout Dout A6Dout
tRTP Precharge begins here
first 4-bit prefetch
second 4-bit prefetch
tRTP
Publication Release Date:Feb. 2009 Revision
10.23. Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP 2clks)
PRELIMINARY W971GG6JB
10.24. Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP>2clks)
CLK/CLK
Post READA
tRTP
Bank Activate
DQS,
DQ's
4-bit prefetch
10.25. Burst read with Auto-precharge followed activation same bank (tRC Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP 2clks)
CLK/CLK
Post READA
tRAS(min)
Auto-precharge Begins
DQS,
DQ's
Dout Dout Dout Dout
Publication Release Date:Feb. 2009 Revision
Dout Dout Dout Dout
tRTP Precharge begins here
Bank Activate
PRELIMINARY W971GG6JB
10.26. Burst read with Auto-precharge followed activation same bank (tRP Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP 2clks)
CLK/CLK
Post READA
tRAS(min) Auto-precharge Begins
DQS/DQS
DQ's
Dout Dout Dout Dout
10.27. Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3
CLK/CLK
Post Bank
DQS,
Completion Burst Write Auto-precharge Begins
DQ's
Publication Release Date:Feb. 2009 Revision
Bank Activate
Bank Activate
PRELIMINARY W971GG6JB
10.28. Burst write with Auto-precharge tRP): WL=4, WR=2, BL=4, tRP=3
CLK/CLK
Post Bank
Bank Activate
DQS,
Completion Burst Write Auto-precharge Begins
DQ's
10.29. Self Refresh Timing
VIL(ac)
VIH(ac)
tAOFD
VIL(ac)
VIH(ac) VIL(ac)
Self Refresh
VIH(dc) VIL(dc)
Non-Read Command
Publication Release Date:Feb. 2009 Revision
tXSNR tXSRD
Read Command
PRELIMINARY W971GG6JB
10.30. Active Power Down Mode Entry Exit Timing
CLK/CLK Tn+1 Tn+2
Activate
Valid Command
tXARD tXARDS
Active Power Down Entry
Active Power Down Exit
10.31. Precharged Power Down Mode Entry Exit Timing
CLK/CLK Tn+1 Tn+2
Precharge
Valid Command
Precharge Power Down Entry
Precharge Power Down Exit
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
10.32. Clock frequency change precharge Power Down mode
RESET
TX+1
TY+1
TY+2
TY+3
TY+4
Valid
Clocks
tAOFD
Frequency change Occurs here
during RESET
Minimum clocks required before changing frequency
Stable clock before power down exit
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
PACKAGE SPECIFICATION
Package Outline WBGA-84 (8x12.5 mm2)
index
index
Seating plane DIMENSION (MM) MIN. NOM. MAX. -0.30 0.40 12.40 7.90 -12.50 8.00 11.2 BSC. 6.40 BSC. 0.80 BSC. 0.80 BSC. -1.20 0.40 0.50 12.60 8.10
SYMBOL
-0.1
0.15 -0.2
Publication Release Date:Feb. 2009 Revision
PRELIMINARY W971GG6JB
REVISION HISTORY
VERSION
DATE
Feb. 2009
PAGE
DESCRIPTION
Create preliminary data sheet
Important Notice
Winbond products designed, intended, authorized warranted components systems equipment intended surgical implantation, atomic energy control instruments, airplane spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, other applications intended support sustain life. Further more, Winbond products intended applications wherein failure Winbond products could result lead situation wherein personal injury, death severe property environmental damage could occur. Winbond customers using selling these products such applications their risk agree fully indemnify Winbond damages resulting from such improper sales.
Publication Release Date:Feb. 2009 Revision
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