Table Contents1. GENERAL DESCRIPTION FEATURES PARAMETERS.5 BALL CONFIG

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Table Contents1. GENERAL DESCRIPTION FEATURES PARAMETERS.5 BALL CONFIG

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PRELIMINARY W9464G2IB 512K BANKS BITS GDDR SDRAM
Table Contents1. GENERAL DESCRIPTION FEATURES PARAMETERS.5 BALL CONFIGURATION.6 BALL DESCRIPTION BLOCK DIAGRAM.9 FUNCTIONAL DESCRIPTION Power Sequence.10 Command Function 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.10 Bank Activate Command Bank Precharge Command Precharge Command Write Command Write with Auto-precharge Command Read Command Read with Auto-precharge Command Mode Register Command Extended Mode Register Command No-Operation Command Burst Read Stop Command.12 Device Deselect Command Auto Refresh Command Self Refresh Entry Command.13 Self Refresh Exit Command Data Write Enable /Disable Command.13
Read Operation Write Operation Precharge.14 Burst Termination Refresh Operation Power Down Mode Input Clock Frequency Change during Precharge Power Down Mode.15 Mode Register Operation 7.10.1 7.10.2 Burst Length field Addressing Mode Select (A3).16
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
7.10.3 7.10.4 7.10.5 7.10.6 7.10.7 Latency field A4).17 Reset (A8).17 Mode Register /Extended Mode register change bits (BA0, BA1) Extended Mode Register field Reserved field
OPERATION MODE.19 Simplified Truth Table.19 Function Truth Table Function Truth Table, continued.21 Function Truth Table, continued.22 Function Truth Table CKE.23 Simplified Stated Diagram
ELECTRICAL CHARACTERISTICS.25 Absolute Maximum Ratings.25 Recommended Operating Conditions Capacitance Leakage Output Buffer Characteristics.26 Characteristics.27 Characteristics Operating Condition Test Conditions.29
TIMING WAVEFORMS 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Command Input Timing Timing Signals Read Timing (Burst Length Write Timing (Burst Length 4).34 DATA MASK (W9464G2IB) Mode Register (MRS) Timing.36 Extend Mode Register (EMRS) Timing Auto-precharge Timing (Read Cycle, 2).38 Auto-precharge Timing (Read cycle, continued.39
10.10 Auto-precharge Timing (Write Cycle) 10.11 Read Interrupted Read 8).41 10.12 Burst Read Stop 10.13 Read Interrupted Write 10.14 Read Interrupted Precharge 10.15 Write Interrupted Write 8).43 10.16 Write Interrupted Read 10.17 Write Interrupted Read 10.18 Write Interrupted Precharge 8).44
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PRELIMINARY W9464G2IB
10.19 Bank Interleave Read Operation 2).45 10.20 Bank Interleave Read Operation 4).45 10.21 Bank Interleave Read Operation 2).46 10.22 Bank Interleave Read Operation 4).46 10.23 Auto Refresh Cycle.47 10.24 Precharge/Activate Power Down Mode Entry Exit Timing 10.25 Input Clock Frequency Change during Precharge Power Down Mode Timing.47 10.26 Self Refresh Entry Exit Timing.48 PACKAGE SPECIFICATION.49 11.1 144L LFBGA (12X12X1.40 mm^3,
REVISION HISTORY
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
GENERAL DESCRIPTION
W9464G2IB CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM); organized 524,288 words banks bits. W9464G2IB delivers data bandwidth 500M words second (-4). fully comply with personal computer industrial standard, W9464G2IB sorted into following speed grades: -5I. compliant DDR500/CL3 specification. -5/-5I compliant DDR400/CL3 specification (the grade which guaranteed support -40° compliant DDR333/CL2.5 specification. Input reference positive edge (except CKE). timing reference point differential clock when signals cross during transition. Write Read data synchronized with both edges (Data Strobe). having programmable Mode Register, system change burst length, latency cycle, interleave sequential burst maximize performance. W9464G2IB ideal high performance applications.
FEATURES
2.5V ±0.2V Power Supply DDR333/400 2.6V ±0.1V Power Supply DDR500 Clock Frequency Double Data Rate architecture; data transfers clock cycle Differential clock inputs (CLK edge-aligned with data Read; center-aligned with data Write Latency: Burst Length: Auto Refresh Self Refresh Precharged Power Down Active Power Down Write Data Mask Write Latency 15.6µS Refresh interval (2K/32 Refresh) Maximum burst refresh cycle: Interface: SSTL_2 Packaged 144L LFBGA, using Lead free materials with RoHS compliant
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PRELIMINARY W9464G2IB
PARAMETERS
SYMBOL DESCRIPTION MIN./MAX. Min. Max. Min. Max. Min. Max. Min. Max. Min. Min. Max. Max. Max. Max. Max. Max. -5/-5I
Clock Cycle Time
tRAS IDD0 IDD1 IDD4R IDD4W IDD5 IDD6
Active Precharge Command Period Active Ref/Active Command Period Operating Current: Bank Active-Precharge Operating Current: Bank Active-Read-Precharge Burst Operation Read Current Burst Operation Write Current Auto Refresh Current Self-Refresh Current
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PRELIMINARY W9464G2IB
BALL CONFIGURATION
DQS0
VSSQ
DQ31
DQ29
DQ28
VSSQ
DQS3
VDDQ
VDDQ
VDDQ
VDDQ
DQ30
VDDQ
VDDQ
DQ27
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ26
DQ25
VDDQ
VSSQ
VSSQ
VDDQ
DQ24
DQ17
DQ16
VDDQ
VSSQ
VSSQ
VDDQ
DQ15
DQ14
DQ19
DQ18
VDDQ
VSSQ
VSSQ
VDDQ
DQ13
DQ12
DQS2
VSSQ
VSSQ
DQS1
DQ21
DQ20
VDDQ
VSSQ
VSSQ
VDDQ
DQ11
DQ10
DQ22
DQ23
VDDQ
VSSQ
VSSQ
VDDQ
/CAS
/RAS
/CLK
A8/AP
VREF
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PRELIMINARY W9464G2IB
BALL DESCRIPTION
BALL LOCATION
M4,M5,L5,M6,M7,L8, M8,M9,M10,L7,K5 M3,L4 A6,B5,A5,A4,B1,C2, C1,D1,J12,J11,H12, H11,F12,F11,E12, E11,E2,E1,F2,F1,H2, H1,J1,J2,D12,C12, C11,B12,A9,A8,B8,A7
SYMBOL
A0-A10
FUNCTION
Address
DESCRIPTION
Multiplexed pins column address. address: A0-A10. Column address: A0-A7. used Auto-precharge) Select bank activate during address latch time, bank read/write during column address latch time.
BA0,
Bank Address
DQ0-DQ31
Data Input/ Output
DQ0-DQ31 input output data synchronized with both edges DQS.
A1,G12,G1,A12
DQS0-DQS3
Data Strobe
Bi-directional signal. input signal during write operation output signal during read operation. Edge-aligned with read data, Center-aligned with write data. Disable enable command decoder. When command decoder disabled, command ignored previous operation continues. Command inputs (along with define command being entered. input mask signal writes data. When asserted "high" burst write, input data masked. synchronized with both edges DQS. address control input signals sampled crossing positive edge negative edge
Chip Select Command Inputs Write mask
K1,K2
A2,G11,G2,A11
DM0-DM3
L10,L11
CLK,
Differential clock inputs
controls clock activation deactivation. synchronous POWER-DOWN entry exit, SELF REFRESH entry must maintained high Clock Enable throughout READ WRITE accesses. Input buffers, excluding CLK, disabled during POWER-DOWN. Input buffers, excluding disabled during SELF REFRESH. Reference Voltage VREF reference voltage inputs.
VREF
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PRELIMINARY W9464G2IB
BALL DESCRIPTION, continued
BALL LOCATION
C6,C7,D3,D10,K3,K6, K7,K10 D4,D6,D7,D9,E5,E6, E7,E8,F5,F6,F7,F8, G5,G6,G7,G8,H5,H6, H7,H8,J5,J6,J7,J8, K4,K9 B2,B4,B6,B7,B9,B11, D2,D11,E3,E10,F3, F10,H3,H10,J3,J10 A3,A10,C3,C4,C5,C8, C9,C10,D5,D8,E4,E9, F4,F9,G4,G9,H4,H9, J4,J9 B3,B10,G3,G10,K11, K12,L2,L3,L6,L12,M2 K8,L9
SYMBOL
FUNCTION
Power
DESCRIPTION
Power logic circuit inside SDRAM.
Ground
Ground logic circuit inside SDRAM.
VDDQ
Power Separated power from VDD, used output buffer, buffer improve noise immunity.
VSSQ
Ground Separated ground from VSS, used output buffer, improve noise immunity. buffer
Connection connection Connection Reserved Future Use.
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BLOCK DIAGRAM
CLOCK BUFFER
CONTROL
DECODER
SIGNAL GENERATOR COMMAND
DECODER
COLUMN DECODER
COLUMN DECODER
CELL ARRAY BANK
DECODER
CELL ARRAY BANK
ADDRESS
MODE REGISTER SENSE AMPLIFIER BUFFER
SENSE AMPLIFIER
PREFETCH REGISTER DATA CONTROL CIRCUIT REFRESH COUNTER COLUMN COUNTER BUFFER
DQSn
COLUMN DECODER
COLUMN DECODER
DECODER
CELL ARRAY BANK
DECODER
CELL ARRAY BANK
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: cell array configuration 2048
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FUNCTIONAL DESCRIPTION
Power Sequence
Apply power attempt state 0.2V), other inputs undefined Apply before same time VDDQ. Apply VDDQ before same time VREF. Start Clock maintain stable condition (min.). After stable power clock, apply take high. Issue precharge command banks device. Issue EMRS (Extended Mode Register Set) enable establish Output Driver Type. Issue (Mode Register Set) reset device idle with additional cycles(min) clock required Lock before executable command applied.) Issue precharge command banks device. Issue more Auto Refresh commands. Issue MRS-Initialize device operation with reset deactivated low.
Clock min.
Command
PREA
EMRS
Clock min.
Clock min.
PREA
AREF tRFC
Clock min.
AREF tRFC
Inputs maintain stable min.
Enable
reset with High
Disable reset with
Initialization sequence after power-up
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7.2.1
Command Function
Bank Activate Command
"L", "H", "H", BA0, Bank, Address) Bank Activate command activates bank designated (Bank address) signal. addresses latched when this command issued cell data read sense amplifiers. maximum time that each bank held active state specified tRAS (max). After this command issued, Read Write operation executed.
7.2.2
Bank Precharge Command
"L", "H", "L", BA0, Bank, "L", Don't Care) Bank Precharge command percharges bank designated precharged bank switched from active state idle state.
7.2.3
Precharge Command
"L", "H", "L", BA0, Don't Care, "H", Don't Care) Precharge command precharges banks simultaneously. Then banks switched idle state.
7.2.4
Write Command
"H", "L", "L", BA0, Bank, "L", Column Address) write command performs Write operation bank designated write data latched both edges DQS. length write data (Burst Length) column access sequence (Addressing Mode) must Mode Register power-up prior Write operation.
7.2.5
Write with Auto-precharge Command
"H", "L", "L", BA0, Bank, "H", Column Address) Write with Auto-precharge command performs Precharge operation automatically after Write operation. This command must interrupted other commands.
7.2.6
Read Command
"H", "L", "H", BA0, Bank, "L", Column Address) Read command performs Read operation bank designated read data synchronized with both edges DQS. length read data (Burst Length), Addressing Mode Latency (access time from command clock cycle) must programmed Mode Register power-up prior Read operation.
7.2.7
Read with Auto-precharge Command
"H", "L", "H", BA0, Bank, "H", Column Address) Read with Auto-precharge command automatically performs Precharge operation after Read operation.
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READA tRAS (min) (BL/2) Internal precharge operation begins after BL/2 cycle from Read with Auto-precharge command. tRCD(min) READA tRAS(min) (BL/2) Data read with shortest latency, internal Precharge operation does begin until after tRAS (min) completed. This command must interrupted other command.
7.2.8
Mode Register Command
"L", "L", "L", "L", "L", Register Data) Mode Register command programs values Latency, Addressing Mode, Burst Length reset Mode Register. default values Mode Register after powerup undefined, therefore this command must issued during power-up sequence. Also, this command issued while banks idle state. Refer table specific codes.
7.2.9
Extended Mode Register Command
"L", "L", "L", "H", "L", Register data) Extended Mode Register command implemented needed function extensions standard (SDR-SDRAM). Currently only available mode EMRS enable/disable, decoded default value extended mode register defined; therefore this command must issued during power-up sequence enabling DLL. Refer table specific codes.
7.2.10 No-Operation Command
"H", "H", "H") No-Operation command simply performs operation (same command Device Deselect).
7.2.11
Burst Read Stop Command
"H", "H", "L") Burst stop command used stop burst operation. This command only valid during Burst Read operation.
7.2.12 Device Deselect Command
"H") Device Deselect command disables command decoder that Address inputs ignored. This command similar No-Operation command.
7.2.13
Auto Refresh Command
"L", "L", "H", "H", BA0, BA1, Don't Care) AUTO REFRESH used during normal operation SDRAM analogous CAS- BEFORE-RAS (CBR) refresh previous DRAM types. This command non-persistent, must issued each time refresh required. refresh addressing generated internal refresh controller. This makes address bits "Don't Care" during AUTO REFRESH command. SDRAM requires AUTO
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FRESH cycles average periodic interval tREFI (maximum). allow improved efficiency scheduling switching between tasks, some flexibility absolute refresh interval provided. maximum eight AUTO REFRESH commands posted given SDRAM, maximum absolute interval between AUTO REFRESH command next AUTO REFRESH command tREFI.
7.2.14
Self Refresh Entry Command
"L", "L", "H", "L", BA0, BA1, Don't Care) SELF REFRESH command used retain data SDRAM, even rest system powered down. When self refresh mode, SDRAM retains data without external clocking. SELF REFRESH command initiated like AUTO REFRESH command except disabled (LOW). automatically disabled upon entering SELF REFRESH, automatically enabled upon exiting SELF REFRESH. time enabled Reset must follow clock cycles should occur before READ command issued. Input signals except "Don't Care" during SELF REFRESH. Since SSTL_2 input, VREF must maintained during SELF REFRESH.
7.2.15
Self Refresh Exit Command
(CKE "H", "H", "H", "H") procedure exiting self refresh requires sequence commands. First, must stable prior going back HIGH. Once HIGH, SDRAM must have commands issued tXSNR because time required completion internal refresh progress. simple algorithm meeting both refresh requirements apply NOPs clock cycles before applying other command. SELF REFREH mode introduces possibility that internally timed event missed when raised exit from self refresh mode. Upon exit from SELF REFRESH extra auto refresh command recommended.
7.2.16
Data Write Enable /Disable Command
"L/H" DM0-DM3 "L/H") During Write cycle, DM0-DM3, signal functions Data Mask control every word input data. signal controls DQ7, signal controls DQ15, signal controls DQ16 DQ23 signal controls DQ24 DQ31.
Read Operation
Issuing Bank Activate command idle bank puts into active state. When Read command issued after tRCD from Bank Activate command, data read sequentially, synchronized with both edges (Burst Read operation). initial read data becomes available after Latency from issuing Read command. Latency must Mode Register power-up. When Precharge Operation performed bank during Burst Read operation, Burst operation terminated. When Read with Auto-precharge command issued, Precharge operation performed automatically after Read cycle, then bank switched idle state. This command cannot interrupted other commands. Refer diagrams Read operation.
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Write Operation
Issuing Write command after tRCD from bank activate command. input data latched sequentially, synchronizing with both edges (rising falling) after Write command (Burst write operation). burst length Write data (Burst Length) Addressing Mode must Mode Register power-up. When Precharge operation performed bank during Burst Write operation, Burst operation terminated. When Write with Auto-precharge command issued, Precharge operation performed automatically after Write cycle, then bank switched idle state, Write with Autoprecharge command cannot interrupted other command entire burst data duration. Refer diagrams Write operation.
Precharge
There Commands, which perform precharge operation (Bank Precharge Precharge All). When Bank Precharge command issued active bank, bank precharged then switched idle state. Bank Precharge command precharge bank independently other bank hold un-precharged bank active state. maximum time each bank held active state specified tRAS (max). Therefore, each bank must precharged within tRAS(max) from bank activate command. Precharge command used precharge banks simultaneously. Even banks active state, Precharge command still issued. this case, Precharge operation performed only active bank precharge bank then switched idle state.
Burst Termination
When Precharge command used bank Burst cycle, Burst operation terminated. When Burst Read cycle interrupted Precharge command, read operation disabled after clock cycle (CAS Latency) from Precharge command. When Burst Write cycle interrupted Precharge command, input circuit reset same clock cycle which precharge command issued. this case, signal must asserted "high" during prevent writing invalided data cell array. When Burst Read Stop command issued bank Burst Read cycle, Burst Read operation terminated. Burst read Stop command supported during write burst operation. Refer diagrams Burst termination.
Refresh Operation
types Refresh operation performed device: Auto Refresh Self Refresh. repeating Auto Refresh cycle, each bank turn refreshed automatically. Refresh operation must performed 2048 times (rows) within 32mS. period between Auto Refresh command next command specified tRFC. Self Refresh mode enter issuing Self Refresh command (CKE asserted "low"), while banks idle state. device Self Refresh mode long held "low". case distributed Auto Refresh commands, distributed auto refresh commands must issued every 15.6 last distributed Auto Refresh commands must performed within 15.6 before entering self refresh mode. After exiting from Self Refresh mode, refresh operation must performed within 15.6 Self Refresh mode, input/output buffers disabled,
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resulting lower power dissipation (except buffer). Refer diagrams Refresh operation.
Power Down Mode
types Power Down Mode performed device: Active Power Down Mode Precharge Power Down Mode. When device enters Power Down Mode, input/output buffers disabled resulting power dissipation (except buffer). Power Down Mode enter asserting "low" while device running burst cycle. Taking "high" exit this mode. When goes high, operation command must input next rising edge. Refer diagrams Power Down Mode.
Input Clock Frequency Change during Precharge Power Down Mode
SDRAM input clock frequency changed under following condition: SDRAM must precharged power down mode with logic level. After minimum clocks after goes LOW, clock frequency change frequency between minimum maximum operating frequency specified particular speed grade. During input clock frequency change, must held LOW. Once input clock frequency changed, stable clock must provided DRAM before precharge power down mode exited. must RESET EMRS after precharge power down exit. additional command need issued appropriately etc. After relock time, DRAM ready operate with clock frequency.
7.10 Mode Register Operation
mode register programmed Mode Register command (MRS/EMRS) when banks idle state. data Mode Register transferred using BA0, address inputs. Mode Register designates operation mode read write cycle. register divided into five filed: Burst Length field length burst data Addressing Mode selected designate column access sequence Burst cycle Latency field assess time clock cycle reset field reset Regular/Extended Mode Register filed select type (Regular/Extended MRS). EMRS cycle implemented extended function (DLL enable/Disable mode). initial value Mode Register (including EMRS) after power undefined; therefore Mode Register command must issued before power operation.
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7.10.1 Burst Length field
This field specifies data length column access using pins sets Burst Length words.
BURST LENGTH
Reserved words words words Reserved
7.10.2 Addressing Mode Select (A3)
Addressing Mode modes; Interleave mode Sequential Mode, When "0", Sequential mode selected. When "1", Interleave mode selected. Both addressing Mode support burst length words.
ADDRESSING MODE
Sequential Interleave
Addressing Sequence Sequential Mode
column access performed incrementing column address input device. address varied Burst Length following.
Addressing Sequence Sequential Mode
DATA ACCESS ADDRESS BURST LENGTH
Data Data Data Data Data Data Data Data
words (address bits carried from words (address carried from words (address bits carried from
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Addressing Sequence Interleave Mode
Column access started from inputted column address performed interleaving address bits sequence shown following.
Address Sequence Interleave Mode
DATA ACCESS ADDRESS BURST LENGTH
Data Data Data Data Data Data Data Data
words
words
words
7.10.3 Latency field
This field specifies number clock cycles from assertion Read command first data read. minimum values Latency depend frequency CLK.
LATENCY
Reserved Reserved Reserved Reserved
7.10.4 Reset (A8)
This used reset DLL. When "1", reset.
7.10.5 Mode Register /Extended Mode register change bits (BA0, BA1)
These bits used select MRS/EMRS.
A10-A0
Regular Cycle Extended Cycle Reserved
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7.10.6 Extended Mode Register field
Switch field (A0) This used select enable disable
Output Driver Strength Control field (A6,
Enable Disable
100%, matched impedance driver strength required Extended Mode Register (EMRS) following:
BUFFER STRENGTH
100% Strength Strength Reserved Strength
7.10.7 Reserved field
Test mode entry (A7) This used enter Test mode must normal operation. Reserved bits (A9, A10) These bits reserved future operations. They must normal operation.
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OPERATION MODE
following table shows operation commands.
Simplified Truth Table
COMMAND
Bank Active Bank Precharge Precharge Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Extended Mode Register Operation Burst Read Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Power Down Mode Entry Power Down Mode Exit Data Write Enable Data Write Disable
SYM.
PREA WRIT WRITA READ READA EMRS AREF SELF SELEX
DEVICE STATE
Idle(3)
CKEn-1
CKEn
DM(4)
BA0,BA1
A0-A7 A9,A10
Active
Active(3) Active
Active(3) Idle Idle Active Idle Idle Idle (Self Refresh) Idle/ Active(5) (Power Down) Active Active
PDEX
Notes:
Valid Don't Care level High level CKEn signal input level when commands issued. CKEn-1 signal input level clock cycle before commands issued. These state designated BA0, signals. DM0-DM3 (W9464G2IB). Power Down Mode entry burst cycle.
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Function Truth Table
Idle Active Read Write
(Note
CURRENT STATE
ADDRESS
Op-Code Op-Code Op-Code Op-Code
COMMAND
NOP/BST READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS NOP/BST READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS ILLEGAL ILLEGAL activating
ACTION
NOTES
Refresh Self refresh Mode register accessing Begin read: Determine Begin write: Determine ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst Continue burst Burst stop Term burst, read: Determine ILLEGAL ILLEGAL Term burst, precharging ILLEGAL ILLEGAL Continue burst Continue burst ILLEGAL Term burst, start read: Determine Term burst, start read: Determine ILLEGAL Term burst, Precharging ILLEGAL ILLEGAL
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Function Truth Table, continued
Read with Autoprecharge Write with Autoprecharge Precharging Activating
CURRENT STATE
ADDRESS
Op-Code Op-Code Op-Code Op-Code
COMMAND
READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS
ACTION
Continue burst Continue burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst Continue burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after NOP-> Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after ILLEGAL ILLEGAL NOP-> active after tRCD NOP-> active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
NOTES
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Function Truth Table, continued
Write Recovering with Autoprecharge Refreshing Mode Register Accessing
CURRENT STATE
Write Recovering
ADDRESS
Op-Code Op-Code
COMMAND
ACTION
NOP->Row active after NOP->Row active after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Enter precharge after NOP->Enter precharge after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Idle after NOP->Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Row after tMRD NOP->Row after tMRD ILLEGAL ILLEGAL ILLEGAL
NOTES
READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/READA WRIT/WRITA PRE/PREA AREF/SELF MRS/EMRS READ/WRIT ACT/PRE/PREA
AREF/SELF/MRS/EMRS
READ/WRIT ACT/PRE/PREA/ARE F/SELF/MRS/EMRS
Notes: entries assume that active (High level) during preceding clock cycle current clock cycle. Illegal bank idle. Illegal bank specified states; Function legal bank indicated Bank Address (BA), depending state that bank. Illegal tRCD satisfied. Illegal tRAS satisfied. Must satisfy burst interrupt condition. Must avoid contention, turn around, and/or satisfy write recovery requirements. Must mask preceding data which don't satisfy
Remark: High level, level, High level (Don't Care), Valid data
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PRELIMINARY W9464G2IB
Function Truth Table
Self Refresh Power Down banks Idle Active State Other Than Listed Above
CURRENT STATE
ADDRESS
INVALID
ACTION
NOTES
Exit Self Refresh->Idle after tXSNR Exit Self Refresh->Idle after tXSNR ILLEGAL ILLEGAL Maintain Self Refresh INVALID Exit Power down->Idle after Maintain power down mode Refer Function Truth Table Enter Power down Enter Power down Self Refresh ILLEGAL ILLEGAL Power down Refer Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer Function Truth Table
Notes:
Self refresh enter only from banks idle state. Power Down occurs when banks idle; this mode referred precharge power down. Power Down occurs when there active bank; this mode referred active power down.
Remark:
High level, level, High level (Don't Care), Valid data
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PRELIMINARY W9464G2IB
Simplified Stated Diagram
SELF REFRESH
SREF SREFX
IDLE
MRS/EMRS
MODE REGISTER
AREF
AUTO REFRESH
PDEX
ACTIVE POWERDOWN POWER DOWN
PDEX
ACTIVE
Read Read
Write
Write
Write
Read
Read
Write Write
Read Read Read
Write
Read
POWER APPLIED
POWER
CHARGE
Automatic Sequence Command Sequence
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER SYMBOL RATING UNIT
Input/Output Voltage Power Supply Voltage Operating Temperature (-4/-5/-6) Operating Temperature (-5I) Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current
VIN, VOUT VDD, VDDQ TOPR TOPR TSTG TSOLDER IOUT
-0.3 VDDQ -0.3
Note: Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device.
This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Recommended Operating Conditions
PARAMETER
Power Supply Voltage (for -5/-5I/-6) Power Supply Voltage (for Buffer Supply Voltage (for -5/-5I/-6) Buffer Supply Voltage (for Input reference Voltage Termination Voltage (System) Input High Voltage (DC) Input Voltage (DC) Differential Clock Input Voltage Input Differential Voltage. inputs (DC) Input High Voltage (AC) Input Voltage (AC) Input Differential Voltage. inputs (AC) Differential input Cross Point Voltage Differential Clock Middle Point
-4/-5/-6, 85°C -5I)
SYMBOL
VDDQ VDDQ VREF (DC) (DC) VICK (DC) (DC) (AC) (AC) (AC) (AC) VISO (AC)
MIN.
0.49 VDDQ VREF 0.04 VREF 0.15 -0.3 -0.3 0.36 VREF 0.31 VDDQ/2 VDDQ/2
TYP.
0.50 VDDQ VREF
MAX.
0.51 VDDQ VREF 0.04 VDDQ VREF 0.15 VDDQ VDDQ VREF 0.31 VDDQ VDDQ/2 VDDQ/2
UNIT
NOTES
Notes: Undershoot Limit: (min) -1.5V with pulse width Overshoot Limit: (max) VDDQ +1.5V with pulse width (DC) (DC) levels maintain current logic state.
(AC) (AC) levels change logic state.
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
Capacitance
DELTA (MAX.)
0.25
(VDD VDDQ 2.5V ±0.2V, MHz, VOUT (DC) VDDQ/2, VOUT (Peak Peak) 0.2V)
SYMBOL
CCLK CI/O
PARAMETER
Input Capacitance (except pins) Input Capacitance (CLK pins) DQS, Capacitance
MIN.
MAX.
UNIT
Notes: These parameters periodically sampled 100% tested.
Leakage Output Buffer Characteristics
PARAMETER
Input Leakage Current input VDD, VREF 1.35V (All other pins under test Output Leakage Current (Output disabled, VOUT VDDQ) Output High Voltage (under test load condition) Output Voltage (under test load condition) Output Levels: Full drive option High Current (VOUT VDDQ 0.373V, min. VREF, min. Current (VOUT 0.373V, max. VREF, max. VTT) Output Levels: Reduced drive option High Current (VOUT VDDQ 0.763V, min. VREF, min. Current (VOUT 0.763V, max. VREF, max. VTT) Output Levels: Reduced drive option High Current (VOUT VDDQ 1.056V, min. VREF, min. Current (VOUT 1.056V, max. VREF, max. VTT)
SYMBOL
MIN.
MAX.
UNIT
NOTES
+0.76
-0.76
IOHR
IOLR
IOHR(30)
-4.5
IOLR(30)
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
Characteristics
PARAMETER
Operating current: Bank Active-Precharge; min; min; inputs changing once clock cycle; Address control inputs changing once every clock cycles Operating current: Bank Active-Read-Precharge; Burst min; min; IOUT Address control inputs changing once clock cycle. Precharge Power Down standby current: Banks Idle; Power down mode; max; min; VREF Idle standby current: min; Banks Idle; min; min; Address other control inputs changing once clock cycle; Active Power Down standby current: Bank Active; Power down mode; max; min; VREF Active standby current: min; min; Bank Active-Precharge; tRAS max; min; inputs changing twice clock cycle; Address other control inputs changing once clock cycle Operating current: Burst Reads; Continuous burst; Bank Active; Address control inputs changing once clock cycle; CL=3; min; IOUT Operating current: Burst Write; Continuous burst; Bank Active; Address control inputs changing once clock cycle; min; inputs changing twice clock cycle Auto Refresh current: tRFC Self Refresh current: 0.2V; external clock Random Read current: Banks Active Read with activate every 20nS, Auto-Precharge Read every Burst tRCD IOUT 0mA; inputs changing twice clock cycle; Address changing once clock cycle
SYM.
MAX.
-5/-5I
UNIT
NOTES
IDD0
IDD1
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W IDD5 IDD6
IDD7
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
SYM.
tRFC tRAS tRCDRD tRCDWR tRAP tCCD tRRD tDAL
Characteristics Operating Condition
PARAMETER MIN.
Active Ref/Active Command Period Ref/Active Command Period Active Precharge Command Period delay Read delay Write Active Read with Auto-precharge Enable Read/Write(a) Read/Write(b) Command Period Precharge Active Command Period Active(a) Active(b) Command Period Write Recovery Time Auto-precharge Write Recovery Precharge Time -0.6 -0.6 -0.6 -0.6 0.45 0.45 (tCL,tCH) -0.5 1.75 0.55 0.55 0.45 0.45 min, (tCL,tCH) -0.5 1.75 70000
MAX.
-5/-5I MIN.
-7.5 -0.7 -0.6 -0.7 0.55 0.55 0.45 0.45 min, 100000
MIN.
100000
UNIT MAX.
NOTES
MAX.
-7.5 -0.7 -0.6 -0.7 tDQSCK tDQSQ Output Access Time from CLK, Data Strobe Edge Output Data Edge Skew High Level Width Level Width Half Period (minimum actual tCH, tCL) 0.55 0.55
Cycle Time
Data Access Time from CLK,
(tCL,tCH) -0.5 1.75
tRPRE tRPST tDIPW tDQSH tDQSL tDSS tDSH tWPRES
Output Data Hold Time from Read Preamble Time Read Postamble Time Setup Hold Time Input Pulse Width (for each input) Input High Pulse Width Input Pulse Width Falling Edge Setup Time Falling Edge Hold Time from Clock Write Preamble Set-up Time
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
Characteristics Operating Condition, continued
SYM.
tWPREH tWPST tDQSS
PARAMETER MIN.
Clock Write Preamble Hold Time Write Postamble Time 0.25
MAX. MIN.
0.25 1.25 0.72 0.75 0.75 -0.7
MAX. MIN.
0.25 1.25 0.75 -0.7
MAX.
UNIT
NOTES
1.25
Write Command First Latching 0.72 Transition Input Setup Time Input Hold Time Data-out CLK, Data-out CLK, SSTL Input Transition Internal Write Read Command Delay Exit Self Refresh non-Read Command Exit Self Refresh Read Command Refresh Interval Time (2K/ 32mS) Mode Register Cycle Time Low-impedance Time from High-impedance Time from 0.75 0.75 -0.7
tT(SS) tWTR tXSNR tXSRD tREFi tMRD
-0.7
-0.7
-0.7
15.6
15.6
15.6
Test Conditions
SYMBOL
PARAMETER Input High Voltage (AC) Input Voltage (AC) Input Reference Voltage Termination Voltage Input Signal Peak Peak Swing Differential Clock Input Reference Voltage
Input Difference Voltage. Inputs (AC) Input Signal Minimum Slew Rate Output Timing Measurement Reference Voltage
VREF VSWING (AC) SLEW VOTR
VALUE VREF 0.31 VREF 0.31 VDDQ VDDQ (AC)
UNIT
V/nS
VDDQ
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
VDDQ (AC) SWING (MAX) VREF
(AC)
Output
Output V(out)
30pF
SLEW (VIH (AC) VILmax (AC))
Timing Reference Load
Notes:
Conditions outside limits listed under "Absolute Maximum Ratings" cause permanent damage device. voltages referenced VSS, VSSQ. 2.6V±0.1V DDR500) Peak peak noise VREF exceed VREF(DC). 1.95V, 0.35V 1.9V, 0.4V values IOH(DC) based VDDQ 2.3V 1.19V. values IOL(DC) based VDDQ 2.3V 1.11V. These parameters depend cycle rate these values measured cycle rate with minimum values tRC. applied directly device. system supply signal termination resistors expected equal VREF must track variations level VREF. These parameters depend output loading. Specified values obtained with output open.
min(AC)
(10) Transition times measured between slope.
max(AC).Transition (rise fall) input signals have fixed
(11) result nominal calculation with regard contains more than decimal place, result rounded nearest decimal place. (i.e., TDQSS 0.75 tCK, 0.75 5.625 rounded nS.) (12) differential clock cross point voltage where input timing measurement referenced. (13) magnitude difference between input level input level. (14) VISO means {VICK(CLK)+VICK( )}/2. (15) Refer figure below.
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
VICK VID(AC) VICK VICK VICK
VID(AC)
Differential
VISO VISO(min) VISO(max)
(16) tDQSCK depend clock jitter. These timing measured stable clock. (17) maximum eight AUTO REFRESH commands posted given SDRAM device. (18) tDAL (tWR/tCK) (tRP/tCK)
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
TIMING WAVEFORMS
10.1 Command Input Timing
A0~A10 BA0,
Refer Command Truth Table
10.2 Timing Signals
VIH(AC) VIL(AC)
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.3 Read Timing (Burst Length
READ
tDQSCK
Latency Hi-Z Preamble
tDQSCK tRPRE
tDQSCK tRPST
Hi-Z
tDQSQ
Postamble
tDQSQ
tDQSQ
Hi-Z
Output (Data)
Hi-Z
Latency Hi-Z Preamble
tDQSCK tRPRE tDQSCK tDQSCK tRPST
Hi-Z
tDQSQ
Postamble
tDQSQ
tDQSQ
Hi-Z
Output (Data)
Hi-Z
Notes: correspondence DQS0-DQS3 (W9464G2IB)
DQS0 DQS1 DQS2 DQS3
DQ0-7 DQ8-15 DQ16-23 DQ24-31
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.4 Write Timing (Burst Length
device
Pream Postam
Pream Postam
24~31
Note: four DQSs. (DQS0 lower byte DQS3 upper byte)
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.5 DATA MASK (W9464G2IB)
DIPW
DQ0~DQ
Masked
24~DQ31
Masked
DIPW
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.6 Mode Register (MRS) Timing
tMRD NEXT
Register data
Addressing Mode Burst Length Reserved Mode Register Extended Mode Register Reserved Reset Latency "Reserved" should stay during cycle. Reserved
Burst Length Sequential Reserved Interleaved Reserved
Reserved
Addressing Mode Sequential Interleaved Latency Reserved Reserved Reserved Reset EMRS Regular cycle Extended cycle Reserved
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.7 Extend Mode Register (EMRS) Timing
tMRD
EMRS NEXT
Register data
Switch Buffer Strength
Switch Enable Disable
Reserved Buffer Strength
Buffer Strength 100% Strength Strength Reserved Strength
Reserved Mode Register Extended Mode Register
EMRS Regular cycle Extended cycle Reserved
Reserved
should stay
during EMRS cycle
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.8 Auto-precharge Timing (Read Cycle,
tRCD (READA) tRAS (min) (BL/2)
tRAS BL=2 READA
BL=4 READA
BL=8
READA
Notes: CL=2 shown; same command operation timing with CL=2.5 CL=3 this case, internal precharge operation begin after BL/2 cycle from READA command.
Represents start internal precharging. Read with Auto-precharge command cannot interrupted other command.
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.9 Auto-precharge Timing (Read cycle, continued
tRCD/RAP(min) tRCD (READA) tRAS (min) (BL/2)
tRAS BL=2 tRAP tRCD
READA
BL=4 tRAP tRCD READA
BL=8 tRAP tRCD READA
Notes: shown; same command operation timing with 2.5, CL=3.
this case, internal precharge operation does begin until after tRAS (min) command.
Represents start internal precharging.
Read with Auto-precharge command cannot interrupted other command.
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.10 Auto-precharge Timing (Write Cycle)
tDAL BL=2 WRITA
tDAL
BL=4 WRITA
tDAL
BL=8 WRITA
Write with Auto-precharge command cannot interrupted other command.
Represents start internal precharging.
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.11 Read Interrupted Read
READ
READ
READ
READ
READ
tRCD
Address COl,Add,A
tCCD
Col,Add,B
tCCD
Col,Add,C
tCCD
Col,Add,D
tCCD
Col,Add,E
10.12 Burst Read Stop
READ
Latency
Latency
Latency
Latency
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.13 Read Interrupted Write
Latency READ WRIT
Burst Read cycle must terminated Command avoid conflict.
10.14 Read Interrupted Precharge
Latency
Latency
Latency
Latency
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.15 Write Interrupted Write
WRIT
WRIT
WRIT
WRIT
WRIT
tRCD
Address
tCCD
COl. Add. Col.Add.B
tCCD
tCCD
tCCD
Col. Add.
Col. Add.
Col. Add.
10.16 Write Interrupted Read
WRIT
READ
tWTR
Data must masked
Data masked READ command, input ignored.
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.17 Write Interrupted Read
WRIT
READ
tWTR
Data must masked
10.18 Write Interrupted Precharge
WRIT
Data must masked
Data masked command, input ignored.
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.19 Bank Interleave Read Operation
tRC(b) tRC(a) tRRD ACTa ACTb tRCD(a) tRAS(a) tRCD(b) tRAS(b) tRP(b) tRP(a) READAa READAb ACTa tRRD ACTb
Preamble CL(a)
Postamble
Preamble
Postamble
CL(b)
ACTa/b Bank Act. bank READAa/b Read with Auto Pre.CMD bank APa/b Auto Pre. bank
10.20 Bank Interleave Read Operation
tRC(b) tRC(a) tRRD ACTa ACTb tRCD(a) tRAS(a) tRCD(b) tRAS(b) tRP(b) tRP(a) READAa READAb ACTa tRRD ACTb
Preamble CL(a)
Postamble CL(b)
ACTa/b Bank Act. bank READAa/b Read with Auto Pre.CMD bank APa/b Auto Pre. bank
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.21 Bank Interleave Read Operation
EADAa
READ
EADAc
S(b) D(c)
Pream L(a)
Postam CL(b)
Pream
Ta/b/c/d Bank Act. bank a/b/c/d Aa/b/c/d Read Auto Pre.C bank a/b/c/d APa/b/c/d Auto Pre. bank a/b/c/d
10.22 Bank Interleave Read Operation
EADAa
ACTc
READAb
ACTd
READ
ACTa
READAd
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.23 Auto Refresh Cycle
PREA
AREF
AREF
tRFC
tRFC
Note: kept "High" level Auto-Refresh cycle.
10.24 Precharge/Activate Power Down Mode Entry Exit Timing
Precharge/Activate Note Entry Exit
Note:
power down occurs when banks idle, this mode referred precharge power down. power down occurs when there active bank, this mode referred active power down.
10.25 Input Clock Frequency Change during Precharge Power Down Mode Timing
Frequency Change Occurs here
RESET
clocks
Minmum clocks required before changing frequency
Stable clock before power down exit
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
10.26 Self Refresh Entry Exit Timing
PREA
SELF
SELEX
Entry
Exit
tXSNR tXSRD
SELF
SELFX
READ
Entry
Exit
Note:
clock frequency changed during self refresh mode, reset required upon exit.
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
PACKAGE SPECIFICATION
11.1 144L LFBGA (12X12X1.40 mm^3,
Publication Release Date:Dec. 2008 Revision
PRELIMINARY W9464G2IB
REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
Dec. 2008
Initial preliminary data sheet
Important Notice
Winbond products designed, intended, authorized warranted components systems equipment intended surgical implantation, atomic energy control instruments, airplane spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, other applications intended support sustain life. Further more, Winbond products intended applications wherein failure Winbond products could result lead situation wherein personal injury, death severe property environmental damage could occur. Winbond customers using selling these products such applications their risk agree fully indemnify Winbond damages resulting from such improper sales.
Publication Release Date:Dec. 2008 Revision

Table Contents1. GENERAL DESCRIPTION FEATURES PARAMETERS.5 BALL CONFIG

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