Download

PDF Abstract Text:

High-Speed / Logic Gate Optocoupler SFH67XX Series

SFH6700 / 19 NC 1 Anode 2 Cathode 3 NC 4 8 VCC 7 Out 6 VE 5 GND Three-State-Output SFH6705 NC 1 Anode 2 Cathode 3 NC 4

Application Note 73
Vishay Semiconductors
High-Speed / Logic Gate Optocoupler (SFH67XX Series)
INTRODUCTION
The new SFH67XX series of high-speed optocouplers is capable of transmitting data rates up to 5 Mb / s typical and 2.5 Mb / s over the full specified operating temperature range. The combination of low input current (1.6 mA) and active logic-level output is a fit for nearly all logic applications where a galvanic insulation is necessary. The SFH67XX series features positive logic with TTL output levels. For improved noise immunity the detector incorporates a schmitt-trigger stage. The SFH6700 / 19 provides an enable input, which allows switching the output into the high ohmic state for bus applications. For applications which need an open collector output, the
SFH6700 / 19 NC 1 Anode 2 Cathode 3 NC 4 8 VCC 7 Out 6 VE 5 GND Three-State-Output SFH6705 NC 1 Anode 2 Cathode 3 NC 4
SFH6702 / 12 8 VCC 7 Out 6 NC 5 GND NC 1 Anode 2 Cathode 3 NC 4 Totem-Pole-Output SFH6731 / 32 8 VCC 7 NC 6 Out 5 GND
SFH6701 / 11 NC 1 Anode 2 Cathode 3 NC 4 Totem-Pole-Output
Anode 1 Cathode 2 Cathode 3 Anode 4
Open-Collector-Output
Dual / Totem-Pole-Output
Fig. 1 - Variations in the SFH67XX Family
TABLE 1
LED SFH6700 / 19 On Off On Off SFH6701 / 02 / 05 / 11 / 12 / 31 / 32 On Off H L L L H H H L Z Z ENABLE OUTPUT
DESIGN CONSIDERATIONS
The circuits shown below are intended to give the design engineer a guideline for logic family interconnection. Input Circuitry Below are stated the most common interface circuits which work for this coupler series. Totem Pole Drive Circuits Figures 2 and 3 are two of the most commonly used circuits. The designer chooses R1 according to the equation:
(valid for Figure 2)
www.vishay.com 1076
For technical questions, please contact: optocoupler.answers@vishay.com
Document Number: 83701 Rev. 1.2, 24-Apr-08
Application Note 73
High-Speed / Logic Gate Optocoupler Vishay Semiconductors (SFH67XX Series)
50 40 30 20 10 0 - 10 - 20 - 30 - 60 - 40 - 20 0 20 40 60 TA - Temperature (°C) 80 100
SFH6700 / 19 VDD
Data LS TTL IN LOGIC
Fig. 2 - Series LED Drive
SFH6700 / 19 1 NC VDD
TTL / CMOS LOGIC
Fig. 4 - Typical Input Current Threshold (Normalized) vs. Temperature
Data IN
VE 6 SFH6700 / 19 GND 5 VDD R1 R2 3 4 NC
Fig. 3 - Series LED Drive
Data CMOS IN LOGIC
Fig. 5 - Shunt LED Drive Circuit with Leakage Current Protection
TABLE 2
FIGURE 2 3 LOGIC GATE (E.G.) 74LS04 74LS04 74HCT04 R1 VALUE 750 1.10 k 1.10 k
The resistor R1 determines the forward LED current, and R2 shunts the LED. The choice of R2 depends on power dissipation considerations and the expected leakage current. The following equations can help designers determine the appropriate resistor values:
Document Number: 83701 Rev. 1.2, 24-Apr-08
For technical questions, please contact: optocoupler.answers@vishay.com
www.vishay.com 1077
Application Note 73
Vishay Semiconductors
TABLE 3
VDD 5V IF 3 mA R1 VALUE 1.0 k R2 VALUE 4.7 k
High-Speed / Logic Gate Optocoupler (SFH67XX Series)
SFH6700 / 19 VDD Data Open Collector IN Drain R1 2 3 GND 4 NC
Typical input circuit values to shunt around 250 µA away from the LED (according to figure 5) A better way to handle leakage current is presented in figure 6. This circuit provides excellent speed properties and leakage current protection. The silicon diode D1 ensures that the current is only sourced by VDD and is therefore not required for units driven by an open collector or open drain. The low forward voltage of D1 ensures that the LED stays off at logic low. The equation to choose R1 is:
Fig. 7 - Open Collector / Drain Shunt Drive Circuit
TABLE 4
VDD IF 3 mA 3 mA 3 mA R1 VALUE 1.10 k 2.80 k 4.42 k 5V 10 V 15 V
Typical input circuit values for a circuit according to figure 7 Input Circuitry for Improved Switching Speeds
SFH6700 / 19 VDD
TTL / CMOS LOGIC
Data IN
If switching speed is a concern, the use of a speed-up capacitor is a good solution. The resistor R2 limits the peak transient current IFpeak, whereas R1 and R2 determine the current at steady-state operation. The equations and reasonable resistor values are printed below. A reasonable value for the speed-up capacitor CS is 100 pF.
SFH6700 / 19 1 NC VCC 8 Out 7
Fig. 6 - Logic Gate Shunt Drive Circuit
Open Collector Drive Circuits A simple circuit, which also works for open collector drive circuits, has been presented in figures 3 and 5. In figure 5, the resistor R2 represents a leakage current protection path. A more efficient but more power-dissipating solution is presented in figure 7. This drive circuit provides good speed and protection against leakage currents. The resistor R1 is chosen in accordance with
Data IN
TTL / CMOS LOGIC
Fig. 8 - Series LED Drive with Speed-up Capacitor
The equations for the resistor values are:
Refer to table 4 for some typical resistor values. Note that leakage protection generally might only be an issue in some special applications.
The maximum IFpeak for this transient is 50 mA for the SFH67XX series.
www.vishay.com 1078
For technical questions, please contact: optocoupler.answers@vishay.com
Document Number: 83701 Rev. 1.2, 24-Apr-08
Application Note 73
High-Speed / Logic Gate Optocoupler Vishay Semiconductors (SFH67XX Series)
TABLE 5
VDD 5V CS VALUE 100 pF R1 VALUE 1.0 k R2 VALUE 75
Typical input circuit values for a circuit according to figure 8 Output Circuitry One advantage of the SFH67XX series is its easy connection to any logic system, because of the active output stage (totem pole / three state output). Either directly or via a pull-up resistor, all couplers can drive up to 16 LS TTL loads (4 TTL loads) easily. In general, a 0.1 µF bypass capacitor is strongly recommended for proper operation. The SFH6700 / 19 with its three-state output fits best in bus applications because of the possibility to switch the couplers output into the high ohmic state (for a typical setup please refer to figure 28). Drive Circuits for the Dual-Channel Devices The SFH6731 / 32 can be driven as simply as the single channel devices. All the above drive circuits and equations (1) to (8) can be adapted to drive the dual-channel devices. (The use of the dual-channel devices reduces the number of parts and the required board space.) Interfacing to TTL / TTL-Compatible Logic Interfacing the SFH67XX coupler to LS TTL or any other compatible logic is quite simple. The active output of this coupler eliminates the need for an external pull up resistor, and minimizes parts count and board space requirements. The typical connection is seen in figure 9. Even HCT logic can be interfaced this way.
HCT Input
VCC Data Out at CMOS Logic Level
0.1 µF GND
Fig. 10 - Interfacing to CMOS Logic Level via a HCT Device
Using the open collector device, as in figure 11, requires an external pull-up resistor RP . To determine the correct value of this pull-up resistor, use following equations:
TTL / LS TTL INPUT
VCC Data Out
NC 6 0.1 µF GND 5 GND
Fig. 9 - Interfacing the Coupler to TTL, LSTTL or Compatible Logic
Document Number: 83701 Rev. 1.2, 24-Apr-08
For technical questions, please contact: optocoupler.answers@vishay.com
www.vishay.com 1079
Application Note 73
Vishay Semiconductors
High-Speed / Logic Gate Optocoupler (SFH67XX Series)
in which CL represents the total capacitance of the load, including the coupler (which is around 6 pF). The resistor value is a compromise between the requirement of power dissipation and switching speed. A low RP produces symmetrical and fast switching times but results in a higher power dissipation. Reasonable values are shown in table 6. Details of the relationship between the rise time t r and the pull-up resistor RP / load capacitance CL are shown in figure 14.
SFH6705 1 NC 2 3 4 NC GND
Rp SFH6701 / 11
CMOS Input
Data Out GND
3.3 V Logic
Data Out
NC 6 0.1 µF GND 5 GND
Fig. 11 - Interfacing SFH6705 (Open Collector Output) to CMOS Logic
By using a totem pole device, the equations (9) and (10) are also valid, but the pull-up resistor has only to bring up the voltage difference between VOH ( VCC - 1.8 V) and the input switching limit, e.g. 3.5 V for HC logic, which makes a V of 0.3 V. This allows the use of a higher RP which results in lower power consumption.
Interfacing to other Levels
CMOS Input
VCC Data Out
If shifting to any other level is intended (e.g. 2.5 V logic, like the ALVC or ALVT series), the SFH6705 with its open collector output is qualified. RP works as a pull-up resistor to ensure the proper logic high level. The basic principles are the same as described in the section "interfacing to CMOS logic" in equations (9) to (12). Pull-Up Resistor Considerations for the Open Collector Type SFH6705
NC 6 0.1 µF GND 5 GND
Fig. 12 - Interfacing SFH67XX (Totem Pole Output) to CMOS Logic
TABLE 6
VCC 5V RP (OPEN COLLECTOR) RP (TOTEM POLE) 820 1.10 k
Typical values for Rp by connecting to CMOS logic (according to figures 11 and 12). Note that generally the RP value has a negligible influence on
www.vishay.com 1080 For technical questions, please contact: optocoupler.answers@vishay.com Document Number: 83701 Rev. 1.2, 24-Apr-08
Application Note 73
High-Speed / Logic Gate Optocoupler Vishay Semiconductors (SFH67XX Series)
SFH6719
VCC (top layer)
Rise Time, t r (ns)
1 10 100 RC Time Constant (ns) 1000
0.1 µF
GND (bottom layer)
Fig. 16 - Principle Board Layout for Enhanced CMTI (Fits to Schematic in Figure 18)
SFH6705 1 NC 2 3 4 NC GND
A circuit which enhances CMTI safety is shown in figure 17. The diode D1 is intended to sink parasitic current, which is caused by stray capacitance, away from the LED to prevent a false turn-on.
SFH6719 D1 VDD R1 Data IN
CMOS LOGIC
Fig. 15 - Test Circuit for Rise Time tr vs. Time Constant
COMMON-MODE TRANSIENT IMMUNITY (CMTI)
The SFH6711 / 12 / 19 feature a guaranteed common mode transient immunity (CMTI) of 2.5 kV / µs at 400 V. This is achieved by using a faraday shield which is transparent to infrared light, but electrically conducting. This shield prevents the photodiode from being turned on by common-mode transients. In general there are some design rules to achieve a high CMTI. These recommendations are especially important for low LED drive current devices, like the SFH67XX series: · Connect the unused pins 1 and 4 to the virtually grounded input potential (either GND or VDD). · Minimize stray capacitance. · Avoid long distances between LED input circuit and coupler. · Choose an appropriate high LED forward current to improve CMH (common mode transient immunity at logic "high" level). A layout which implements these hints is seen in figure 16. Note that this layout reduces creepage and clearance distance as well.
Fig. 17 - Input Circuitry for Improved CMTI
Document Number: 83701 Rev. 1.2, 24-Apr-08
For technical questions, please contact: optocoupler.answers@vishay.com
www.vishay.com 1081
Application Note 73
Vishay Semiconductors
High-Speed / Logic Gate Optocoupler (SFH67XX Series)
Pulse Width Distor tion, PWD (ns)
SFH6719 1 NC VDD R1 2 Data IN RS Q1 3 4 NC
GND Transistor Q1: Any switching transistor (e.g. 2N2222)
Fig. 18 - Input Circuitry for High CMTI
0 20 40 60 Temperature, TA (°C)
Propagation Delay Skew Propagation delay skew (tPSK) is the difference between the minimum propagation delay, either tPHL or tPLH, and the maximum propagation delay, either tPLH or tPHL, between any SFH67XX coupler under the same operation conditions. Propagation delay skew is therefore an important value for parallel data transmission, where synchronized data is needed.
Propagation Delay Skew, t PSK (ns)
SFH6719 1 NC VDD R3 2 Q1 Signal IN R4 GND
Fig. 19 - Balanced Input Impedance Circuitry
Transistor Q1: Any switching transistor
TA - Temperature (°C)
DYNAMIC OPERATION
www.vishay.com 1082
In logic circuits, the overall PWD and tPSK are determined by all input and output logic gates in the signal path. To minimize the overall PWD, two identical couplers may be used as shown in figure 22. But the minimum PWD is achieved at the cost of a higher overall propagation delay.
For technical questions, please contact: optocoupler.answers@vishay.com
Document Number: 83701 Rev. 1.2, 24-Apr-08
Application Note 73
High-Speed / Logic Gate Optocoupler Vishay Semiconductors (SFH67XX Series)
DESIGN IDEAS
74LS04
Optocouplers are commonly used as an interface between two circuits, where galvanic insulation is required, either to protect humans or sensitive electronic equipment. Based on this requirement, some designs are presented below, which use the SFH67XX series. IGBT / IPM Driver The SFH67XX series can be used as a fast driver for intelligent power modules (IPMs) using IGBT or MOSFET technology. The SFH67XX optocoupler series provide level shifting and galvanic insulation and is therefore the ideal interface to the control logic. With its guaranteed minimum 2.5 kV / µs at 400 V common mode transient immunity, the SFH671X also fulfills enhanced switching requirements. Switching Loads The SFH67XX series can easily handle currents up to 25 mADC and voltages up to 15 V. Figures 26 and 27 show how it can handle loads which are beyond these limits. In figure 26, R1 is used as a pull-up resistor and the load current is handled and limited by the external transistor Q1. Unlike figure 27, the schematic in figure 26 is qualified to support both high voltages and currents. The 5 V power supply might be raised up to 15 V to achieve a proper VGS voltage to turn the transistor fully on. The combination of the SFH67XX series with logic level power transistors provides a fast-switching solution that helps to reduce parts count.
74LS04
Fig. 22
Eye Pattern Diagram A typical eye pattern diagram for 5 Mb / s data transmission is presented in figure 23. The eye pattern testing was done with a pseudo random data sequence (NRZ coding).
Fig. 23
SFH6701 / 11 1 NC
Output Monitoring 5V
74LS04
0.1 µF
Input Monitoring
Fig. 24
Document Number: 83701 Rev. 1.2, 24-Apr-08
For technical questions, please contact: optocoupler.answers@vishay.com
www.vishay.com 1083
Application Note 73
Vishay Semiconductors
High-Speed / Logic Gate Optocoupler (SFH67XX Series)
+ VS IPM - Intelligent Power Module + HV
Galvanic Insulation + VCC SFH6711 1 NC BAR 74 5V 1.1 k Data IN
74HCT04
IGBT / MOSFET Driver
IGBT Module
Out 7 Protection / Suppression Unit
GND 5 GND
Fig. 25
LOAD R1 1 k Q1 BSP89 0.1µF BUZ104SL BUZ73L GND
Time Multiplexed Bus Line Access with Optical Insulation Barrier The schematic in figure 28 shows the use of a common data bus line with 4 independent data lines in time multiplexing mode. The 2-line to 4-line address decoder selects one of the 4 data lines by enabling the output, whereas all the other outputs remain in the high ohmic state. Opto-Insulated DAC Interface When galvanic insulation in digital-to-analog-conversion or analog-to-digital-conversion systems is required, the SFH67XX series is a good choice for an interface. Setups like the one in figure 29 provide a fast and part saving insulation barrier. The low propagation delay skew of the SFH67XX devices makes them ideal for use in parallel data transfer. The SFH67XX series provide an optimal interface solution for the SAB 80 C167 / C165 micro-controllers by supporting the 5 Mb / s data rate at a 20 MHz CPU clock.
Fig. 26
Transistor Q1: Any n-channel enhancement-mode transistor
Resistor R1: R1 might be omitted, depending on the necessary VGS of Q1 to turn Q1 fully on
SFH6711 1 NC 2 3 4 NC VCC 8 Out 7 NC 6 GND 5 0.1µF LOAD GND
VSS 1 k Q1 SP0610T
Fig. 27
Transistor Q1: Any p-channel enhancement-mode transistor
www.vishay.com 1084
For technical questions, please contact: optocoupler.answers@vishay.com
Document Number: 83701 Rev. 1.2, 24-Apr-08
Application Note 73
High-Speed / Logic Gate Optocoupler Vishay Semiconductors (SFH67XX Series)
Galvanic Insulation Barrier 5 SFH6700 / 19 1 NC 1.1 k 2 V CC 8 Out 7
Common Data Bus
0.1 µF Data Line 1
74HCT04
SFH6700 / 19 1 NC 1.1 k 2 Data Line 2 3 4 NC V CC 8 Out 7 0.1 µF
74HCT04
VE 6 GND 5 Y0 B Y1 74HCT139 2-Line to 4-Line Y2 Decoder G Out 7 0.1 µF VE 6 Y3 Enable A
Select Inputs
SFH6700 / 19 1 NC 1.1 k 2 Data Line 3 3 4 NC V CC 8
74HCT04
Truth Tabl e
Active on Bus Line None (all high ohmic) Data Line 1 Data Line 2 Data Line 3 Data Line 4
SFH6700 / 19 1 NC 1.1 k 2 3 4 NC V CC 8 Out 7 0.1 µF Data Line 4
74HCT04
Common Data Bus
Fig. 28 - Typical Setup for a Common Bus Line with 4 Different Lines in Time Multiplex Mode
Document Number: 83701 Rev. 1.2, 24-Apr-08
For technical questions, please contact: optocoupler.answers@vishay.com
www.vishay.com 1085
Application Note 73
Vishay Semiconductors
High-Speed / Logic Gate Optocoupler (SFH67XX Series)
5V 0.33 µF V CC FS D1 MAX845 Transformer Driver SD D2 GND1 GND2
Galvanic Insulation Barrier 78L05 + 0.33 µF
5V 2.2 µF
MAX873
0.33 µF
2 x BAW56 Diodes HALO TGM-030P3 Transformer V DD SFH6731 / 32
0.1 µF
SAB 80C167 Microcontroller Synchronous Serial Channel (SSC) / SPI P3.13 / SCLK CLK P3.9 / MTSR Data
74HCT04
REFAB CL SCLK 0.1 µF 6 DIN MAX525 Digital-to-Analog Converter OUTA FBB OUTB 10 k FBC 10 k CS 0.1 µF DOUT UPO PDL GNDD OUTD AGND OUTC FBD 10 k 10 k Channel C 0..5 V 10 k 10 k REFCD 10 k FBA 10 k Channel A 0..5 V
74HCT04
GND 5 SFH6701 / 11
Channel B 0..5 V
74HCT04
Channel D 0..5 V
Fig. 29 - Fully Galvanic Insulated Digital-to-Analog-Conversion System (4 Channel DAC)
Inverter 74HCT04 is used to allow 3 mA LED current
Any C16X micro-controller can be used
www.vishay.com 1086
For technical questions, please contact: optocoupler.answers@vishay.com
Document Number: 83701 Rev. 1.2, 24-Apr-08