SFH67XX series high-speed optocouplers capable transmitting data rates
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High-Speed/Logic Gate Optocoupler (SFH67XX Series)
SFH67XX series high-speed optocouplers capable transmitting data rates Mb/s typical Mb/s over full specified operating temperature range. combination input current (1.6 active logic-level output nearly logic applications where galvanic insulation necessary. SFH67XX series features positive logic with output levels. improved noise immunity detector incorporates schmitt-trigger stage. SFH6700/19 provides enable input, which allows switching output into high ohmic state applications. applications which need open collector output,
SFH6700/19 Anode Cathode Three-State-Output SFH6705 Anode Cathode
17850
SFH6705 offered.The SFH6731 SFH6732 dual versions. channels free crosstalk interference. ensure high common mode transient immunity guaranteed kV/µs SFH671X/6732 series features internal shield which consists additional layer. (indium oxide) layer optically transparent electrically conductive layer detector. standard SFH670X series withstands kV/µs SFH67XX series also available version (option with creepage clearance distance).
SFH6702/12 Anode Cathode Totem-Pole-Output SFH6731/32
SFH6701/11 Anode Cathode Totem-Pole-Output
Anode Cathode Cathode Anode
Open-Collector-Output
Dual/Totem-Pole-Output
Fig. Variations SFH67XX Family
TABLE
SFH6700/19 SFH6701/02/05/11/12/31/32 ENABLE OUTPUT
DESIGN CONSIDERATIONS
circuits shown below intended give design engineer guideline logic family interconnection. Input Circuitry Below stated most common interface circuits which work this coupler series. Totem Pole Drive Circuits Figures most commonly used circuits. designer chooses according equation:
Truth table (positive logic) logic high level, logic level, high ohmic state
(valid Figure
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Document Number: 83701 Rev. 1.2, 24-Apr-08
High-Speed/Logic Gate Optocoupler Vishay Semiconductors (SFH67XX Series)
(valid Figure coupler's typically input current threshold 0.50 negative temperature gradient input current threshold (see figure output leakage current driver element high temperatures become issue certain applications where circuit operated upper temperature range. critical applications, where high leakage current expected, shunt circuit, shown figure good solution.
Normalized Input Current Threshold
Temperature (°C)
SFH6700/19
TTL/
Data LOGIC
17851
Fig. Series Drive
SFH6700/19
TTL/ CMOS LOGIC
17853
Fig. Typical Input Current Threshold (Normalized) Temperature
Data
SFH6700/19
17854
17852
Fig. Series Drive
good compromise between power dissipation symmetrical propagation delays with respect some guard band some applications speed-up capacitor (typically around across used achieve faster switching times (please refer this section details).
Data CMOS LOGIC
TTL/
Fig. Shunt Drive Circuit with Leakage Current Protection
TABLE
FIGURE LOGIC GATE (E.G.) 74LS04 74LS04 74HCT04 VALUE 1.10 1.10
resistor determines forward current, shunts LED. choice depends power dissipation considerations expected leakage current. following equations help designers determine appropriate resistor values:
Typical values Both circuits simple feature minimal component count with power dissipation. logic source drive, shown figure recommended speed current limitations (especially CMOS logic family), lower common mode transient immunity.
Fmax(LEDoff) Leak Temp Leakage
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TABLE
VALUE VALUE
High-Speed/Logic Gate Optocoupler (SFH67XX Series)
SFH6700/19 Data Open Collector Drain
17856
Typical input circuit values shunt around away from (according figure better handle leakage current presented figure This circuit provides excellent speed properties leakage current protection. silicon diode ensures that current only sourced therefore required units driven open collector open drain. forward voltage ensures that stays logic low. equation choose
Fig. Open Collector/Drain Shunt Drive Circuit
TABLE
VALUE 1.10 2.80 4.42
Typical input circuit values circuit according figure Input Circuitry Improved Switching Speeds
SFH6700/19
TTL/ CMOS LOGIC
Data
switching speed concern, speed-up capacitor good solution. resistor limits peak transient current IFpeak, whereas determine current steady-state operation. equations reasonable resistor values printed below. reasonable value speed-up capacitor
SFH6700/19
17855
Fig. Logic Gate Shunt Drive Circuit
Open Collector Drive Circuits simple circuit, which also works open collector drive circuits, been presented figures figure resistor represents leakage current protection path. more efficient more power-dissipating solution presented figure This drive circuit provides good speed protection against leakage currents. resistor chosen accordance with
Data
TTL/ CMOS LOGIC
17857
Fig. Series Drive with Speed-up Capacitor
equations resistor values are:
Fpeak
Refer table some typical resistor values. Note that leakage protection generally might only issue some special applications.
maximum IFpeak this transient SFH67XX series.
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Document Number: 83701 Rev. 1.2, 24-Apr-08
High-Speed/Logic Gate Optocoupler Vishay Semiconductors (SFH67XX Series)
TABLE
VALUE VALUE VALUE
SFH67XX coupler family: Using SFH67XX (totem pole) pull-up resistor (see figure Using SFH6705 (open collector) pull-up resistor (see figure Using logic device (see figure Using device simplest most convenient solution eliminate external pull-up resistor (see figure 10). designer doesn't have worry about power consumption, rise times, system speed.
SFH6701/11
17858
Typical input circuit values circuit according figure Output Circuitry advantage SFH67XX series easy connection logic system, because active output stage (totem pole/three state output). Either directly pull-up resistor, couplers drive loads loads) easily. general, bypass capacitor strongly recommended proper operation. SFH6700/19 with three-state output fits best applications because possibility switch couplers output into high ohmic state (for typical setup please refer figure 28). Drive Circuits Dual-Channel Devices SFH6731/32 driven simply single channel devices. above drive circuits equations adapted drive dual-channel devices. (The dual-channel devices reduces number parts required board space.) Interfacing TTL/TTL-Compatible Logic Interfacing SFH67XX coupler other compatible logic quite simple. active output this coupler eliminates need external pull resistor, minimizes parts count board space requirements. typical connection seen figure Even logic interfaced this way.
Input
Data CMOS Logic Level
Fig. Interfacing CMOS Logic Level Device
Using open collector device, figure requires external pull-up resistor determine correct value this pull-up resistor, following equations:
CCmax OLmin Pmin OLmax
SFH6701/11
TTL/ INPUT
Data
where represents total load current level VOL. ensure VOLmax over temperature IOLmax should higher than mA). maximum value determined
CCmin IHmin Pmin OHmax
(10)
CMOS applications however, where region, limiting factor also determined maximum allowable rise time (500 logic). equation leads
18014
Fig. Interfacing Coupler TTL, LSTTL Compatible Logic
(11)
Interfacing CMOS Logic ensure reliable logic switching, pull-up resistor between output recommended (see Figures 12). logic family, this pull-up resistor omitted, matching switching level coupler's output input. There three simple ways connect CMOS logic
Document Number: 83701 Rev. 1.2, 24-Apr-08
Pmax IHmin CCmin
(12)
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High-Speed/Logic Gate Optocoupler (SFH67XX Series)
delay time strongly determines rise time, especially open collector type. Interfacing Level Interfacing logic families (e.g. AHC, quite easy, presented figure totem pole/three-state coupler operated with then output "high" level coupler, which then typically matches perfectly with logic input levels. general, output "high" voltage determined (Even with output voltage within limits, guaranteed higher than over temperature fulfill logic requirement).
which represents total capacitance load, including coupler (which around pF). resistor value compromise between requirement power dissipation switching speed. produces symmetrical fast switching times results higher power dissipation. Reasonable values shown table Details relationship between rise time pull-up resistor RP/load capacitance shown figure
SFH6705
17859
SFH6701/11
CMOS Input
Data
Logic
Data
Fig. Interfacing SFH6705 (Open Collector Output) CMOS Logic
17861
using totem pole device, equations (10) also valid, pull-up resistor only bring voltage difference between input switching limit, e.g. logic, which makes This allows higher which results lower power consumption.
Fig. Interfacing Logic with
Interfacing other Levels
SFH6701/11
17860
CMOS Input
Data
shifting other level intended (e.g. logic, like ALVC ALVT series), SFH6705 with open collector output qualified. works pull-up resistor ensure proper logic high level. basic principles same described section "interfacing CMOS logic" equations (12). Pull-Up Resistor Considerations Open Collector Type SFH6705
Fig. Interfacing SFH67XX (Totem Pole Output) CMOS Logic
previously mentioned above, pull-up resistor chosen accordance with equations (9), (10), (12). Figure plots expected rise time versus time constant Unlike rise time fall time mostly independent around
TABLE
(OPEN COLLECTOR) (TOTEM POLE) 1.10
Typical values connecting CMOS logic (according figures 12). Note that generally value negligible influence
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High-Speed/Logic Gate Optocoupler Vishay Semiconductors (SFH67XX Series)
1000
SFH6719
(top layer)
Rise Time, (ns)
Time Constant (ns) 1000
17863
18015
Fig. Typical Rise Time Load (Test Circuit Figure
(bottom layer)
Fig. Principle Board Layout Enhanced CMTI (Fits Schematic Figure
SFH6705
17862
Time
circuit which enhances CMTI safety shown figure diode intended sink parasitic current, which caused stray capacitance, away from prevent false turn-on.
SFH6719 Data
CMOS LOGIC
Fig. Test Circuit Rise Time Time Constant
COMMON-MODE TRANSIENT IMMUNITY (CMTI)
SFH6711/12/19 feature guaranteed common mode transient immunity (CMTI) kV/µs This achieved using faraday shield which transparent infrared light, electrically conducting. This shield prevents photodiode from being turned common-mode transients. general there some design rules achieve high CMTI. These recommendations especially important drive current devices, like SFH67XX series: Connect unused pins virtually grounded input potential (either VDD). Minimize stray capacitance. Avoid long distances between input circuit coupler. Choose appropriate high forward current improve (common mode transient immunity logic "high" level). layout which implements these hints seen figure Note that this layout reduces creepage clearance distance well.
17864
Fig. Input Circuitry Improved CMTI
Diode signaling diode Another input circuit high CMTI shown figure transistor shunts off-state prevents false turn This circuit tolerates very high common mode transients off-state. improvement on-state reached choosing high current. typically around
Document Number: 83701 Rev. 1.2, 24-Apr-08
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High-Speed/Logic Gate Optocoupler (SFH67XX Series)
required, e.g. systems which based pulse width modulation. transmission systems, should exceed minimum propagation delay time. forward current, SFH67xx typical around over temperature, which corresponds maximum Note that speed capacitor decreases tPLH might increase PWD.
Pulse Width Distor tion, (ns)
SFH6719 Data
17865
Transistor switching transistor (e.g. 2N2222)
Fig. Input Circuitry High CMTI
common achieve ultra-high CMTI presented figure balanced input impedance principle works with four resistors, used minimize noticeable current when transistor achieve maximum performance, stray capacitance from anode cathode output side coupler kept possible. Reasonable values with 2N2222 omitted. Note that omitted, depending transistor
17867
Temperature, (°C)
Fig. Typical Pulse Width Distortion over Temperature (Test Circuit Figure
Propagation Delay Skew Propagation delay skew (tPSK) difference between minimum propagation delay, either tPHL tPLH, maximum propagation delay, either tPLH tPHL, between SFH67XX coupler under same operation conditions. Propagation delay skew therefore important value parallel data transmission, where synchronized data needed.
Propagation Delay Skew, (ns)
SFH6719 Q1** Signal
17866
Fig. Balanced Input Impedance Circuitry
Resistor achieve balanced input impedance
Transistor switching transistor
17868
Temperature (°C)
DYNAMIC OPERATION
SFH67XX series active pull-up outputs offer guaranteed maximum propagation delay time over temperature well guaranteed Mb/s data rate over temperature. Pulse Width Distortion Pulse width distortion (PWD) defined difference between tPHL tPLH (PWD |tPHL tPLH|). This value important applications where symmetrical switching times
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Fig. Typical Propagation delay Skew over Temperature (Test Circuit Figure
logic circuits, overall tPSK determined input output logic gates signal path. minimize overall PWD, identical couplers used shown figure minimum achieved cost higher overall propagation delay.
technical questions, please contact: optocoupler.answers@vishay.com
Document Number: 83701 Rev. 1.2, 24-Apr-08
High-Speed/Logic Gate Optocoupler Vishay Semiconductors (SFH67XX Series)
DESIGN IDEAS
SFH6702/12 SFH6702/12
74LS04
Optocouplers commonly used interface between circuits, where galvanic insulation required, either protect humans sensitive electronic equipment. Based this requirement, some designs presented below, which SFH67XX series. IGBT/IPM Driver SFH67XX series used fast driver intelligent power modules (IPMs) using IGBT MOSFET technology. SFH67XX optocoupler series provide level shifting galvanic insulation therefore ideal interface control logic. With guaranteed minimum kV/µs common mode transient immunity, SFH671X also fulfills enhanced switching requirements. Switching Loads SFH67XX series easily handle currents mADC voltages Figures show handle loads which beyond these limits. figure used pull-up resistor load current handled limited external transistor Unlike figure schematic figure qualified support both high voltages currents. power supply might raised achieve proper voltage turn transistor fully combination SFH67XX series with logic level power transistors provides fast-switching solution that helps reduce parts count.
74LS04
17869
Fig.
Pattern Diagram typical pattern diagram Mb/s data transmission presented figure pattern testing done with pseudo random data sequence (NRZ coding).
17870
Fig.
SFH6701/11
Output Monitoring
74LS04
74LS04
Input Monitoring
17871
Fig.
Document Number: 83701 Rev. 1.2, 24-Apr-08
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High-Speed/Logic Gate Optocoupler (SFH67XX Series)
Intelligent Power Module
Galvanic Insulation SFH6711 Data
74HCT04
IGBT/MOSFET Driver
IGBT Module
Protection/ Suppression Unit
Fig.
17872
SFH6712
LOAD R1** BSP89 0.1µF BUZ104SL BUZ73L
17873
Time Multiplexed Line Access with Optical Insulation Barrier schematic figure shows common data line with independent data lines time multiplexing mode. 2-line 4-line address decoder selects data lines enabling output, whereas other outputs remain high ohmic state. Opto-Insulated Interface When galvanic insulation digital-to-analog-conversion analog-to-digital-conversion systems required, SFH67XX series good choice interface. Setups like figure provide fast part saving insulation barrier. propagation delay skew SFH67XX devices makes them ideal parallel data transfer. SFH67XX series provide optimal interface solution C167/C165 micro-controllers supporting Mb/s data rate clock.
Fig.
Transistor n-channel enhancement-mode transistor
Resistor might omitted, depending necessary turn fully
SFH6711 0.1µF LOAD
17874
SP0610T
Fig.
Transistor p-channel enhancement-mode transistor
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Document Number: 83701 Rev. 1.2, 24-Apr-08
High-Speed/Logic Gate Optocoupler Vishay Semiconductors (SFH67XX Series)
Galvanic Insulation Barrier SFH6700/19
Common Data
Data Line
74HCT04
SFH6700/19 Data Line
74HCT04
74HCT139 2-Line 4-Line Decoder Enable
Select Inputs
SFH6700/19 Data Line
74HCT04
Truth Tabl
Active Line None (all high ohmic) Data Line Data Line Data Line Data Line
SFH6700/19 Data Line
74HCT04
Common Data
17875
Fig. Typical Setup Common Line with Different Lines Time Multiplex Mode
Document Number: 83701 Rev. 1.2, 24-Apr-08
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High-Speed/Logic Gate Optocoupler (SFH67XX Series)
0.33 MAX845 Transformer Driver GND1 GND2
Galvanic Insulation Barrier 78L05 0.33
MAX873
0.33
BAW56 Diodes HALO TGM-030P3 Transformer SFH6731/32
80C167 Microcontroller** Synchronous Serial Channel (SSC)/SPI P3.13/SCLK P3.9/MTSR Data
74HCT04*
REFAB SCLK MAX525 Digital-to-Analog Converter OUTA OUTB DOUT GNDD OUTD AGND OUTC Channel REFCD Channel
74HCT04*
SFH6701/11
Channel
PX.Y
74HCT04*
Channel
17876
Fig. Fully Galvanic Insulated Digital-to-Analog-Conversion System Channel DAC)
Inverter 74HCT04 used allow current
C16X micro-controller used
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Document Number: 83701 Rev. 1.2, 24-Apr-08
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