PowerPAK® 1212 Mounting Thermal Considerations Johnson Zhao MOSFE

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PowerPAK® 1212 Mounting Thermal Considerations Johnson Zhao MOSFE

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PowerPAK® 1212 Mounting Thermal Considerations
Johnson Zhao MOSFETs switching applications available with resistances around with capability handle While these capabilities represent major advance over what available just years ago, important power MOSFET packaging technology keep pace. should obvious that degradation high performance package undesirable. PowerPAK package technology that addresses these issues. PowerPAK 1212-8 provides ultra-low thermal impedance small package that ideal space-constrained applications. this application note, PowerPAK 1212-8's construction described. Following this, mounting information presented. Finally, thermal electrical performance discussed. PowerPAK PACKAGE PowerPAK 1212-8 package (Figure derivative PowerPAK SO-8. utilizes same packaging technology, maximizing area. bottom attach exposed provide direct, resistance thermal path substrate device mounted PowerPAK 1212-8 thus translates benefits PowerPAK SO-8 into smaller package, with same level thermal performance. (Please refer application note "PowerPAK SO-8 Mounting Thermal Considerations.") PowerPAK 1212-8 footprint area comparable TSOP-6. over smaller than standard TSSOP-8. capacity more than twice size standard TSOP-6's. thermal performance order magnitude better than SO-8, times better than TSSOP-8. thermal performance better than current packages market. will take advantage board heat sink capability. Bringing junction temperature down also increases efficiency around compared with TSSOP-8. applications where bigger packages typically required solely thermal consideration, PowerPAK 1212-8 good option. Both single dual PowerPAK 1212-8 utilize same pin-outs single dual PowerPAK SO-8. 1.05 PowerPAK height profile makes both versions excellent choice applications with space constraints. PowerPAK 1212 SINGLE MOUNTING take advantage single PowerPAK 1212-8's thermal performance Application Note 826, Recommended Minimum Patterns With Outline Drawing Access Vishay Siliconix MOSFETs. Click PowerPAK 1212-8 single index this document. this figure, drain land pattern given make full contact drain PowerPAK package. This land pattern extended left, right, drawn pattern. This extension will serve increase heat dissipation decreasing thermal resistance from foot PowerPAK board therefore ambient. Note that increasing drain land area beyond certain point will yield little decrease foot-to-board foot-toambient thermal resistance. Under specific conditions board configuration, copper weight, layer stack, experiments have found that adding copper beyond area about will yield little improvement thermal performance.
Figure PowerPAK 1212 Devices
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PowerPAK 1212 DUAL take advantage dual PowerPAK 1212-8's thermal performance, minimum recommended land pattern found Application Note 826, Recommended Minimum Patterns With Outline Drawing Access Vishay Siliconix MOSFETs. Click PowerPAK 1212-8 dual index this document. between drain pads mils. This matches spacing drain pads PowerPAK 1212-8 dual package. This land pattern extended left, right, drawn pattern. This extension will serve increase heat dissipation decreasing thermal resistance from foot PowerPAK board therefore ambient. Note that increasing drain land area beyond certain point will yield little decrease foot-to-board foot-toambient thermal resistance. Under specific conditions board configuration, copper weight, layer stack, experiments have found that adding copper beyond area about will yield little improvement thermal performance.
ture profile used, temperatures time duration, shown Figures lead (Pb)-free solder profile, http://www.vishay.com/ doc?73257.
Ramp-Up Rate Temperature Temperature Above Maximum Temperature
/Second Maximum Seconds Maximum Seconds Seconds °C/Second Maximum
REFLOW SOLDERING Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices subjected solder reflow preconditioning test then reliability-tested using temperature cycle, bias humidity, HAST, pressure pot. solder reflow tempera-
Time Maximum Temperature Ramp-Down Rate
Figure Solder Reflow Temperature Profile
(max) (max) (max) (max) (min) Pre-Heating Zone Reflow Zone (max)
Maximum peak temperature allowed.
Figure Solder Reflow Temperatures Time Durations
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TABLE EQIVALENT STEADY STATE PERFORMANCE
Package Configuration Thermal Resiatance RthJC(C/W) SO-8 Single Dual TSSOP-8 Single Dual TSOP-8 Single Dual PPAK 1212 Single Dual PPAK SO-8 Single Dual
PowerPAK 1212 49.8
Standard SO-8
Standard TSSOP-8
TSOP-6
°C/W Board
°C/W
°C/W
°C/W
Figure Temperature Devices Board
THERMAL PERFORMANCE Introduction basic measure device's thermal performance junction-to-case thermal resistance, Rjc, junction foot thermal resistance, Rjf. This parameter measured device mounted infinite heat sink therefore characterization device only, other words, independent properties object which device mounted. Table shows comparison PowerPAK 1212-8, PowerPAK SO-8, standard TSSOP-8 SO-8 equivalent steady state performance. minimizing junction-to-foot thermal resistance, MOSFET temperature very close temperature board. Consider four devices mounted board with board temperature (Figure Suppose each device dissipating Using junction-to-foot thermal resistance characteristics PowerPAK 1212-8 other packages, temperatures determined 49.8 PowerPAK 1212-8, standard SO-8, standard TSSOP-8, TSOP-6. This rise above board temperature PowerPAK 1212-8, over other packages. rise minimal effect rDS(ON) whereas rise over will cause increase rDS(ON) high Spreading Copper Designers additional copper, spreading copper, drain conducting heat from device. helpful have some information about thermal performance given area spreading copper. Figure Figure show thermal resistance PowerPAK 1212-8 single dual devices mounted 2-in. 2-in., four-layer FR-4 boards. internal layers backside layer solid copper. internal layers were chosen solid copper model large power ground planes common many applications. layer back smaller area each step junction-to-ambient thermal resistance measurements were taken. results indicate that area above square inches spreading copper gives additional thermal performance improvement. subsequent experiment where copper back-side reduced, first stripes mimic circuit traces, then totally removed. significant effect observed.
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Spreading Copper (sq. in.) RthJA (°C/W) RthJ (°C/W) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 Spreading Copper (sq. in.)
Figure Spreading Copper Si7401DN
Figure Spreading Copper Junction-to-Ambient Performance
CONCLUSIONS derivative PowerPAK SO-8, PowerPAK 1212-8 uses same packaging technology been shown have same level thermal performance while having footprint that more than smaller than standard TSSOP-8. Recommended PowerPAK 1212-8 land patterns provided board layout designs using this package.
PowerPAK 1212-8 combines small size with attractive thermal characteristics. minimizing thermal rise above board temperature, PowerPAK simplifies thermal design considerations, allows device cooler, keeps rDS(ON) low, permits device handle more current than same- larger-size MOSFET standard TSSOP-8 SO-8 packages.
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Document Number 71681 03-Mar-06

PowerPAK® 1212 Mounting Thermal Considerations Johnson Zhao MOSFE

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