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ST6255C ST6265C ST6265B
8-bit MCUs with ADC, safe reset, auto-reload timer, EEPROM
Features 6.0V supply operating range maximum clock frequency +125°C operating temperature range Run, Wait Stop modes interrupt vectors Look-up table capability program memory Data storage program memory: user selectable size Data RAM: bytes Data EEPROM: bytes (not ST6255C) User programmable options pins, fully programmable Input with pull-up resistor Input without pull-up resistor Input with interrupt generation Open-drain push-pull output Analog Input lines sink drive LEDs TRIACs directly 8-bit Timer/Counter with 7-bit programmable prescaler 8-bit Auto-reload timer with 7-bit programmable prescaler Timer) Digital watchdog Oscillator safe guard (not ST6265B devices) voltage detector safe reset (not ST6265B devices) 8-bit converter with analog inputs 8-bit synchronous peripheral interface (SPI) On-chip clock oscillator driven quartz crystal, ceramic resonator network User configurable power-on reset external non-maskable interrupt ST626x-EMU2 Emulation Development System (connects MS-DOS parallel port)
PDIP28
PS028
SS0P28
CDIP28W
(See Datasheet Ordering Information)
Table Device summary
Partnumber ST6255C ST6265C ST6265B OTP/EPROM/ROM program memory (Bytes) 3884 3884 3884 EEPROM (Bytes)
March 2009
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Table Contents
Document Page
ST6255C ST6265C ST6265B
GENERAL DESCRIPTION INTRODUCTION DESCRIPTIONS MEMORY PROGRAMMING MODES CENTRAL PROCESSING UNIT INTRODUCTION REGISTERS CLOCKS, RESET, INTERRUPTS POWER SAVING MODES CLOCK SYSTEM DIGITAL WATCHDOG INTERRUPTS POWER SAVING MODES ON-CHIP PERIPHERALS PORTS TIMER AUTO-RELOAD TIMER CONVERTER (ADC) SERIAL PERIPHERAL INTERFACE (SPI) SOFTWARE ARCHITECTURE ADDRESSING MODES INSTRUCTION ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS CONVERTER CHARACTERISTICS TIMER CHARACTERISTICS CHARACTERISTICS ARTIMER ELECTRICAL CHARACTERISTICS PACKAGE MECHANICAL DATA ORDERING INFORMATION OTP/EPROM DEVICES FASTROM DEVICES DEVICES REVISION HISTORY
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GENERAL DESCRIPTION
INTRODUCTION ST6255C, ST6265C devices cost members ST62xx 8-bit HCMOS family microcontrollers, which targeted medium complexity applications. ST62xx devices based building block approach: common core surrounded number on-chip peripherals. ST62E65C erasable EPROM version ST62T65C device, which used emulate ST62T55C ST62T65C devices, well respective ST6255C ST6265C devices. EPROM devices functionally identical. based versions offer same functionality selecting options options defined programmable option byte OTP/ EPROM versions. devices offer advantages user programmability cost, which make them ideal choice wide range applications where frequent code changes, multiple code versions last minute programmability required. These compact low-cost devices feature Timer comprising 8-bit counter 7-bit programmable prescaler, 8-bit Auto-Reload Timer, EEPROM data capability (except ST62T55C), serial port communication interface, 8-bit Converter with analog inputs Digital Watchdog timer, making them well suited wide range automotive, appliance industrial applications.
Figure Block Diagram
8-BIT CONVERTER TEST/VPP TEST PORT INTERRUPT DATA USER SELECTABLE DATA
3884 bytes (ST62T55C, T65C, E65C) Bytes
PORT
PA0.PA7 PB0.PB5 Sink ARTimin Sink ARTimout Sink Tim1 Sout
PORT
PROGRAM MEMORY AUTORELOAD TIMER
DATA EEPROM
Bytes (ST62T65C/E65C)
TIMER
STACK LEVEL STACK LEVEL STACK LEVEL STACK LEVEL STACK LEVEL STACK LEVEL POWER SUPPLY
(SERIAL PERIPHERAL INTERFACE)
CORE
DIGITAL WATCHDOG
OSCILLATOR
RESET
OSCin OSCout
RESET
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DESCRIPTIONS VSS. Power supplied these pins. power connection ground connection. OSCin OSCout. These pins internally connected on-chip oscillator circuit. quartz crystal, ceramic resonator external clock signal connected between these pins. OSCin input pin, OSCout output pin. RESET. active-low RESET used restart microcontroller. TEST/VPP. TEST must held normal operation. TEST connected +12.5V level during reset phase, EPROM/ programming Mode entered. NMI. provides capability asynchronous interruption, applying external maskable interrupt MCU. input falling edge sensitive. provided with on-chip pullup resistor option been enabled), Schmitt trigger characteristics. PA0-PA7. These lines organized port (A). Each line configured under software control inputs with without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain push-pull outputs, analog inputs converter. PB0-PB5. These lines organized port (B). Each line configured under software control inputs with without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain push-pull outputs. PB0-PB5 also sink 30mA direct driving. PB6/ARTIMin, PB7/ARTIMout. These pins either Port bits Input Output pins TIMER. used timer input function programmed input with without pull-up. dedicated TIMER Mode Control Register sets timer output function. PB6-PB7 also sink 30mA direct driving. PC0-PC4. These lines organized port (C). Each line configured under software control input with without internal pullup resistor, interrupt generating input with pull-up resistor, analog input converter, opendrain push-pull output. also used Timer while PC2-PC4 also used respectively Data Data Clock pins on-chip carry synchronous serial signals. Figure Configuration
VPP/TEST ARTIMin/PB6 ARTIMout/PB7 Ain/PA1 Ain/PA2 PC0/Ain PC1/TIM1/Ain PC2/Sin/Ain PC3/Sout/Ain PC4/Sck/Ain RESET OSCout OSCin PA7/Ain PA6/Ain PA5/Ain PA4/Ain PA3/Ain
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MEMORY 1.3.1 Introduction operates three separate memory spaces: Program space, Data space, Stack space. Operation these three memory spaces described following paragraphs. Figure Memory Addressing Diagram Briefly, Program space contains user program code user vectors; Data space contains user data OTP, Stack space accommodates levels stack subroutine interrupt service routine nesting.
PROGRAM SPACE
DATA SPACE
0000h
000h EEPROM BANKING AREA 0-63 03Fh 040h DATA READ-ONLY MEMORY WINDOW 07Fh 080h 081h 082h 083h 084h 0C0h REGISTER REGISTER REGISTER REGISTER DATA READ-ONLY MEMORY WINDOW SELECT DATA BANK SELECT ACCUMULATOR
PROGRAM MEMORY
0FF0h INTERRUPT RESET VECTORS 0FFFh 0FFh
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MEMORY (Cont'd) 1.3.2 Program Space Program Space comprises instructions executed, data required immediate addressing mode instructions, reserved factory test area user vectors. Program Space addressed 12-bit Program Counter register register). Program Memory Protection Program Memory EPROM devices protected against external readout memory selecting READOUT PROTECTION option option byte. EPROM parts, READOUT PROTECTION option deactivated only U.V. erasure that also results into whole EPROM context erasure. Note: Once Readout Protection activated, longer possible, even STMicroelectronics, gain access contents. Returned parts with protection therefore accepted.
Figure Program Memory
0000h
RESERVED*
007Fh 0080h
USER PROGRAM MEMORY 3872 BYTES
0F9Fh 0FA0h 0FEFh 0FF0h 0FF7h 0FF8h 0FFBh 0FFCh 0FFDh 0FFEh 0FFFh
RESERVED* INTERRUPT VECTORS RESERVED VECTOR USER RESET VECTOR
Reserved areas should filled with 0FFh
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MEMORY (Cont'd) 1.3.3 Data Space Data Space accommodates data necessary processing user program. This space comprises resource, processor core peripheral registers, well read-only data such constants look-up tables OTP/ EPROM. Data read-only data physically stored program memory, which also accommodates Program Space. program memory consequently contains program code executed, well constants look-up tables required application. Data Space locations which different constants look-up tables addressed processor core thought 64-byte window through which possible access read-only data stored OTP/EPROM. Data RAM/EEPROM ST62T55C, ST62T65C ST62E65C devices, data space includes bytes RAM, accumulator (A), indirect registers (X), (Y), short direct registers (V), (W), port registers, peripheral data control registers, interrupt option register Data Window register (DRW register). Additional EEPROM pages also addressed using banks bytes located between addresses 3Fh. 1.3.4 Stack Space Stack space consists 12-bit registers which used stack subroutine interrupt return addresses, well current program counter contents. Table Additional RAM/EEPROM Banks
Device ST62T55C ST62T65C/E65C bytes bytes EEPROM bytes
Table Data Memory Space
EEPROM 000h 03Fh 040h 07Fh 080h 081h 082h 083h 084h 0BFh 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h* 0C9h* 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h 0D6h 0D7h 0D8h 0D9h 0DAh 0DBh 0DCh* 0DDh 0DEh 0DFh 0E0h 0E1h 0E2h 0E3h 0E7h 0E8h* 0E9h 0EAh 0EBh 0FEh 0FFh
DATA WINDOW AREA REGISTER REGISTER REGISTER REGISTER DATA BYTES PORT DATA REGISTER PORT DATA REGISTER PORT DATA REGISTER RESERVED PORT DIRECTION REGISTER PORT DIRECTION REGISTER PORT DIRECTION REGISTER RESERVED INTERRUPT OPTION REGISTER DATA WINDOW REGISTER RESERVED PORT OPTION REGISTER PORT OPTION REGISTER PORT OPTION REGISTER RESERVED DATA REGISTER CONTROL REGISTER TIMER PRESCALER REGISTER TIMER COUNTER REGISTER TIMER STATUS CONTROL REGISTER TIMER MODE CONTROL REGISTER TIMER STATUS/CONTROL REGISTER1 TIMER STATUS/CONTROL REGISTER2 WATCHDOG REGISTER TIMER RELOAD/CAPTURE REGISTER TIMER COMPARE REGISTER TIMER LOAD REGISTER OSCILLATOR CONTROL REGISTER MISCELLANEOUS RESERVED DATA REGISTER DIVIDER REGISTER MODE REGISTER RESERVED DATA RAM/EEPROM REGISTER RESERVED EEPROM CONTROL REGISTER RESERVED ACCUMULATOR
WRITE ONLY REGISTER
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MEMORY (Cont'd) 1.3.5 Data Window Register (DWR) Data read-only memory window located from address 0040h address 007Fh Data space. allows direct reading consecutive bytes located anywhere program memory, between address 0000h 0FFFh (top memory address depends specific device). program memory therefore used store either instructions read-only data. Indeed, window moved steps bytes along program memory writing appropriate code Data Window Register (DWR). addressed like location Data Space, however write-only register therefore cannot accessed using singlebit operations. This register used position 64-byte read-only data window (from address address Data space) program memory 64-byte steps. effective address byte read data program memory obtained concatenating least significant bits register address given instruction least significant bits) content register most significant bits), illustrated Figure below. instance, when addressing location 0040h Data Space, with loaded register, physical location addressed program memory 00h. register cleared reset, therefore must written prior first access Data readonly memory window area.
Data Window Register (DWR) Address: 0C9h Write Only
DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
Bits used. DWR5-DWR0: Data read-only memory Window Register Bits. These Data readonly memory Window bits that correspond upper bits data read-only memory space. Caution: This register undefined reset. Neither read single instructions used address this register. Note: Care required when handling register write only. this reason, contents should changed while executing interrupt service routine, service routine cannot save then restore register's previous contents. impossible avoid writing during interrupt service routine, image register must saved location, each time program writes DWR, must also write image register. image register must written first that, interrupt occurs between instructions, affected.
Figure Data read-only memory Window Memory Addressing
DATA WINDOW REGISTER CONTENTS (DWR) PROGRAM SPACE ADDRESS READ DATA SPACE ADDRESS 40h-7Fh INSTRUCTION
Example: DWR=28h DATA SPACE ADDRESS
ADDRESS:A19h
VR01573C
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MEMORY (Cont'd) 1.3.6 Data RAM/EEPROM (DRBR) Address: Write only
DRBR
Bank
Register
DRBR DRBR
These bits used DRBR4. This bit, when set, selects Page Reserved. These bits used. DRBR1. This bit, when set, selects EEPROM Page when available. DRBR0. This bit, when set, selects EEPROM Page when available. selection bank made programming Data Bank Switch register (DRBR register) located address Data Space according Table more than bank should time. DRBR register addressed like Data Space address E8h; nevertheless write only register that cannot accessed with single-bit operations. This register used select desired 64-byte RAM/EEPROM bank Data Space. bank number loaded DRBR register instruction point selected location bank (from address address). This register cleared during initialization, therefore must written before first access Data Space bank region. Refer
Data Space description additional information. DRBR register modified when interrupt subroutine occurs. Notes: Care required when handling DRBR register write only. this reason, allowed change DRBR contents while executing interrupt service routine, service routine cannot save then restore previous content. impossible avoid writing this register interrupt service routine, image this register must saved location, each time program writes DRBR must write also image register. image register must written first, interrupt occurs between instructions DRBR affected. DRBR Register, only must set. Otherwise more pages enabled parallel, producing errors. Care must also taken change page (when available) when parallel writing mode defined EECTL register. Table Data Bank Register Set-up
DRBR other ST62T55C None Available Available Available Page Reserved ST62T65C/E65C None EEPROM Page EEPROM Page Available Page Reserved
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MEMORY (Cont'd) 1.3.7 EEPROM Description EEPROM memory located 64-byte pages data space. This memory used user program non-volatile data storage. Data space from paged described Table EEPROM locations accessed directly addressing these paged sections data space. EEPROM does require dedicated instructions read write access. Once selected Data Bank Register, active EEPROM page controlled EEPROM Control Register (EECTL), which described below. E20FF EECTL register must reset prior write read access EEPROM. bank been selected, E2OFF set, access meaningless. Programming must enabled setting E2ENA EECTL register. E2BUSY EECTL register when EEPROM performing programming cycle. access EEPROM when E2BUSY meaningless. Provided E2OFF E2BUSY reset, EEPROM location read just like other data location, also terms access time. Writing EEPROM carried modes: Byte Mode (BMODE) Parallel Mode
(PMODE). BMODE, byte accessed time, while PMODE bytes same programmed simultaneously (with consequent speed power consumption advantages, latter being particularly important battery powered circuits). General Notes: Data should written directly intended address EEPROM space. There buffer memory between data EEPROM space. When EEPROM busy (E2BUSY "1") EECTL cannot accessed write mode, only possible read status E2BUSY. This implies that long EEPROM busy, possible change status EEPROM Control Register. EECTL bits reserved must never set. Care required when dealing with EECTL register, some bits write only. this reason, EECTL contents must altered while executing interrupt service routine. impossible avoid writing this register within interrupt service routine, image register must saved location, each time program writes EECTL must also write image register. image register must written first that, interrupt occurs between instructions, EECTL will affected.
Table Arrangement Parallel Writing EEPROM Locations
Dataspace addresses. Banks Byte ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 38h-3Fh 30h-37h 28h-2Fh 20h-27h 18h-1Fh 10h-17h 08h-0Fh 00h-07h bytes each programmed simultaneously Parallel Write mode. number available 64-byte banks device dependent.
Note: EEPROM disabled soon STOP instruction executed order achieve lowest power-consumption.
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MEMORY (Cont'd) Additional Notes Parallel Mode: user wishes perform parallel programming, first step should E2PAR2 bit. From this time EEPROM will addressed write mode, address data will latched will possible change them only programming cycle resetting E2PAR2 without programming EEPROM. After address latched, only "see" selected EEPROM attempt write read other rows will produce errors. EEPROM should read while E2PAR2 set. soon E2PAR2 set, volatile latches cleared. From this moment user load data part ROW. Setting E2PAR1 will modify EEPROM registers corresponding latches accessed after E2PAR2. example, software sets E2PAR2 accesses EEPROM writing addresses 18h, 1Bh, then sets E2PAR1, these three registers will modified simultaneously; remaining bytes will unaffected. Note that E2PAR2 internally reset programming cycle. This implies that user must E2PAR2 between parallel programming cycles. Note that user tries E2PAR1 while E2PAR2 set, there will programming cycle E2PAR1 will unaffected. Consequently, E2PAR1 cannot E2ENA low. E2PAR1 user, only E2ENA E2PAR2 bits also set. Notes: EEPROM page shall changed through DRBR register when E2PAR2 set.
EEPROM Control Register (EECTL) Address: Read/Write Reset status:
E2PA E2PA E2BU
Unused. E2OFF: Stand-by Enable Bit. WRITE ONLY. this EEPROM disabled (any access will meaningless) power consumption EEPROM reduced lowest value. D5-D4: Reserved. MUST kept reset. E2PAR1: Parallel Start Bit. WRITE ONLY. Once Parallel Mode, soon user software sets E2PAR1 bit, parallel writing adjacent registers will start. This internally reset programming procedure. Note that less than bytes written required, undefined bytes being unaffected parallel programming cycle; this explained greater detail Additional Notes Parallel Mode overleaf. E2PAR2: Parallel Mode Bit. WRITE ONLY. This must user program order perform parallel programming. E2PAR2 parallel start (E2PAR1) reset, adjacent bytes written simultaneously. These adjacent bytes considered row, whose address lines fixed while changing bits, illustrated Figure E2PAR2 automatically reset parallel programming procedure. reset user software before starting programming procedure, thus leaving EEPROM registers unchanged. E2BUSY: EEPROM Busy Bit. READ ONLY. This automatically EEPROM control logic when EEPROM programming mode. user program should test before EEPROM read write operation; attempt access EEPROM while busy will aborted writing procedure progress will completed. E2ENA: EEPROM Enable Bit. WRITE ONLY. This enables programming EEPROM cells. must before write EEPROM register. attempt write EEP-
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when E2ENA meaningless will trigger write cycle. PROGRAMMING MODES 1.4.1 Option Bytes Option Bytes allow configuration capability MCUs. Option byte's content automatically read, selected options enabled, when chip reset activated. only accessed during programming mode. This access made either automatically (copy from master device) selecting OPTION BYTE PROGRAMMING mode programmer. option bytes located non-user map. address specified. EPROM Code Option Byte (LSB)
PROTECT EXTCNTL PB2-3 PB0-1 WDACT PULL PULL DELAY
OSCIL OSGEN
EPROM Code Option Byte (MSB)
SYNCHRO PULL
D15-D13. Reserved. Must cleared. SYNCHRO. When set, conversion started upon WAIT instruction execution, order reduce supply noise. When this low, conversion started soon Converter Control Register set. D11-D10. Reserved, must cleared. PULL. Pull-Up. This must high configure with pull-up resistor. When low, pull-up provided.
LVD. RESET enable.When this set, safe RESET performed when supply voltage low. When this cleared, only power-on reset external RESET active. PROTECT. Readout Protection. This allows protection software contents against piracy. When PROTECT high, readout contents prevented hardware. When this low, user program read. EXTCNTL. External STOP MODE control. When EXTCNTL high, STOP mode available with watchdog active setting one. When EXTCNTL low, STOP mode available with watchdog active. PB2-3 PULL. When this removes pull-up reset PB2-PB3 pins. When cleared PB2-PB3 pins have internal pull-up resistor reset. PB0-1 PULL. When this removes pull-up reset PB0-PB1 pins. When cleared PB0-PB1 pins have internal pull-up resistor reset. WDACT. This controls watchdog activation. When high, hardware activation selected. software activation selected when WDACT low. DELAY. This enables selection delay internally generated after internal reset (external pin, LVD, watchdog activated) released. When DELAY low, delay 2048 cycles oscillator, 32768 cycles when DELAY high. OSCIL. Oscillator selection. When this low, oscillator must controlled quartz crystal, ceramic resonator external frequency. When high, oscillator must controlled network, with only resistor having externally provided. OSGEN. Oscillator Safe Guard. This must high enable Oscillator Safe Guard. When this low, disabled. Option byte written during programming either using menu driven Mode) automatically (stand-alone mode).
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PROGRAMMING MODES (Cont'd) 1.4.2 EPROM Erasing EPROM windowed package MCUs erased exposure Ultra Violet light. erasure characteristic MCUs such that erasure begins when memory exposed light with wave lengths shorter than approximately should noted that sunlight some types fluorescent lamps have wavelengths range thus recommended that window MCUs packages covered opaque label
prevent unintentional erasure problems when testing application such environment. recommended erasure procedure MCUs EPROM exposure short wave ultraviolet light which have wave-length 2537A. integrated dose (i.e. U.V. intensity exposure time) erasure should minimum 15Wsec/cm2. erasure time with this dosage approximately minutes using ultraviolet lamp with 12000µW/cm2 power rating. ST62E65C should placed within 2.5cm (1Inch) lamp tubes during erasure.
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CENTRAL PROCESSING UNIT
INTRODUCTION Core devices independent Memory configuration. such, thought independent central processor communicating with on-chip I/O, Memory Peripherals internal address, data, control buses. In-core communication arranged REGISTERS Family core features registers three pairs flags available programmer. These described following paragraphs. Accumulator (A). accumulator 8-bit general purpose register used arithmetic calculations, logical operations, data manipulations. accumulator addressed Data space location address FFh. Thus manipulate accumulator just like other register Data space. Indirect Registers These indirect registers used pointers memory locations Data space. They used register-indirect addressing mode. These registers addressed data space locations addresses (Y). They also accessed with direct, short direct, direct addressing modes. Accordingly, instruction indirect registers other register data space. Short Direct Registers These registers used save byte short direct addressing mode. They addressed Data space locations addresses (W). They also accessed using direct direct addressing modes. Thus, instruction short direct registers other register data space. Program Counter (PC). program counter 12-bit register which contains address next location processed core. This location opcode, operand, address operand. 12-bit length allows direct addressing 4096 bytes Program space. shown Figure controller being externally linked both Reset Oscillator circuits, while core linked dedicated on-chip peripherals serial data indirectly, interrupt purposes, through control registers.
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Figure Core Block Diagram
0,01 8MHz RESET OSCin OSCout
INTERRUPTS CONTROLLER DATA SPACE
OPCODE
FLAG VALUES
CONTROL SIGNALS ADDRESS/READ LINE
DATA RAM/EEPROM
PROGRAM ROM/EPROM ADDRESS DECODER A-DATA B-DATA
DATA ROM/EPROM DEDICATIONS ACCUMULATOR
Program Counter LAYER STACK
FLAGS RESULTS DATA SPACE (WRITE LINE) VR01811
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REGISTERS (Cont'd) However, program space contains more than 4096 bytes, additional memory program space addressed using Program Bank Switch register. value incremented after reading address current instruction. execute relative jumps, offset shifted through ALU, where they added; result then shifted back into program counter changed following ways: (Jump) instruction PC=Jump address CALL instruction Call address Relative Branch Instruction.PC= offset Interrupt PC=Interrupt vector Reset Reset vector RETI instructions (stack) Normal instruction Flags includes three pairs flags (Carry Zero), each pair being associated with three normal modes operation: Normal mode, Interrupt mode Maskable Interrupt mode. Each pair consists CARRY flag ZERO flag. pair (CN, used during Normal operation, another pair used during Interrupt mode (CI, ZI), third pair used Maskable Interrupt mode (CNMI, ZNMI). uses pair flags associated with current mode: soon interrupt Maskable Interrupt) generated, uses Interrupt flags (resp. flags) instead Normal flags. When RETI instruction executed, previously used flags restored. should noted that each flag only addressed context (Non Maskable Interrupt, Normal Interrupt Main routine). flags cleared during context switching thus retain their status. Carry flag when carry borrow occurs during arithmetic operations; otherwise cleared. Carry flag also value tested test instruction; also participates rotate left instruction. Zero flag result last arithmetic logical operation equal zero; otherwise cleared. Switching between three sets flags performed automatically when NMI, interrupt RETI instructions occurs. mode
automatically selected after reset MCU, core uses first flags. Stack. includes true LIFO hardware stack which eliminates need stack pointer. stack consists separate 12-bit locations that belong data space area. When subroutine call interrupt request) occurs, contents each level shifted into next higher level, while content shifted into first level (the original contents sixth stack level lost). When subroutine interrupt return occurs (RET RETI instructions), first level register shifted back into value each level popped back into previous level. Since accumulator, common with other data space registers, stored this stack, management these registers should performed within subroutine. stack will remain "deepest" position more than nested calls interrupts executed, consequently last return address will lost. will also remain highest position stack empty RETI executed. this case next instruction will executed. Figure Programming Mode
INDEX REGISTER REG. POINTER REG. POINTER REGISTER REGISTER ACCUMULATOR SHORT DIRECT ADDRESSING MODE
PROGRAM COUNTER
LEVELS STACK REGISTER
NORMAL FLAGS INTERRUPT FLAGS FLAGS
VA000423
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CLOCKS, RESET, INTERRUPTS POWER SAVING MODES
CLOCK SYSTEM features Main Oscillator which driven external clock, used conjunction with AT-cut parallel resonant crystal suitable ceramic resonator, with external resistor (RNET). addition, Frequency Auxiliary Oscillator (LFAO) switched security reasons, reduce power consumption, offer benefits back-up clock system. Oscillator Safeguard (OSG) option filters spikes from oscillator lines, provides access LFAO provide backup oscillator event main oscillator failure also automatically limits internal clock frequency (fINT) function VDD, order guarantee correct operation. These functions illustrated Figure Figure Figure Figure programmable divider FINT also provided order adjust internal clock best power consumption performance tradeoff. Figure illustrates various possible oscillator configurations using external crystal ceramic resonator, external clock input, external resistor (RNET), lowest cost solution using only LFAO. should have capacitance range oscillator frequency range. internal clock frequency (fINT) divided drive Timer, converter Watchdog timer, drive core, seen Figure With 8MHz oscillator frequency, fastest machine cycle therefore 1.625µs. machine cycle smallest unit time needed execute operation (for instance, increment Program Counter). instruction require two, four, five machine cycles execution. 3.1.1 Main Oscillator oscillator configuration specified selecting appropriate option. When CRYSTAL/ RESONATOR option selected, must used with quartz crystal, ceramic resonator external signal provided OSCin pin. When NETWORK option selected, system clock generated external resistor. main oscillator turned (when ENABLED option selected) setting OSCOFF Control Register. Frequency Auxiliary Oscillator automatically started. Figure Oscillator Configurations
CRYSTAL/RESONATOR CLOCK CRYSTAL/RESONATOR option
ST6xxx
OSCin
OSCout
CL1n
EXTERNAL CLOCK CRYSTAL/RESONATOR option
ST6xxx
OSCin
OSCout
NETWORK NETWORK option
ST6xxx
OSCin
OSCout
RNET
INTEGRATED CLOCK CRYSTAL/RESONATOR option ENABLED option
ST6xxx
OSCin
OSCout
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CLOCK SYSTEM (Cont'd) Turning main oscillator achieved resetting OSCOFF Converter Control Register resetting MCU. Restarting main oscillator implies delay comprising oscillator start delay period plus duration software instruction fLFAO clock frequency. 3.1.2 Frequency Auxiliary Oscillator (LFAO) Frequency Auxiliary Oscillator three main purposes. Firstly, used reduce power consumption timing critical routines. Secondly, offers fully integrated system clock, without external components. Lastly, acts safety oscillator case main oscillator failure. This oscillator available when ENABLED option selected. this case, automatically starts periods after first missing edge from main oscillator, whatever reason (main oscillator defective, clock circuitry provided, main oscillator switched off.). User code, normal interrupts, WAIT STOP instructions, processed normal, reduced fLFAO frequency. converter accuracy decreased, since internal frequency below 1MHz. power Frequency Auxiliary Oscillator starts faster than Main Oscillator. therefore feeds on-chip counter generating delay until Main Oscillator runs. Frequency Auxiliary Oscillator automatically switched soon main oscillator starts. ADCR Address: 0D1h Read/Write
ADCR ADCR ADCR ADCR ADCR ADCR ADCR
7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0: Control Register. These bits reserved Control. OSCOFF. When low, this enables main oscillator run. main oscillator switched when OSCOFF high. 3.1.3 Oscillator Safe Guard Oscillator Safe Guard (OSG) affords drastically increased operational integrity ST62xx devices. circuit provides three basic func-
tions: filters spikes from oscillator lines which would result over frequency ST62 CPU; gives access Frequency Auxiliary Oscillator (LFAO), used ensure minimum processing case main oscillator failure, offer reduced power consumption provide fixed frequency cost oscillator; finally, automatically limits internal clock frequency function supply voltage, order ensure correct operation even power supply should drop. enabled disabled choosing relevant option. viewed filter whose cross-over frequency device dependent. Spikes oscillator lines result effectively increased internal clock frequency. absence circuit, this lead over frequency given power supply voltage. filters such spikes illustrated Figure cases, when active, maximum internal clock frequency, fINT, limited fOSG, which supply voltage dependent. This relationship illustrated Figure When enabled, Frequency Auxiliary Oscillator accessed. This oscillator starts operating after first missing edge main oscillator (see Figure 10). Over-frequency, given power supply level, seen spikes; therefore filters some cycles order that internal clock frequency device kept within range particular device stand (depending VDD), below fOSG: maximum authorised frequency with enabled. Note. should used wherever possible provides maximum safety. Care must taken, however, increase power consumption reduce maximum operating frequency fOSG. Warning: Care taken when using OSG, internal frequency defined between minimum maximum value accurate. precise timing measurements, recommended should enabled applications that UART. should also noted that power consumption Stop mode higher when enabled (around 50µA nominal conditions room temperature).
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CLOCK SYSTEM (Cont'd) Figure Filtering Principle
Maximum Frequency device work correctly Actual Quartz Crystal Frequency OSCin Noise from OSCin Resulting Internal Frequency
VR001932
Figure Emergency Oscillator Principle
Main Oscillator
Emergency Oscillator
Internal Frequency
VR001933
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CLOCK SYSTEM (Cont'd) Oscillator Control Registers Address: Write only Reset State:
OSCR
Division Ratio
7-4. These bits used. Reserved. Cleared Reset. Must kept cleared. Reserved. Must kept low. RS1-RS0. These bits select division ratio Oscillator Divider order generate internal frequency. following selctions available:
Note: Care required when handling OSCR register some bits write only. this reason, allowed change OSCR contents while executing interrupt service routine, service routine cannot save then restore previous content. impossible avoid writing this register interrupt service routine, image this register must saved location, each time program writes OSCR must write also image register. image register must written first, interrupt occurs between instructions OSCR affected.
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CLOCK SYSTEM (Cont'd) Figure Clock Circuit Block Diagram
Core
TIMER fINT OSCILLATOR DIVIDER RS0,RS1 Watchdog
MAIN OSCILLATOR
LFAO
Main Oscillator
Figure Maximum Operating Frequency (fMAX) versus Supply Voltage (VDD)
Maximum FREQUENCY (MHz) FUNCTIONALITY GUARANTEED THIS AREA fOSG
fOSG 85°C)
fOSG 125°C)
SUPPLY VOLTAGE (VDD) VR01807J
Notes: this area, operation guaranteed quartz crystal frequency. When disabled, operation this area guaranteed crystal frequency. When enabled, operation this area guaranteed frequency least fOSG Min. When disabled, operation this
area guaranteed quartz crystal frequency. When enabled, access this area prevented. internal frequency kept fOSG. When disabled, operation this area guaranteed When enabled, access this area prevented. internal frequency kept fOSG.
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3.1.4 RESETS reset four ways: external Reset input being pulled low; Power-on Reset; digital Watchdog peripheral timing out. Voltage Detection (LVD) 3.1.5 RESET Input RESET connected device application board order reset required. RESET pulled RUN, WAIT STOP mode. This input used reset internal state ensure correct start-up procedure. active features Schmitt trigger input. internal Reset signal generated adding delay external signal. Therefore even short pulses RESET acceptable, provided completed rising phase that oscillator running correctly (normal WAIT modes). kept Reset state long RESET held low. RESET activation occurs WAIT modes, processing user program stopped (RUN mode only), Inputs Outputs configured inputs with pull-up resistors main Oscillator restarted. When level RESET then goes high, initialization sequence executed following expiry internal delay period. RESET activation occurs STOP mode, oscillator starts Inputs Outputs configured inputs with pull-up resistors. When level RESET then goes high, initialization sequence executed following expiry internal delay period. 3.1.6 Power-on Reset function circuit consists waking detecting around dynamic (rising edge) variation Supply. beginning this sequence, configured Reset state: ports configured inputs with pull-up resistors instruction executed. When power supply voltage rises sufficient level, oscillator starts operate, whereupon internal delay initiated, order allow oscillator fully stabilize before executing first instruction. initialization sequence
executed immediately following internal delay. ensure correct start-up, user should take care that Supply stabilized sufficient level chosen frequency (see recommended operation) before reset signal released. addition, supply rising must start from consequence, does allow supervise static, slowly rising, falling, noisy (presenting oscillation) supplies. external network connected RESET pin, reset used instead best performances. Figure Reset Interrupt Processing
RESET
MASK LATCH CLEARED PRESENT
SELECT MODE FLAGS
FFEH ADDRESS
RESET STILL PRESENT?
LOAD FROM RESET LOCATIONS FFE/FFF
FETCH INSTRUCTION VA000427
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RESETS (Cont'd) 3.1.7 Watchdog Reset provides Watchdog timer function order ensure graceful recovery from software upsets. Watchdog register refreshed before end-of-count condition reached, internal reset will activated. This, amongst other things, resets watchdog counter. restarts just though Reset been generated RESET pin, including built-in stabilisation delay period. 3.1.8 Reset on-chip Voltage Detector, selectable user option, features static Reset when supply voltage below reference value. Thanks this feature, external reset circuit removed while keeping application safety. This SAFE RESET effective well Power-on phase power supply drop with different reference val-
ues, allowing hysteresis effect. Reference value case voltage drop been lower than reference value power-on order avoid parasitic Reset when start's running sinking current supply. long supply voltage below reference value, there internal static RESET command. start only when supply voltage rises over reference value. Therefore, only operating mode exist MCU: RESET active below voltage reference, running mode over voltage reference shown Figure that represents powerup, power-down sequence. Note: When RESET state controlled internal RESET sources (Low Voltage Detector, Watchdog, Power Reset), RESET tied logic level.
Figure Reset Power-on Power-down (Brown-out)
RESET
RESET
time VR02106A
3.1.9 Application Notes external resistor required between Reset pin, thanks built-in pull-up device.
Direct external connection RESET must avoided order ensure safe behaviour internal reset sources (AND.Wired structure).
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RESETS (Cont'd) 3.1.10 Initialization Sequence When reset occurs stack reset, loaded with address Reset Vector (located program starting address 0FFEh). jump beginning user program must coded this address. Following Reset, Interrupt flag automatically set, that Maskable Interrupt mode; this prevents initialisation routine from being interrupted. initialisation routine should therefore terminated RETI instruction, order revert normal mode enable interrupts. pending interrupt present initialisation routine, will continue processing instruction immediately following RETI instruction. however, pending interrupt present, will serviced.
Figure Reset Interrupt Processing
RESET
RESET VECTOR
JP:2 BYTES/4 CYCLES
INITIALIZATION ROUTINE RETI
RETI: BYTE/2 CYCLES
VA00181
Figure Reset Block Diagram
fOSC
INTERNAL RESET COUNTER
RESD1) RESET AND. Wired RESET
RESET
POWER RESET WATCHDOG RESET RESET
VR02107A
Resistive protection. Value guaranteed.
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RESETS (Cont'd) Table Register Reset Status
Register Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control TIMER Mode Control Register TIMER Status/Control Register TIMER Status/Control Register TIMER Compare Register TIMER Load Register Miscellaneous Register Registers Register Register Register Register Accumulator Data Data EEPROM Page Register Data Window Register EEPROM Result Register TIMER Load Register TIMER Reload/Capture Register TIMER Counter Register TIMER Prescaler Register Watchdog Counter Register Control Register Address(es) 0DCh 0EAh 0C0h 0C2h 0C4h 0C6h 0CCh 0CEh 0C8h 0D4h 0D5h 0D6h 0D7h 0DAh 0DBh 0DDh 0E0h 0E2h 0E1h 0E2h 0E0h 080H 083H 0FFh 084h 0BFh 0E8h 0C9h 03Fh 0D0h 0DBh 0D9h 0D3h 0D2h 0D8h 0D1h Standby count loaded Undefined written programmed Status Undefined Output connected disabled disabled disabled disabled Comment EEPROM disabled available) Input with pull-up Input with pull-up Input with pull-up Interrupt disabled TIMER disabled TIMER stopped
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DIGITAL WATCHDOG digital Watchdog consists reloadable downcounter timer which used provide controlled recovery from software upsets. Watchdog circuit generates Reset when downcounter reaches zero. User software prevent this reset reloading counter, should therefore written that counter regularly reloaded while user program runs correctly. event software mishap (usually caused externally generated interference), user program will longer behave usual fashion timer register will thus reloaded periodically. Consequently timer will decrement down reset MCU. order maximise effectiveness Watchdog function, user software must written with this concept mind. Watchdog behaviour governed options, known "WATCHDOG ACTIVATION" (i.e. HARDWARE SOFTWARE) "EXTERNAL STOP MODE CONTROL" (see Table SOFTWARE option, Watchdog disabled until DWDR register been set. When Watchdog disabled, power Stop mode available. Once activated, Watchdog cannot disabled, except resetting MCU. HARDWARE option, Watchdog permanently enabled. Since oscillator will continuously, power mode available. STOP instruction interpreted WAIT instruction, Watchdog continues countdown. However, when EXTERNAL STOP MODE CONTROL option been selected power consumption achieved Stop Mode. Execution STOP instruction then governed secondary function associated with pin. STOP instruction encountered when low, interpreted WAIT, described above. however, STOP instruction encountered when high, Watchdog counter frozen enters STOP mode. When exits STOP mode (i.e. when interrupt generated), Watchdog resumes activity.
Table Recommended Option Choices
Functions Required Stop Mode Watchdog Stop Mode Watchdog Recommended Options "EXTERNAL STOP MODE" "HARDWARE WATCHDOG" "SOFTWARE WATCHDOG" "HARDWARE WATCHDOG"
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DIGITAL WATCHDOG (Cont'd) Watchdog associated with Data space register (Digital WatchDog Register, DWDR, location 0D8h) which described greater detail Section 3.2.1 Digital Watchdog Register (DWDR). This register 0FEh Reset: cleared "0", which disables Watchdog; timer downcounter bits, "1", thus selecting longest Watchdog timer period. This time period user's requirements setting appropriate value bits DWDR register. must "1", since this which generates Reset signal when changes "0"; clearing this would generate immediate Reset. should noted that order bits DWDR register inverted with respect associated bits down counter: DWDR register corresponds, fact, user should bear mind fact that these bits inverted shifted with respect physical counter bits when writing this register. relationship between DWDR register bits physical implementation Watchdog timer downcounter illustrated Figure Only most significant bits used define time period, since which triggers Reset when changes "0". This offers user choice timed periods ranging from 3,072 196,608 clock cycles (with oscillator frequency 8MHz, this equivalent timer periods ranging from 384µs 24.576ms).
Figure Watchdog Counter Control
WATCHDOG COUNTER
RESET
WATCHDOG CONTROL REGISTER
VR02068A
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DIGITAL WATCHDOG (Cont'd) 3.2.1 Digital Watchdog Register (DWDR) Address: 0D8h Read/Write Reset status: 1111 1110b
3.2.1.1
Watchdog Control hardware option selected, this forced high user cannot change (the Watchdog always active). When software option selected, Watchdog function activated setting cannot then disabled (save resetting MCU). When kept counter used 7-bit timer. This cleared Reset. Software Reset This triggers Reset when cleared. When (Watchdog disabled) 7-bit timer. This Reset. Bits T5-T0: Downcounter bits should noted that register bits reversed shifted with respect physical counter: bit-7 (T0) Watchdog downcounter bit-2 (T5) MSB. These bits Reset. 3.2.2 Application Notes Watchdog plays important supporting role high noise immunity ST62xx devices,
should used wherever possible. Watchdog related options should selected basis trade-off between application security STOP mode availability. When STOP mode required, hardware activation without EXTERNAL STOP MODE CONTROL should preferred, provides maximum security, especially during power-on. When STOP mode required, hardware activation EXTERNAL STOP MODE CONTROL should chosen. should high default, allow STOP mode entered when idle. connected line (see Figure allow state controlled software. line then used keep while Watchdog protection required, avoid noise bounce. When more processing required, line released device placed STOP mode lowest power consumption. When software activation selected Watchdog activated, downcounter used simple 7-bit timer (remember that bits reverse order). software activation option should chosen only when Watchdog counter used timer. ensure Watchdog been unexpectedly activated, following instructions should executed within first instructions: 0FDH
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DIGITAL WATCHDOG (Cont'd) These instructions test Reset (i.e. disable Watchdog) (i.e. Watchdog active), thus disabling Watchdog. modes, minimum instructions executed after activation, before Watchdog generate Reset. Consequently, user software should load watchdog counter within first instructions following Watchdog activation (software mode), within first instructions executed following Reset (hardware activation). should noted that when (interrupts disabled), interrupt active cannot cause wake from STOP/WAIT modes.
Figure typical circuit making EXERNAL STOP MODE CONTROL feature
SWITCH
VR02002
Figure Digital Watchdog Block Diagram
RESET
RSFF
DB1.7 LOAD
OSCILLATOR CLOCK
WRITE RESET DATA
VA00010
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INTERRUPTS manage four Maskable Interrupt sources, addition Maskable Interrupt source (top priority interrupt). Each source associated with specific Interrupt Vector which contains Jump instruction associated interrupt service routine. These vectors located Program space (see Table When interrupt source generates interrupt request, interrupt processing enabled, register loaded with address interrupt vector (i.e. Jump instruction), which then causes Jump relevant interrupt service routine, thus servicing interrupt. Interrupt sources linked events either external pins, chip peripherals. Several events ORed same interrupt source, relevant flags available determine which event triggered interrupt. Maskable Interrupt request highest priority interrupt interrupt routine time; other four interrupts cannot interrupt each other. more than interrupt request pending, these processed processor core according their priority level: source higher priority while source lower. priority each interrupt source fixed. Table Interrupt Vector
Interrupt Source Interrupt source Interrupt source Interrupt source Interrupt source Interrupt source Priority Vector Address (FFCh-FFDh) (FF6h-FF7h) (FF4h-FF5h) (FF2h-FF3h) (FF0h-FF1h)
ically reset core beginning nonmaskable interrupt service routine. Interrupt request from source configured either edge level sensitive setting accordingly Interrupt Option Register (IOR). Interrupt request from source always edge sensitive. edge polarity configured setting accordingly Interrupt Option Register (IOR). Interrupt request from sources level sensitive. edge sensitive mode, latch when edge occurs interrupt source line cleared when associated interrupt routine started. occurrence interrupt stored, until completion running interrupt routine before being processed. several interrupt requests occurs before completion running interrupt routine, only first request stored. Storage interrupt requests available level sensitive mode. taken into account, level must present interrupt when samples line after instruction execution. every instruction, tests interrupt lines: there interrupt request next instruction executed appropriate interrupt service routine executed instead. Table Interrupt Option Register Description
CLEARED Enable interrupts Disable interrupts Rising edge mode interrupt source Falling edge mode interrupt source Level-sensitive mode interrupt source Falling edge mode interrupt source
3.3.1 Interrupt request interrupt sources Maskable Interrupt source disabled setting accordingly Interrupt Option Register (IOR). This also defines interrupt source, including Maskable Interrupt source, restart from STOP/WAIT modes. Interrupt request from Maskable Interrupt source latched flip flop which automat-
CLEARED CLEARED OTHERS USED
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INTERRUPTS (Cont'd) 3.3.2 Interrupt Procedure interrupt procedure very similar call procedure, indeed user consider interrupt asynchronous call procedure. this asynchronous event, user cannot know context time which occurred. result, user should save Data space registers which used within interrupt routines. There separate sets processor flags normal, interrupt non-maskable interrupt modes, which automatically switched need saved. following list summarizes interrupt procedure: interrupt detected. flags replaced interrupt flags flags). contents stored first level stack. normal interrupt lines inhibited (NMI still active). first internal latch cleared. associated interrupt vector loaded WARNING: some circumstances, when maskable interrupt occurs while core NORMAL mode especially during execution "ldi IOR, 00h" instruction (disabling maskable interrupts): interrupt arrives during first cycles "ldi" instruction (which 4-cycle instruction) core will switch interrupt mode flags will switch interrupt pair User User selected registers saved within interrupt service routine (normally software stack). source interrupt found polling interrupt flags more than source associated with same vector). interrupt serviced. Return from interrupt (RETI)
Automatically switches back normal flag interrupt flag set) pops previous value from stack. interrupt routine usually begins identifying device which generated interrupt request polling). user should save registers which used within interrupt routine software stack. After RETI instruction executed, returns main routine. Figure Interrupt Processing Flow Chart
INSTRUCTION
FETCH INSTRUCTION
EXECUTE INSTRUCTION
INSTRUCTION RETI
LOAD FROM INTERRUPT VECTOR (FFC/FFD)
CLEAR INTERRUPT MASK
CORE ALREADY NORMAL MODE?
INTERRUPT MASK
PUSH INTO STACK
SELECT PROGRAM FLAGS
SELECT INTERNAL MODE FLAG
"POP" STACKED
CHECK THERE INTERRUPT REQUEST INTERRUPT MASK
VA000014
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INTERRUPTS (Cont'd) 3.3.3 Interrupt Option Register (IOR) Interrupt Option Register (IOR) used enable/disable individual interrupt sources select operating mode external interrupt inputs. This register write-only cannot accessed single-bit operations. Address: 0C8h Write Only Reset status:
ESB: Edge Selection bit. selects polarity interrupt source GEN: Global Enable Interrupt. When this one, interrupts enabled. When this cleared zero interrupts (excluding NMI) disabled. When low, interrupt active cannot cause wake from STOP/WAIT modes. This register cleared reset. 3.3.4 Interrupt sources Interrupt sources available these MCUs summarized Table with associated mask enable/disable interrupt request.
Bits Unused. LES: Level/Edge Selection bit. When this one, interrupt source level sensitive. When cleared zero edge sensitive mode interrupt request selected. Table Interrupt Requests Mask Bits
Peripheral GENERAL TIMER CONVERTER TIMER Port Port Port Register TSCR1 ADCR ARMC SPIMOD ORPA-DRPA ORPB-DRPB ORPC-DRPC Address Register C0h-C4h C1h-C5h C2h-C6h
Mask OVIE CPIE SPIE ORPAn-DRPAn ORPBn-DRPBn ORPCn-DRPCn
Masked Interrupt Source
Interrupt vector Vector Vector Vector Vector Vector Vector Vector
Interrupts, excluding
TMZ: TIMER Overflow EOC: Conversion OVF: TIMER Overflow CPF: Successful compare Active edge ARTIMin SPRUN: Transmission
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INTERRUPTS (Cont'd) Figure Interrupt Block Diagram
FROM REGISTER PORT A,B,C SINGLE ENABLE
PORT PORT Bits
Start RESTART FROM STOP/WAIT (FF6,7)
REG. C8H,
PORT Bits
SPIDIV Register SPINT SPIE SPIMOD Register
REG. C8H, OVIE Start
(FF4,5)
TIMER CPIE TIMER1 Start (IOR Register)
(FF2,3)
(FF0,1)
(FFC,D)
VA0426K
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POWER SAVING MODES WAIT STOP modes have been implemented ST62xx family MCUs order reduce product's electrical consumption during idle periods. These power saving modes described following paragraphs. 3.4.1 WAIT Mode goes into WAIT mode soon WAIT instruction executed. microcontroller considered being "software frozen" state where core stops processing program instructions, contents peripheral registers preserved long power supply voltage higher than retention voltage. this mode peripherals still active. WAIT mode used when user wants reduce power consumption during idle periods, while losing track time capability monitoring external events. active oscillator stopped order provide clock signal peripherals. Timer counting enabled well Timer interrupt, before entering WAIT mode: this allows WAIT mode exited when Timer interrupt occurs. same applies other peripherals which clock signal. WAIT mode exited Reset (either activating external generated Watchdog), enters normal reset procedure. interrupt generated during WAIT mode, MCU's behaviour depends state processor core prior WAIT instruction, also kind interrupt request which generated. This described following paragraphs. processor core does generate delay following occurrence interrupt, because oscillator clock still available stabilisation period necessary. 3.4.2 STOP Mode Watchdog disabled, STOP mode available. When STOP mode, placed lowest power consumption mode. this operating mode, microcontroller considered being "frozen", instruction executed, oscillator stopped, contents peripheral registers preserved long power supply voltage higher than retention voltage, ST62xx core waits occurrence external interrupt request Reset exit STOP state. STOP state exited Reset activating external pin) will enter normal reset procedure. Behaviour response interrupts depends state processor core prior issuing STOP instruction, also kind interrupt request that generated. This case will described following paragraphs. processor core generates delay after occurrence interrupt request, order wait complete stabilisation oscillator, before executing first instruction.
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POWER SAVING MODE (Cont'd) 3.4.3 Exit from WAIT STOP Modes following paragraphs describe exits from WAIT STOP modes, when interrupt occurs (not Reset). should noted that restart sequence depends original state (normal, interrupt non-maskable interrupt mode) prior entering WAIT STOP mode, well interrupt type. Interrupts affect oscillator selection. Normal Mode main routine when WAIT STOP instruction executed, exit from Stop Wait mode will occur soon interrupt occurs; related interrupt routine executed and, completion, instruction which follows STOP WAIT instruction then executed, providing other interrupts pending. Maskable Interrupt Mode STOP WAIT instruction been executed during execution non-maskable interrupt routine, exits from Stop Wait mode soon interrupt occurs: instruction which follows STOP WAIT instruction executed, remains non-maskable interrupt mode, even another interrupt been generated. Normal Interrupt Mode interrupt mode before STOP WAIT instruction executed, exits from STOP WAIT mode soon interrupt occurs. Nevertheless, cases must considered: interrupt normal one, interrupt routine which WAIT STOP mode
tered will completed, starting with execution instruction which follows STOP WAIT instruction, still interrupt mode. this routine pending interrupts will serviced accordance with their priority. event non-maskable interrupt, non-maskable interrupt service routine processed first, then routine which WAIT STOP mode entered will completed executing instruction following STOP WAIT instruction. remains normal interrupt mode. Notes: achieve lowest power consumption during WAIT modes, user program must take care configuring unused I/Os inputs without pull-up (these should externally tied well defined logic levels); placing peripherals their power down modes before entering STOP mode; When hardware activated Watchdog selected, when software Watchdog enabled, STOP instruction disabled WAIT instruction will executed place. interrupt sources disabled (GEN low), only restarted Reset. Although setting does mask interrupt, will stop generating wake-up signal. WAIT STOP instructions executed enabled interrupt request pending.
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ON-CHIP PERIPHERALS
PORTS features Input/Output lines which individually programmed following input output configurations: Input without pull-up interrupt Input with pull-up interrupt Input with pull-up, without interrupt Analog input Push-pull output Open drain output lines organised bytewise Ports. Each port associated with registers Data space. Each these registers associated with particular line (for instance, bits Port Data, Direction Option registers associated with line Port DATA registers (DRx), used read voltage level values lines which have been configured inputs, write logic value signal output lines configured outputs. port data registers read effective logic levels pins, they Figure Port Block Diagram
CONTROLS RESET
also written user software, conjunction with related option registers, select different input mode options. Single-bit operations registers possible care necessary because reading input mode done from pins while writing will directly affect Port data register causing undesired change input configuration. Data Direction registers (DDRx) allow data direction (input output) each set. Option registers (ORx) used select different port options available both input output mode. registers read written just other location Data space, extra cells needed port data storage manipulation. During initialization, registers cleared input mode with pull-ups interrupt generation selected pins, thus avoiding conflicts.
DATA DIRECTION REGISTER
INPUT/OUTPUT DATA REGISTER SHIFT REGISTER OPTION REGISTER
SOUT INTERRUPT
VA00413
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PORTS (Cont'd) 4.1.1 Operating Modes Each individually programmed input output with various configurations. This achieved writing relevant Data (DR), Data Direction (DDR) Option registers (OR). Table illustrates various port configurations which selected user software. Input Options Pull-up, High Impedance Option. input lines individually programmed with without internal pull-up programming registers accordingly. pull-up option selected, input will high-impedance state. Table Port Option Selection
Mode Input Input Input Input Output Output
Interrupt Options input lines individually connected software interrupt system programming registers accordingly. interrupt trigger modes (falling edge, rising edge level) configured software described Interrupt Chapter each port. Analog Input Options Some pins configured analog inputs programming registers accordingly. These analog inputs connected onchip 8-bit Analog Digital Converter. ONLY should programmed analog input time, since selecting more than input simultaneously their pins will effectively shorted.
Option With pull-up, interrupt pull-up, interrupt With pull-up with interrupt Analog input (when available) Open-drain output (20mA sink when available) Push-pull output (20mA sink when available)
Note: Don't care
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PORTS (Cont'd) 4.1.2 Safe State Switching Sequence Switching ports from state another should done sequence which ensures that unwanted side effects occur. recommended safe transitions illustrated Figure other transitions potentially risky should avoided when changing operating mode, most likely that undesirable sideeffects will experienced, such spurious interrupt generation pins shorted together analog multiplexer. Single instructions (SET, RES, DEC) should used with great caution Ports Data registers, since these instructions make implicit read write back entire register. port input mode, however, data register reads from input pins directly, from data register latches. Since data register information input mode used characteristics input (interrupt, pull-up, analog input), these unintentionally reprogrammed depending state input pins. general rule, better limit single instructions data registers when whole (8-bit) port output mode. case inputs mixed inputs
outputs, advisable keep copy data register RAM. Single instructions then used copy, after which whole copy register written port data register: bit, datacopy datacopy DRA, Warning: Care must also taken instructions that whole port register (INC, DEC, read operations) when bits available device. Unavailable bits must masked software (AND instruction). WAIT STOP instructions allow ST62xx used situations where power consumption needed. lowest power consumption achieved configuring I/Os input mode with well-defined logic levels. user must take care switch outputs with heavy loads during conversion analog inputs order avoid disturbance conversion.
Figure Diagram showing Safe State Transitions Interrupt pull-up Input pull-up (Reset state) Output Open Drain Output Push-pull Input Analog Input
010*
Output Open Drain Output Push-pull
Note DDR, Bits respectively
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PORTS (Cont'd) Table Port Option Selections
MODE AVAILABLE ON(1) SCHEMATIC
PA0-PA7 Input PB0-PB5, PB6-PB7 PC0-PC4 Data Interrupt
Input with pull
PA0-PA7 PB0-PB5, PB6-PB7 PC0-PC4 Data Interrupt
Input with pull with interrupt
PA0-PA7 PB0-PB5, PB6-PB7 PC0-PC4 Data Interrupt
Analog Input
PA0-PA7 PC0-PC4
Open drain output
PA0-PA7 PC0-PC4 Data
Open drain output 30mA Push-pull output
PB0-PB5, PB6-PB7
PA0-PA7 PC0-PC4 Data
Push-pull output 30mA
PB0-PB5, PB6-PB7
Note Provided correct configuration been selected.
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PORTS (Cont'd) 4.1.3 Timer Alternate function Option When TOUT register TSCR1 low, PC1/ Timer configured through port registers standard Port addition connected Timer input Gated Event counter modes. When TOUT register TSCR1 high, PC1/Timer forced Timer output, independently port registers configuration. 4.1.4 Timer Alternate function Option When PWMOE register ARMC low, ARTIMout/PB7 configured standard port through port registers. When PWMOE high, ARTIMout/PB7 output, independently port registers configuration. ARTIMin/PB6 connected Timer input. configured through port registers standard port ARTIMin/PB6 Timer input, must configured input through DDRB.
4.1.5 Alternate function Option PC2/PC4 used standard long SPCLK Mode Register kept low. When PC2/Sin configured input, automatically connected shift register input, independent state SPCLK. PC3/SOUT configured push-pull output setting Miscellaneous register (address DDh), regardless state Port registers. PC4/SCK configured push-pull output clock (master mode) programming pushpull output through DDRC register setting SPCLK Mode Register. PC4/SCK configured input clock (slave mode) programming input through DDRC register clearing SPCLK Mode Register. With this configuration, simultaneously used input.
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PORTS (Cont'd) Figure Peripheral Interface Configuration SPI, Timer Timer
PP/OD MISC. REGISTER PC2/Sin
PC3/Sout
CLOCK PC4/SCK CLOCK SPCLK REGISTER
TOUT PC1/TIM1
TIMER
ARTIMin ARTIMin
TIMER
PWMOE PP/OD ARTIMout
ARTIMout
VR0C1661
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TIMER features on-chip Timer peripheral, consisting 8-bit counter with 7-bit programmable prescaler, giving maximum count 215. peripheral configured three different operating modes. Figure shows Timer Block Diagram. external TIMER available user. content 8-bit counter read/written Timer/Counter register, TCR, while state 7-bit prescaler read register. control logic device managed TSCR register described following paragraphs. 8-bit counter decremented output (rising edge) coming from 7-bit prescaler loaded read under program control. When decrements zero then (Timer Zero) TSCR "1". (Enable Timer Interrupt) TSCR also "1", interrupt request generated described Interrupt Chapter. Timer interrupt used exit from WAIT mode. prescaler input internal frequency fINT divided external clock applied TIMER pin. prescaler decrements rising edge. Depending division factor programmed PS2, bits TSCR. clock input timer/counter register multiplexed different sources. division factor clock input prescaler also that timer/ counter; factor prescaler register connected clock input TCR. This changes state half frequency prescaler input clock. factor connected clock input TCR, forth. prescaler initialize bit, PSI, TSCR register must allow prescaler (and hence counter) start. cleared "0", prescaler bits counter inhibited from counting. prescaler loaded with value between 7Fh, "1". prescaler selected means PS2/PS1/PS0 bits control register. Figure illustrates Timer's working principle.
Figure Timer Block Diagram
DATABUS 8-BIT COUNTER
SELECT
STATUS/CONTROL REGISTER
TOUT DOUT
TIMER INTERRUPT LINE SYNCHRONIZATION LOGIC LATCH
fOSC
VA00009
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TIMER (Cont'd) 4.2.1 Timer Operating Modes There three operating modes, which selected TOUT DOUT bits (see TSCR register). These three modes correspond clocks which connected 7-bit prescaler (fINT TIMER signal), output mode. Gated Mode (TOUT "0", DOUT "1") this mode prescaler decremented Timer clock input (fINT 12), ONLY when signal TIMER held high (allowing pulse width measurement). This mode selected clearing TOUT TSCR register (i.e. input) setting DOUT "1". must configured input mode Event Counter Mode (TOUT "0", DOUT "0") this mode, TIMER input clock prescaler which decremented rising edge. Output Mode (TOUT "1", DOUT data out)
TIMER connected DOUT latch, hence Timer prescaler clocked prescaler clock input (fINT 12). user select desired prescaler division ratio through PS2, PS1, bits. When count reaches sets TSCR. tested under program control perform timer function whenever goes high. low-to-high transition used latch DOUT TSCR transfer TIMER pin. This operating mode allows external signal generation TIMER pin. Table Timer Operating Modes
TOUT DOUT Timer Input Input Output Output Timer Function Event Counter Gated Input Output Output
4.2.2 Timer Interrupt When counter register decrements zero with (Enable Timer Interrupt) one, interrupt request generated described Interrupt Chapter. When counter decrements zero, TSCR register one.
Figure Timer Working Principle
7-BIT PRESCALER CLOCK BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6
MULTIPLEXER
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
8-BIT COUNTER
VA00186
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TIMER (Cont'd) 4.2.3 Application Notes user select presence on-chip pull-up TIMER option. when counter reaches zero; however, also writing register setting TSCR register. must cleared user software when servicing timer interrupt avoid undesired interrupts when leaving interrupt service routine. After reset, 8-bit counter register loaded with 0FFh, while 7-bit prescaler loaded with 07Fh, TSCR register cleared. This means that Timer stopped (PSI="0") timer interrupt disabled. Timer programmed output mode, DOUT transferred TIMER when software counter decrement). When high, latch transparent DOUT copied timer pin. When goes low, DOUT latched. write register will predominate over 8-bit counter decrement function, i.e. write register decrement occur simultaneously, write will take precedence, until 8-bit counter reaches again. values registers read accurately time. 4.2.4 Timer Registers Timer Status Control Register (TSCR) Address: 0D4h Read/Write
TOUT DOUT
When low, this selects input mode TIMER pin. When high output mode selected. DOUT: Data Output Data sent timer output when high (output mode only). Input mode selection (input mode only). PSI: Prescaler Initialize Used initialize prescaler inhibit counting. When PSI="0" prescaler counter inhibited. When PSI="1" prescaler enabled count downwards. long PSI="0" both counter prescaler running. PS2, PS1, PS0: Prescaler Mux. Select. These bits select division ratio prescaler register. Table Prescaler Division Factors
Divided
Timer Counter Register Address: 0D3h Read/Write
TMZ: Timer Zero low-to-high transition indicates that timer count register decrement zero. This must cleared user software before starting count. ETI: Enable Timer Interrupt When set, enables timer interrupt request (vector #4). ETI=0 timer interrupt disabled. ETI=1 TMZ=1 interrupt request generated. TOUT: Timers Output Control
D7-D0: Counter Bits. Prescaler Register Address: 0D2h Read/Write
Always read "0". D6-D0: Prescaler Bits.
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AUTO-RELOAD TIMER Auto-Reload Timer Timer) on-chip peripheral consists 8-bit timer/counter with compare capture/reload capabilities 7-bit prescaler with clock multiplexer, enabling clock input selected fINT, fINT/3 external clock source. Mode Control Register, ARMC, Status Control Registers, ARSC0 ARSC1, output pin, ARTIMout, input pin, ARTIMin, allow Auto-Reload Timer used modes: Auto-reload (PWM generation), Output compare reload external event (PLL), Input capture output compare time measurement. Input capture output compare period measurement. Timer used wake from WAIT mode either with internal with external clock. also used wake from STOP mode, used with external clock signal connected ARTIMin pin. Load register allows program read write counter fly. 4.3.1 Timer Description COUNTER 8-bit up-counter incremented input clock's rising edge. counter loaded from ReLoad/Capture Register, ARRC, auto-reload capture operations, well initialization. Direct access counter possible; however, reading writing ARLR load register, possible read write counter's contents fly. Timer's input clock either internal clock (from Oscillator Divider), internal clock divided clock signal connected ARTIMin pin. Selection between these clock sources effected suitably programming bits CC0-CC1 ARSC1 register. output Multiplexer feeds 7-bit programmable Prescaler, ARPSC, which selects available taps prescaler, defined PSC0-PSC2 Mode Control Register. Thus division factor prescaler (where 1,.7). clock input counter enabled (Timer Enable) ARMC register. When reset, counter stopped prescaler counter contents frozen. When set, counter runs rate selected clock source. counter cleared system reset. counter also initialized writing ARLR load register, which also causes immediate copy value placed counter, regardless whether counter running not. Initialization counter, either method, will also clear ARPSC register, whereupon counting will start from known value. 4.3.2 Timer Operating Modes Four different operating modes available Timer: Auto-reload Mode with Generation. This mode allows Pulse Width Modulated signal generated ARTIMout with minimum Core processing overhead. free running 8-bit counter prescaler's output, incremented every rising edge clock signal. When counter overflow occurs, counter automatically reloaded with contents Reload/Capture Register, ARCC, ARTIMout set. When counter reaches value contained compare register (ARCP), ARTIMout reset. overflow, flag ARSC0 register overflow interrupt request generated overflow interrupt enable bit, OVIE, Mode Control Register (ARMC), set. flag must reset user software. When counter reaches compare value, flag ARSC0 register compare interrupt request generated, Compare Interrupt enable bit, CPIE, Mode Control Register (ARMC), set. interrupt service routine then adjust period loading value into ARCP. flag must reset user software. signal generated ARTIMout (refer Block Diagram). frequency this signal controlled prescaler setting auto-reload value present Reload/Capture register, ARRC. duty cycle signal controlled Compare Register, ARCP.
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AUTO-RELOAD TIMER (Cont'd) Figure Timer Block Diagram
DATA DDRB7
DRB7 COMPARE REGISTER
PB7/ ARTIMout COMPARE PWMOE 7-Bit PRESCALER 8-Bit COUNTER LOAD OVIE TCLD
CC0-CC1
PS0-PS2
CPIE TIMER INTERRUPT
PB6/ ARTIMin SL0-SL1 SYNCHRO RELOAD/CAPTURE REGISTER LOAD REGISTER
DATA
VR01660A
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AUTO-RELOAD TIMER (Cont'd) should noted that reload values will also affect value resolution duty cycle output signal. obtain signal ARTIMout, contents ARCP register must greater than contents ARRC register. maximum available resolution ARTIMout duty cycle Resolution 1/[256-(ARRC)] Where ARRC content Reload/Capture register. compare value loaded Compare Register, ARCP, must range from (ARRC) 255. Figure Auto-reload Timer Function
COUNTER COMPARE VALUE
ARTC counter initialized writing ARRC register then setting TCLD (Timer Load) (Timer Clock Enable) bits Mode Control register, ARMC. Enabling selection clock source controlled CC0, CC1, bits Status Control Register, ARSC1. prescaler division ratio selected PS0, bits ARSC1 register. Auto-reload Mode, three available clock sources selected: Internal Clock, Internal Clock divided clock signal present ARTIMin pin.
RELOAD REGISTER
tHIGH
OUTPUT
tLOW
VR001852
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AUTO-RELOAD TIMER (Cont'd) Capture Mode with Generation. this mode, counter operates free running 8-bit counter prescaler output. counter incremented every clock rising edge. 8-bit capture operation from counter ARRC register performed every active edge ARTIMin pin, when enabled Edge Control bits SL0, ARSC1 register. same time, External Flag, ARSC0 register external interrupt request generated External Interrupt Enable bit, EIE, ARMC register, set. flag must reset user software. Each ARTC overflow sets ARTIMout, while match between counter ARCP (Compare Register) resets ARTIMout sets compare flag, CPF. compare interrupt request generated related compare interrupt enable bit, CPIE, set. signal generated ARTIMout. flag must reset user software. frequency generated signal determined prescaler setting. duty cycle determined ARCP register. Initialization reading counter identical auto-reload mode (see previous description). Enabling selection clock sources controlled bits Status Control Register, ARSC1. prescaler division ratio selected programming PS0, bits ARSC1 Register. Capture mode, allowed clock sources internal clock internal clock divided external ARTIMin input should used clock source. Capture Mode with Reset counter prescaler, Generation. This mode identical previous one, with difference that capture condition also resets counter prescaler, thus allowing easy measurement time between captures (for input period measurement ARTIMin pin). Note: this mode recommended change ARTimer counter value from other value writing this value ARRC register setting TLCD ARMC register.
Load External Input. counter operates free running 8-bit counter prescaler. count incremented every clock rising edge. Each counter overflow sets ARTIMout pin. match between counter ARCP (Compare Register) resets ARTIMout sets compare flag, CPF. compare interrupt request generated related compare interrupt enable bit, CPIE, set. signal generated ARTIMout. flag must reset user software. Initialization counter described previous paragraph. addition, external ARTIMin input enabled, active edge input will copy contents ARRC register into counter, whether counter running not. Notes: allowed Timer clock sources following:
Timer Mode Auto-reload mode Capture mode Capture/Reset mode External Load mode Clock Sources fINT, fINT/3, ARTIMin fINT, fINT/3 fINT, fINT/3 fINT, fINT/3
clock frequency should modified while counter counting, since counter unpredictable value. instance, multiplexer setting should modified while counter counting. Loading counter means auto-reload, through ARLR, ARRC Core) resets prescaler same time. Care should taken when both Capture interrupt Overflow interrupt used. Capture overflow asynchronous. capture occurs when Overflow Interrupt Flag, OVF, high (between counter overflow flag being reset software, interrupt routine), External Interrupt Flag, cleared simultaneusly without interrupt being taken into account. solution consists resetting flag writing ARSC0 register. value affected this operation. interrupt occured, will processed when exits from interrupt routine (the second interrupt latched).
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AUTO-RELOAD TIMER (Cont'd) 4.3.3 Timer Registers Mode Control Register (ARMC) Address: Read/Write Reset status:
TCLD PWMOE CPIE OVIE ARMC1 ARMC0
Mode Control Register ARMC used program different operating modes Timer, enable clock initialize counter. read written Core cleared system reset (the Timer disabled). Note: Care should taken when writing ARMC register while Timer running: signal being output while ARMC register overwritten with previous value, ARTIMout remains previous state programmed time equal tHIGH (refer Figure 28). Then, count starts. TLCD: Timer Load Bit. This bit, when set, will cause contents ARRC register loaded into counter contents prescaler register, ARPSC, cleared order initialize timer before starting count. This write-only attempt read will yield logical zero. TEN: Timer Clock Enable. This bit, when set, allows timer count. When cleared, will stop timer freeze ARPSC ARTSC. PWMOE: Output Enable. This bit, when set, enables output ARTIMout pin. When reset, output disabled. EIE: External Interrupt Enable. This bit, when set, enables external interrupt request. When reset, external interrupt request masked. related flag, ARSC0 register also set, interrupt request generated. CPIE: Compare Interrupt Enable. This bit, when set, enables compare interrupt request. CPIE reset, compare interrupt request masked. CPIE related flag, CPF, ARSC0 register also set, interrupt request generated.
OVIE: Overflow Interrupt. This bit, when set, enables overflow interrupt request. OVIE reset, compare interrupt request masked. OVIE related flag, ARSC0 register also set, interrupt request generated. ARMC1-ARMC0: Mode Control Bits 1-0. These operating mode control bits. following combinations will select various operating modes:
ARMC1 ARMC0 Operating Mode Auto-reload Mode Capture Mode Capture Mode with Reset ARTC ARPSC Load External Edge Mode
Timer Status/Control Registers ARSC0 ARSC1. These registers contain Timer status information bits also allow programming clock sources, active edge prescaler multiplexer setting. ARSC0 register bits contain interrupt flags Timer. These bits read normally. Each reset software. Writing does affect value. Status Control Register (ARSC0) Address: Read/Clear
Bits D7-D3: Unused External Interrupt Flag. This active edge external ARTIMin input pin. flag cleared writing zero bit. CPF: Compare Interrupt Flag. This contents counter ARCP register equal. flag cleared writing zero bit. OVF: Overflow Interrupt Flag. This transition counter from (overflow). flag cleared writing zero bit.
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AUTO-RELOAD TIMER (Cont'd) Status Control Register 1(ARSC1) Address: Read/Write
Load Register ARLR. ARLR load register used read write ARTC counter register fly" (while counting). ARLR register affected system reset. Load Register (ARLR) Address: Read/Write
Bist PS2-PS0: Prescaler Division Selection Bits 2-0. These bits determine Prescaler division ratio. prescaler itself affected these bits. prescaler division ratio listed following table: Table Prescaler Division Ratio Selection
ARPSC Division Ratio
D7-D0: Load Register Data Bits. These load register data bits. Reload/Capture Register. ARRC reload/ capture register used hold auto-reload value which automatically loaded into counter when overflow occurs. Reload/Capture (ARRC) Address: Read/Write
Reserved. Must kept reset. SL1-SL0: Timer Input Edge Control Bits These bits control edge function Timer input external synchronization. reset, edge detection disabled; edge detection enabled. reset, Timer input rising edge sensitive; set, falling edge sensitive.
Edge Detection Disabled Rising Edge Falling Edge
D7-D0: Reload/Capture Data Bits. These Reload/Capture register data bits. Compare Register. compare register used hold compare value compare function. Compare Register (ARCP) Address: Read/Write
CC1-CC0: Clock Source Select 1-0. These bits select clock source Timer through Multiplexer. programming clock sources explained following Table Table Clock Source Selection.
Clock Source Fint Fint Divided ARTIMin Input Clock Reserved
D7-D0: Compare Data Bits. These Compare register data bits.
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CONVERTER (ADC) converter peripheral 8-bit analog digital converter with analog inputs alternate functions (the number which device dependent), offering 8-bit resolution with typical conversion time 70us oscillator clock frequency 8MHz). converts input voltage process successive approximations, using clock frequency derived from oscillator with division factor twelve. With oscillator clock frequency less than 1.2MHz, conversion accuracy decreased. Selection input done configuring related line analog input Option Data registers (refer ports description additional information). Only line must configured analog input time. user must avoid situation which more than selected analog input simultaneously, avoid device malfunction. uses registers data space: data conversion register, ADR, which stores conversion result, control register, ADCR, used program functions. conversion started writing Start (STA) control register. This automatically clears (resets "0") Conversion (EOC). When conversion complete, automatically "1", order flag that conversion complete that data data conversion register valid. Each conversion separately initiated writing bit. continuously scanned that, user sets while previous conversion progress, conversion started before completing previous one. start (STA) write only bit, attempt read will show logical "0". converter features maskable interrupt associated with conversion. This interrupt associated with interrupt vector occurs when (i.e. when conversion completed). interrupt masked using (interrupt mask) control register. power consumption device reduced turning peripheral. This done setting control register "0". PDS="1", powered enabled conversion. This must least instruction before beginning conversion allow stabilisation converter. This action also needed before entering WAIT mode, since comparator automatically disabled WAIT mode. During Reset, conversion progress stopped, control register reset interrupt masked (EAI=0). Figure Block Diagram
CONVERTER
INTERRUPT CLOCK RESET AVSS AVDD
CONTROL REGISTER CORE CONTROL SIGNALS
RESULT REGISTER CORE
VA00418
4.4.1 Application Notes converter does feature sample hold circuit. analog voltage measured should therefore stable during entire conversion cycle. Voltage variation should exceed ±1/2 optimum conversion accuracy. pass filter used analog input pins reduce input voltage variation during conversion. When selected analog channel, input internally connected capacitor typically 12pF. maximum accuracy, this capacitor must fully charged beginning conversion. worst case, conversion starts instruction (6.5 after channel been selected. worst case conditions, impedance, ASI, analog voltage source calculated using following formula: 6.5µs (capacitor charged over 99.9%), i.e. including guardband. higher been charged longer period adding instructions before start conversion (adding more than cycles pointless).
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CONVERTER (Cont'd) Since same chip microprocessor, user should switch heavily loaded output signals during conversion, high precision required. Such switching will affect supply voltages used analog references. accuracy conversion depends quality power supplies (VDD VSS). user must take special care ensure well regulated reference voltage present pins (power supply voltage variations must less than 5V/ms). This implies, particular, that suitable decoupling capacitor used pin. converter resolution given by::
noise during conversion. first conversion step performed before execution WAIT when most clocks signals still enabled synchronize start with effective execution WAIT. This achieved setting SYNC option. This way, conversion starts effective WAIT maximum accuracy. Note: With this extra option, mandatory execute WAIT instruction just after start instruction. Insertion extra instruction cause spurious interrupt request interrupt vector. Converter Control Register (ADCR) Address: 0D1h Read/Write
-256
Input voltage (Ain) which converted must constant before conversion remain constant during conversion. Conversion resolution improved power supply voltage (VDD) microcontroller lowered. order optimise conversion resolution, user configure microcontroller WAIT mode, because this mode minimises noise disturbances power supply variations output switching. Nevertheless, WAIT instruction should executed soon possible after beginning conversion, because execution WAIT instruction cause small variation voltage. negative effect this variation minimized beginning conversion when converter less sensitive, rather than conversion, when less significant bits determined. best configuration, from accuracy standpoint, WAIT mode with Timer stopped. Indeed, only peripheral oscillator then still working. must woken from WAIT mode interrupt conversion. should noted that waking microcontroller could also done using Timer interrupt, this case Timer will working resulting noise could affect conversion accuracy. extra feature available better accuracy. fact, each conversion followed WAIT instruction minimize
EAI: Enable Interrupt. this interrupt enabled, when EAI=0 interrupt disabled. EOC: conversion. Read Only. This read only indicates when conversion been completed. This automatically reset when written. user using interrupt option then this used interrupt pending bit. Data data conversion register valid only when this "1". STA: Start Conversion. Write Only. Writing this will start conversion selected channel automatically reset bit. again when conversion progress, present conversion stopped will take place. This write only, attempt read will show logical zero. PDS: Power Down Selection. This activates converter "1". Writing this will power down mode (idle mode). D3-D0. used Converter Data Register (ADR) Address: 0D0h Read only
D7-D0: Conversion Result.
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SERIAL PERIPHERAL INTERFACE (SPI) peripheral optimized synchronous serial interface with programmable transmission modes master/slave capabilities supporting wide range industry standard specifications. interface also implement asynchronous data transfer, which case processor overhead limited data transfer from shift register interrupt driven basis. controlled simple user software perform serial data exchange with lowcost external memory, with serially controlled peripherals drive displays, motors relays. SPI's shift register simultaneously feeds Sout pin, thus transmission reception essentially same process. Suitable setting number bits data frame allow filtering unwanted leading data bits incoming data stream. comprises 8-bit Data/Shift Register, DSR, Divide register, DIV, Mode Control Register MOD, Miscellaneous register, MISCR. operated either Master mode Slave mode. Master mode defined synchronous serial clock being supplied MCU, suitably programming clock divider (DIV register). Slave Figure Block Diagram
CYCLE CLOCK DIVIDER
mode defined serial clock being supplied externally external Master device. maximum versatility programmed sample data either rising falling edge SCK, with without phase shift (clock Polarity Phase selection). Sin, Sout signals connected alternate functions. serial input operation, must configured input. serial output operation, Sout selected output programming Miscellaneous Register: clearing this will standard line, while setting will select Sout function. interrupt request associated with transmission reception cycle; this defined programming number bits data frame enabling interrupt. This request associated with interrupt vector masked programming SPIE register. Since interrupt "ORed" with port interrupt source, interrupt flag available register allowing discrimination interrupt request.
FILTER
CLOCK FILTER Sout
DATA
SHIFT REGISTER
VR001693
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SERIAL PERIPHERAL INTERFACE (Cont'd) 4.5.1 Registers Mode Control Register (MOD) Address: Read/Write Reset status:
SPRUN SPIE CPHA SPCLK SPIN SPSTRT EFILT CPOL
register defines controls transmission modes characteristics. This register read/write bits cleared reset. Setting SPSTRT SPIN allowed must avoided. SPRUN: Run. This activity flag. This used either transmit receive modes; automatically cleared transmission reception generates interrupt request (providing that SPIE Interrupt Enable set). Core stop transmission reception time resetting SPRUN bit; this will also generate interrupt request (providing that SPIE Interrupt enable set). SPRUN used start condition parameter, conjunction with SPSTRT bit, when external signal present pin. Note that rising edge then necessary initiate reception; this require external data inversion. This used poll reception transmission. SPIE: Interrupt Enable. This Interrupt Enable bit. this interrupt (vector enabled, when SPIE reset, interrupt disabled. CPHA: Clock Phase Selection. This selects clock phase clock signal. this cleared zero normal state selected; this case data frame present Sout soon Shift Register loaded. this shifted state' selected; this case data frame present Sout first falling edge Shift Register clock. polarity relation division ratio between Shift Register base clock also programmable; refer register Timing Diagrams more information. SPCLK: Base Clock Selection This selects base clock source. either core cycle clock (fINT/13) (Master mode) signal provided external device (slave mode). SPCLK
configured input, slave mode selected. SPCLK high, automaticcally configured push pull output master mode selected. this case, phase polarity clock controlled CPOL CPHA. Note: When master mode enabled, mandatory configure input mode through port registers. SPIN: Input Selection This enables transfer data input Shift Register receive mode. this cleared Shift Register input this set, Shift Register input corresponds input signal present pin. SPSTRT: Start Selection This selects transmission reception start mode. SPSTRT cleared, internal start condition occurs soon SPRUN set. SPSTRT set, internal start signal logic "AND" between SPRUN external signal present pin; this case transmission will start after latest both signals providing that first signal still present (note that this implies rising edge). After transmission recetion been started, will continue even signal reset. EFILT: Enable Filters This enables/disables input noise filters inputs. cleared zero filters enabled, filters disabled. These noise filters will eliminate pulse with pulse width smaller than Core clock periods (depending occurrence signal edge with respect Core clock edge). example, ST6260B/ runs with 8MHz crystal, will delayed 250ns. CPOL: Clock Polarity This controls relationship between data Sout pins SCK. CPOL selects clock edge which captures data allows change state. greatest impact first transmitted (the MSB) does does not) allow clock transition before first data capture edge. Refer timing diagrams this section additional details. These show relationship between CPOL, CPHA SCK, indicate active clock edges strobe times.
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SERIAL PERIPHERAL INTERFACE (Cont'd) Register (DIV) Address: Read/Write Reset status:
SPINT DOV6 DIV5 DIV4 DIV3
Table Burst Mode Clock Periods
DIV6-DIV3 Refer description DIV6-DIV3 bits Register Number bits sent Reserved (not used)
SPIDIV register defines transmission rate frame format contains interrupt flag. Bits CD0-CD2, DIV3-DIV6 read/write while SPINT read cleared only. Write access allowed SPRUN register set. SPINT: Interrupt Flag. SPIE bit=1, SPINT automatically transmission reception interrupt request generated depending state interrupt mask control register. This write read must cleared user software interrupt service routine. DIV6-DIV3: Burst Mode Clock Period Selection. Define number shift register bits that transmitted received frame. available selections listed Table normal maximum setting bits, since shift register bits wide. Note that setting greater number bits, conjunction with SPIN register, unwanted data bits filtered from data stream. CD2-CD0: Base/Bit Clock Rate Selection. Define division ratio between core clock (fINT divided clock supplied Shift Register Master mode. Table Base/Bit Clock Ratio Selection
CD2-CD0 Divide Ratio (decimal) Divide Divide Divide Divide Divide Divide Divide Divide
Data/Shift Register (SPIDSR) Address: Read/Write Reset status:
SPIDSR read/write, however write access allowed SPRUN Mode Control register one. Data sampled into SPDSR edge determined CPOL CPHA bits. affect these setting shown following diagrams. Shift Register transmits receives Most Significant first. DSR7-DSR0: Data Bits. These shift register data bits. Miscellaneous Register (MISCR) Address: Write only Reset status: xxxxxxxb
Note: example, when 8MHz clock used, asynchronous operation 9600 Baud possible (8MHz/13/64). Other Baud rates available proportionally selecting division factors depending clock frequency. Data setup time typically 250ns min, while data hold time typically 50ns min.
D7-D1: Reserved. This bit, when set, selects Sout output line. When this cleared, Sout acts standard line.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 4.5.2 Timing Diagrams Figure CPOL Clock Polarity Normal, CPHA Phase Selection Normal
SPRUN
Sampling
Sout
VR001694
Figure CPOL Clock Polarity Inverted, CPHA Phase Selection Normal
SPRUN
Sampling
Sout
VR0A1694
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SERIAL PERIPHERAL INTERFACE (Cont'd) Figure CPOL Clock Polarity Normal, CPHA Phase Selection Shifted
SPRUN
Sampling
Sout
VR0B1694
Figure CPOL Clock Polarity Inverted, CPHA Phase Selection Shifted
SPRUN
Sampling
Sout
VR0C1694
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SOFTWARE
ARCHITECTURE software been designed fully hardware most efficient possible while keeping byte usage minimum; short, provide byte efficient programming capability. core ability clear register location Data space with ADDRESSING MODES core offers nine addressing modes, which described following paragraphs. Three different address spaces available: Program space, Data space, Stack space. Program space contains instructions which executed, plus data immediate mode instructions. Data space contains Accumulator, X,Y,V registers, peripheral Input/ Output registers, locations Data locations (for storage tables constants). Stack space contains 12-bit cells used stack return addresses subroutines interrupts. Immediate. immediate addressing mode, operand instruction follows opcode location. operand byte, immediate addressing mode used access constants which change during program execution (e.g., constant used initialize loop counter). Direct. direct addressing mode, address byte which processed instruction stored location which follows opcode. Direct addressing allows user directly address bytes Data Space memory with single two-byte instruction. Short Direct. core address four registers X,Y,V,W (locations 80h, 81h, 82h, 83h) short-direct addressing mode. this case, instruction only byte selection location processed contained opcode. Short direct addressing subset direct addressing mode. (Note that also indirect registers). Extended. extended addressing mode, 12-bit address needed define instruction obtained concatenating four less significant bits opcode with byte following opcode. instructions (JP, CALL) which extended addressing mode able branch address bytes Program space. extended addressing mode instruction twobyte long. Program Counter Relative. relative addressing mode only used conditional branch instructions. instruction used perform test and, condition true, branch with span locations around address relative instruction. condition true, instruction which follows relative instruction executed. relative addressing mode instruction one-byte long. opcode obtained adding three most significant bits which characterize kind test, which determines whether branch forward (when backward (when branch four less significant bits which give span branch which must added subtracted address relative instruction obtain address branch. Direct. direct addressing mode, cleared part opcode, byte following opcode points address byte which specified must cleared. Thus, locations Data space memory cleared. Test Branch. test branch addressing mode combination direct addressing relative addressing. test branch instruction three-byte long. identification tested condition included opcode byte. address byte tested follows immediately opcode Program space. third byte jump displacement, which range -127 +128. This displacement determined using label, which converted assembler. Indirect. indirect addressing mode, byte processed register-indirect instruction address pointed content indirect registers, (80h,81h). indirect register selected opcode. register indirect instruction byte long. Inherent. inherent addressing mode, information necessary execute instruction contained opcode. These instructions byte long. single instruction. Furthermore, program branch selected address depending status Data space. carry stored with value when instruction processed.
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INSTRUCTION core offers basic instructions which, when combined with nine addressing modes, yield usable opcodes. They divided into different types: load/store, arithmetic/logic, conditional branch, control instructions, jump/call, manipulation. following paragraphs describe different types. instructions belonging given type presented individual tables. Table Load Store Instructions
Instruction (X), (Y), Addressing Mode Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Indirect Indirect Immediate Immediate Bytes Cycles Flags
Load Store. These instructions one, three bytes relation with addressing mode. operand Accumulator LOAD other operand obtained from data memory using addressing modes. Load Immediate operand data space bytes while other always immediate data.
Notes: X,Y. Indirect Register Pointers, Short Direct Registers Immediate data (stored memory) Data space register Affected Affected
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INSTRUCTION (Cont'd) Arithmetic Logic. These instructions used perform arithmetic calculations logic operations. AND, ADD, instructions operand always accumulator while other either data space memory conTable Arithmetic Logic Instructions
Instruction ADDI ANDI SUBI Addressing Mode Indirect Indirect Direct Immediate Indirect Indirect Direct Immediate Short Direct Direct Inherent Indirect Indirect Direct Immediate Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Inherent Inherent Indirect Indirect Direct Immediate Bytes Cycles Flags
tent immediate value relation with addressing mode. CLR, DEC, instructions operand data space addresses. COM, RLC, operand always accumulator.
Notes: X,Y.Indirect Register Pointers, Short Direct RegistersD. Affected Immediate data (stored memory)* Affected Data space register
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INSTRUCTION (Cont'd) Conditional Branch. branch instructions achieve branch program when selected condition met. Manipulation Instructions. These instructions handle data space memory. group either sets clears. other group (see Conditional Branch) performs test branch operations. Table Conditional Branch Instructions
Instruction JRNC JRNZ Branch Bytes Cycles Flags
Control Instructions. control instructions control operations during program execution. Jump Call. These instructions used perform long (12-bit) jumps subroutines call inside whole program space.
Notes: 3-bit address signed displacement range +16<F128M> signed displacement range -126 +129
Data space register Affected. tested shifted into carry. Affected
Table Manipulation Instructions
Instruction b,rr b,rr
Notes: 3-bit address; Data space register;
Addressing Mode Direct Direct
Bytes
Cycles
Not<M> Affected
Flags
Table Control Instructions
Instruction RETI STOP WAIT Addressing Mode Inherent Inherent Inherent Inherent Inherent Bytes Cycles Flags
Notes: This instruction deactivated<N>and WAIT automatically executed instead STOP watchdog function selected. Affected Affected
Table Jump Call Instructions
Instruction CALL
Notes: abc. 12-bit address; Affected
Addressing Mode Extended Extended
Bytes
Cycles
Flags
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Opcode Summary. following table contains opcode instructions used
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ 0000 JRNZ 0001 CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL 0010 JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC 0011 b0,rr,ee b0,rr,ee b4,rr,ee b4,rr,ee b2,rr,ee b2,rr,ee b6,rr,ee b6,rr,ee b1,rr,ee b1,rr,ee b5,rr,ee b5,rr,ee b3,rr,ee b3,rr,ee b7,rr,ee b7,rr,ee a,(x) ANDI a,nn a,(x) SUBI a,nn (x),a 0100 0101 0110 a,(x) a,nn a,(x) a,nn a,(x) ADDI a,nn 0111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Abbreviations Addressing Modes: Direct Short Direct Immediate Inherent Extended Direct Test Program Counter Relative Indirect
Legend: Indicates Illegal Instructions Displacement Address 1byte dataspace address byte immediate data address Displacement
Cycle Operand Bytes Addressing Mode
Mnemonic
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Opcode Summary (Continued)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ 1000 JRNZ 1001 1010 JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC 1011 b0,rr b0,rr b4,rr b4,rr b2,rr b2,rr b6,rr b6,rr b1,rr b1,rr b5,rr b5,rr b3,rr b3,rr b7,rr b7,rr WAIT STOP RETI 1100 1101 rr,nn a,rr a,(y) a,rr (y),a rr,a a,(y) a,rr a,(y) a,rr a,(y) a,rr 1110 a,(y) 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Abbreviations Addressing Modes: Direct Short Direct Immediate Inherent Extended Direct Test Program Counter Relative Indirect
Legend: Indicates Illegal Instructions Displacement Address 1byte dataspace address byte immediate data address Displacement
Cycle Operand Bytes Addressing Mode
Mnemonic
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ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS This product contains devices protect inputs against damage high static voltages, however advisable take normal precaution avoid application voltage higher than specified maximum rated voltages. proper operation recommended that higher than lower than VDD. Reliability enhanced unused inputs connected appropriate logic voltage level (VDD VSS). Power Considerations.The average chip-junction temperature, Celsius obtained from: Tj=TA RthJA Where:TA Ambient Temperature. RthJA =Package thermal resistance (junction-to ambient). Pint Pport. Pint =IDD (chip internal power). Pport =Port power dissipation (determined user).
Value -0.3
Symbol IVDD IVSS TSTG Supply Voltage Input Voltage Output Voltage
Parameter
Unit
0.3(1)
Total Current into (source) Total Current (sink) Junction Temperature Storage Temperature
Notes: Stresses above those listed "absolute maximum ratings" cause permanent damage device. This stress rating only functional operation device these conditions implied. Exposure maximum rating conditions extended periods affect device reliability. Within these limits, clamping diodes guarantee conductive. Voltages outside these limits authorised long injection current kept within specification.
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RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Test Conditions Suffix Version Suffix Version Suffix Version Value Min. Typ. Max. Unit
Operating Temperature
fOSC 4MHz, Suffix fOSC 4MHz, Suffix Operating Supply Voltage (Except ST626xB devices) fosc= 8MHz Suffix fosc= 8MHz Suffix Operating Supply Voltage (ST626xB devices) fOSC 4MHz, Suffix fOSC 4MHz, Suffix fosc= 8MHz Suffix fosc= 8MHz Suffix
fOSC
3.0V, Suffix Oscillator Frequency2) 3.0V Suffix (Except ST626xB devices) 3.6V Suffix 3.6V Suffix Oscillator Frequency2) (ST626xB devices) 3.0V, Suffix 3.0V Suffix 4.0V Suffix 4.0V Suffix 5.5V 5.5V
IINJ+ IINJ-
Injection Current (positive) Injection Current (negative)
Notes: Care must taken case negative current injection, where adapted impedance must respected analog sources affect conversion. -1mA injection, maximum recommended. 2.An oscillator frequency above 1MHz recommended reliable results
Figure Maximum Operating FREQUENCY (Fmax) Versus SUPPLY VOLTAGE (VDD)
Maximum FREQUENCY (MHz) Suffix version Suffix version FUNCTIONALITY Suffix GUARANTEED version THIS AREA Suffix version
SUPPLY VOLTAGE (VDD)
devices except ST626xB devices ST626xB devices shaded area outside recommended operating range; device functionality guaranteed under these conditions.
65/84
ST6255C ST6265C ST6265B
ELECTRICAL CHARACTERISTICS +125°C unless otherwise specified)
Symbol Parameter Test Conditions Value Min. Typ. Max. Unit
Input Level Voltage Input pins Input High Level Voltage Input pins Hysteresis Voltage Input pins VDD= VDD=
VHys
Threshold power-on threshold powerdown Level Output Voltage VDD= 5.0V; +10µA Output pins VDD= 5.0V; VDD= 5.0V; +10µA Level Output Voltage VDD= 5.0V; +7mA Sink pins VDD= 5.0V; +15mA High Level Output Voltage VDD= 5.0V; -10µA Output pins VDD= 5.0V; -3.0mA Input pins Pull-up Resistance RESET Input Leakage Current Pull-Up configured) Input pins RESET Input Leakage Current RESET Supply Current RESET VRESET=VSS Mode fOSC=8MHz Supply Current VDD=5.0V fINT=8MHz Mode Supply Current WAIT VDD=5.0V fINT=8MHz Mode ILOAD=0mA Supply Current STOP Mode, with disabled(3) VDD=5.0V ILOAD=0mA Supply Current STOP Mode, with enabled(3) VDD=5.0V Retention EPROM Data Retention 55°C
Notes: Hysteresis voltage between switching levels peripherals running peripherals stand-by
years
66/84
ST6255C ST6265C ST6265B
ELECTRICAL CHARACTERISTICS (Cont'd) +85°C unless otherwise specified))
Symbol Parameter Test Conditions Value Min. Typ. Max. Unit
Threshold power-on threshold powerdown Level Output Voltage Output pins VDD= 5.0V; +10µA VDD= 5.0V; VDD= 5.0V; 10mAv VDD= 5.0V; +10µA VDD= 5.0V; +10mA VDD= 5.0V; +20mA VDD= 5.0V; +30mA VDD= 5.0V; -10µA VDD= 5.0V; -5.0mA ILOAD=0mA VDD=5.0V
Level Output Voltage Sink pins High Level Output Voltage Output pins Supply Current STOP Mode, with disabled(*)
Note: Peripherals stand-by.
ELECTRICAL CHARACTERISTICS +125°C unless otherwise specified)
Symbol tREC TWEE En
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