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TransilTM, transient voltage suppressor Transient voltage suppres


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LFTVS10-1F3
TransilTM, transient voltage suppressor
Transient voltage suppressor Electrostatic discharge protection Electrical overstress protection Unidirectional device clamping factor VCL/VBR Fast response time Very thin package: 0.605 RoHS compliant Figure configuration (bump side)
Flip Chip bumps)
Complies with following standards:
61000-4-2 level (air discharge) (contact discharge)
Description
LFTVS10-1F3 single line diode designed specifically protection integrated circuits portable equipment miniaturized electronic devices subject transient overvoltages. Figure Device configuration
Transil trademark STMicroelectronics
November 2008
www.st.com
Characteristics
LFTVS10-1F3
Characteristics
Table
Symbol
Absolute maximum ratings (Tamb
Parameter Peak pulse power dissipation (10/1000 pulse) Test condition Value initial Tamb initial Tamb +150 Unit
Peak pulse power dissipation (8/20 pulse) repetitive surge peak forward current Storage temperature range Maximum operating junction temperature
IFSM Tstg
Table
Symbol Symbol Cline
Electrical characteristics (Tamb
Parameter Breakdown voltage
Leakage current Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Voltage temperature coefficient Forward voltage drop Test conditions
Slope 1/Rd
Min.
Typ.
Max.
Unit
1.05
10-4
VOSC
pulse waveform current recommended more than Even diode failure mode short circuit bumps could exceed melting temperature component disassembled from board.
LFTVS10-1F3
Characteristics
Figure
Relative variation peak pulse power versus initial junction temperature
Figure
Peak pulse power versus exponential pulse duration (typical value)
initial
PPP[Tj initial] PPP[Tj initial=25°C]
10000
PPP(W)
1000
Tj(°C)
tp(µs)
1000
Figure
Clamping voltage versus peak pulse current (typical values)
Figure
Relative variation leakage current versus junction temperature (typical values)
10.0
IPP(A)
1000
Pulse
IR[Tj] IR[Tj=25°C]
VCL(V)
Tj(°C)
Figure
Forward voltage drop versus peak forward current (typical values)
Figure
Junction capacitance versus line voltage (typical values)
IFM(A)
Capacitance(pF)
Vr=0 VOSC=30mVRMS TJ=25°C
0.01
initial
initial initial
0.001
VFM(V)
0.0001
Voltage(V)
Ordering information scheme Figure
LFTVS10-1F3
Breakdown voltage versus initial junction temperature (typical value)
13.0
VBR(V)
12.0
11.0
10.0
Tj(°
Ordering information scheme
Figure Ordering information scheme
forward voltage Transient voltage suppressor Breakdown voltage VMAX Number lines single line Package Flip Chip Lead-free, pitch
LFTVS10-1F3
Package information
Package information
order meet environmental requirements, offers these devices ECOPACK® packages. These packages have lead-free second level interconnect. category second level interconnect marked inner label, compliance with JEDEC Standard JESD97. maximum ratings related soldering conditions also marked inner label. ECOPACK trademark. ECOPACK specifications available www.st.com. Figure Flip Chip dimensions
0.77
0.77
Figure Footprint recommendations
Copper Diameter: recommended maximum Solder mask opening: minimum
Figure Marking
marking manufacturing location datecode year week)
Solder stencil opening: recommended
Ordering information Figure Flip Chip tape reel specifications
0.05 0.20 0.05 1.55 0.05
LFTVS10-1F3
1.75 0.05
0.69 0.05
dimensions
0.87
User direction unreeling
0.87
Note:
More information available application notes: AN2348: "400 flip chip: Package description recommendations use" AN1751: "EMI Filters: Recommendations measurements"
Ordering information
Table Ordering information
Marking Package Flip Chip Weight 0.86 Base Delivery mode Tape reel (7")
Order code LFTVS10-1F3
Revision history
Table
Date 21-Nov-2008
Document revision history
Revision Initial release. Changes
LFTVS10-1F3
Please Read Carefully:
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