3.3V range 8-bit automotive with Kbyte Flash, 10-bit ADC, timers, SPI,
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ST72321BLJ6-Auto
3.3V range 8-bit automotive with Kbyte Flash, 10-bit ADC, timers, SPI, SCI, interface
Memories
Kbyte dual voltage high density Flash (HDFlash) with readout protection capability (in-application programming in-circuit programming HDFlash devices) bytes Kbyte HDFlash endurance: cycles, data retention years
LQFP44
16-bit timer with input capture, output compare, external clock input, pulse generator modes 16-bit timer with input captures, output compares, pulse generator modes 8-bit auto-reload timer with input captures, outputs, output compare time base interrupt, external clock with event detector
Clock, reset supply management
Clock sources: Crystal/ceramic resonator oscillators, internal oscillator bypass external clock frequency multiplication power saving modes: Halt, active halt, wait slow
communication interfaces
synchronous serial interface asynchronous serial interface multimaster interface
Interrupt management
Nested interrupt controller interrupt vectors plus TRAP reset external interrupt lines vectors)
analog peripheral (low current coupling)
10-bit with robust input ports
ports
Instruction
32/24 multifunctional bidirectional lines 22/17 alternate function lines 12/10 high sink outputs
8-bit data manipulation basic instructions main addressing modes unsigned multiply instruction
timers
Main clock controller with real-time base, beep clock-out capabilities Configurable watchdog timer Device summary
Program memory Flash Kbytes
Development tools
Full HW/SW development package In-circuit testing capability
Table
Device ST72321BLJ6-Auto
(stack) 1024 (256) bytes
Oper. voltage 3.6V
Temp. range +85°C
Package LQFP44 10x10
January 2008
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Contents
ST72321BLxx-Auto
Contents
Description Package pinout description Register memory Flash program memory
Introduction Main features Structure
4.3.1 Readout protection
interface In-circuit programming (ICP) In-application programming (IAP) Related documentation
4.7.1 Register description
Central processing unit
Introduction Main features registers
Supply, reset clock management
Introduction Main features Phase locked loop Multi-oscillator (MO)
6.4.1 6.4.2 6.4.3 External clock source Crystal/ceramic oscillators Internal oscillator
Reset sequence manager (RSM)
6.5.1 6.5.2 Introduction Asynchronous external RESET
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ST72321BLxx-Auto 6.5.3 6.5.4
Contents External power-on reset Internal watchdog reset
Interrupts
Introduction Masking processing flow
7.2.1 7.2.2 7.2.3 7.2.4 Servicing pending interrupts Different interrupt vector sources Non-maskable sources Maskable sources
7.10
Interrupts power modes Concurrent nested management Interrupt registers Interrupt related instructions External interrupts
7.7.1 port interrupt sensitivity
External interrupt control register (EICR) Nested interrupts register reset value Interrupt mapping
Power saving modes
Introduction Slow mode Wait mode Active halt halt modes
8.4.1 8.4.2 Active halt mode Halt mode
ports
Introduction Functional description
9.2.1 9.2.2 9.2.3 Input modes Output modes Alternate functions
port implementation
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Contents
ST72321BLxx-Auto
power modes Interrupts
On-chip peripherals
10.1 Watchdog timer (WDG)
10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.1.7 10.1.8 10.1.9 Introduction Main features Functional description program watchdog timeout power modes Hardware watchdog option Using halt mode with (WDGHALT option) Interrupts Control register (WDGCR)
10.1.10 Watchdog timer register reset values
10.2
Main clock controller with real-time clock beeper (MCC/RTC)
10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 10.2.8 Programmable clock prescaler Clock-out capability Real-time clock timer (RTC) Beeper power modes Interrupts MCC/RTC registers register reset values
10.3
auto-reload timer (ART)
10.3.1 10.3.2 10.3.3 Introduction Functional description registers
10.4
16-bit timer
10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 Introduction Main features Functional description power modes Interrupts Summary timer modes 16-bit timer registers
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ST72321BLxx-Auto
Contents
10.5
Serial peripheral interface (SPI)
10.5.1 10.5.2 10.5.3 10.5.4 10.5.5 10.5.6 10.5.7 10.5.8 Introduction Main features General description Clock phase clock polarity Error flags power modes Interrupts registers
10.6
Serial communications interface (SCI)
10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 10.6.6 10.6.7 Introduction Main features General description Functional description power modes Interrupts registers
10.7
interface (I2C)
10.7.1 10.7.2 10.7.3 10.7.4 10.7.5 10.7.6 10.7.7 Introduction Main features General description Functional description power modes Interrupts Register description
10.8
10-bit converter (ADC)
10.8.1 10.8.2 10.8.3 10.8.4 10.8.5 10.8.6 Introduction Main features Functional description power modes Interrupts 10-bit registers
Instruction
11.1 addressing modes
11.1.1 11.1.2 Inherent instructions Immediate instructions
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Contents 11.1.3 11.1.4 11.1.5 11.1.6 11.1.7
ST72321BLxx-Auto Direct instructions Indexed instructions offset, short, long) Indirect instructions (short, long) Indirect indexed instructions (short, long) Relative mode instructions (direct, indirect)
11.2 11.3
Instruction groups Using prebyte
Electrical characteristics
12.1 Parameter conditions
12.1.1 12.1.2 12.1.3 12.1.4 12.1.5 Minimum maximum values Typical values Typical curves Loading capacitor input voltage
12.2
Absolute maximum ratings
12.2.1 12.2.2 12.2.3 Voltage characteristics Current characteristics Thermal characteristics
12.3 12.4
Operating conditions Supply current characteristics
12.4.1 12.4.2 12.4.3 Current consumption Supply clock managers On-chip peripherals
12.5
Clock timing characteristics
12.5.1 12.5.2 12.5.3 12.5.4 12.5.5 General timings External clock source Crystal ceramic resonator oscillators oscillators characteristics
12.6
Memory characteristics
12.6.1 12.6.2 hardware registers Flash memory
12.7
Electromagnetic compatibility (EMC) characteristics
12.7.1 12.7.2 Functional electromagnetic susceptibility (EMS) Electromagnetic interference (EMI)
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ST72321BLxx-Auto 12.7.3
Contents Absolute maximum ratings (electrical sensitivity)
12.8
port characteristics
12.8.1 12.8.2 General characteristics Output driving current
12.9
Control characteristics
12.9.1 12.9.2 Asynchronous RESET ICCSEL/VPP
12.10 Timer peripheral characteristics
12.10.1 16-bit timer
12.11 Communication interface characteristics
12.11.1 Serial peripheral interface (SPI) 12.11.2 inter control interface
12.12 10-bit characteristics
12.12.1 Analog power supply reference pins 12.12.2 General design guidelines 12.12.3 accuracy
Package characteristics
13.1 13.2 13.3 Package mechanical data Thermal characteristics Soldering information
Device configuration ordering information
14.1 14.2 Introduction Flash devices
14.2.1 14.2.2 Flash configuration Flash ordering information
14.3 14.4
FASTROM device ordering information transfer customer code Development tools
14.4.1 14.4.2 14.4.3 14.4.4 14.4.5 Introduction Evaluation tools starter kits Development debugging tools Programming tools Socket emulator adapter information
14.5
application notes
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Contents
ST72321BLxx-Auto
Known limitations
15.1 Flash devices
15.1.1 15.1.2 15.1.3 15.1.4 15.1.5 15.1.6 15.1.7 15.1.8 15.1.9 Safe connection OSC1/OSC2 pins External interrupt missed Unexpected reset fetch Clearing active interrupts outside interrupt routine 16-bit timer mode TIMD simultaneously with interrupt wrong break duration multimaster exit from halt/active halt
Revision history
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ST72321BLxx-Auto
List tables
List tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Device summary Device description (LQFP44) Hardware register Sectors available Flash devices Flash control/status register address reset value register description clock source Interrupt software priority levels register description. ISPRx interrupt vector correspondence Dedicated interrupt instruction EICR register description Nested interrupts register reset values Interrupt mapping Active halt halt power saving modes register value output status port mode options port configurations Port register configurations Effect power modes ports interrupt control/wake-up capability port register reset values Effect power modes watchdog timer WDGCR register description Watchdog timer register reset values Effect power modes MCC/RTC MCC/RTC interrupt control/wake-up capability. MCCSR register description MCCBCR register description. Main clock controller register reset values. ARTCSR register description Prescaler selection ARTCAR register description ARTAAR register description frequency versus resolution PWMCR register description output signal polarity selection PWMDCRx register description ARTICCSR register description ARTICRx register description auto-reload timer register reset values. Effect power modes 16-bit timer 16-bit timer interrupt control/wake-up capability Summary timer modes register description register description register description 16-bit timer register reset values
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List tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 100.
ST72321BLxx-Auto
Effect power modes interrupt control/wake-up capability SPICR register description SPICSR register description register reset values Frame formats Effect power modes interrupt control/wake-up capability SCISR register description SCICR1 register description SCICR2 register description SCIBRR register description SCIERPR register description SCIETPR register description Baud rate selection register reset values Effect power modes interrupt control/wake-up capability register description register description register description register description. register description OAR1 register description. OAR2 register description. register reset values Effect power modes 10-bit ADCCSR register description ADCDRH register description ADCDRL register description register reset values addressing mode groups addressing mode overview Inherent instructions Immediate instructions Instructions supporting direct, indexed, indirect indirect indexed addressing modes Short instructions functions Relative mode instructions (direct indirect) Instruction groups Instruction overview Voltage characteristics Current characteristics Thermal characteristics. General operating conditions Current consumption Oscillators, current consumption On-chip peripherals General timings. External clock source Oscillator parameters Examples typical resonators oscillators
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ST72321BLxx-Auto Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128.
List tables
characteristics hardware registers Characteristics dual voltage HDFlash memory. Electromagnetic test results emissions absolute maximum ratings Latch-up results general port characteristics Output driving current Asynchronous RESET ICCSEL/VPP characteristics 16-bit timer characteristics control interface characteristics frequency table 10-bit characteristics accuracy with 3.3V 44-pin profile quad flat package mechanical data Thermal characteristics. Soldering compatibility (wave reflow soldering process) Flash option bytes. Option byte description Option byte description Flash user programmable device types FASTROM factory coded device types. Development tool order codes ST72321BL family Suggested list socket types Document revision history
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List figures
ST72321BLxx-Auto
List figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Device block diagram 44-pin LQFP 10x10 package pinout Memory Memory sector address Typical interface registers Stack manipulation example Clock, reset supply block diagram Reset sequence phases Reset block diagram Reset sequences Interrupt processing flowchart. Priority decision process Concurrent interrupt management Nested interrupt management External interrupt control bits Power saving mode transitions Slow mode clock transitions Wait mode flowchart Active halt timing overview Active halt mode flowchart Halt timing overview Halt mode flowchart port general block diagram Interrupt port state transitions Watchdog block diagram Approximate timeout duration Exact timeout duration (tmin tmax). Main clock controller (MCC/RTC) block diagram auto-reload timer block diagram Output compare control auto-reload timer function signal from 100% duty cycle External event detector example counts) Input capture timing diagram Timer block diagram 16-bit read sequence Counter timing diagram, internal clock divided Counter timing diagram, internal clock divided Counter timing diagram, internal clock divided Input capture block diagram Input capture timing diagram(1) Output compare block diagram. Output compare timing diagram, fTIMER fCPU/2 Output compare timing diagram, fTIMER fCPU/4 pulse mode sequence pulse mode timing example(1) Pulse width modulation mode timing example with output compare functions(1)
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ST72321BLxx-Auto Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
List figures
Pulse width modulation cycle Serial peripheral interface block diagram Single master/single slave application Generic timing diagram Hardware/software slave select management Data clock timing diagram Clearing WCOL (write collision flag) software sequence Single master/multiple slave configuration block diagram Word length programming baud rate extended prescaler block diagram sampling reception mode. protocol interface block diagram Transfer sequencing Interrupt control logic diagram block diagram loading conditions input voltage fCPU versus Typical mode Typical slow mode Typical wait mode Typical slow wait mode Typical application with external clock source Typical application with crystal ceramic resonator. Integrated jitter signal frequency. Unused pins configured input. Typical versus with Typical versus 3.3V (standard ports) Typical versus 3.3V (high-sink ports). Typical versus 3.3V Typical versus Typical versus (high-sink ports) Typical versus -2mA RESET protection typical applications with ICCSEL/VPP slave timing diagram with CPHA slave timing diagram with CPHA master timing diagram Typical application with timing diagram(1) RAIN maximum versus fADC with CAIN Recommended CAIN RAIN values. Typical converter application Power supply filtering accuracy characteristics 44-pin profile quad flat package outline Flash commercial product code structure FASTROM commercial product code structure
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Description
ST72321BLxx-Auto
Description
ST72321BLJ6-Auto device member microcontroller family designed mid-range automotive applications running 3.3V. devices based common industry-standard 8-bit core, featuring enhanced instruction available with Flash memory. family architecture offers both power flexibility software developers, enabling design highly efficient compact application code. on-chip peripherals include converter, autoreload timer, general purpose timers, SPI, interface. power economy, microcontroller switch dynamically into wait, slow, active halt halt mode when application idle standby state. Typical applications include:
types body applications such window lift, motor control rain sensors Safety microcontrollers airbag engine management applications Auxiliary functions radios Device block diagram
8-bit core Reset Control
(1024 bytes)
Figure
Program memory Kbytes)
Watchdog OSC1 OSC2 Address data Port MCC/RTC/BEEP Port PF7:6,4,2:0 bits) Timer BEEP Port Port Timer PD5:0 bits) Port 10-bit VAREF VSSA PC7:0 bits) PA7:3 bits)
Port
PB4:0 bits)
PE1:0 bits)
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ST72321BLxx-Auto
Package pinout description
Package pinout description
Figure 44-pin LQFP 10x10 package pinout
RDI/PE1 (HS) AIN0/PD0 AIN1/PD1 AIN2/PD2 AIN3/PD3 AIN4/PD4
PE0/TDO VDD_2 OSC1 OSC2 VSS_2 RESET VPP/ICCSEL (HS) (HS) (HS) (HS) VSS_1 VDD_1 (HS) PC7/SS/AIN15 PC6/SCK/ICCCLK PC5/MOSI/AIN14 PC4/MISO/ICCDATA (HS)/ICAP1_B (HS)/ICAP2_B PC1/OCMP1_B/AIN13 PC0/OCMP2_B/AIN12 AIN5/PD5 VAREF VSSA MCO/AIN8/PF0 BEEP/(HS) (HS) OCMP1_A/AIN10/PF4 ICAP1_A/(HS) EXTCLK_A/(HS) VDD_0 VSS_0
(HS) 20mA high sink capability associated external interrupt vector
external connection guidelines refer Section Electrical characteristics page 173. Table below, refer Section ports page more details software configuration ports. RESET configuration each shown bold. This configuration valid long device reset state.
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Package pinout description Table Device description (LQFP44)(1)
Port Type Level Input Output Input int(2) float Output OD(3) Main function (after reset)
ST72321BLxx-Auto
Alternate function
Name RDI/PE1 (HS) AIN0/PD0 AIN1/PD1 AIN2/PD2
Port Port Port Port Port Port Port Port Port Port Port Port
receive data
analog input analog input analog Input analog Input analog Input analog Input
AIN3/PD3 AIN4/PD4 AIN5/PD5 VAREF(4) VSSA(4)
Analog reference voltage Analog ground voltage Port Port Port Port Port Port Timer output analog compare input Timer input capture Timer external clock source Main clock (fCPU) analog input
MCO/AIN8/PF0 BEEP/(HS) (HS)
Beep signal output
OCMP1_A/AIN10/PF4 ICAP1_A/(HS) EXTCLK_A/(HS) VDD_0(4) VSS_0
Digital main supply voltage Digital ground voltage Port Port Port Port Port Timer output analog compare input Timer output analog compare input Timer input capture Timer input capture master slave data data input
PC0/OCMP2_B/ AIN12 PC1/OCMP1_B/ AIN13
(HS)/ICAP2_B (HS)/ICAP1_B PC4/MISO/ICCDATA
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ST72321BLxx-Auto Table Device description (LQFP44)(1) (continued)
Port Type Level Input Output Input int(2) float Output OD(3)
Package pinout description
Name
Main function (after reset)
Alternate function
PC5/MOSI/AIN14 PC6/SCK/ICCCLK
Port Port
master analog /slave data input serial clock slave select (active low) clock output analog input
PC7/SS/AIN15 (HS) VDD_1(4) VSS_1
Port Port
Digital main supply voltage Digital ground voltage Port Port Port Port Must tied low. Flash programming mode, this acts programming voltage input VPP. Section 12.9.2: ICCSEL/VPP page more details. priority non-maskable interrupt Digital ground voltage Resonator oscillator inverter output External clock input resonator oscillator inverter input Digital main supply voltage Port transmit data
(HS) (HS) (HS) (HS)
VPP/ICCSEL
RESET VSS_2(4) OSC2(5)
OSC1(5) VDD_2(4) PE0/TDO
Legend/abbreviations Table Type: input, output, supply Input level: CMOS 0.3VDD/0.7VDD with input trigger Output level: 20mA high sink N-buffer only) Port control configuration inputs: float floating, weak pull-up, interrupt, analog ports Port control configuration outputs: open drain, push-pull `eiX' defines associated external interrupt vector. weak pull-up column (wpu) merged with interrupt column (int), then configuration pull-up interrupt input; otherwise configuration floating interrupt input defines true open drain (P-buffer protection diode implemented). Section ports page Section 12.8: port characteristics page more details mandatory connect available VAREF pins supply voltage VSSA pins ground. OSC1 OSC2 pins connect crystal/ceramic resonator, external source on-chip oscillator; Section Description page Section 12.5: Clock timing characteristics page more details
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Register memory
ST72321BLxx-Auto
Register memory
shown Figure capable addressing Kbytes memories registers. available memory locations consist bytes register locations, 1024 bytes Kbytes user program memory. space includes bytes stack from 0100h 01FFh. highest address bytes contain user reset interrupt vectors. Important: Memory locations marked `reserved' must never accessed. Accessing reserved area have unpredictable effects device. Figure
0000h 007Fh 0080h
Memory
0080h Short addressing (zero page) 00FFh 0100h (1024 bytes) bytes stack 01FFh 0200h 027Fh 047Fh 16-bit addressing 8000h
registers (see Table
047Fh 0480h 7FFFh 8000h
Reserved Program memory Kbytes)
FFDFh FFE0h Interrupt reset vectors (see Table FFFFh
Kbytes
FFFFh
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ST72321BLxx-Auto Table
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 0030h MCCSR MCCBCR Flash SPIDR SPICR SPICSR ISPR0 ISPR1 ISPR2 ISPR3 EICR FCSR I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR
Register memory
Hardware register map(1)
Block Port A(2) Register label PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR PDADR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR PFOR Register name Port data register Port data direction register Port option register Port data register Port data direction register Port option register Port data register Port data direction register Port option register Port data register Port data direction register Port option register Port data register Port data direction register Port option register Port data register Port data direction register Port option register Reserved area bytes) control register status register status register clock control register address register address register2 data register Reserved area bytes) data register control register control/status register Interrupt software priority register Interrupt software priority register Interrupt software priority register Interrupt software priority register External interrupt control register Flash control/status register Watchdog control register Reserved area byte) Main clock control/status register Main clock controller: beep control register Reserved area bytes) Read only Read only Reset status 00h(3) 00h(3) 00h(3) 00h(3) 00h(3) 00h(3) Remarks R/W(2) R/W(2)
Port B(2)
Port
Port
D(2)
Port
E(2)
Port F(2)
Watchdog WDGCR
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Register memory Table
Address 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 006Fh 0070h 0071h 0072h ADCCSR ADCDRH ADCDRL TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR
ST72321BLxx-Auto
Hardware register map(1) (continued)
Block Register label TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Register name Timer control register Timer control register Timer control/status register Timer input capture high register Timer input capture register Timer output compare high register Timer output compare register Timer counter high register Timer counter register Timer alternate counter high register Timer alternate counter register Timer input capture high register Timer input capture register Timer output compare high register Timer output compare register Reserved area byte) Timer control register Timer control register Timer control/status register Timer input capture high register Timer input capture register Timer output compare high register Timer output compare register Timer counter high register Timer counter register Timer alternate counter high register Timer alternate counter register Timer input capture high register Timer input capture register Timer output compare high register Timer output compare register status register data register baud rate register control register control register extended receive prescaler register Reserved area extended transmit prescaler register Reserved area bytes) Control/status register Data high register Data register Read only Read only xxxx x0xxb x000 0000b -00h Read only Read only Read only Read only Read only Read only Read only Read only Read only Reset status xxxx x0xxb Remarks Read only Read only Read only Read only Read only Read only Read only Read only
Timer
Timer
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ST72321BLxx-Auto Table
Address 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh
Legend: undefined; read/write bits associated with unavailable pins must always keep their reset value.
Register memory
Hardware register map(1) (continued)
Block Register label Register name Timer Duty Cycle Register Timer Duty Cycle Register Timer Duty Cycle Register Timer Duty Cycle Register Timer Control Register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register Timer Input Capture Control/Status Reg. Timer Input Capture Register Timer Input Capture Register Reserved area bytes) Reset status Remarks Read only Read only
PWMDCR3 PWMDCR2 PWMDCR1 PWMDCR0 PWMCR ARTCSR ARTCAR ARTARR ARTICCSR ARTICR1 ARTICR2
contents port registers readable only output configuration. input configuration, values pins returned instead register contents.
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Flash program memory
ST72321BLxx-Auto
Flash program memory
Introduction
dual voltage high density Flash (HDFlash) non-volatile memory that electrically erased single block individual sectors programmed byte-by-byte basis using external supply. HDFlash devices programmed erased off-board (plugged programming tool) on-board using (in-circuit programming) (in-application programming). array matrix organization means that each sector erased reprogrammed without affecting other sectors.
Main features
Flash programming modes: Insertion programming tool: this mode, sectors including option bytes programmed erased. (in-circuit programming): this mode, sectors including option bytes programmed erased without removing device from application board. (in-application programming): this mode, sectors except sector programmed erased without removing device from application board while application running.
(in-circuit testing) downloading executing user application test patterns Readout protection Register access security system (RASS) prevent accidental programming erasing
Structure
Flash memory organized sectors used both code data storage. Depending overall Flash memory size microcontroller device, there three user sectors (see Table Each these sectors erased independently avoid unnecessary erasing whole Flash memory when only partial erasing required. first sectors have fixed size Kbytes (see Figure Memory sector address page 23). They mapped upper part addressing space reset interrupt vectors located sector (F000h-FFFFh). Table Sectors available Flash devices
Flash size (bytes) Available sectors Sectors
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ST72321BLxx-Auto Figure Memory sector address
7FFFh Sector DFFFh EFFFh FFFFh Kbytes Kbytes Kbytes Flash memory size
Flash program memory
Sector Sector
4.3.1
Readout protection
Readout protection, when selected, provides protection against program memory content extraction against write access Flash memory. Even protection considered totally unbreakable, feature provides very high level protection general purpose microcontroller. Flash devices, this protection removed reprogramming option. this case, entire program memory first automatically erased. Readout protection selection Flash devices enabled removed through FMP_R option byte.
interface
needs minimum four pins connected programming tool (see Figure Typical interface page 24). These pins are: RESET: VSS: ICCCLK: ICCDATA: ICCSEL/VPP: VDD: Device reset Device power supply ground output serial clock input/output serial data Programming voltage Application board power supply (optional, Figure Typical interface page Note
OSC1(or OSCIN): Main clock input external source (optional)
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Flash program memory Figure Typical interface
Programming tool connector cable note
ST72321BLxx-Auto
Application board connector HE10 connector type
note
Application reset source note Application power supply note Application OSC2 OSC1 ICCSEL/VPP ICCDATA ICCCLK RESET
ICCCLK ICCDATA pins only used outputs application, signal isolation necessary. soon programming tool plugged board, even session progress, ICCCLK ICCDATA pins available application. they used inputs application, isolation such serial resistor implemented case another device forces signal. Refer programming tool documentation recommended resistor values. During session, programming tool must control RESET pin. This lead conflicts between programming tool application reset circuit drives more than high level (push pull output pull-up resistor <1K). Schottky diode used isolate application reset circuit this case. When using classical network with reset management with open drain output pull-up resistor >1K, additional components needed. cases user must ensure that external reset generated application during session. connector depends programming tool architecture. This must connected when using most programming tools used monitor application power supply). Please refer programming tool manual. must connected OSC1 OSCIN when clock available application selected clock option programmed option byte. devices with multioscillator capability must have OSC2 grounded this case.
In-circuit programming (ICP)
perform microcontroller must switched (in-circuit communication) mode external controller programming tool. Depending code downloaded RAM, Flash memory programming fully customized (number bytes program, program locations, selection serial communication interface downloading). When using STMicroelectronics third-party programming tool that supports specific microcontroller device, user needs only implement hardware interface application board (see Figure more details locations, refer Section Package pinout description page
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ST72321BLxx-Auto
Flash program memory
In-application programming (IAP)
This mode uses BootLoader program previously stored sector user mode plugging device programming tool). This mode fully controlled user software, which means adapted user application (such user-defined strategy entering programming mode, choice communications protocol used fetch data stored). example, possible download code from SPI, SCI, interfaces program Flash. mode used program Flash sectors except sector which write/erase protected allow recovery case errors occur during programming operation.
Related documentation
details Flash programming protocol, refer Flash programming reference manual protocol reference manual.
4.7.1
Register description
Flash control/status register (FCSR)
FCSR Reset value: 0000 0000 (00h)
This register reserved programming tool software. controls Flash programming erasing operations. Table Flash control/status register address reset value
Register label FCSR Reset value
Address (Hex.) 0029h
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Central processing unit
ST72321BLxx-Auto
Central processing unit
Introduction
This full 8-bit architecture contains internal registers allowing efficient 8-bit data manipulation.
Main features
Enables execution basic instructions Fast 8-bit 8-bit multiply main addressing modes (with indirect addressing mode) 8-bit index registers 16-bit stack pointer power halt wait modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
registers
registers shown Figure present memory mapping accessed specific instructions. Figure registers
Reset value Reset value Reset value Program counter Reset value reset vector FFFEh-FFFFh Reset value Stack pointer Reset value stack higher address undefined value index register index register Accumulator
Condition code register
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ST72321BLxx-Auto
Central processing unit
Accumulator
accumulator 8-bit general purpose register used holding operands results arithmetic logic calculations well results data manipulations.
Index registers
These 8-bit registers used create effective addresses temporary storage areas data manipulation (the cross-assembler generates precede instruction (PRE) indicate that following instruction refers register). register affected interrupt automatic procedures.
Program counter (PC)
program counter 16-bit register containing address next instruction executed CPU. made 8-bit registers (program counter which LSB) (program counter high which MSB).
Condition code register (CC)
Reset value: 111x 1xxx
8-bit condition code register contains interrupt masks four flags representative result instruction just executed. This register also handled PUSH instructions. These bits individually tested and/or controlled specific instructions.
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Central processing unit Table
ST72321BLxx-Auto register description
name Function Interrupt management bits interrupt combination bits gives current interrupt software priority: Interrupt software priority level (main) Interrupt software priority level Interrupt software priority level Interrupt software priority level interrupt disable) These bits set/cleared hardware when entering interrupt. loaded value given corresponding bits interrupt software priority registers (ISPRx). They also set/cleared software with RIM, SIM, IRET, HALT, PUSH/POP instructions. Section Interrupts page more details. Arithmetic management half carry This hardware when carry occurs between bits during instruction. reset hardware during same instruction. half carry occurred half carry occurred This tested using JRNH instruction. useful arithmetic subroutines. Arithmetic management negative This cleared hardware. representative result sign last arithmetic, logical data manipulation. copy result bit. result last operation positive null result last operation negative (i.e. most significant logic This accessed JRMI JRPL instructions. Arithmetic management zero This cleared hardware. This indicates that result last arithmetic, logical data manipulation zero. result last operation different from zero result last operation zero This accessed JREQ JRNE test instructions. Arithmetic management carry/borrow This cleared hardware software. indicates overflow underflow occurred during last arithmetic operation. overflow underflow occurred overflow underflow occurred This driven instructions tested JRNC instructions. also affected `bit test branch', shift rotate instructions.
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Central processing unit
Stack pointer register (SP)
SP[7:0] Reset value:
stack pointer 16-bit register which always pointing next free location stack. then decremented after data been pushed onto stack incremented before data popped from stack (see Figure Stack manipulation example page 30). Since stack bytes deep, most significant bits forced hardware. Following reset, after reset stack pointer instruction (RSP), stack pointer contains reset value (the bits set) which stack higher address. least significant byte stack pointer (called directly accessed instruction. Note: When lower limit exceeded, stack pointer wraps around stack upper limit, without indicating stack overflow. previously stored information then overwritten therefore lost. stack also wraps case underflow. stack used save return address during subroutine call context during interrupt. user also directly manipulate stack means PUSH instructions. case interrupt, stored first location pointed Then other registers stored next locations shown Figure
When interrupt received, decremented context pushed stack return from interrupt, incremented context popped from stack
subroutine call occupies locations interrupt five locations stack area.
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Central processing unit Figure Stack manipulation example
Interrupt event PUSH
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Call subroutine 0100h
IRET
01FFh
Stack higher address 01FFh Stack lower address 0100h
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Supply, reset clock management
Supply, reset clock management
Introduction
device includes range utility features securing application critical situations (for example case power brown-out), reducing number external components. overview shown Figure
Main features
Optional multiplying frequency (not used with internal oscillator order respect maximum operating frequency) Reset sequence manager (RSM) Multi-oscillator clock management (MO) crystal/ceramic resonator oscillators internal oscillator
Phase locked loop
clock frequency input range MHz, used multiply frequency obtain fOSC2 MHz. enabled option byte opt0 (see Table 123: Option byte description page 208). disabled, then fOSC2 fOSC/2.
Caution: Caution: Caution:
recommended applications where timing accuracy required. must used with internal oscillator. When used with external clock signal, clock signal must available OSCIN before reset signal released. Figure Clock, reset supply block diagram
block OSC2 OSC1 Multioscillator (MO) fOSC option RESET Reset sequence manager (RSM) Watchdog timer (WDG) fOSC2 Main clock fCPU controller with real-time clock (MCC/RTC)
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Supply, reset clock management
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Multi-oscillator (MO)
main clock generated three different source types coming from multi-oscillator block:
external source crystal ceramic resonator oscillators internal high frequency oscillator
Each oscillator optimized given frequency range terms consumption selectable through option byte. associated hardware configurations shown Table clock source page Refer electrical characteristics section more details. Caution: OSC1 and/or OSC2 pins must left unconnected. purposes failure mode effect analysis, should noted that OSC1 and/or OSC2 pins left unconnected, main oscillator start and, this configuration, could generate fOSC clock frequency excess allowed maximum MHz), putting unsafe/undefined state. product behavior must therefore considered undefined when pins left unconnected.
6.4.1
External clock source
this external clock mode, clock signal (square, sinus triangle) with ~50% duty cycle drive OSC1 while OSC2 tied ground.
6.4.2
Crystal/ceramic oscillators
This family oscillators advantage producing very accurate rate main clock ST7. selection within list four oscillators with different frequency ranges made option byte order reduce consumption (refer Section 14.2.1: Flash configuration page more details frequency ranges). this mode multi-oscillator, resonator load capacitors have placed close possible oscillator pins order minimize output distortion start-up stabilization time. loading capacitance values must adjusted according selected oscillator. These oscillators stopped during reset phase avoid losing time oscillator start-up phase.
6.4.3
Internal oscillator
This oscillator provides cost solution main clock using only internal resistor capacitor. Internal oscillator mode drawback lower frequency accuracy should used applications that require accurate timing. this mode, oscillator pins have tied ground. order exceed maximum operating frequency, internal oscillator must used with PLL.
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ST72321BLxx-Auto Table clock source
Supply, reset clock management
Hardware configuration
External clock
OSC1 OSC2
External source
Crystal/ceramic resonators
OSC1 OSC2
Load capacitors
Internal oscillator
OSC1 OSC2
6.5.1
Reset sequence manager (RSM)
Introduction
reset sequence manager includes three reset sources shown Figure Reset block diagram page
External RESET source pulse Internal watchdog reset
These sources RESET which always kept during delay phase. reset service routine vector fixed addresses FFFEh-FFFFh memory map. basic reset sequence consists three phases shown Figure Reset sequence phases page
Active phase depending reset source 4096 clock cycle delay (selected option byte) Reset vector fetch
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Supply, reset clock management Caution:
ST72321BLxx-Auto
When unprogrammed fully erased, Flash blank reset vector programmed. this reason, recommended keep RESET state until programming mode entered, order avoid unwanted behavior. 4096 clock cycle delay allows oscillator stabilize ensures that recovery taken place from reset state. shorter longer clock cycle delay should selected option byte correspond stabilization time external oscillator used application. reset vector fetch phase duration clock cycles. Figure Reset sequence phases
Reset Active phase Internal reset 4096 clock cycles Fetch vector
6.5.2
Asynchronous external RESET
RESET both input open-drain output with integrated weak pull-up resistor. This pull-up fixed value varies according input voltage. pulled external circuitry reset device. Section Electrical characteristics page 173. reset signal originating from external source must have duration least th(RSTL)in order recognized (see Figure Reset sequences page 35). This detection asynchronous therefore enter reset state even halt mode. Figure Reset block diagram
RESET
Filter
Internal reset
Pulse generator
Watchdog reset
RESET asynchronous signal which plays major role performance. noisy environment, recommended follow guidelines mentioned electrical characteristics section.
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Supply, reset clock management
6.5.3
External power-on reset
start microcontroller correctly, user must ensure means external reset circuit that reset signal held until over minimum level specified selected fOSC frequency. proper reset signal slow rising supply generally provided external network connected RESET pin.
6.5.4
Internal watchdog reset
reset sequence generated internal watchdog counter overflow shown Figure Starting from watchdog counter underflow, device RESET acts output that pulled during least tw(RSTL)out. Figure Reset sequences
External reset Active phase Active phase Watchdog reset
th(RSTL)in External RESET source RESET Watchdog reset Watchdog underflow
tw(RSTL)out
Internal reset (256 4096 TCPU) Vector fetch
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Interrupts
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Interrupts
Introduction
enhanced interrupt management provides following features:
Hardware interrupts Software interrupt (TRAP) Nested concurrent interrupt management with flexible interrupt priority level management: software programmable nesting levels interrupt vectors fixed hardware maskable events: reset, TRAP
This interrupt management based
register (I1:0) Interrupt software priority registers (ISPRx) Fixed interrupt vector addresses located high addresses memory (FFE0h FFFFh) sorted hardware priority order
This enhanced interrupt controller guarantees full upward compatibility with standard (not nested) interrupt controller.
Masking processing flow
interrupt masking managed bits register ISPRx registers which give interrupt software priority level each interrupt vector (see Table Interrupt software priority levels page 37). processing flow shown Figure Interrupt processing flowchart page When interrupt request serviced:
Normal processing suspended current instruction execution registers saved onto stack bits register according corresponding values ISPRx registers serviced interrupt vector then loaded with interrupt vector interrupt service first instruction interrupt service routine fetched (refer Table Interrupt mapping page vector addresses).
interrupt service routine should with IRET instruction which causes contents saved registers recovered from stack. Note: consequence IRET instruction, bits restored from stack program previous level resumes.
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ST72321BLxx-Auto Table Interrupt software priority levels
Interrupt software priority Level (main) Level Level Level interrupt disable) Level
Interrupts
High
Figure Interrupt processing flowchart
Pending interrupt Interrupt same lower software priority than current
Reset
TRAP I1:0
Fetch next instruction
interrupt stays pending
`IRET'
Interrupt higher software priority than current
Restore from stack
Execute instruction
Stack Load I1:0 from interrupt register Load from interrupt vector
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Interrupts
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7.2.1
Servicing pending interrupts
several interrupts pending same time, interrupt taken into account determined following two-step process:
highest software priority interrupt serviced several interrupts have same software priority then interrupt with highest hardware priority serviced first.
Figure describes this decision process. Figure Priority decision process
Pending interrupts
Same
Software priority
Different
Highest software priority serviced
Highest hardware priority serviced
When interrupt request serviced immediately, latched then processed when software priority combined with hardware priority becomes highest one. Note: hardware priority exclusive while software not. This allows previous process succeed with only interrupt. Reset TRAP considered having highest software priority decision process.
7.2.2
Different interrupt vector sources
interrupt source types managed interrupt controller: non-maskable type (reset, TRAP) maskable type (external from internal peripherals).
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Interrupts
7.2.3
Non-maskable sources
These sources processed regardless state bits register (see Figure Interrupt processing flowchart page 37). After stacking registers (except reset), corresponding vector loaded register bits disable interrupts (level These sources allow processor exit halt mode.
TRAP (non maskable software interrupt)
This software interrupt serviced when TRAP instruction executed. will serviced according flowchart Figure Interrupt processing flowchart page
Reset
reset source highest priority ST7. This means that first current routine highest software priority (level highest hardware priority. Section 6.5: Reset sequence manager (RSM) page
7.2.4
Maskable sources
Maskable interrupt vector sources serviced corresponding interrupt enabled interrupt software priority ISPRx registers) higher than currently being serviced register). these conditions false, interrupt latched thus remains pending.
External interrupts
External interrupts allow processor exit from halt power mode. External interrupt sensitivity software selectable through external interrupt control register (EICR). external interrupt triggered edge latched interrupt request automatically cleared upon entering interrupt service routine. several input pins group connected same interrupt line selected simultaneously, these logically ORed.
Peripheral interrupts
Usually peripheral interrupts cause exit from halt mode except those mentioned Table Interrupt mapping page peripheral interrupt occurs when specific flag peripheral status registers corresponding enable peripheral control register. general sequence clearing interrupt based access status register followed read write associated register. Note: clearing sequence resets internal latch. pending interrupt (that waiting serviced) therefore lost clear sequence executed.
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Interrupts
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Interrupts power modes
interrupts allow processor exit wait power mode. contrary, only external other specified interrupts allow processor exit from halt modes (see column `exit from halt' Table Interrupt mapping page When several pending interrupts present while exiting halt mode, first serviced only interrupt with exit from halt mode capability selected through same decision process shown Figure Priority decision process page
Note:
interrupt, that able exit from halt mode, pending with highest priority when exiting halt mode, this interrupt serviced after first serviced.
Concurrent nested management
Figure Figure Nested interrupt management page show different interrupt management modes. first called concurrent mode does allow interrupt interrupted, unlike nested mode Figure interrupt hardware priority given this order from lowest highest: MAIN, IT4, IT3, IT2, IT1, IT0. software priority given each interrupt.
Warning:
stack overflow occur without notifying software failure.
Figure Concurrent interrupt management
TRAP
TRAP Hardware priority MAIN 11/10 MAIN
Software priority level
Used stack bytes
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ST72321BLxx-Auto Figure Nested interrupt management
TRAP Software priority level
Interrupts
TRAP Hardware priority MAIN 11/10 MAIN
Used stack bytes
Interrupt registers
register interrupt bits
Reset value: 111x 1010 (xAh)
Table
register description
name Function Software interrupt priority These bits indicate current interrupt software priority: Interrupt software priority level (main) Interrupt software priority level Interrupt software priority level Interrupt software priority level interrupt disable(1)) These bits set/cleared hardware when entering interrupt. loaded value given corresponding bits interrupt software priority registers (ISPRx). They also set/cleared software with RIM, SIM, HALT, WFI, IRET PUSH/POP instructions (see Table Dedicated interrupt instruction page 43).
TRAP reset events interrupt level program.
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Interrupts
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Interrupt software priority registers (ISPRX)
ISPR0 I1_3 ISPR1 I1_7 ISPR2 I1_11 ISPR3 I1_13 I0_13 I0_11 I1_10 I0_10 I1_9 I0_9 I0_7 I1_6 I0_6 I1_5 I0_5 I0_3 I1_2 I0_2 I1_1 I0_1 Reset value: 1111 1111 (FFh) I1_0 I0_0
Reset value: 1111 1111 (FFh) I1_4 I0_4
Reset value: 1111 1111 (FFh) I1_8 I0_8
Reset value: 1111 1111 (FFh) I1_12 I0_12
These four registers contain interrupt software priority each interrupt vector.
Each interrupt vector (except reset TRAP) corresponding bits ISPRx registers where software priority stored. This correspondence shown Table Each I1_x I0_x value ISPRx registers same meaning bits register. Level cannot written (I1_x I0_x this case, previously stored value kept (example, previous CFh, write 64h, result 44h). ISPRx interrupt vector correspondence
Vector address FFFBh-FFFAh FFF9h-FFF8h FFE1h-FFE0h ISPRx bits I1_0 I0_0 bits* I1_1 I0_1 bits I1_13 I0_13 bits
Table
reset, TRAP vectors have software priorities. When serviced, bits register both set. Caution: I1_x I0_x bits modified while interrupt executed following behavior considered: interrupt still pending (new interrupt flag cleared) software priority higher than previous one, interrupt re-entered. Otherwise, software priority stays unchanged next interrupt request (after IRET interrupt
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Interrupts
Interrupt related instructions
Table
Instruction HALT IRET JRNM TRAP
Dedicated interrupt instruction set(1)
description Entering halt mode Interrupt routine return Jump I1:0 (level Jump I1:0 from stack Enable interrupt (level set) I1:0 I1:0 Load I1:0 Function/example
Disable interrupt (level set) Load I1:0 Software trap Wait interrupt Software
During execution interrupt routine, HALT, RIM, instructions change current software priority next IRET instruction previously mentioned instructions.
7.7.1
External interrupts
port interrupt sensitivity
external interrupt sensitivity controlled IPA, ISxx bits EICR register (Figure External interrupt control bits page 44). This control allows four fully independent external interrupt source sensitivities. Each external interrupt source generated four five) different events pin:
Falling edge Rising edge Falling rising edge Falling edge level Rising edge high level (only ei2)
guarantee correct functionality, sensitivity bits EICR register modified only when bits register both (level This means that interrupts must disabled before changing sensitivity. pending interrupts cleared writing different value ISx[1:0], bits EICR.
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Interrupts Figure External interrupt control bits
Port interrupt PAOR.3 PADDR.3 EICR IS20 IS21
ST72321BLxx-Auto
Sensitivity control
interrupt source
Port [2:0] interrupts PFOR.2 PFDDR.2
EICR
IS20 IS21 interrupt source
Sensitivity control
Port [3:0] interrupts PBOR.3 PBDDR.3
EICR IS10 IS11 interrupt source
Sensitivity control
Port interrupts PBOR.4 PBDDR.4
EICR IS10 IS11
Sensitivity control
interrupt source
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Interrupts
External interrupt control register (EICR)
EICR IS1[1:0] IS2[1:0] Reset value: 0000 0000 (00h) Reserved
Table
EICR register description
name Function Interrupt sensitivity (ei2 ei3) interrupt sensitivity, defined using IS1[1:0] bits, applied following external interrupts: External interrupt (port B[3:0]): External interrupt sensitivity falling edge level (IPB rising edge high level (IPB External interrupt sensitivity rising edge only (IPB falling edge only (IPB External interrupt sensitivity falling edge only (IPB rising edge only (IPB External interrupt sensitivity rising falling edge (IPB External interrupt (port B[4]): external interrupt sensitivity falling edge level external interrupt sensitivity rising edge only external interrupt sensitivity falling edge only external interrupt sensitivity rising falling edge These bits written only when register both (level Interrupt polarity port This used invert sensitivity port [3:0] external interrupts. cleared software only when register both (level sensitivity inversion Sensitivity inversion
IS1[1:0]
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Interrupts Table
ST72321BLxx-Auto EICR register description (continued)
name Function Interrupt sensitivity (ei0 ei1) interrupt sensitivity, defined using IS2[1:0] bits, applied following external interrupts: External interrupt (port A[3]): External interrupt sensitivity falling edge level (IPA rising edge high level (IPA External interrupt sensitivity rising edge only (IPA falling edge only (IPA External interrupt sensitivity falling edge only (IPA rising edge only (IPA External interrupt sensitivity rising falling edge (IPA External interrupt port ([F2:0]): External interrupt sensitivity falling edge level External interrupt sensitivity rising edge only External interrupt sensitivity falling edge only External interrupt sensitivity rising falling edge These bits written only when register both (level Interrupt polarity port This used invert sensitivity port A[3] external interrupts. cleared software only when register both (level sensitivity inversion Sensitivity inversion Reserved, must always kept cleared
IS2[1:0]
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Interrupts
Table
Nested interrupts register reset value
Nested interrupts register reset values
Register label 0024h ISPR0 Reset value I1_3 0025h ISPR1 Reset value I1_7 I0_7 I1_6 0026h ISPR2 Reset value I1_10 I0_10 I0_6 I1_5 I0_3 I1_2 I0_2
Address (Hex.)
I1_1 I0_5 I1_4 I0_1 I0_4
Timer I1_9 I1_13 IS20 I0_9 I0_13
Timer I1_8 I1_12 I0_8 I0_12
0027h
ISPR3 Reset value EICR Reset value
IS11
IS10
IS21
0028h
7.10
Table
Interrupt mapping
Interrupt mapping
Description Reset TRAP Software interrupt used Register Priority label order Higher priority Exit from halt MCCSR SPICSR TASR TBSR SCISR Lower priority Exit from active halt Address vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h Source block Reset
Timer Timer MCC/RTC
Main clock controller time base interrupt External interrupt port A[3:0] External interrupt port F[2:0] External interrupt port B[3:0] External interrupt port B[7:4] used peripheral interrupts Timer peripheral interrupts Timer peripheral interrupts peripheral interrupts
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Power saving modes
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Power saving modes
Introduction
give large measure flexibility application terms power consumption, four main power saving modes implemented (see Figure 17): Slow, wait (slow wait), active halt halt. After reset normal operating mode selected default (run mode). This mode drives device (CPU embedded peripherals) means master clock which based main oscillator frequency divided multiplied (fOSC2). From mode, different power saving modes selected setting relevant register bits calling specific software instruction whose action depends oscillator status. Figure Power saving mode transitions
High
Slow
Wait
Slow Wait
Active Halt
Halt Powe consumption
Slow mode
This mode targets:
reduce power consumption decreasing internal clock device adapt internal clock frequency (fCPU) available supply voltage
Slow mode controlled three bits MCCSR register: which enables disables slow mode bits which select internal slow frequency (fCPU). this mode, master clock frequency (fOSC2) divided peripherals clocked this lower frequency (fCPU). Note: Slow wait mode activated when entering wait mode while device already slow mode.
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ST72321BLxx-Auto Figure Slow mode clock transitions
fOSC2/2 fCPU fOSC2/4 fOSC2
Power saving modes
fOSC2 MCCSR CP1:0
Normal mode request slow frequency request
Wait mode
Wait mode places power consumption mode stopping CPU. This power saving mode selected calling `WFI' instruction. peripherals remain active. During wait mode, I[1:0] bits register forced `10', enable interrupts. other registers memory remain unchanged. remains wait mode until interrupt reset occurs, whereupon program counter branches starting address interrupt reset service routine. remains Wait mode until reset interrupt occurs, causing wake Refer Figure Wait mode flowchart page
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Power saving modes Figure Wait mode flowchart
Oscillator Peripherals I[1:0] bits
ST72321BLxx-Auto
instruction
Reset
Interrupt Oscillator Peripherals I[1:0] bits
4096 clock cycle delay
Oscillator Peripherals I[1:0] bits
XX(1)
Fetch reset vector service interrupt
Before servicing interrupt, register pushed stack. I[1:0] bits register current software priority level interrupt routine recovered when register popped.
Active halt halt modes
Active halt halt modes lowest power consumption modes MCU. They both entered executing `HALT' instruction. decision enter either Active halt halt mode given MCC/RTC interrupt enable flag (OIE MCCSR register). Table
MCCSR
Active halt halt power saving modes
Power saving mode entered when HALT instruction executed Halt mode Active halt mode
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Power saving modes
8.4.1
Active halt mode
Active halt mode lowest power consumption modes with real-time clock available. entered executing `HALT' instruction when main clock controller status register (MCCSR) (see Section 10.2: Main clock controller with real-time clock beeper (MCC/RTC) page more details MCCSR register). exit active halt mode reception either MCC/RTC interrupt, specific interrupt (see Table Interrupt mapping page reset. When exiting active halt mode means interrupt, 4096 cycle delay occurs. resumes operation servicing interrupt fetching reset vector which woke (see Figure Active halt mode flowchart page 52). When entering active halt mode, I[1:0] bits register forced `10b' enable interrupts. Therefore, interrupt pending, wakes immediately. active halt mode, only main oscillator associated counter (MCC/RTC) running keep wake time base. other peripherals clocked except those which their clock supply from another clock generator (such external auxiliary oscillator). safeguard against staying locked active halt mode provided oscillator interrupt.
Note:
soon interrupt capability oscillators selected (MCCSR.OIE set), entering active halt mode while watchdog active does generate reset. This means that device cannot spend more than defined delay this power saving mode. When exiting active halt mode following interrupt, MCCSR register must cleared before tDELAY after interrupt occurs (tDELAY 4096 tCPU delay depending option byte). Otherwise, enters halt mode remaining tDELAY period. Figure Active halt timing overview
Caution:
Active halt
4096 cycle delay(1)
HALT instruction [MCCSR.OIE
Reset interrupt Fetch vector
This delay occurs only exits active halt mode means reset
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Power saving modes Figure Active halt mode flowchart
Oscillator Peripherals(1) I[1:0] bits
ST72321BLxx-Auto
HALT instruction (MCCSR.OIE
Reset
Interrupt(2) Oscillator Peripherals I[1:0] bits
XX(3)
4096 clock cycle delay Oscillator Peripherals I[1:0] bits
XX(3)
Fetch reset vector service interrupt
Peripheral clocked with external clock source still active Only MCC/RTC interrupt some specific interrupts exit from active halt mode (such external interrupt). Refer Table Interrupt mapping page more details. Before servicing interrupt, register pushed stack. I[1:0] bits register current software priority level interrupt routine restored when register popped.
8.4.2
Halt mode
halt mode lowest power consumption modes MCU. entered executing `HALT' instruction when main clock controller status register (MCCSR) cleared (see Section 10.2: Main clock controller with real-time clock beeper (MCC/RTC) page more details MCCSR register). exit halt mode reception either specific interrupt (see Table reset. When exiting halt mode means reset interrupt, oscillator immediately turned 4096 cycle delay used stabilize oscillator. After start delay, resumes operation servicing interrupt fetching reset vector which woke (see Figure Halt mode flowchart page 54). When entering halt mode, I[1:0] bits register forced `10b' enable interrupts. Therefore, interrupt pending, wakes immediately. halt mode, main oscillator turned causing internal processing stopped, including operation on-chip peripherals. Peripherals clocked except those which their clock supply from another clock generator (such external auxiliary oscillator).
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Power saving modes
compatibility watchdog operation with halt mode configured `WDGHALT' option option byte. HALT instruction when executed while watchdog system enabled, generate watchdog reset (see Section 14.2.1: Flash configuration page 207) more details. Figure Halt timing overview
Halt
4096 cycle delay
HALT instruction [MCCSR.OIE
Reset interrupt Fetch vector
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Power saving modes Figure Halt mode flowchart
HALT instruction (MCCSR.OIE Enable
ST72321BLxx-Auto
Watchdog Disable
WDGHALT(1)
Watchdog reset
Oscillator Peripherals(2) I[1:0] bits
Reset
Interrupt(3) Oscillator Peripherals I[1:0] bits XX(4)
4096 clock cycle delay
Oscillator Peripherals I[1:0] bits
XX(4)
Fetch reset vector service interrupt
WDGHALT option bit. Section 14.2.1: Flash configuration page more details. Peripherals clocked with external clock source still active. Only some specific interrupts exit from halt mode (such external interrupt). Refer Table Interrupt mapping page more details. Before servicing interrupt, register pushed stack. I[1:0] bits register current software priority level interrupt routine recovered when register popped.
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Power saving modes
Halt mode recommendations
Make sure that external event available wake microcontroller from halt mode When using external interrupt wake microcontroller, reinitialize corresponding `input pull-up with interrupt' before executing HALT instruction. main reason this that wrongly configured external interference unforeseen logical condition. same reason, reinitialize level sensitiveness each external interrupt precautionary measure. opcode HALT instruction avoid unexpected HALT instruction program counter failure, advised clear occurrences data value from memory. example, avoid defining constant with value HALT instruction clears interrupt mask register allow interrupts, user choose clear pending interrupt bits before executing HALT instruction. This avoids entering other peripheral interrupt routines after executing external interrupt routine corresponding wake event (reset external interrupt).
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ports
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ports
Introduction
ports offer different functional modes:
Transfer data through digital inputs outputs External interrupt generation Alternate signal input/output on-chip peripherals
specific pins they offer following:
port contains pins. Each programmed independently digital input (with without interrupt generation) digital output.
Functional description
Each port main registers:
Data register (DR) Data direction register (DDR) Option register (OR)
Each port also optional register:
Each programmed using corresponding register bits registers: corresponding port. same correspondence used register. following description takes into account register, (for specific ports which provide this register refer Section 9.3: port implementation page 60). generic block diagram shown Figure port general block diagram page
9.2.1
Input modes
input configuration selected clearing corresponding register bit. this case, reading register returns digital value applied external pin. Different input modes selected software through register.
Note:
Writing register modifies latch value does affect status. When switching from input output mode, register written first drive correct level soon port configured output. read/modify/write instructions (BSET BRES) modify register this might corrupt content I/Os configured input.
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ports
External interrupt function
When configured input with interrupt, event this generate external interrupt request CPU. Each independently generate interrupt request. interrupt sensitivity independently programmable using sensitivity bits EICR register. Each external interrupt vector linked dedicated group port pins (see Section Package pinout description page Section Interrupts page 36). several input pins selected simultaneously interrupt sources, these first detected according sensitivity bits EICR register then logically ORed. external interrupts hardware interrupts, which means that request latch (not accessible directly application) automatically cleared when corresponding interrupt vector fetched. clear unwanted pending interrupt software, sensitivity bits EICR register must modified.
9.2.2
Output modes
output configuration selected setting corresponding register bit. this case, writing register applies this digital value through latch. Then reading register returns previously stored value. different output modes selected software through register: Output push-pull open-drain. Table register value output status. Table
register value output status
Push-pull Open-drain Floating
9.2.3
Alternate functions
When on-chip peripheral configured pin, alternate function automatically selected. This alternate function takes priority over standard programming. When signal coming from on-chip peripheral, automatically configured output mode (push-pull open drain according peripheral). When signal going on-chip peripheral, must configured input mode. this case, state also digitally readable addressing register.
Note:
Input pull-up configuration cause unexpected value input alternate peripheral input. When on-chip peripheral uses input output, this configured input floating mode.
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ports Figure port general block diagram
Register access
ST72321BLxx-Auto
Alternate output
P-buffer (see table below)
Alternate enable
Pull-up (see table below)
Pull-up condition Data implemented N-buffer Diodes (see table below)
Analog input CMOS Schmitt trigger
Alternate input
External interrupt source (eix)
Table
port mode options
Diodes Configuration mode Floating with/without interrupt Pull-up Off(1) On(2) Off(1) NI(3) P-buffer
Input Pull-up with/without interrupt Push-pull Output Open drain (logic level) True open drain
Implemented activated Implemented activated implemented
Off(1) On(2) Off(1) NI(3) NI(4) On(2) On(2)
diode implemented true open drain pads. local protection between implemented protect device against positive stress.
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ST72321BLxx-Auto Table port configurations
Hardware configuration
implemented true open drain ports Pull-up condition register access
ports
register
Data
Input(1)
Alternate input
External interrupt source (eix) Interrupt condition
Analog input
Open-drain output(2)
implemented true open drain ports
register access
register
Data
Alternate enable
Alternate output
Push-pull output(2)
implemented true open drain ports
register access
register
Data
Alternate enable
Alternate output
When port input configuration associated alternate function enabled output, reading register reads alternate function output status. When port output configuration associated alternate function enabled input, alternate function reads status given register content.
Caution:
alternate function must activated long configured input with interrupt, order avoid generating spurious interrupts.
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ports
ST72321BLxx-Auto
Analog alternate function
When used input, must configured floating input. analog multiplexer (controlled registers) switches analog voltage present selected common analog rail which connected input. recommended change voltage level loading port while conversion progress. Furthermore recommended have clocking pins located close selected analog pin.
Warning:
analog input voltage level must within limits stated absolute maximum ratings.
port implementation
hardware implementation each port depends settings registers specific features port such input true open drain. Switching these ports from state another should done sequence that prevents unwanted side effects. Recommended safe transitions illustrated Figure Other transitions potentially risky should avoided, since they likely present unwanted side-effects such spurious interrupt generation. port register configurations summarized Table Port register configurations page Figure Interrupt port state transitions
Input floating/pull-up interrupt Input floating (reset state) Output open-drain Output push-pull
DDR,
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Port
ports Port register configurations
Input (DDR name PA[7:6] Floating Pull-up Floating interrupt PB[3] True open-drain Output (DDR
Port
PA[5:4] PA[3]
Port
PB[4] PB[2:0] PC[7:0] PD[5:0] PE[1:0] PF[7:6] PF[4] PF[2:0] Floating
Pull-up interrupt Open drain Push-pull
Port Port Port
Pull-up
Port
Pull-up interrupt
power modes
Table
Mode Wait Halt
Effect power modes ports
Description effect ports. External interrupts cause device exit from wait mode. effect ports. External interrupts cause device exit from halt mode.
Interrupts
external interrupt event generates interrupt corresponding configuration selected with registers interrupt mask register active (RIM instruction). Table interrupt control/wake-up capability
Event flag Enable control DDRx Exit from wait Exit from halt
Interrupt event External interrupt selected external event
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ports Table port register reset values
Register label
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Address (Hex.)
Reset value port registers 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h PADR PADDR PAOR PBDR PBDDR PBOR PCDR PCDDR PCOR PDDR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR PFOR
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On-chip peripherals
10.1
10.1.1
On-chip peripherals
Watchdog timer (WDG)
Introduction
watchdog timer used detect occurrence software fault, usually generated external interference unforeseen logical conditions, which causes application program abandon normal sequence. watchdog circuit generates reset expiry programmed time period, unless program refreshes counter's contents before becomes cleared.
10.1.2
Main features
Programmable free-running downcounter Programmable reset Reset watchdog activated) when reaches zero Optional reset HALT instruction (configurable option byte) Hardware watchdog selectable option byte
10.1.3
Functional description
counter value stored watchdog control register (WDGCR bits T[6:0]), decremented every 16384 fOSC2 cycles (approx.), length timeout period programmed user increments. watchdog activated (the WDGA set) when 7-bit timer (bits T[6:0]) rolls over from cleared), initiates reset cycle pulling RESET typically 30µs. application program must write WDGCR register regular intervals during normal operation prevent reset. This downcounter free-running: counts down even watchdog disabled. value stored WDGCR register must between C0h:
WDGA (watchdog enabled) prevent generating immediate reset T[5:0] bits contain number increments which represents time delay before watchdog produces reset (see Figure Approximate timeout duration page 64). timing varies between minimum maximum value unknown status prescaler when writing WDGCR register (see Figure Exact timeout duration (tmin tmax) page 65).
Following reset, watchdog disabled. Once activated cannot disabled, except reset. used generate software reset (the WDGA cleared). watchdog activated, HALT instruction generates reset.
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On-chip peripherals Figure Watchdog block diagram
ST72321BLxx-Auto
fOSC2 MCC/RTC
Reset
Watchdog control register (WDGCR) WDGA
6-bit downcounter (CNT)
12-bit counter TB[1:0] bits (MCCSR register)
prescaler
10.1.4
program watchdog timeout
Figure shows linear relationship between 6-bit value loaded watchdog counter (CNT) resulting timeout duration milliseconds. This used quick calculation without taking timing variations into account. more precision needed, formulae Figure Exact timeout duration (tmin tmax) page
Caution:
When writing WDGCR register, always write avoid generating immediate reset. Figure Approximate timeout duration
value (hex.)
Watchdog timeout (ms) fOSC2
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ST72321BLxx-Auto Figure Exact timeout duration (tmin tmax)
Where: tmin0 (LSB 128) tOSC2 tmax0 16384 tOSC2 tOSC2 125ns fOSC2 value T[5:0] bits WDGCR register bits)
On-chip peripherals
values from table below depending timebase selected TB[1:0] bits MCCSR register.
(MCCSR reg.)
(MCCSR reg.)
Selected MCCSR timebase 10ms 25ms
calculate minimum watchdog timeout (tmin): Then Else min0
16384
osc2
4CNT 16384 min0
4CNT -MSB
osc2
calculate maximum watchdog timeout (tmax): Then Else max0
16384
osc2
max0
4CNT 16384
4CNT -MSB
osc2
Note: above formulae, division results must rounded down next integer value. Example: with timeout selected MCCSR register
Value T[5:0] bits WDGCR register (Hex.)
Min. watchdog timeout (ms) tmin 1.496
Max. watchdog timeout (ms) tmax 2.048 128.552
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On-chip peripherals
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10.1.5
power modes
Table
Mode Slow Wait effect watchdog effect watchdog MCCSR register WDGHALT option byte watchdog reset generated. enters halt mode. watchdog counter decremented once then stops counting longer able generate watchdog reset until receives external interrupt reset. external interrupt received, watchdog restarts counting after 4096 clocks. reset generated, watchdog disabled (reset state) unless hardware watchdog selected option byte. application recommendations Section 10.1.7 below. reset generated. reset generated. enters active halt mode. watchdog counter decremented. stops counting. When receives oscillator interrupt external interrupt, watchdog restarts counting immediately. When receives reset watchdog restarts counting after 4096 clocks.
Effect power modes watchdog timer
Description
Halt
10.1.6
Hardware watchdog option
hardware watchdog selected option byte, watchdog always active WDGA WDGCR used. Refer Section 14.2.1: Flash configuration page 207.
10.1.7
Using halt mode with (WDGHALT option)
following recommendation applies halt mode used when watchdog enabled: Before executing HALT instruction, refresh counter, avoid unexpected reset immediately after waking microcontroller.
10.1.8
Interrupts
None
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On-chip peripherals
10.1.9
Control register (WDGCR)
WDGCR WDGA T[6:0] Reset value: 0111 1111 (7Fh)
Table
WDGCR register description
name Function Activation bit(1) This software only cleared hardware after reset. When WDGA watchdog generate reset. Watchdog disabled Watchdog enabled 7-bit counter (MSB LSB) These bits contain value watchdog counter. They decremented every 16384 fOSC2 cycles (approx.). reset produced when rolls over from cleared).
WDGA
T[6:0]
WDGA used hardware watchdog option enabled option byte.
10.1.10
Watchdog timer register reset values
Table Watchdog timer register reset values
Register label WDGCR Reset value WDGA
Address (Hex.) 002Ah
10.2
Main clock controller with real-time clock beeper (MCC/RTC)
main clock controller consists three different functions:
programmable clock prescaler clock-out signal supply external devices real-time clock timer with interrupt capability
Each function used independently simultaneously.
10.2.1
Programmable clock prescaler
programmable clock prescaler supplies clock internal peripherals. manages Slow power saving mode (see Section 8.2: Slow mode page more details). prescaler selects fCPU main clock frequency controlled three bits MCCSR register: CP[1:0] SMS.
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On-chip peripherals
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10.2.2
Clock-out capability
clock-out capability alternate function port that outputs fOSC2 clock drive external devices. controlled MCCSR register.
Caution:
When selected, clock suspends clock during active halt mode.
10.2.3
Real-time clock timer (RTC)
counter real-time clock timer allows interrupt generated based accurate real-time clock. Four different time bases depending directly fOSC2 available. whole functionality controlled four bits MCCSR register: TB[1:0], OIF. When interrupt enabled (OIE set), enters active halt mode when HALT instruction executed. Section 8.4: Active halt halt modes page more details.
10.2.4
Beeper
beep function controlled MCCBCR register. output three selectable frequencies BEEP (I/O port alternate function). Figure Main clock controller (MCC/RTC) block diagram
MCCBCR Beep signal selection Beep
watchdog timer 12-bit counter
MCCSR fOSC2
MCC/RTC interrupt
fCPU
clock peripherals
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On-chip peripherals
10.2.5
power modes
Table
Mode Wait Active Halt
Effect power modes MCC/RTC
Description effect MCC/RTC peripheral. MCC/RTC interrupt causes device exit from wait mode. effect MCC/RTC counter (OIE set), registers frozen. MCC/RTC interrupt causes device exit from active halt mode. MCC/RTC counter registers frozen. MCC/RTC operation resumes when woken interrupt with `exit from halt' capability.
Halt
10.2.6
Interrupts
MCC/RTC interrupt event generates interrupt MCCSR register interrupt mask register active (RIM instruction). Table MCC/RTC interrupt control/wake-up capability
Event flag Enable control Exit from wait Exit from halt No(1)
Interrupt event Time base overflow event
MCC/RTC interrupt wakes from Active Halt mode, from Halt mode
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On-chip peripherals
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10.2.7
MCC/RTC registers
control/status register (MCCSR)
MCCSR CP[1:0] TB[1:0] Reset value: 0000 0000 (00h)
Table
MCCSR register description
name Function Main clock selection This enables alternate function port. cleared software. alternate function disabled (I/O free general-purpose I/O) alternate function enabled (fCPU port) Note: reduce power consumption, function active active halt mode. clock prescaler These bits select clock prescaler which applied different slow modes. Their action conditioned setting bit. These bits cleared software. fCPU slow mode fOSC2/2 fCPU slow mode fOSC2/4 fCPU slow mode fOSC2/8 fCPU slow mode fOSC2/16 Slow mode select This cleared software. Normal mode, fCPU fOSC2 Slow mode, fCPU given CP1, CP0; Section 8.2: Slow mode page Section 10.2: Main clock controller with real-time clock beeper (MCC/RTC) page more details. Time base control These bits select programmable divider time base. They cleared software: Time base (for counter prescaler 16000) (fOSC2 MHz) (fOSC2 MHz) Time base (for counter prescaler 32000) (fOSC2 MHz) (fOSC2 MHz) Time base (for counter prescaler 80000) 20ms (fOSC2 MHz) 10ms (fOSC2 MHz) Time base (for counter prescaler 200000) 50ms (fOSC2 MHz) 25ms (fOSC2 MHz) modification time base taken into account current period (previously set) avoid unwanted time shift. This allows this time base real-time clock.
CP[1:0]
TB[1:0]
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On-chip peripherals MCCSR register description (continued)
name Function Oscillator interrupt enable This cleared software. Oscillator interrupt disabled Oscillator interrupt enabled This interrupt used exit from active halt mode. When this set, calling software HALT instruction enters active halt power saving mode
Oscillator interrupt flag This hardware cleared software reading MCCSR register. indicates when that main oscillator reached selected elapsed time (TB1:0). Timeout reached Timeout reached Caution: BRES BSET instructions must used MCCSR register avoid unintentionally clearing bit.
beep control register (MCCBCR)
MCCBCR Reserved Reset value: 0000 0000 (00h) BC[1:0]
Table
MCCBCR register description
name Function Reserved, must kept cleared. Beep control These bits select beep capability: Beep mode (with fOSC2 MHz) Beep mode (with fOSC2 MHz) (output beep signal duty cycle) Beep mode (with fOSC2 MHz) (output beep signal duty cycle) beep mode (with fOSC2 MHz) ~500 (output beep signal duty cycle) beep output signal available active halt mode disabled reduce consumption.
BC[1:0]
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10.2.8
register reset values
Table Main clock controller register reset values
Register label MCCSR Reset value MCCBCR Reset value
Address (Hex.) 002Ch 002Dh
10.3
10.3.1
auto-reload timer (ART)
Introduction
pulse width modulated auto-reload timer on-chip peripheral consists 8-bit autoreload counter with compare/capture capabilities 7-bit prescaler clock source. These resources allow five possible operating modes:
Generation independent signals Output compare time base interrupt input capture functions External event detector external interrupt sources
three first modes used together with single counter frequency. timer used wake from wait halt modes.
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ST72321BLxx-Auto Figure auto-reload timer block diagram
PWMCR OCRx register
On-chip peripherals
DCRx register Load
PWMx
Port alternate function
Polarity control
Compare
register
8-bit counter (car register)
Load
ARTICx
Input capture control
LOAD
ICRx register
ICSx
ICIEx
ICFx
ICCSR interrupt
ARTCLK
fEXT fCPU fCOUNTER
fINPUT
Programmable prescaler
EXCL
FCRL
ARTCSR interrupt
10.3.2
Functional description
Counter
free running 8-bit counter output prescaler, incremented every rising edge clock signal. possible read write contents counter reading writing counter access register (ARTCAR). When counter overflow occurs, counter automatically reloaded with contents ARTARR register (the prescaler affected).
Counter clock prescaler
counter clock frequency given fCOUNTER fINPUT/2CC[2:0] timer counter's input clock (fINPUT) feeds 7-bit programmable prescaler, which selects available taps prescaler, defined CC[2:0] bits
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On-chip peripherals
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control/status register (ARTCSR). Thus division factor prescaler (where 1,.7). This fINPUT frequency source selected through EXCL ARTCSR register either fCPU external input frequency fEXT. clock input counter enabled (timer counter enable) ARTCSR register. When reset, counter stopped prescaler counter contents frozen. When set, counter runs rate selected clock source.
Counter prescaler initialization
After reset, counter prescaler cleared fINPUT fCPU. counter initialized
Writing ARTARR register then setting FCRL (force counter reload) (timer counter enable) bits ARTCSR register Writing ARTCAR counter access register
both cases 7-bit prescaler also cleared, whereupon counting will start from known value. Direct access prescaler possible.
Output compare control
timer compare function based four different comparisons with counter (one each PWMx output). Each comparison made between counter value output compare register (OCRx) value. This OCRx register cannot accessed directly, loaded from duty cycle register (PWMDCRx) each overflow counter. This double buffering method avoids glitch generation when changing duty cycle fly. Figure Output compare control
fCOUNTER ARTARR COUNTER
OCRx
PWMDCRx
PWMx
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On-chip peripherals
Independent signal generation
This mode allows four pulse width modulated signals generated PWMx output pins with minimum core processing overhead. This function stopped during halt mode. Each PWMx output signal selected independently using corresponding control register (PWMCR). When this set, corresponding configured output push-pull alternate function. signals have same frequency which controlled counter period ARTARR register value. fPWM fCOUNTER/(256 ARTARR) When counter overflow occurs, PWMx level changed depending corresponding (output polarity) PWMCR register. When counter reaches value contained output compare register (OCRx) corresponding PWMx level restored. should noted that reload values also affect value resolution duty cycle output signal. obtain signal PWMx pin, contents OCRx register must greater than contents ARTARR register. maximum available resolution PWMx duty cycle Resolution 1/(256 ARTARR) Note: maximum resolution (1/256), ARTARR register must With this maximum resolution, 100% obtained changing polarity. Figure auto-reload timer function
Duty cycle register (PWMDCRx) Counter
Auto-reload register (ARTARR)
PWMx output
With OEx=1 OPx=0 With OEx=1 OPx=1
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On-chip peripherals Figure signal from 100% duty cycle
fCOUNTER ARTARR Counter
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OCRx=FCh PWMx output With OEx=1 OPx=0 OCRx=FDh OCRx=FEh OCRx=FFh
Output compare time base interrupt
overflow, flag ARTCSR register overflow interrupt request generated overflow interrupt enable bit, OIE, ARTCSR register, set. flag must reset user software. This interrupt used time base application.
External clock event detector mode
Using fEXT external prescaler input clock, auto-reload timer used external clock event detector. this mode, ARTARR register used select nEVENT number events counted before setting flag. nEVENT ARTARR Caution: external clock function available halt mode. halt mode used application, prior executing HALT instruction, counter must disabled clearing ARTCSR register avoid spurious counter increments. Figure External event detector example counts)
fEXT fCOUNTER ARTARR
Counter
ARTCSR read Interrupt Interrupt
ARTCSR read
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On-chip peripherals
Input capture function
This mode allows measurement external signal pulse widths through ARTICRx registers. Each input capture generate interrupt independently selected input signal transition. This event flagged corresponding bits input capture control/status register (ARTICCSR). These input capture interrupts enabled through CIEx bits ARTICCSR register. active transition (falling rising edge) software programmable through bits ARTICCSR register. read only input capture registers (ARTICRx) used latch auto-reload counter value when transition detected ARTICx (CFx ARTICCSR register). After fetching interrupt vector, flags read identify interrupt source. Note: After capture detection, data transfer ARTICRx register inhibited until read (clearing bit). timer interrupt remains pending while flag when interrupt enabled (CIEx set). This means that ARTICRx register read each capture event clear flag. timing resolution given auto-reload counter cycle time (1/fCOUNTER). Note: During halt mode, both input capture external clock enabled, ARTICRx register value guaranteed input capture external clock change simultaneously.
External interrupt capability
This mode allows input capture capabilities used external interrupt sources. interrupts generated edge ARTICx signal. edge sensitivity external interrupts programmable (CSx ARTICCSR register) they independently enabled through CIEx bits ARTICCSR register. After fetching interrupt vector, flags read identify interrupt source. During halt mode, external interrupts used wake microcontroller CIEx set). Figure Input capture timing diagram
fCOUNTER
Counter
Interrupt
ARTICx flag ICRx register
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On-chip peripherals
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10.3.3
registers
Control/status register (ARTCSR)
ARTCSR EXCL CC[2:0] FCRL Reset value: 0000 0000 (00h)
Table
Name
ARTCSR register description
Function External clock This cleared software. selects input clock 7-bit prescaler. clock External clock Counter clock control These bits cleared software. They determine prescaler division ratio from fINPUT (see Table page 79). Timer counter enable This cleared software. puts timer lowest power consumption mode. Counter stopped (prescaler counter frozen) Counter running Force counter reload This write-only attempt read will yield logical zero. When set, causes contents ARTARR register loaded into counter, content prescaler register cleared order initialize timer before starting count. Overflow interrupt enable This cleared software. allows enable/disable interrupt which generated when set. Overflow Interrupt disable Overflow Interrupt enable Overflow flag This hardware cleared software reading ARTCSR register. indicates transition counter from ARTARR value. transition reached Transition reached
EXCL
CC[2:0]
FCRL
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ST72321BLxx-Auto Table Prescaler selection
With fINPUT 62.5
On-chip peripherals
fCOUNTER fINPUT fINPUT/2 fINPUT/4 fINPUT/8 fINPUT/16 fINPUT/32 fINPUT/64 fINPUT/128
Counter access register (ARTCAR)
ARTCAR CA[7:0] Reset value: 0000 0000 (00h)
Table
ARTCAR register description
Function Counter access data These bits cleared either hardware software. ARTCAR register used read write auto-reload counter fly' (while counting).
Name
CA[7:0]
Auto-reload register (ARTARR)
ARTARR AR[7:0] Reset value: 0000 0000 (00h)
Table
ARTAAR register description
Function Counter auto-reload data These bits cleared software. They used hold auto-reload value which automatically loaded counter when overflow occurs. same time, output levels changed according corresponding PWMCR register.
Name
AR[7:0]
This register management functions: Adjusting frequency Setting duty cycle resolution
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On-chip peripherals Table frequency versus resolution
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fPWM ARTARR value 0.127 128.191 192.223 224.239 Resolution 8-bit 7-bit 6-bit 5-bit 4-bit ~0.244 ~0.244 ~0.488 ~0.977 ~1.953 31.25 62.5
control register (PWMCR)
PWMCR OE[3:0] OP[3:0] Reset value: 0000 0000 (00h)
Table
PWMCR register description
Function
Name
output enable These bits cleared software. They enable disable OE[3:0] output channels independently acting corresponding pin. output disabled output enabled OP[3:0] output polarity These bits cleared software. They independently select polarity four output signals (see Table 37).
Table
output signal polarity selection
PWMx output level OPx(1)
Counter OCRx
Counter OCRx
When modified, PWMx output signal polarity immediately reversed.
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On-chip peripherals
Duty cycle registers (PWMDCRx)
PWMDCRx DC[7:0] Reset value: 0000 0000 (00h)
Table
PWMDCRx register description
Function Duty cycle data These bits cleared software.
Name DC[7:0]
PWMDCRx register associated with OCRx register each channel determine second edge location signal (the first edge location common channels given ARTARR register). These PWMDCR registers allow duty cycle independently each channel.
Input capture control/status register (ARTICCSR)
ARTICCSR Reserved CS[2:1] CIE[2:1] Reset value: 0000 0000 (00h) CF[2:1]
Table
ARTICCSR register description
Function Reserved, always read Capture sensitivity These bits cleared software. They determine trigger event polarity corresponding input capture channel. Falling edge triggers capture channel Rising edge triggers capture channel
Name
CS[2:1]
Capture interrupt enable These bits cleared software. They enable disable Input CIE[2:1] capture channel interrupts independently. Input capture channel interrupt disabled Input capture channel interrupt enabled Capture flag These bits hardware cleared software reading corresponding ARTICRx register. Each indicates that input capture occurred. input capture channel input capture occurred channel
CF[2:1]
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On-chip peripherals
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Input capture registers (ARTICRx)
ARTICRx IC[7:0] Reset value: 0000 0000 (00h)
Table
ARTICRx register description
Function Input capture data These read only bits cleared hardware. ARTICRx register contains 8-bit auto-reload counter value transferred input capture channel event.
Name
IC[7:0]
Table
auto-reload timer register reset values
EXCL CIE2 FCRL CIE1
Address (Hex.) Register label 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh PWMDCR3 Reset value PWMDCR2 Reset value PWMDCR1 Reset value PWMDCR0 Reset value PWMCR Reset value ARTCSR Reset value ARTCAR Reset value ARTARR Reset value ARTICCSR Reset value ARTICR1 Reset value ARTICR2 Reset value
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On-chip peripherals
10.4
10.4.1
16-bit timer
Introduction
timer consists 16-bit free-running counter driven programmable prescaler. used variety purposes, including pulse length measurement input signals (input capture) generation output waveforms (output compare PWM). Pulse lengths waveform periods modulated from microseconds several milliseconds using timer prescaler clock prescaler. Some devices have on-chip 16-bit timers. They completely independent, share resources. They synchronized after reset long timer clock frequencies modified. This description covers 16-bit timers. devices with timers, register names prefixed with (Timer (Timer
10.4.2
Main features
Programmable prescaler: fCPU divided Overflow status flag maskable interrupt External clock input (must least four times slower than clock speed) with choice active edge output compare functions each with: dedicated 16-bit registers dedicated programmable signals dedicated status flags dedicated maskable interrupt dedicated 16-bit registers dedicated active edge selection signals dedicated status flags dedicated maskable interrupt
input capture functions each with:
Pulse width modulation mode (PWM pulse mode Reduced power mode alternate functions ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)(a)
block diagram shown Figure Timer block diagram page
Some timer pins available (not bonded) some devices. Refer Section Package pinout description page When reading input signal non-bonded pin, value always `1'.
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On-chip peripherals
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10.4.3
Functional description
Counter
main block programmable timer 16-bit free running upcounter associated 16-bit registers. 16-bit registers made 8-bit registers called high low. Counter register (CR)
Counter high register (CHR) most significant byte byte) Counter register (CLR) least significant byte byte) Alternate counter high register (ACHR) most significant byte byte) Alternate counter register (ACLR) least significant byte byte)
Alternate counter register (ACR)
These read-only 16-bit registers contain same value with difference that reading ACLR register does clear (timer overflow flag), located status register, (SR), (see 16-bit read sequence (from either counter register alternate counter register) page 86). Writing register ACLR register resets free running counter FFFCh value. Both counters have reset value FFFCh (this only value which reloaded 16-bit timer). reset value both counters also FFFCh pulse mode mode. timer clock depends clock control bits (bits register, illustrated Table register description page 100. value counter register repeats every 131072, 262144 524288 clock cycles depending CC[1:0] bits. timer frequency fCPU/2, fCPU/4, fCPU/8 external frequency. Caution: Flash devices, timer functionality following restrictions:
TAOC2HR TAOC2LR registers write only Input capture implemented corresponding interrupts cannot used (ICF2, OCF2 forced hardware zero)
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ST72321BLxx-Auto Figure Timer block diagram
internal
On-chip peripherals
fCPU MCU-peripheral interface
high
8-bit buffer High High High High
EXEDG
EXTCLK Counter register
Output compare register
Output compare register
Input capture register
Input capture register
Alternate counter register
CC[1:0] Timer internal
Overflow detect circuit
Output compare circuit
Edge detect circuit
ICAP1
Edge detect circuit
ICAP2
Latch1 ICF1 OCF1 ICF2 OCF2 TIMD Latch2
OCMP1
(control/status register)
OCMP2
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 (control register
OC1E OC2E
IEDG2 EXEDG (control register
Timer interrupt interrupt requests have separate vectors then last present (see Table Interrupt mapping page 47).
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On-chip peripherals
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16-bit read sequence (from either counter register alternate counter register)
Figure 16-bit read sequence
Beginning sequence Read byte byte buffered
Other instructions
Read byte
Returns buffered byte value
Sequence completed
user must read byte first, then byte value buffered automatically. This buffered value remains unchanged until 16-bit read sequence completed, even user reads byte several times. After complete reading sequence, only register ACLR register read, they return byte count value time read. Whatever timer mode used (input capture, output compare, pulse mode mode) overflow occurs when counter rolls over from FFFFh 0000h then:
register timer interrupt generated TOIE register register cleared
these conditions false, interrupt remains pending issued soon they both true. Clearing overflow interrupt request done steps: Note: Reading register while access (read write) register
cleared accesses ACLR register. advantage accessing ACLR register rather than register that allows simultaneous overflow function reading free running counter random times (for example, measure elapsed time) without risk clearing erroneously. timer affected wait mode. halt mode, counter stops counting until mode exited. Counting then resumes from previous count (MCU awakened interrupt) from reset count (MCU awakened reset).
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On-chip peripherals
External clock
external clock (where available) selected register. status EXEDG register determines type level transition external clock EXTCLK that triggers free running counter. counter synchronized with falling edge internal clock. minimum four falling edges clock must occur between consecutive active edges external clock; thus external clock frequency must less than quarter clock frequency. Figure Counter timing diagram, internal clock divided
clock Internal reset
Timer clock Counter register FFFD FFFE FFFF 0000 0001 0002 0003
Timer overflow flag (TOF)
Figure Counter timing diagram, internal clock divided
clock Internal reset
Timer clock Counter register FFFC FFFD 0000 0001
Timer overflow flag (TOF)
Figure Counter timing diagram, internal clock divided
clock Internal reset
Timer clock Counter register FFFC FFFD 0000
Timer overflow flag (TOF)
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On-chip peripherals Note:
ST72321BLxx-Auto
reset state when internal reset signal high, when running.
Input capture
this section, index, because there input capture functions 16-bit timer. 16-bit input capture registers (IC1R IC2R) used latch value free running counter after transition detected ICAPi (see below).
ICiR ICiHR ICiLR
ICiR register read-only register. active transition software programmable through IEDGi control registers (CRi). Timing resolution count free running counter: (fCPU/CC[1:0]).
Procedure
input capture function select following register:
timer clock (CC[1:0]) (see Table register description page 100) edge active transition ICAP2 with IEDG2 (the ICAP2 must configured floating input input with pull-up without interrupt this configuration available). ICIE generate interrupt after input capture coming from either ICAP1 ICAP2 pin. Select edge active transition ICAP1 with IEDG1 (the ICAP1pin must configured floating input input with pull-up without interrupt this configuration available). ICFi ICiR register contains value free running counter active transition ICAPi (see Figure Input capture timing diagram(1) page 89). timer interrupt generated ICIE cleared register. Otherwise, interrupt remains pending until both conditions become true. reading register while ICFi accessing (reading writing) ICiLR register
Select following register:
When input capture occurs:
Clearing input capture interrupt request (i.e. clearing ICFi bit) done steps:
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On-chip peripherals
After reading ICiHR register, transfer input capture data inhibited ICFi never until ICiLR register also read. ICiR register contains free running counter value which corresponds most recent input capture. input capture functions used together even timer also uses output compare functions. pulse mode mode only input capture used. alternate inputs (ICAP1 ICAP2) always directly connected timer. transitions these pins activates input capture function. Moreover ICAPi pins configured input second output, interrupt generated user toggles output ICIE set. This avoided input capture function disabled reading ICiHR (see note
used with interrupt generation order measure events that beyond timer range (FFFFh). Figure Input capture block diagram
ICAP1 ICAP2 Edge detect circuit Edge detect circuit ICIE
(control register IEDG1 (status register) IC2R register IC1R register ICF1 ICF2
16-bit 16-bit free running counter
(control register IEDG2
Figure Input capture timing diagram(1)
Timer clock Counter register FF01 FF02 FF03
ICAPi ICAPi flag ICAPi register FF03
rising edge active edge.
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On-chip peripherals
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Output compare
this section, index, because there output compare functions 16-bit timer. This function used control output waveform indicate when period time elapsed. When match found between output compare register free running counter, output compare function:
Assigns pins with programmable value OCiE Sets flag status register Generates interrupt enabled
16-bit registers, output compare register (OC1R) output compare register (OC2R) contain value compared counter register each timer clock cycle (see below).
OCiR OCiHR OCiLR
These registers readable writable affected timer hardware. reset event changes OCiR value 8000h. Timing resolution count free running counter: (fCPU/CC[1:0]).
Procedure
output compare function, select following register:
OCiE output needed then OCMPi dedicated output compare signal. Select timer clock (CC[1:0]) (see Table register description page 100) Select OLVLi applied OCMPi pins after match occurs OCIE generate interrupt needed OCFi OCMPi takes OLVLi value (OCMPi latch forced during reset) timer interrupt generated OCIE register cleared register (CC).
Select following register:
When match found between OCRi register register:
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On-chip peripherals
OCiR register value required specific timing application calculated using following formula:
OCiR
Where:
fCPU
PRESC
Output compare period seconds)
fCPU clock frequency hertz)
PRESC
Timer prescaler factor depending CC[1:0] bits, Table register description page 100)
timer clock external clock, formula
OCiR fEXT
Where:
Output compare period seconds)
fEXT External timer clock frequency hertz) Clearing output compare interrupt request (i.e. clearing OCFi bit) done Reading register while OCFi Accessing (reading writing) OCiLR register
following procedure recommended prevent OCFi from being between time read write OCiR register:
Write OCiHR register (further compares inhibited) Read register (first step clearance OCFi bit, which already set) Write OCiLR register (enables output compare function clears OCFi bit)
Note:
After processor write cycle OCiHR register, output compare function inhibited until OCiLR register also written. OCiE set, OCMPi general port OLVLi does appear when match found interrupt could generated OCIE set. both internal external clock modes, OCFi OCMPi while counter value equals OCiR register value (see Figure Output compare timing diagram, fTIMER fCPU/2 page example with fCPU/2 Figure Output compare timing diagram, fTIMER fCPU/4 page example with fCPU/4). This behavior same mode. output compare functions used both generating external events
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