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STM32F10xxx LCD glass driver firmware

Doc ID 14144 Rev 2

AN2656 Application note
STM32F10xxx LCD glass driver firmware
Introduction
April 2009
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www.st.com
Contents
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Contents
4.1.1 4.1.2 4.1.3 4.1.4 How to select the LCD glass by firmware . . . . . . . . . . . . . . . . . . . . . . . 18 How to select GPIOs to connect the LCD glass to STM32F10xxx . . . . 18 How to select the timer interrupt priority that drives the LCD . . . . . . . . 20 LCD contrast control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.1 4.2.2 4.2.3 LCD with high interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 LCD with low-high interrupt priority (using boosting priority) . . . . . . . . . 22 LCD interrupt always with lowest priority . . . . . . . . . . . . . . . . . . . . . . . . 23
LCD glass in battery-powered and low-power applications . . . . . . . . 24
5.2.1 Some current and CPU load measurements . . . . . . . . . . . . . . . . . . . . . 25
5.3.1 Some current and CPU load measurements . . . . . . . . . . . . . . . . . . . . . 27
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Contents
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List of figures
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List of figures
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LCD principle
Figure 1. LCD principle
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The higher the multiplexing rates, the lower the contrast. The signal period also has to be short enough to avoid visible flickering on the display. Figure 2. Equivalent electrical schematic of an LCD segment
RS COM
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Note:
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LCD drive signals
Single backplane LCD drive
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Duplexed LCD drive
In a duplexed drive, two backplanes are used instead of one. Each LCD segment line (Sx) is connected to two LCD segments, whose other side is connected to one of the two backplanes or common lines (refer to Figure 4). Thus, only (S / 2)+2 MCU pins are necessary to drive an LCD with S segments. Three different voltage levels have to be generated on the backplanes: 0, VDD / 2 and VDD. The Segment voltage levels are 0 and VDD only. Figure 4 shows typical backplane, segment and LCD waveforms. The intermediate voltage VDD / 2 is only required for the backplane voltages. The STM32F10xxx I / O pins selected as backplanes are set by firmware to output mode for 0 or VDD levels and to high impedance input mode for VDD / 2. When one backplane is active, the other is neutralized by applying VDD / 2 to it. This VDD / 2 voltage is determined by two resistors of equal value, externally connected to the I / O pin. By using an MCU with
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LCD drive signals
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flexible I / O pin configuration, a duplexed LCD drive can be implemented with only 2 external resistor bridges (each on two COM lines). Figure 4. Basic LCD segment connection in duplexed mode
S11 COM1
S12 S21
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Figure 5.
LCD signals for duplexed mode
COM1 +VDD +VDD / 2
COM2 +VDD +VDD / 2
S1 +VDD
Case 1
Case 2
Case 3
Case 4
-VDD / 2 -VDD Segment 2 On On Off Off
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LCD drive signals
Quadruplex LCD drive
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LCD drive signals Figure 7. LCD timing diagram for quadruplex mode
Single-frame period Control period
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COM4 Vsegx
Vseg - VCOM
Vseg - VCOM1
Vseg - VCOM4
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AN2656 Figure 8. LCD timing diagram for a single segment
Vsegx
LCD drive signals
- VCOM1
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LCD mean voltage calculation
VCOM is the maximum voltage on the COM line Vr / 2 is the voltage in the middle of the resistor bridge, applied on the COM line Vseg is the maximum voltage on the Segx line VCC is the microcontroller power supply
Contrast calculation
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LCD drive signals
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Example of a quadruplex LCD with STM32F10xxx
The following example describes a drive for a quadruplex mode (4COM) LCD using the STM32F10xxx. Refer to Figure 9. The only external components needed for driving the LCD are eight resistors of 470 k each. To get the best DC voltage on the LCD, the user can use precision resistors to have a precise VDD / 2 when the GPIOs are in high impedance. The higher the resistor precision, the lower the DC value. One I / O port per segment and one I / O port for each COM line are needed to drive the LCD. For example, to drive a quadruplex LCD that has 128 segments (with 32 segment lines and 4 COM lines) a total of 36 I / O ports only is required. Figure 9. Hardware connection diagram (1 / 2 bias control)
Resistor network
Common lines LCD Glass Segment lines 16 only for 128-segment LCDs PC8-PC11 STM32F10xxx
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16 for 64- and 128-segment LCDs
PD0-PD15
PE0-PE15
The LCD timing is generated by a timer output-compare interrupt. Each cycle consists of four phases, one for each backplane. Each COM line generates its waveform during the corresponding phase, e.g. COM1 line during phase1. During other phases, it remains at level VDD / 2. Each phase consists of two parts: 1. 2. Active time Dead time
During the active time, segment lines and common lines are used to drive the LCD. During the dead time, Segment lines and common lines are used to tune the contrast. Active time starts after the Output Compare 2 interrupt and dead time starts after the Output Compare 1 interrupt. A total of 16 interrupts are generated in each frame period with four
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Example of a quadruplex LCD with STM32F10xxx
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Figure 10. LCD timing diagram with active and dead time (to decrease Vrms)
Dead time
Active time Control period
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Example of a quadruplex LCD with STM32F10xxx Figure 11. LCD timing diagram with active and dead time (to increase Vrms)
Dead time VCOM +VDD / 2 COM1 T / 4 VCOM +VDD / 2 COM2 VCOM +VDD / 2 COM3 VCOM +VDD / 2 COM4 Vsegx T / 2 3T / 4 T Active time Control period
Segx On
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Example of a quadruplex LCD with STM32F10xxx Figure 12. Screenshot of Vcom3 and Vsegx (Segment1 of digit2)
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Vsegx
Vcom2
Vsegx-Vcom2 (Mean)
Figure 13. Screenshot of the four common lines Vcom1
Vcom2
Vcom3
Vcom4
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Firmware description
In the STM32F10xxx LCD demonstration, the PE0-PE15, PD0-PD15 port pins are connected to the 32 segment lines and are used to generate the segment signals. The PC8 to PC11 pins are connected to the 4 COM lines and used to generate the COM signals. The LCD driver consists of five initialization routines (system clock configuration, NVIC configuration, GPIO initialization, timer configuration and EXTI configuration). To activate the LCD, these four initialization routines have to be called. After the routines have been called, the STM32F10xxx gets the timer Output Compare 1 (CC1) and Output Compare 2 (CC2) interrupts. The ports are flexible, configurable by firmware, that is, the user can change the hardware implementation with minimum changes in firmware. This is done by changing the defines in the glasslcd.h file. Example: the user can change the port to which the common lines are connected (port X), and its offset, according to PX0 (where X can be A, B C D or E). By default, in the firmware, common lines COM1 to COM4 are driven by PC8 to PC11, segment lines of lower quarter digits (Digit1 to Digit4) are connected to port E and segment lines of higher quarter digits (Digit5 to Digit8) are connected to port D. The timer used by default in the firmware to drive the LCD is TIM3 it can be changed to another timer. Figure 14 presents the LCD timings used in the firmware. The LCD demo consists of displaying a message on LCD glass. Figure 14. Timing used by the STM32F10xxx LCD library
Vsegy
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In Figure 14, the orange arrows represent CC1 events and the blue arrows represent CC2 events. The timer interrupt routine is called every 3.6 ms by Output Compare 2 (CC2) to handle LCD segment switching. The timer interrupt routine is called again after a delay specified by Output Compare 1 (CC1) to handle contrast control (to switch all voltages off for instance).
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Firmware description
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How to use the LCD library
How to select the LCD glass by firmware
The implemented firmware can drive two reference types of glass LCD: 64- and 128segment LCDs
CT4-098: 64 segments (4 digits: 64 segments, manufacturer: ZHIYI Technology) PD 878: 128 segments (8 digits: 128 segments, manufacturer: Pacific Display) VIM 878: 128 segments (8 digits: 128 segments, manufacturer: Varitronix)
Note:
The user has to comment one of the line and uncomment the other (select one type of LCD reference), otherwise the compiler generates an error.
How to select GPIOs to connect the LCD glass to STM32F10xxx
Each digit (16 segments) is driven by 4 common lines and 4 segment lines to form a matrix of 16 segments. So each digit occupies 4 GPIOs to drive the common lines and 4 others to drive the segment Lines. (common lines and segment lines are driven by different ports).
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AN2656 Figure 15. LCD timing diagram for a single segment
Firmware description
Lower quarter digits (lower 4 digits)
Higher quarter digits (higher 4 digits)
Digit1..........Digit4 Digit5..........Digit8
The first digit (16 segments)
Lower quarter digits alone
Digit1.............Digit4
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Segment line configuration
The first line is used to select the port connected to the LCD segment lines of the first 4 digits (LQD: lower quarter digits), the second line is used to select the second 4 digits (HQD: higher quarter digits). Refer to Figure 9. In the configuration shown above port E drives digit 1 to digit 4 and port D drives digit 5 to digit 8. Note: In the case where CT4-098 LCD Glass is selected, the second line has no effect.
Common line configuration:
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Firmware description
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The first line defines the port to which common lines are connected (in the case shown above, the common lines are connected to port C, they cannot be connected to the same port as the segment lines). The second line is used to determine to which eight port pins the common lines are connected.
Lower eight port pins: PX0 to PX7 Higher eight port pins: PX8 to PX15
Timer selection
How to select the timer interrupt priority that drives the LCD
Refer to Section 4.2 for more details.
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Firmware description
LCD contrast control
Example
LCD timer interrupt
LCD with high interrupt priority
In this configuration, the LCD always has the high interrupt priority (priority 0). It interrupts all other ongoing interrupts and no interrupt can interrupt an LCD interrupt. To run the LCD in this configuration:
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Firmware description
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Impact
In this case the Vseg and Vcom pulses are kept at the same width, so the DC voltage value is kept near 0 V (in the worst case 5 mV). The PD-878 manufacturer specifies that the maximum allowed DC voltage is 50 mV. So here we have a DC voltage 10 times less than the value specified by the manufacturer.
LCD with low-high interrupt priority (using boosting priority)
When the LCD is configured in low-high interrupt priority, the LCD interrupt priority toggles between a low priority value and the highest priority value. By default, the LCD interrupt is configured with the lowest priority value (configuration in main()). When the interrupt occurs, the LCD priority interrupt is boosted to have the highest priority (priority 0), so that no other interrupt can interrupt it. Before returning from the LCD interrupt, its priority returns to the previous lowest priority value defined by the user in the glasslcd.h file. This avoids a delay between the setting of the GPIO segment line and common line pins subsequent to decreasing the DC voltage value. This boosting is performed using the priority boosting mechanism of the Cortex-M3 core on which the STM32F10xxx microcontroller is based. To run the LCD in this configuration:
Impact
The user firmware is never interrupted by the LCD interrupt. The DC voltage is higher than the DC value presented in the previous configuration (LCD in higher priority). This is due to user interrupts that have the highest priority and occur at the same time as the LCD interrupt (with lowest priority). So the LCD interrupt is a nested interrupt and is delayed until the user interrupt execution is finished. This causes an inequality between segment and com pulses (Vseg and Vcom pluses are not kept at the same width), consequently the DC voltage is increased in accordance with the number of user interrupts and their execution time. So the higher the number of user interrupts that postpone the LCD execution, the higher the DC voltage. The higher the execution time of the user interrupt that postpones the LCD execution, the higher the DC voltage. In this configuration, the measured DC value is 18 mV (depending on the number of user interrupts that postpone the LCD interrupt, and their execution time). The PD-878 manufacturer specifies that the maximum allowed DC voltage is 50 mV. Here, we have a DC voltage 2.5 times less than the value specified by the manufacturer.
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Firmware description
LCD interrupt always with lowest priority
The LCD interrupt always has the lowest priority. All user interrupts can interrupt the LCD execution, and the LCD interrupt cannot interrupt any other interrupt. To run the LCD in this configuration:
Comment this line in glasslcd.h file as follows:
Impact
The DC voltage is higher than the DC value presented in the two previous configurations (LCD with higher priority and boosted LCD priority). This is due to:
The user interrupts that interrupt the LCD routine between the settings of segment line and common line GPIOs. An undesirable jitter appears on the Vseg-Vcom signals, and its average is added to the DC value of Vseg-Vcom, consequently the DC value is increased. The user interrupts that have highest priority and occur at the same time as the LCD interrupt (with lowest priority). The LCD interrupt is a nested interrupt and is delayed until user interrupt execution is finished. This causes the inequality of the segment line and common line pulses, consequently the DC voltage is increased according to the number of user interrupts and their execution time.
In this configuration, we can measure a DC value of about 50 mV (depending on the number of user interrupts that delay or interrupt the LCD interrupt and their execution time).
Default demo configurations
When the user runs the demonstration, the "STM32" message is displayed on the LCD glass.
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LCD glass in battery-powered and low-power applications
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LCD glass in battery-powered and low-power applications
This section describes how to manage the LCD glass in low-power designs like batterypowered applications. It is divided into two parts. The first part describes, the timer method for driving the LCD glass using the STM32F10xxx Sleep mode. The second part describes how to drive the LCD glass using the RTC feature combined with the STM32F10xxx Stop mode to have minimum power consumption.
Hardware implementation
Resistor network
Common lines LCD Glass Segment lines 16 only for 128-segment LCDs PC7 PC8-PC11 STM32F10xxx
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16 for 64- and 128-segment LCDs
PD0-PD15
PE0-PE15
LCD bias pin configuration by software
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LCD glass in battery-powered and low-power applications
LCD glass managed by the timer using the Sleep low-power mode
TIM CC1 interrupt CC1 Task
CC1 interrupt occurred Return from interrupt
Sleep
Return from interrupt Return from interrupt
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Some current and CPU load measurements
Some current measurements are provided in Table 1. These measurements correspond to the (microcontroller + resistor network + LCD glass) consumption. The measurement conditions are:
Table 1.
Execution from Flash Consumption CPU load Execution from RAM Consumption
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Sleep mode I (µA) IRUN IWFI 0 T1 T
Timer Interrupts (Run mode)
t Sleep mode T2 Period T Run mode T1
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Period T is the sum of the interrupt execution time and the Sleep time:
Mean current Im can be calculated as shown below:
LCD glass managed by the RTC and using the Stop lowpower mode
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LCD glass in battery-powered and low-power applications Figure 19. RTC method state machine
RTC Alarm interrupt Task1
- Return from interrupt
RTC Alarm interrupt Task2
STOP -Return from interrupt
RTC Alarm interrupt Task3 -Return from interrupt
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Some current and CPU load measurements
Some current measurements are presented in Table 2. They correspond to the (microcontroller + resistor network + LCD glass) consumption. The measurement conditions are:
Table 2.
Flash Execution Consumption CPU load RAM Execution Consumption
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LCD glass in battery-powered and low-power applications Figure 20. RTC method chronogram
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Task3 Task1 Task2
Task1 Task3
I (µA) IRUN ISTOP 0 T1 T
Stop mode T2
Period T
RTC Interrupts (Run mode) T1
t Stop mode Period T T2 Run mode T1
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Period T is the sum of the interrupt execution time and the Stop time:
Mean current Im is expressed by the following equation
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Comparison of the timer and RTC methods
Timer method
However:
RTC method
Stop mode supported: minimum power consumption at 2 MHz ~ 174 µA typical RTC configuration independent of the APB clock configuration. RTC is not available for the calendar feature. More instructions are required to execute in RTC Alarm interrupt (enter the configuration mode, poll on the RTOFF flag, etc.): higher CPU load. Some peripherals do not support the Stop mode to wake up the core: additional software is required to manage this feature.
However:
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S3-D1 S2-D1 S3-D2 S2-D2 S3-D3 S2-D3 S3-D4 S2-D4 S3-D5 S2-D5 S3-D6 S2-D6 S3-D7 S2-D7 S3-D8 S2-D8
COM1 COM2 COM3 COM4
S1-D8 S0-D8 S1-D7 S0-D7 S1-D6 S0-D6 S1-D5 S0-D5 S1-D4 S0-D4 S1-D3 S0-D3 S1-D2 S0-D2 S1-D1 S0-D1
Hardware implementation
Schematic
23 24 25 26 29 30 31 32 PA0-WKUP PA1 PA2 PA3 PA4 PA5 PA6 PA7 LCDBIAS+ COM1 COM2 COM3 COM4 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
Digit 1.......................Digit8
PD-878 or VIM 878 LCD-8 Digits
SWDIO SWCLK
Hardware implementation
Figure 21. LCD - STM32F10xxx connection example
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R10 94 BOOT0 NRST 14
RESET
PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7
97 98 1 2 3 4 5 38 S0-D1 S1-D1 S2-D1 S3-D1 S0-D2 S1-D2 S2-D2 S3-D2
LCDBIAS+
S1 SW-PB 20 VDDA 21 VREFVREF+
R1 470k
R3 470k
R5 470k
R7 470k
6 VBAT
PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15
39 40 41 42 43 44 45 46 S0-D3 S1-D3 S2-D3 S3-D3 S0-D4 S1-D4 S2-D4 S3-D4
Ferrite Bead
R2 470k
R4 470k
R6 470k
R8 470k
VDDA STM32F103VBT6
C2 10uF C8 1uF C9 10nF
C3 100nF
C4 100nF
C5 100nF
C6 100nF
C7 100nF
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Hardware implementation
LCD segment line connections
Table 3. LCD segment line mapping
1. X and Y represent the ports to which the segment lines are connected, X is different from Y, and X, Y can be: A, B, C, D or E.
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Revision history
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Revision history
Table 4.
Date 22-Jul-2008 30-Apr-2009
Document revision history
Revision 1 2 Initial release. Example modified in Section 4.1.4: LCD contrast control. Titles of Figure 18 and Figure 19 modified. Changes
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