This application note describes technique driving liquid crystal displ

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This application note describes technique driving liquid crystal displ

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STM32F10xxx glass driver firmware
This application note describes technique driving liquid crystal displays (LCD) with STM32F10xxx microcontrollers (MCU), that without specific on-chip driver hardware. This technique offers solution applications that require display cost together with versatile capabilities standard STM32F10xxx MCUs. This application note also provides technique control contrast through firmware. After introduction LCDs, Section Section Section describe typical waveforms required drive with multiplexing rate (duplex) (quadruplex). Section presents solution based standard STM32F10xxx directly driving quadruplex LCD. This solution implemented with STM32F10xxx only requires standard ports timer, which standard features STM32F10xxx MCUs. Section describes STM32F10xxx glass library gives brief presentation glass demo. Section describes low-power management using glass, gives current load measurements. Finally, Section gives example connections STM32 (two types LCDs: digits segments: CT4-098-LV) digits (128 segments: ref: PD-878). With STM32F10xxx glass library, load controlling around 0.05% MHz), number external components kept minimum (two external resistors line). number I/Os involved same solutions using on-chip hardware driver external hardware driver. With firmware contrast control, STM32F10xxx offers very flexible solution that adapted easily range applications. measured value depends used resistors (refer Section user configuration: interruption priority configuration (refer Section 4.2).
April 2009
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Contents
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Contents
principle drive signals
Single backplane drive Duplexed drive Quadruplex drive
2.3.1 2.3.2 mean voltage calculation Contrast calculation
Example quadruplex with STM32F10xxx Firmware description
library
4.1.1 4.1.2 4.1.3 4.1.4 select glass firmware select GPIOs connect glass STM32F10xxx select timer interrupt priority that drives contrast control
timer interrupt
4.2.1 4.2.2 4.2.3 with high interrupt priority with low-high interrupt priority (using boosting priority) interrupt always with lowest priority
Default demo configurations
glass battery-powered low-power applications
Hardware implementation glass managed timer using Sleep low-power mode
5.2.1 Some current load measurements
glass managed using Stop lowpower mode
5.3.1 Some current load measurements
Comparison timer methods
Timer method
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Contents
method
Hardware implementation
Schematic segment line connections
Revision history
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List figures
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List figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure principle Equivalent electrical schematic segment. signals direct drive. Basic segment connection duplexed mode signals duplexed mode Basic segment connection quadruplexed mode timing diagram quadruplex mode timing diagram single segment. Hardware connection diagram (1/2 bias control) timing diagram with active dead time decrease Vrms) timing diagram with active dead time increase Vrms) Screenshot Vcom3 Vsegx (Segment1 digit2) Screenshot four common lines Timing used STM32F10xxx library timing diagram single segment. Hardware connection diagram (1/2 bias control) Timer method state machine Timer method chronogram this case duty cycle 50%) method state machine method chronogram STM32F10xxx connection example
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principle
principle
Figure principle
panel composed many layers. liquid crystal filled between them (glass plates), that separated thin spacers coated with transparent electrodes orientation layers. orientation layer usually consists polymer (e.g. polyimide) that been unidirectionally rubbed using, instance, soft cloth. result, liquid crystal molecules fixed, with their alignment more less parallel plates, direction rubbing. crystal alignment directions surface plates perpendicular that molecules between plates undergo homogeneous twist deformation alignment form helix. electric field applied, birefringent liquid crystal molecules keep their helical structure rotate linearly polarized light waves passing through plates. transmitted light wave then allowed through crossed exit polarizer. result, modulator bright appearance. other hand, voltage volts applied, resulting electric field forces liquid crystal molecules align themselves along field direction twist deformation (the helix) unwound. this case, polarization incident light rotated crystal molecules crossed exit polarizer blocks light wave. result, modulator appears dark. inverse switching behavior obtained with parallel polarizers. must also noted that gray scale modulation easily achieved varying voltage between crystal molecule reorientation threshold (reorientation resisted elastic properties liquid crystals) saturation field. LCDs sensitive root mean square voltage (Vrms= Mean Signal levels. With root mean square voltage applied practically transparent (the segment then inactive off). turn segment causing segment turn dark (from light gray opaque black), voltage greater than threshold voltage applied LCD. voltage voltage across capacitor Figure which equal potential difference between values. threshold voltage depends quality liquid used temperature. optical contrast defined difference transparency segment that (dark) segment that (transparent). optical contrast depends difference between voltage segment (VON) voltage segment (VOFF). higher difference between VON(rms) VOFF(rms), higher optical contrast. optical contrast also depends level versus threshold voltage. below close threshold voltage, completely almost transparent. VOFF close above threshold voltage, completely black.
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principle this document, contrast defined VON(rms) VOFF(rms). applied voltage must also alternate give zero value prevent electrolytic process ensure long lifetime.
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higher multiplexing rates, lower contrast. signal period also short enough avoid visible flickering display. Figure Equivalent electrical schematic segment
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Note:
value should never more than (refer manufacturer's datasheet), otherwise lifetime shortened. frequency range typically. less, flickers, greater, power consumption increases.
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drive signals
drive signals
Single backplane drive
single backplane drive, each segment connected segment line (Sx) backplane (common line) common segments. display using segments driven with output lines. backplane driven with signal between with duty cycle 50%. When switching segment signal with opposite polarity sent corresponding Segment pin. When noninverted signal sent Segment pin, segment off. Using MCU, operates output mode either logic Figure signals direct drive
+VDD +VDD +VDD
+VDD +VDD
-VDD
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Duplexed drive
duplexed drive, backplanes used instead one. Each segment line (Sx) connected segments, whose other side connected backplanes common lines (refer Figure Thus, only (S/2)+2 pins necessary drive with segments. Three different voltage levels have generated backplanes: VDD/2 VDD. Segment voltage levels only. Figure shows typical backplane, segment waveforms. intermediate voltage VDD/2 only required backplane voltages. STM32F10xxx pins selected backplanes firmware output mode levels high impedance input mode VDD/2. When backplane active, other neutralized applying VDD/2 This VDD/2 voltage determined resistors equal value, externally connected pin. using with
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drive signals
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flexible configuration, duplexed drive implemented with only external resistor bridges (each lines). Figure Basic segment connection duplexed mode
COM1
COM2
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Figure
signals duplexed mode
COM1 +VDD +VDD/2
COM2 +VDD +VDD/2
+VDD
Case
Case
Case
Case
COM1 +VDD +VDD/2
-VDD/2 -VDD Segment COM2 +VDD +VDD/2
-VDD/2 -VDD Segment
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drive signals
Quadruplex drive
quadruplex drive, four backplanes used. Each connected four segments, whose other side connected four backplanes. Thus, only (S/4)+4 pins necessary drive with segments. example, drive with segments only ports required ports drive segments, ports drive backplanes). Three different voltage levels have generated common lines: VDD/2, VDD. Segment line voltage levels only. segment inactive voltage below threshold voltage, active voltage above threshold. Figure shows typical backplane, Segment waveforms. intermediate voltage VDD/2 only required Backplane voltages. pins selected backplanes firmware output mode levels high-impedance input mode VDD/2. VDD/2 voltage determined resistors equal value, externally connected pins. When backplane active, other ones neutralized applying VDD/2 them. Figure Basic segment connection quadruplexed mode
COM1
COM2
COM3
COM4
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drive signals Figure timing diagram quadruplex mode
Single-frame period Control period
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VCOM +VDD/2 COM1
3T/4
COM2
COM3
COM4 Vsegx
Segx_1
Segx_2
Segx_3
Segx_4
Vseg VCOM
Vseg VCOM1
Vseg VCOM4
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Vsegx
Segx
drive signals
Vsegx Segx_1
VCOM1
Segx_1
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2.3.1
mean voltage calculation
mean voltage must very close zero guarantee long life LCD. mean voltage periods calculated shown below: Vmean(On) Vseg (-VCOM) 3(Vseg Vr/2) 3(-Vr/2) Vmean(Off) 3(Vseg/2) 3(-Vr/2) Vmean(On) Vmean(Off) assume identical periods each phase. Equating equations zero, that putting Vmean(On) Vmean(Off) gives: Vseg VCOM VCC, where:
VCOM maximum voltage line Vr/2 voltage middle resistor bridge, applied line Vseg maximum voltage Segx line microcontroller power supply
2.3.2
Contrast calculation
frame period where active time dead time. proportion dead time voltage during dead time. Vrms
Vrms
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drive signals
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Vrms
Vrms
Since case decrease Vrms) Vrms Vrms -1+x -0.661
Vrms
Vrms
Since case decrease Vrms) Vrms -0.18 where Contrast calculation with contrast control method .661 contrast between VOFF constant (quality contrast). only change optical contrast tuning close threshold value LCD. Note: contrast must controlled instantaneously firmware depending external temperature supply voltage value. user measure both ambient temperature using temperature sensor microcontroller supply voltage using example channel.
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Example quadruplex with STM32F10xxx
Example quadruplex with STM32F10xxx
following example describes drive quadruplex mode (4COM) using STM32F10xxx. Refer Figure only external components needed driving eight resistors each. best voltage LCD, user precision resistors have precise VDD/2 when GPIOs high impedance. higher resistor precision, lower value. port segment port each line needed drive LCD. example, drive quadruplex that segments (with segment lines lines) total ports only required. Figure Hardware connection diagram (1/2 bias control)
Resistor network
Common lines Glass Segment lines only 128-segment LCDs PC8-PC11 STM32F10xxx
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128-segment LCDs
PD0-PD15
PE0-PE15
timing generated timer output-compare interrupt. Each cycle consists four phases, each backplane. Each line generates waveform during corresponding phase, e.g. COM1 line during phase1. During other phases, remains level VDD/2. Each phase consists parts: Active time Dead time
During active time, segment lines common lines used drive LCD. During dead time, Segment lines common lines used tune contrast. Active time starts after Output Compare interrupt dead time starts after Output Compare interrupt. total interrupts generated each frame period with four
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Example quadruplex with STM32F10xxx
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interrupts control period. There Output Compare events (CC2_1 CC2_2) Output Compare events each phase. These explained follows:
During CC2_1: applied segments which have turned applied segments which have turned off. Common line which corresponds this phase level. Other Common lines level VDD/2. During CC1: decrease Vrms, segment lines Common lines inactive, that level (see Figure 10). increase Vrms, Common lines segment lines high level (see Figure 11). During CC2_2: Segment lines supplied with voltage levels that inverted compared applied during CC2_1. Common line that corresponds this phase high level. Other Common lines VDD/2. Again during CC1: decrease Vrms, Segments Common lines inactive, that level (see Figure 10). increase Vrms, Common lines high Segments lines level (see Figure 11).
Figure timing diagram with active dead time decrease Vrms)
VCOM +VDD/2 COM1 VCOM +VDD/2 COM2 VCOM +VDD/2 COM3 VCOM +VDD/2 COM4 Vsegx +VDD Segx_1
Dead time
Active time Control period
3T/4
VCOM +VDD/2 Segx_1 cc2_1 cc2_2 cc2_1
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Example quadruplex with STM32F10xxx Figure timing diagram with active dead time increase Vrms)
Dead time VCOM +VDD/2 COM1 VCOM +VDD/2 COM2 VCOM +VDD/2 COM3 VCOM +VDD/2 COM4 Vsegx 3T/4 Active time Control period
Segx
Vsegx +VDD/2 Segx_1
Vsegx +VDD/2 Segx_1 cc2_1 cc2_2
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Example quadruplex with STM32F10xxx Figure Screenshot Vcom3 Vsegx (Segment1 digit2)
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Vsegx
Vcom2
Vsegx-Vcom2 (Mean)
Figure Screenshot four common lines Vcom1
Vcom2
Vcom3
Vcom4
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Firmware description
Firmware description
STM32F10xxx demonstration, PE0-PE15, PD0-PD15 port pins connected segment lines used generate segment signals. PC11 pins connected lines used generate signals. driver consists five initialization routines (system clock configuration, NVIC configuration, GPIO initialization, timer configuration EXTI configuration). activate LCD, these four initialization routines have called. After routines have been called, STM32F10xxx gets timer Output Compare (CC1) Output Compare (CC2) interrupts. ports flexible, configurable firmware, that user change hardware implementation with minimum changes firmware. This done changing defines glasslcd.h file. Example: user change port which common lines connected (port offset, according (where default, firmware, common lines COM1 COM4 driven PC11, segment lines lower quarter digits (Digit1 Digit4) connected port segment lines higher quarter digits (Digit5 Digit8) connected port timer used default firmware drive TIM3; changed another timer. Figure presents timings used firmware. demo consists displaying message glass. Figure Timing used STM32F10xxx library
full cycle, stages/CC2 events 28.8 (34.7 Full period (34.7 Control period Active time VCOMx
Vsegy
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Figure orange arrows represent events blue arrows represent events. timer interrupt routine called every Output Compare (CC2) handle segment switching. timer interrupt routine called again after delay specified Output Compare (CC1) handle contrast control switch voltages instance).
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Firmware description
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library
firmware made flexible configurable adapt user's needs.
4.1.1
select glass firmware
implemented firmware drive reference types glass LCD: 128segment LCDs
CT4-098: segments digits: segments, manufacturer: ZHIYI Technology) 878: segments digits: segments, manufacturer: Pacific Display) 878: segments digits: segments, manufacturer: Varitronix)
Note:
LCDs pin-to-pin compatible. These LCDs selectable firmware commenting uncommenting following lines glasslcd.h file: #define USE_LCD_REF_PD_878 #define USE_LCD_REF_CT4_098 first (CT4-098), comment #define USE_LCD_REF_PD_878 line uncomment #define USE_LCD_REF_CT4_098. second 878), comment #define USE_LCD_REF_CT4_098 line uncomment #define USE_LCD_REF_PD_878. each case, letter number initially selected preprocessor.
Note:
user comment line uncomment other (select type reference), otherwise compiler generates error.
4.1.2
select GPIOs connect glass STM32F10xxx
Each digit segments) driven common lines segment lines form matrix segments. each digit occupies GPIOs drive common lines others drive segment Lines. (common lines segment lines driven different ports).
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AN2656 Figure timing diagram single segment
Firmware description
Lower quarter digits (lower digits)
Higher quarter digits (higher digits)
Digit1.Digit4 Digit5.Digit8
first digit segments)
Lower quarter digits alone
Digit1.Digit4
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Segment line configuration
(Refer toTable more pinout details.) CT4-098 segment lines common lines, port GPIOs) reserved segment lines common lines connected another GPIO port (refer CT4098 Glass datasheet). PD-878 selected, ports reserved segment lines common lines connected third (refer PD-878 Glass datasheet). configuration segment lines made modifying following lines: #define SegmentsLines_LQD_Port #define SegmentsLines_HQD_Port GPIOE GPIOD
first line used select port connected segment lines first digits (LQD: lower quarter digits), second line used select second digits (HQD: higher quarter digits). Refer Figure configuration shown above port drives digit digit port drives digit digit Note: case where CT4-098 Glass selected, second line effect.
Common line configuration:
LCDs have common lines (COM1 COM4). firmware configuration done glasslcd.h file using three following lines: #define CommonLines_Port GPIOC
//#define CommonLines_EightHighPortPins #define CommonLines_Pin_Offset
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Firmware description
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first line defines port which common lines connected case shown above, common lines connected port they cannot connected same port segment lines). second line used determine which eight port pins common lines connected.
Lower eight port pins: Higher eight port pins: PX15
#define CommonLines_EightHighPortPins commented, COM1 COM4 connected GPIOs with range Otherwise (the line uncommented), common lines connected GPIOs with range third line defines offset regarding pin0 pin8 (depending whether second line commented not). CommonLines_Pin_Offset value must exceed otherwise firmware does work correctly. configuration shown above, COM1 connected PC8, COM2 PC9, COM3 PC10 COM4 PC11. #define CommonLines_EightHighPortPins uncommented, COM1 connected PC8, COM2 PC9, COM3 PC10 COM4 PC11. user configure used GPIO clocks line below: #define RCC_APB1Periph_Used_GPIO RCC_APB2Periph_GPIOC RCC_APB2Periph_GPIOD RCC_APB2Periph_GPIOE
Timer selection
Three lines have configured user: #define TIMER_LCD #define TIMx_IRQChannel #define RCC_APB1Periph_TIMx TIM3 TIM3_IRQChannel RCC_APB1Periph_TIM3
first line, determines which timer will drive LCD. second line determines which channel will used generate interrupt. third line configures timer clock. configurations shown above, TIM3 drives LCD. user wants change default timer, above mentioned lines have changed. Also, code TIM3_IRQHandler() function cut/pasted used timer handler. example, TIM2 used, code TIM3_IRQHandler() must moved into TIM2_IRQHandler().
4.1.3
select timer interrupt priority that drives
Refer Section more details.
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Firmware description
4.1.4
contrast control
firmware contrast control under pending patent from STMicroelectronics. this technique with non-STMicroelectronics microcontroller agreed STMicroelectronics. contrast entirely controlled firmware without external components. contrast adjusted optimal value depending operating voltage used. controlled varying dead phase timing shown timing diagram(Figure Figure Dead time used decrease increase voltage (Vrms) LCD. Dead time voltage compensation time regulate voltage down. Dead time implemented either after each control period frame. avoid flickering, dead time must adjusted depending quality frame frequency. example shown Figure value decreases when dead time increases value increases when dead time decreases. Figure works opposite way. LCD_SettingContrast() function controls contrast that sets channel2 pulse length.
Example
uint16_t ContrastValue 0xE5C; ContrastValue range 0x0000 0x1CB8. 0x0000 value corresponds maximum contrast: completely dark (100% duty cycle). 0x1CB8 value corresponds minimum contrast: completely transparent duty cycle).
timer interrupt
interrupt routine TIMER_LCD: timer used drive glass) optimized have minimum voltage value. Direct access registers used reduce execution time jumping time arising from function calls.
4.2.1
with high interrupt priority
this configuration, always high interrupt priority (priority interrupts other ongoing interrupts interrupt interrupt interrupt. this configuration:
Modify value interrupt priority glasslcd.h file follows: #define LCD_Priority_Value priority value Comment this line glasslcd.h file follows: #define LCD_Use_Boost_Priority
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Firmware description
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Impact
this case Vseg Vcom pulses kept same width, voltage value kept near worst case mV). PD-878 manufacturer specifies that maximum allowed voltage here have voltage times less than value specified manufacturer.
4.2.2
with low-high interrupt priority (using boosting priority)
When configured low-high interrupt priority, interrupt priority toggles between priority value highest priority value. default, interrupt configured with lowest priority value (configuration main()). When interrupt occurs, priority interrupt boosted have highest priority (priority that other interrupt interrupt Before returning from interrupt, priority returns previous lowest priority value defined user glasslcd.h file. This avoids delay between setting GPIO segment line common line pins subsequent decreasing voltage value. This boosting performed using priority boosting mechanism Cortex-M3 core which STM32F10xxx microcontroller based. this configuration:
Modify value interrupt priority glasslcd.h file lowest priority value: #define LCD_Priority_Value priority value lowest user interrupt priority value this case interrupt priority value must lower than lowest user interrupt priority.
Ucomment this line glasslcd.h file follows: #define LCD_Use_Boost_Priority
Impact
user firmware never interrupted interrupt. voltage higher than value presented previous configuration (LCD higher priority). This user interrupts that have highest priority occur same time interrupt (with lowest priority). interrupt nested interrupt delayed until user interrupt execution finished. This causes inequality between segment pulses (Vseg Vcom pluses kept same width), consequently voltage increased accordance with number user interrupts their execution time. higher number user interrupts that postpone execution, higher voltage. higher execution time user interrupt that postpones execution, higher voltage. this configuration, measured value (depending number user interrupts that postpone interrupt, their execution time). PD-878 manufacturer specifies that maximum allowed voltage Here, have voltage times less than value specified manufacturer.
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Firmware description
4.2.3
interrupt always with lowest priority
interrupt always lowest priority. user interrupts interrupt execution, interrupt cannot interrupt other interrupt. this configuration:
Modify value interrupt priority glasslcd.h file lowest priority: #define LCD_Priority_Value priority value lowest user interrupt priority value this case interrupt priority value must lower than lowest user interrupt priority.
Comment this line glasslcd.h file follows:
#define LCD_Use_Boost_Priority
Impact
voltage higher than value presented previous configurations (LCD with higher priority boosted priority). This
user interrupts that interrupt routine between settings segment line common line GPIOs. undesirable jitter appears Vseg-Vcom signals, average added value Vseg-Vcom, consequently value increased. user interrupts that have highest priority occur same time interrupt (with lowest priority). interrupt nested interrupt delayed until user interrupt execution finished. This causes inequality segment line common line pulses, consequently voltage increased according number user interrupts their execution time.
this configuration, measure value about (depending number user interrupts that delay interrupt interrupt their execution time).
Default demo configurations
firmware runs from with frequency. used PD-878 878) Segment lines lower quarter digits connected port Segment lines higher quarter digits connected port Common lines connected port four common lines connected follows: COM1 PC8, COM2 PC9, COM3 PC10 COM4 PC11 TIM3 drives glass priority value Boost priority used entry interrupt priority exit interrupt routine priority returns
When user runs demonstration, "STM32" message displayed glass.
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glass battery-powered low-power applications
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glass battery-powered low-power applications
This section describes manage glass low-power designs like batterypowered applications. divided into parts. first part describes, timer method driving glass using STM32F10xxx Sleep mode. second part describes drive glass using feature combined with STM32F10xxx Stop mode have minimum power consumption.
Hardware implementation
hardware same described Section except additional line called LCD_Bias+, that added power LCD, save power, when application enters low-power mode. segments common lines thus preventing Leakage current GPIOs. Figure Hardware connection diagram (1/2 bias control)
LCD_BIAS+
Resistor network
Common lines Glass Segment lines only 128-segment LCDs PC8-PC11 STM32F10xxx
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128-segment LCDs
PD0-PD15
PE0-PE15
bias configuration software
#define LCD_Bias_Port #define LCD_BiasPlus_Pin GPIOC GPIO_Pin_7
first line defines port which LCD_BIAS+ connected power on/off glass. second line defines GPIO connected LCD_BIAS+.
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glass battery-powered low-power applications
glass managed timer using Sleep low-power mode
described previously, timer method based output compare interrupt (CC1 CC2). divided into tasks called CC2_1 CC2_2, which managed (enabled) software flag (CC2_1_Phase_Execute). Figure shows timer method state machine that explains interactions different tasks. Figure Timer method state machine
interrupt Task
interrupt occurred Return from interrupt
interrupt CC2_1 Task
interrupt occured CC2_1_Phase_Execute
interrupt occured CC2_1_Phase_Execute
Sleep
Return from interrupt Return from interrupt
interrupt CC2_2 Task
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5.2.1
Some current load measurements
Some current measurements provided Table These measurements correspond (microcontroller resistor network glass) consumption. measurement conditions are:
Hardware environment: STM32F103xx used, ref: PD-878, (internal clock used, power supply HCLK PCLK1 PCLK2 Tool chain: 4.42, configuration: high optimization size, Inline threshold Current consumption frequency
load/ Consumption load HCLK frequency 4.68% 5.91% 2.33% 3.39% 1.18% 1.57%
Table
Execution from Flash Consumption load Execution from Consumption
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glass battery-powered low-power applications Figure Timer method chronogram this case duty cycle 50%)
Control period Active time 3.6/2
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CC2_2
CC2_1
CC2_2
Sleep mode (µA) IRUN IWFI
Timer Interrupts (Run mode)
Sleep mode Period mode
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Period interrupt execution time Sleep time:
Mean current calculated shown below:
Sleep Sleep Sleep
glass managed using Stop lowpower mode
method based Alarm interrupt software flags. There three tasks Task1, Task2 Task3 instead CC1, CC2_1 CC2_2, respectively, timer method. alarm register updated each time Task1, Task2 Task3 executed, have timings needed drive glass. Alarm interrupt capability wake core from Stop mode (EXTI line 17). Figure shows method works tasks organized generate adequate signals drive glass using Stop mode minimize power consumption. sequence three tasks managed software flags: EnableTask1 EnableTask2_3. contrast defined glasslcd_RTC.h file modified user (the value percent): #define LCDContrastValue contrast
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glass battery-powered low-power applications Figure method state machine
Alarm interrupt Task1
Return from interrupt
Alarm interrupt Task2
-RTC Alarm occured -EnableTask1 FALSE -EnableTask2_3 TRUE
Alarm occurred EnableTask1 TRUE
-RTC Alarm occured -EnableTask1 FALSE -EnableTask2_3 FALSE
STOP -Return from interrupt
Alarm interrupt Task3 -Return from interrupt
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5.3.1
Some current load measurements
Some current measurements presented Table They correspond (microcontroller resistor network glass) consumption. measurement conditions are:
Hardware environment: STM32F103xx used, ref: PD-878, (high-speed internal clock used, (low-speed internal) clock used, power supply HCLK PCLK1 PCLK2 Tool chain: 4.42, configuration: high optimization size, Inline threshold Current consumption frequency
HCLK frequency load/consumption load 17.55% 20.31% 13.42% 15.02% 10.52% 10.63%
Table
Flash Execution Consumption load Execution Consumption
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glass battery-powered low-power applications Figure method chronogram
Control period Active time 3.6/2
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Task3 Task1 Task2
Task1 Task3
(µA) IRUN ISTOP
Stop mode
Period
Interrupts (Run mode)
Stop mode Period mode
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Period interrupt execution time Stop time:
Mean current expressed following equation
STOP
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Comparison timer methods
Comparison timer methods
Timer method
timer used (two Output Compare): remaining Output Compare free used another application. Very load: 4.6% timer configuration depends APB1 clock configuration low-power mode, only supported mode Sleep mode
However:
method
Stop mode supported: minimum power consumption typical configuration independent clock configuration. available calendar feature. More instructions required execute Alarm interrupt (enter configuration mode, poll RTOFF flag, etc.): higher load. Some peripherals support Stop mode wake core: additional software required manage this feature.
However:
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S3-D1 S2-D1 S3-D2 S2-D2 S3-D3 S2-D3 S3-D4 S2-D4 S3-D5 S2-D5 S3-D6 S2-D6 S3-D7 S2-D7 S3-D8 S2-D8
COM1 COM2 COM3 COM4
S1-D8 S0-D8 S1-D7 S0-D7 S1-D6 S0-D6 S1-D5 S0-D5 S1-D4 S0-D4 S1-D3 S0-D3 S1-D2 S0-D2 S1-D1 S0-D1
100nF_X7R_0603
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Hardware implementation
Schematic
PA0-WKUP LCDBIAS+ COM1 COM2 COM3 COM4
Digit 1.Digit8
PD-878 LCD-8 Digits
SWDIO SWCLK
PA10 PA11 PA12 PA13/JTMS/SWDIO PA14/JTCK/SWCLK PA15/JTDI PC10 PC11 PC12 PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT
Hardware implementation
PB2/BOOT1 PB3/JTDO PB4/JNTRST PB10 PB11 PB12 PB13 PB14 PB15 OSC_IN OSC_OUT PD10 PD11 PD12 PD13 PD14 PD15 S0-D7 S1-D7 S2-D7 S3-D7 S0-D8 S1-D8 S2-D8 S3-D8 S0-D5 S1-D5 S2-D5 S3-D5 S0-D6 S1-D6 S2-D6 S3-D6
Figure STM32F10xxx connection example
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BOOT0 NRST
10K_1%_0603
10K_1%_0603
RESET
S0-D1 S1-D1 S2-D1 S3-D1 S0-D2 S1-D2 S2-D2 S3-D2
LCDBIAS+
SW-PB VDDA VREFVREF+
470k
470k
470k
470k
VBAT
PE10 PE11 PE12 PE13 PE14 PE15
S0-D3 S1-D3 S2-D3 S3-D3 S0-D4 S1-D4 S2-D4 S3-D4
COM1
COM2
COM3
COM4
VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDDA VSSA VSS_1 VSS_2 VSS_3 VSS_4 VSS_5
Ferrite Bead
470k
470k
470k
470k
VDDA STM32F103VBT6
10uF 10nF
100nF
100nF
100nF
100nF
100nF
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Hardware implementation
segment line connections
Table segment line mapping
Digit Segment line(1) reference (PX.0) (PX.1) (PX.2) (PX.3) (PX.4) (PX.5) (PX.6) (PX.7) (PX.8) (PX.9) (PX.10) (PX.11) (PX.12) (PX.13) (PX.14) (PX.15) (PY.0) (PY.1) (PY.2) (PY.3) (PY.4) (PY.5) (PY.6) (PY.7) (PY.8) (PY.9) (PY.10) (PY.11) (PY.12) (PY.13) (PY.14) (PY.15) number CT4-098 PD-878
represent ports which segment lines connected, different from A,B,C,D
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Revision history
AN2656
Revision history
Table
Date 22-Jul-2008 30-Apr-2009
Document revision history
Revision Initial release. Example modified Section 4.1.4: contrast control. Titles Figure Figure modified. Changes
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This application note describes technique driving liquid crystal displ

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