Variable-Length Encoding (VLE) extension programming interface manual
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UM0438 User manual
Variable-Length Encoding (VLE) extension programming interface manual
This user manual defines programming model with variable-length encoding (VLE) instruction extension. Three types programming interfaces described herein:
application binary interface (ABI) defining low-level coding conventions assembly language interface simplified mnemonic assembly language interface
July 2007
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Contents
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Contents
Preface
About this book Audience Organization Suggested reading Related documentation General information Conventions Terminology conventions Acronyms abbreviations.
Overview
Application Binary Interface (ABI) Assembly language interface Simplified mnemonics assembly language interface
Application Binary Interface (ABI)
Instruction data representation Executable Linking Format (ELF) object files
2.2.1 2.2.2 2.2.3 information section identification Relocation types
Instruction
Appendix Simplified mnemonics instructions
Overview Subtract simplified mnemonics
A.2.1 A.2.2 Subtract immediate Subtract
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Rotate shift simplified mnemonics
A.3.1 Operations words.
Branch instruction simplified mnemonics
UM0438 A.4.1 A.4.2 A.4.3 A.4.4
Contents facts about simplified branch mnemonics Eliminating BO32 BO16 operands BI32 BI16 operand-CR field representations BI32 BI16 operand instruction encoding
Simplified mnemonics that incorporate BO32 BO16 operands
A.5.1 A.5.2 A.5.3 A.5.4 Examples that eliminate BO32 BO16 operands Simplified mnemonics that incorporate conditions (eliminates BO32 BO16 replaces BI32 with crS)33 Branch simplified mnemonics that incorporate conditions: examples Branch simplified mnemonics that incorporate conditions: listings.
Compare word simplified mnemonics Trap instructions simplified mnemonics. Simplified mnemonics accessing SPRs Recommended simplified mnemonics.
A.9.1 A.9.2 A.9.3 A.9.4 A.9.5 No-Op(nop) Load Address (la) Move Register (mr). Complement Register (not) Move Condition Register (mtcr)
A.10 A.11
EIS-Specific simplified mnemonics
A.10.1 Integer Select (isel)
Comprehensive list simplified mnemonics
Appendix Glossary
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Revision history
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List tables
List tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Terminology conventions Acronyms abbreviated terms Typical note section format identifier relocation fields relocation field descriptions. Notation conventions relocation types Relocation types with special semantics Subtract immediate simplified mnemonics Subtract simplified mnemonics Word rotate shift simplified mnemonics Branch instructions BO32 BO16 operand encodings fields updated integer floating-point instructions. BI32 BI16 operand settings fields branch comparisons field identification symbols Branch simplified mnemonics Branch instructions Simplified mnemonics e_bc se_bc without update Simplified mnemonics e_bcl with update Standard coding branch conditions Branch instructions simplified mnemonics that incorporate conditions Simplified mnemonics with comparison conditions. Simplified mnemonics e_bc se_bc without comparison conditions updating35 Simplified mnemonics e_bcl with comparison conditions updating Word compare simplified mnemonics Standard codes trap instructions Trap simplified mnemonics operand Encoding Additional simplified mnemonics Accessing SPRGs Simplified mnemonics Document revision history
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List figures
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List figures
Figure Figure Branch conditional (e_bc, se_bc) instruction formats BI32 BI16 fields
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Preface
Preface
About this book
primary objective this manual help programmers provide software that compatible across family processors using variable-length encoding (VLE) extension. Individual technology implementations beyond scope this manual. Each processor unique implementation extension. information this book subject change without notice. with technical documentation, reader's responsibility ensure they using most recent version documentation. more information, contact your sales representative.
Audience
This manual system software application programmers want develop products using extension. understanding operating systems, microprocessor system design, basic principles RISC processing, instruction assumed.
Organization
Following summary major sections this manual:
Section Overview provides general understanding what programming model defines extension. Section Application Binary Interface (ABI) describes extensions PowerPCe500 Application Binary Interface (e500 ABI) support technology. Section Instruction provides overview instruction architecture. detailed description each instruction, including assembly language syntax, refer section EREF. Appendix Simplified mnemonics instructions describes simplified mnemonics, which provided easier coding assembly language programs using technology.
Suggested reading
This section lists background reading this manual well general information extension PowerPC architecture.
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Preface
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Related documentation
STMicroelectronics processor documentation organized following types documents:
RM0004: Programmer Reference Manual Book processor higher-level view programming model defined Book User's manuals-Provide details individual implementations with Programming Environments Manual 32-Bit Implementations PowerPCArchitecture Datasheet-Specific data regarding timing, signal behavior, thermal characteristics, well other design considerations. Application notes-Address-specific design issues useful programmers engineers working with STMicroelectronics processors.
Additional literature released processors become available.
General information
following documentation, published Morgan-Kaufmann Publishers, Pine Street, Sixth Floor, Francisco, provides useful information PowerPC architecture computer architecture general:
PowerPC Architecture: Specification Family RISC Processors, Second Edition, International Business Machines, Inc. updates specification, Computer Architecture: Quantitative Approach, Third Edition, John Hennessy David Patterson Computer Organization Design: Hardware/Software Interface, Second Edition, David Patterson John Hennessy
Conventions
This document uses following notational conventions: cleared/set When takes value zero, said cleared; when takes value one, said set. mnemonics italics Instruction mnemonics shown lowercase bold. Italics indicate variable command parameters, example, bcctrx. Book titles text italics. Internal signals italics, example, qual REG[FIELD] Prefix denote hexadecimal number Prefix denote binary number Instruction syntax used identify source Instruction syntax used identify destination Abbreviations registers shown uppercase text. Specific bits, fields, ranges appear brackets. example, MSR[LE] refers little-endian mode enable machine state register.
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Preface some contexts, such signal encodings, unitalicized indicates don't care. italicized indicates alphanumeric variable. italicized indicates numeric variable. logical operator logical operator logical operator
Terminology conventions
Table lists certain terms used this manual that differ from architecture terminology conventions. Table Terminology conventions
Architecture specification Change Extended mnemonics order memory accesses Privileged mode privileged state) Problem mode problem state) Reference Relocation Storage (locations) Storage (the Changed Simplified mnemonics Speculative memory accesses Supervisor level User level Referenced Translation Memory Access This manual
Acronyms abbreviations
Table contains acronyms abbreviations that used this document. Table Acronyms abbreviated terms
Term DTLB IEEE Condition register Count register Data control register Data translation lookaside buffer Effective address Error checking correction Floating-point register General-purpose register Institute Electrical Electronics Engineers Meaning
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Term ITLB LIFO No-op RISC SIMM UIMM UISA
UM0438 Acronyms abbreviated terms (continued)
Meaning Instruction translation lookaside buffer Secondary cache Last-in-first-out Link register Least recently used Least-significant byte Least-significant Memory management unit Most-significant byte Most-significant Machine state register number Next instruction address operation Page table entry Reduced instruction computing Register transfer language Signed immediate value Special-purpose register Translation lookaside buffer Unsigned immediate value User instruction architecture Virtual address Variable-length encoding Register used primarily indicating conditions such carries overflows integer operations
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Overview
Overview
This document defines programming model with variable-length encoding (VLE) instruction extension. Three types programming interfaces described herein:
application binary interface (ABI) defining low-level coding conventions assembly language interface simplified mnemonic assembly language interface
Application Binary Interface (ABI)
programming model extends existing PowerPCABIs. This extension independent endian mode with regard data; however, instructions supported only big-endian mode. reviews instruction data representations memory management distinguishes between PowerPC Book instructions. also discusses section identification relocation types used executable linking format (ELF).
Note:
this chapter conjunction with PowerPC e500 Application Binary Interface (e500 ABI). Except sections discussed this chapter, follows e500 standard. information register usage availability, function calling sequence, parameter passing, stack frames, other topics, refer e500 ABI.
Assembly language interface
assembly language interface provides overview instructions. description each instruction along with instruction mnemonic operands found section EREF.
Simplified mnemonics assembly language interface
Simplified mnemonics provided easier coding assembly language programs. They defined most frequently used forms branch conditional, compare, trap, rotate shift, certain other instructions defined extension. Some assemblers define additional simplified mnemonics listed this document; however, assemblers should support simplified mnemonics listed Appendix
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Application Binary Interface (ABI)
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Note:
Application Binary Interface (ABI)
extensions described herein applications still under review PowerPC industry working group subject change. modifications will highlighted revisions this document. This chapter specifies extensions PowerPC e500 Application Binary Interface (e500 ABI) that defines both big-endian little-endian ABI. This extension independent endian mode with regards data; however, instructions supported only big-endian mode.
Note:
This chapter should used conjunction with PowerPC e500 Application Binary Interface (e500 ABI). Except sections discussed this chapter, follows e500 standard. information topics covered this section, including function calling sequence, register usage availability, stack frame layout, parameter passing, other topics, please refer e500 ABI.
Instruction data representation
extension includes additional operations with alternate instruction encoding enable reduced code footprint. This alternate encoding selected instruction page basis. single page attribute selects between standard PowerPC Book instruction encodings instructions particular page memory. This page attribute extension existing PowerPC Book page attributes. Pages freely intermixed, allowing mixture code with both types encodings. Instruction encodings pages marked using either bits long aligned 16-bit boundaries. Therefore, instruction pages marked must bigendian byte ordering. programmer's model uses same register when executing either instruction encoding, although certain registers accessible instructions using 16-bit formats, fields condition register (CR) used condition setting conditional branch instructions when executing from instruction page. addition, immediate fields displacements differ size use, more restrictive encodings imposed instructions. Other than requirement big-endian byte ordering instruction pages, additional page attribute identify whether instruction page corresponds section code, uses identical storage model, interrupts exceptions, timer facilities, debug facilities, special-purpose registers (SPRs) defined throughout Book
Executable Linking Format (ELF) object files
Both Book instructions coexist same binary separated into different sections allowing easy identification defining memory management page tables run-time environments. Because implementations supporting extension existing PowerPC Book page attributes, providing single additional page attribute select between Book encodings, memory pages Book instructions freely intermixed. Binding Book memory pages different memory bounds requires separation Book encodings into different sections.
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Application Binary Interface (ABI) encodings also require additional relocation types, which allow linker resolve immediate branch displacement fields instruction encoding once symbol label address known link time). encodings require additional relocation types resolve fields present PowerPC Book encodings.
2.2.1
information section
e500 defines information section named .PPC.EMB.apuinfo having type SHT_NOTE attributes which matches format typical note section shown Table information section allows disassemblers debuggers interpret instructions properly within binary used operating systems provide emulation error checking extension revisions. Table Typical note section format
length name bytes) length data bytes) type name (null-terminated, padded 4-byte alignment) data
.PPC.EMB.apuinfo section, name APUinfo type type already reserved), data contains series words providing information about extension, word. information contains unsigned half words: upper half contains unique identifier, lower half contains revision number. identifier shown Table Table identifier
APU/Extension
Identifier Bits) 0x0104
Example Object file
0x00000008 0x0000000C 0x00000002 0x41505569 0x6e666f00 0x00010001 0x01040001 0x00040001 bytes "APUinfo\0" bytes words) information NOTE type ASCII "APUi" ASCII "nfo\0" revision VLE, revision revision
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Application Binary Interface (ABI)
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Example Object file
0x00000008 0x00000008 0x00000002 0x41505569 0x6e666f00 0x00010002 0x00040001 bytes "APUinfo\0" bytes words) information NOTE type ASCII "APUi" ASCII "nfo\0" revision revision
Linkers merge .PPC.EMB.apuinfo sections individual object files into one, with merging per-APU information. example, after linking file b.o, merged .PPC.EMB.apuinfo shown example below.
Example PPC.EMB.apuinfo
0x00000008 0x0000000C 0x00000002 0x41505569 0x6e666f00 0x00010002 0x01040001 0x00040001 bytes "APUinfo\0" bytes words) information NOTE type ASCII "APUi" ASCII "nfo\0" revision VLE, revision revision
Note that assumed that later revision extension compatible with earlier one, vice versa. Thus, resultant .PPC.EMB.apuinfo section requires revision greater work, does work revision revision breaks backwards compatibility, must given unique identifier. linker optionally warn when different objects require different revisions, because moving revision make executable longer work processors with older revision. this example, linker could emit warning like "Warning: bumping revision number required b.o."
2.2.2
identification
executable linking format (ELF) allows processor-specific section header program header flag attributes defined. following section header program header flag attribute definitions used mark sections containing instruction encodings.
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UM0438 #define SHF_PPC_VLE 0x10000000 #define PF_PPC_VLE 0x10000000
Application Binary Interface (ABI) section header flag program header flag
SHF_PPC_VLE flag marks sections containing instructions. Similarly, PF_PPC_VLE flag used program headers mark program sections containing instructions. either SHF_PPC_VLE flag PF_PPC_VLE flag set, then instructions those marked sections interpreted instructions; Book instructions reside sections that have these flags set. sections setting SHF_PPC_VLE flag that contain instructions should also SHF_ALLOC SHF_EXECINSTR bits necessary. Setting SHF_PPC_VLE does automatically imply section that marked allocate (SHF_ALLOC) executable (SHF_EXECINSTR). linker keeps sections marked (SHF_PPC_VLE) separate output sections that contain Book instructions. Similarly, program headers setting PF_PPC_VLE flag should PF_X, PF_W, PF_R flags indicate executable, writable, readable attributes. considered error program header with PF_PPC_VLE contain sections that have SHF_PPC_VLE set. program loader debugger then scan section headers program headers detect sections case anything special required section processing downloading.
2.2.3
Relocation types
Relocation entries describe alter instruction relocation fields once symbols labels defined link time. instruction requires relocation types beyond those described PowerPC e500 Application Binary Interface (e500 ABI). Table shows additional relocation fields used instruction set.
Table
Relocation field name
relocation fields
low21
low21
split20 011100
split204:8
split200:3
split209:19
split16a
split16a0:4
split16a5:15
split16d
split16d0:4
split16d5:15
bdh24 bdh24
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Application Binary Interface (ABI) Table
bdh15
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relocation fields (continued)
bdh15
bdh8 bdh8
Table describes additional relocation fields required instructions. Table
Field low21
relocation field descriptions
Descriptions 21-bit field occupying lsbs word (bits 11-31).
20-bit field with msbs occupying bits 17-20, next bits occupying bits 11-15, remaining bits occupying bits 21-31. addition, bits destination word encoded with binary value 011100, encoded with binary value split20 This relocation field specifies opcode e_li instruction, allowing linker force encoding e_li instruction, potentially changing user's specified instruction. This functionality supports small data area relocation types. (R_PPC_VLE_SDA21 R_PPC_VLE_SDA21_LO). split16a split16d 16-bit field with msbs occupying bits 11-15 (the field) remaining bits occupying bits 21-31. 16-bit field with msbs occupying bits 6-10 (the field) remaining bits occupying bits
bdh24 24-bit field occupying bits 7-30 used resolve branch displacements half-word boundaries. bdh15 15-bit field occupying bits 16-30 used resolve branch displacements half-word boundaries. bdh8 8-bit field occupying bits 8-15 half-word. This field used 16-bit branch instruction.
Note:
Relocation entry types applied sections half-word alignment boundaries, because instruction architecture mixes 32-bit encodings within section. Book instruction encodings non-VLE sections e500 alignment specifications. Calculations Table assume actions transforming relocatable file into either executable shared object file. Conceptually, link editor merges more relocatable files form output. determines combine locate input files, updates symbol values, then performs relocations. Relocations applied executable shared object files similar accomplish same result. notations used Table described Table Table
Field
Notation conventions
Descriptions Represents addend used compute value relocatable field. Represents place (section offset address) storage unit being relocated (computed using r_offset). Represents value symbol whose index resides relocation entry.
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Field
Application Binary Interface (ABI) Notation conventions (continued)
Descriptions Represents offset from appropriate base (_SDA_BASE_, _SDA2_BASE_, where linker placed symbol whose index r_info. Represents 5-bit value base register section where linker placed symbol whose index r_info. Acceptable values are: value symbols .sdata .sbss, value symbols .PPC.EMB.sdata2 .PPC.EMB.sbss2, value symbols .PPC.EMB.sdata0 .PPC.EMB.sbss0.
Relocation entries apply half words words. either case, r_offset value designates offset virtual address first byte affected storage unit. relocation type specifies which bits change calculate their values. Processors that implement PowerPC architecture only Elf32_Rela relocation entries with explicit addends. relocation entries, r_addend member serves relocation addend. cases, offset, addend, computed result byte order specified header. following general rules apply interpretation relocation types Table
denote 32-bit modulus addition subtraction. denotes concatenation bits fields. denotes arithmetic right-shifting (shifting with sign copying) value left operand number bits given right operand. relocation types associated with branch displacements, which name relocation type contains upper bits computed value before shifting must same (either zeros ones-that sign-extended displacement). relocation types which name contains upper bits computed value before shifting must same. relocation types which name contains upper bits computed value before shifting must same. relocation types whose names contain 1-bit computed value before shifting must zero (half-word boundary). #hi(value) #lo(value) denote msbs lsbs indicated value. That #lo(x)=(x 0xFFFF) #hi(x)=((x>>16) 0xFFFF). high-adjusted value, #ha(value), compensates #lo() being treated signed number: #ha(x)=(((x 0x8000) 0xFFFF). _SDA_BASE_ symbol defined link editor whose value shared objects same _GLOBAL_OFFSET_TABLE_, executable programs address within small data area. Similarly, _SDA2_BASE_ symbol defined link editor whose value executable programs address within small data area.
Note that relocation types Table apply only sections. Sections containing Book instructions should PowerPC e500 Application Binary Interface. Table relocation types
Name R_PPC_VLE_REL8 R_PPC_VLE_REL15 R_PPC_VLE_REL24 R_PPC_VLE_LO16A Value Field bdh8 bdh15 bdh24 split16a Calculation #lo(S
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Application Binary Interface (ABI) Table relocation types (continued)
Name R_PPC_VLE_LO16D R_PPC_VLE_HI16A R_PPC_VLE_HI16D R_PPC_VLE_HA16A R_PPC_VLE_HA16D R_PPC_VLE_SDA21 R_PPC_VLE_SDA21_LO R_PPC_VLE_SDAREL_LO16A R_PPC_VLE_SDAREL_LO16D R_PPC_VLE_SDAREL_HI16A R_PPC_VLE_SDAREL_HI16D R_PPC_VLE_SDAREL_HA16A R_PPC_VLE_SDAREL_HA16D Value Field split16d split16a split16d split16a split16d low21 split20 low21 split20 split16a split16d split16a split16d split16a split16d #lo(S #hi(S #hi(S #ha(S #ha(S Table #lo(X Table #lo(X #lo(X #hi(X #hi(X #ha(X #ha(X Calculation
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Relocation types with special semantics described Table
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UM0438 Table Relocation types with special semantics
Name R_PPC_VLE_SDA21(1)
Application Binary Interface (ABI)
Description linker computes 21-bit value with msbs having value (for GPR13), (for GPR2), symbol whose index r_info contained .sdata .sbss, linker supplies value symbol .PPC.EMB.sdata2 .PPC.EMB.sbss2, linker supplies value symbol .PPC.EMB.sdata0 .PPC.EMB.sbss0, linker supplies value otherwise, link fails. lsbs this 21-bit value address symbol plus relocation entry r_addend value minus appropriate base symbol section: _SDA_BASE_ symbol .sdata .sbss _SDA2_BASE_ symbol .PPC.EMB.sdata2 .PPC.EMB.sbss2 symbol .PPC.EMB.sdata0 .PPC.EMB.sbss0 msbs computed 21-bit value non-zero, linker uses low21 relocation field, where msbs remain unchanged computed 21-bit value occupies bits 11-31. Otherwise, msbs computed 21-bit value zero, with following results: linker uses split20 relocation field, where only bits occupying 6-10 remain unchanged msbs 21-bit value ignored next copied bits 17-20 sign-extension next msbs copied bits 12-15 remaining bits copied bits 21-31. destination word, bits encoded with binary value 011100, encoded with binary value split20 relocation field forces encoding e_li instruction, which change user's specified instruction. Table
R_PPC_VLE_SDA21_LO Like R_PPC_VLE_SDA21, except that #lo() operator obtains lsbs 21bit value. #lo() operator applied after address symbol plus relocation entry r_addend value calculated, minus appropriate base symbol's section: _SDA_BASE_ symbol .sdata .sbss, _SDA2_BASE_ symbol .PPC.EMB.sdata2 .PPC.EMB.sbss2, symbol .PPC.EMB.sdata0 .PPC.EMB.sbss0. R_PPC_VLE_SDA21 entry describes applying calculated 21-bit value destination word that uses either low21 relocation field split20 relocation field. Table
Note that opcode changed, bits changed instead
Note:
relocations Table load store instructions (such e_lwz e_stw), which should EABI relocation R_PPC_EMB_SDA21. These relocations, written here, only start with e_add16i. linker might convert instruction e_li. Although other relocations specify instructions they apply useful know that these relocations apply only instruction.
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Instruction
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Note:
Instruction
This section provides overview instruction architecture. details each instruction, including assembly mnemonic operands, refer section EREF. extension allows PowerPC Book implementations support more efficient binary representations applications embedded processor spaces where code density plays major role affecting overall system cost, somewhat lesser extent, performance. intent extension define entirely different supplant existing PowerPC ISA. Instead, viewed supplement that applied conditionally application, part application, improve code density. major objectives extension follows:
Maintain coexistence consistency with existing PowerPC Book architecture Maintain common programming model instruction operation model extension Reduce overall code size percent over existing PowerPC text segments Limit increase execution path length under percent most important applications Limit increase hardware complexity implementations containing extension
meeting these objectives, cost-sensitive markets significantly benefit from extension. extension uses same semantics traditional Book limited instruction encoding formats, instructions typically support reduced immediate fields displacements, Book operations encoded extension. basic philosophy capture useful operations, with most frequent operations given priority. Immediate fields displacements provided cover most ranges encountered embedded control code. Instructions encoded either 32-bit format, these formats freely intermixed. Book floating-point registers accessible instructions. Book GPRs SPRs used instructions with following limitations:
instructions using 16-bit formats limited addressing GPR0-GPR7 GPR24-GPR31 most instructions. Move instructions provided transfer register contents between these registers GPR8-GPR23. instructions using 16-bit formats limited addressing CR0. instructions using 32-bit formats limited addressing CR0-CR3.
instruction encodings generally differ from Book instructions, except that most Book instructions falling within Book primary opcode encoded identically 32-bit instructions. Also, they have identical semantics unless they affect access resource supported extension. Primary opcode available support additional instructions using identical encodings both Book VLE. Therefore, implementation include additional APUs, such cache line locking APU, vector scalar single-precision floating-point APU, extension exact encodings.
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Instruction extension does currently fully encompass 64-bit operations, although addition such operations future version envisioned. future compatibility, avoid confusion with Book register numbering remains same traditional Book description each instruction contained section EREF includes mnemonic formatted list operands. instructions have either exact similar semantics Book instructions. Where semantics, side-effects, binary encodings identical, Book mnemonics formats used. Where semantics similar binary encodings differ, Book mnemonic generally preceded with `e_'. distinguish similar instructions available both 32-bit formats under standard Book instructions, instructions encoded with bits have `se_' prefix. instructions encoded with bits that have different binary encodings semantics than equivalent Book instruction have `e_' prefix. Some examples following: RS,D(RA) Standard Book instruction e_stw RS,D(RA) 32-bit instruction se_stw RZ,SD4(RX)// 16-bit instruction detailed functional descriptions each instruction, along with assembly mnemonic operands, refer section EREF.
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Simplified mnemonics instructions
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Appendix
Simplified mnemonics instructions
This appendix describes simplified mnemonics easier coding assembly language programs. Simplified mnemonics defined most frequently used forms branch conditional, compare, trap, rotate shift, certain other instructions defined extension. simplified mnemonics extension similar those defined PowerPC programming environment. result consistent programming view when working with instructions PowerPC architectures. Section A.11: Comprehensive list simplified mnemonics provides alphabetical listing simplified mnemonics used variety processors. Some assemblers define additional simplified mnemonics included here. simplified mnemonics listed here should supported compilers.
Overview
Simplified extended) mnemonics allow assembly-language programmer more intuitive mnemonics symbols than instructions syntax defined instruction architecture. example, code conditional call "branch target specifies greater than condition, setting without simplified mnemonics, programmer would write branch conditional link instruction e_bcl 1,13,target. simplified mnemonic, branch greater than link, e_bgtl cr3,target, incorporates conditions. only easier remember symbols than numbers when programming, also easier interpret simplified mnemonics when reading existing code. Simplified mnemonics formal part architecture, rather recommendation assemblers that support instruction set. Simplified mnemonics instructions provide consistent assembly-language interface with PowerPC architecture. Many simplified mnemonics were originally defined PowerPC architecture documentation. Some assemblers created their own, others have been added support extensions instruction (for example, AltiVec instructions Book auxiliary processing units (APUs)). Simplified mnemonics architecturally defined implementation-specific special-purpose registers (SPRs) described here very generally.
Subtract simplified mnemonics
This section describes simplified mnemonics subtract instructions.
A.2.1
Subtract immediate
effect subtract immediate instruction achieved negating immediate operand immediate instructions, e_add16i, e_add2i., e_add2is, e_addi. Simplified mnemonics include this negation, making intent computation clearer. These listed Table
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Simplified mnemonics instructions Subtract immediate simplified mnemonics
Simplified mnemonic e_sub16i rD,rA,value e_sub2i. rA,value e_sub2is rA,value e_subi rD,rA,value e_subic rD,rA,value e_subic. rD,rA,value Standard mnemonic e_add16i rD,rA,-value e_add2i. rA,-value e_add2is rA,-value e_addi rD,rA,-value e_addic rD,rA,-value e_addic. rD,rA,-value
A.2.2
Subtract
Subtract from instructions subtract second operand (rA) from third (rB). simplified mnemonics Table more common order which third operand subtracted from second. Table Subtract simplified mnemonics
Standard mnemonic(1) subf[o][.] rD,rB,rA subfc[o][.] rD,rB,rA
Simplified mnemonic sub[o][.] rD,rA,rB subc[o][.] rD,rA,rB
rD,rB,rA standard order operands. order reversed show equivalent behavior simplified mnemonic.
Rotate shift simplified mnemonics
Rotate shift instructions provide powerful, general ways manipulate register contents, they difficult understand. Simplified mnemonics provided following operations:
Extract-Select field bits starting position source register; left right justify this field target register; clear other bits target register. Insert-Select left- right-justified field bits source register; insert this field starting position target register; leave other bits target register unchanged. Rotate-Rotate contents register right left bits without masking. Shift-Shift contents register right left bits, clearing vacated bits (logical shift). Clear-Clear leftmost rightmost bits register. Clear left shift left-Clear leftmost bits register, then shift register left bits. This operation used scale (known non-negative) array index width element.
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A.3.1
Operations words
simplified mnemonics Table support coding with suffix. PowerPC instructions, suffix causes underlying instruction. However, following instruction forms support this.
Table
Word rotate shift simplified mnemonics
Operation Simplified mnemonic Equivalent e_rlwinm rA,rS,b,0,n e_rlwinm rA,rS,b n,32 n,31 e_rlwimi rA,rS,32 b,b,(b e_rlwimi rA,rS,32 n),b,(b e_rlwinm rA,rS,n,0,31 e_rlwinm rA,rS,32 n,0,31 e_rlwinm rA,rS,n,0,31 e_rlwinm rA,rS,32 n,n,31 e_rlwinm rA,rS,0,n,31 e_rlwinm rA,rS,0,0,31
Extract left justify word immediate e_extlwi rA,rS,n,b Extract right justify word immediate Insert from left word immediate Insert from right word immediate Rotate left word immediate Rotate right word immediate Shift left word immediate Shift right word immediate Clear left word immediate Clear right word immediate e_extrwi rA,rS,n,b e_inslwi rA,rS,n,b e_insrwi rA,rS,n,b e_rotlwi rA,rS,n e_rotrwi rA,rS,n e_slwi rA,rS,n e_srwi rA,rS,n e_clrlwi rA,rS,n e_clrrwi rA,rS,n
Clear left shift left word immediate e_clrlslwi rA,rS,b,n e_rlwinm rA,rS,n,b n,31
Examples using word mnemonics follow: Extract sign (bit place result right-justified into
e_extrwi rA,rS,1,0
equivalent
e_rlwinm rA,rS,1,31,31 e_rlwimi rB,rA,31,0,0 e_rlwinm rA,rA,8,0,23 e_rlwinm rA,rS,0,16,31
Insert extracted into sign (bit
e_insrwi rB,rA,1,0
Shift contents left bits.
equivalent equivalent equivalent
e_slwi rA,rA,8 e_clrlwi rA,rS,16
Clear high-order bits place result into
Branch instruction simplified mnemonics
Branch conditional instructions coded with operations with condition tested part instruction mnemonic rather than numeric operands (the BO32, BI32 BO16, BI16 operands). Table shows four general types branch instructions. Simplified mnemonics defined only branch conditional instructions that include either BO32, BI32 BO16, BI16 operands; there need simplify other branch mnemonics.
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UM0438 Table Branch instructions
Instruction name Branch Branch Conditional Branch Link Register Branch Count Register
Simplified mnemonics instructions
Mnemonic (e_bl) se_b (se_bl) e_bc (e_bcl) se_bc se_blr (se_blrl) se_bctr (se_bctrl)
Syntax target_addr target_addr BO32,BI32,target_addr BO16,BI16,target_addr
BO32, BI32, BO16, BI16 operands correspond fields instruction opcode, Figure shows Branch Conditional (e_bc, e_bcl, se_bc) instructions. Figure Branch conditional (e_bc, se_bc) instruction formats
e_bc (e_bcl)
BO32
BI32
BD15
se_bc
BO16 BI16
Both BO32 BO16 operands allow testing whether causes branch occur based true false condition. BO32 operand provides additional capability that allows branch operations that involve decrementing testing zero nonzero value. BI32 BI16 operands identify test (whether comparison less than greater than, example). simplified mnemonics avoid need memorize numerical values BO32, BI32, BO16, BI16 operands. example, e_bc 2,0,target conditional branch that, BO32 value (0b10) indicates, decrements CTR, then branches decremented zero. operation specified BO32 abbreviated (for decrement) (for zero), which replace original mnemonic; simplified mnemonic e_bc becomes e_bdnz. branch does depend condition BI32 eliminated, reducing expression e_bdnz target. addition operations, BO32 operand provides branch decisions based true false conditions. example, branch instruction depends equal condition CR0, expression e_bc 1,2,target. specify true condition, BO32 value becomes equal field indicated BI32 value Incorporating branchif-true condition used replace original mnemonic, e_bt. BI32 value replaced symbol. Using simplified mnemonic operand, expression becomes e_bt eq,target. This example tests CR0[EQ]; however, test equal condition 14), expression becomes e_bc 1,14,target. BI32 operand indicates CR[14] (CR3[2],
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BI32 field 0b1110). This expressed simplified mnemonic, e_bt eq,target. notation, first seem awkward, eliminates computing value bit. seen that Note that although 32-bit registers Book processors numbered 32-63, only values 0-15 valid possible) BI32 operands. Book E-compliant processor automatically translates BI32 values; specifying BI32 value selects Book processor, CR3[2] CR3[EQ]. reduce code size, provides 16-bit conditional branch instruction that uses BO16 BI16 operands. example, 32-bit conditional branch e_bc 1,2,target expressed using 16-bit instruction format, se_bc 1,2,target. simplified mnemonic form this becomes se_bt eq,target. BO16 operand only allows testing true false condition, unlike BO32 operand that also allows decrementing CTR. BI16 operand allows testing only CR0, unlike BI32 operand, which allows testing CR0- CR3.
A.4.1
facts about simplified branch mnemonics
following points helpful understanding simplified branch mnemonics:
simplified branch mnemonics eliminate BO32 BO16 operands, operand present branch simplified mnemonic, BI32 BI16 operand reduced form it). involved branch, BI32 BI16 operands deleted. involved branch, BI32 BI16 operands treated following ways: specified numeric value, just architecturally defined instruction, indicated with easier remember formula, [test symbol], where indicates field number. BI16 operands only allowed, BI32 CR0-CR3 allowed. condition test (eq, incorporated into mnemonic, leaving need operand that defines only field. test CR0, operand needed. test CR1-CR3, BI32 operand replaced with operand (that cr1, cr2, cr3). BI16 operand cannot used test bits that CR0.
A.4.2
Eliminating BO32 BO16 operands
2-bit BO32 field, shown Figure encodes following operations 32-bit conditional branch instructions:
Decrement count register (CTR) test result equal zero test result equal zero Test condition true Test condition false
Test condition register (CR)
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Simplified mnemonics instructions 1-bit BO16 field, shown Figure encodes following operations 16-bit conditional branch instructions:
Test condition register (CR) Test condition true Test condition false
shown Table standard mnemonic replaced with operations otherwise specified BO32 BO16 field, decrement, zero, non-zero, true, false). Table
BO32 Field 10(2)
BO32 BO16 operand encodings
BO16 Field Value (Decimal) Description Branch condition FALSE.(1) Branch condition TRUE.
Symbol
Decrement CTR, then branch decremented dnz(3) Decrement CTR, then branch decremented
Instructions which BO32 BO16 (branch condition true) (branch condition false) depend value alternately coded incorporating condition specified BI32 BI16 fields. Section A.5.2: Simplified mnemonics that incorporate conditions (eliminates BO32 BO16 replaces BI32 with crS) Simplified mnemonics branch instructions that test bits (BO32 should specify only target. Otherwise programming error occur. Notice that these instructions branch condition true false operations, simplified mnemonics these should specify BI32 operand.
A.4.3
BI32 BI16 operand-CR field representations
With standard branch mnemonics, BI32 BI16 operands used test bit, shown example Section A.4: Branch instruction simplified mnemonics. With simplified mnemonics, BI32 BI16 operands handled differently depending whether simplified mnemonic incorporates condition test, follows:
Some branch simplified mnemonics incorporate only BO32 BO16 operand. These simplified mnemonics architecturally defined BI32 BI16 operand specify bit, follows: BI32 BI16 operands presented exactly with standard mnemonics-as decimal number, 0-15 BI32 operand, BI16 operand. Symbols used replace decimal operand, shown example Section A.4: Branch instruction simplified mnemonics where e_bt eq,target could used instead e_bt 14,target. This described Section Specifying
simplified mnemonics Section A.5: Simplified mnemonics that incorporate BO32 BO16 operands these methods specify bit.
Additional simplified mnemonics incorporate conditions that would otherwise specified BI32 BI16 operand, BI32 BI16 operand replaced operand specify field. Section A.4.4: BI32 BI16 operand instruction encoding
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These mnemonics described Section A.5.2: Simplified mnemonics that incorporate conditions (eliminates BO32 BO16 replaces BI32 with crS)
A.4.4
BI32 BI16 operand instruction encoding
entire 4-bit BI32 2-bit BI16 fields, shown Figure represent number tested. standard branch mnemonics branch simplified mnemonics that incorporate condition, BI32 operand provides bits BI16 operand provides bits. simplified branch mnemonics described Section A.5.2: Simplified mnemonics that incorporate conditions (eliminates BO32 BO16 replaces BI32 with crS) BI32 BI16 operand replaced operand. understand this, useful view BI32 operand composed parts. Figure shows, BI32[0-1] indicates field BI32[2-3] represents condition test. 2-bit BI16 operand only part, BI16[0-1] represents condition within test. Figure BI32 BI16 fields BI32 Opcode Field
BI16 Opcode Field
BI32[0-1] specifies field, CR0-CR3.
BI32[2-3] BI16[0-1] specifies bits field. (LT,
Simplified mnemonics based conditions values -branch true BO32=1 BO16=1 -branch false: BO32=0 BO16=0
Specified Incorporated into separate, reduced simplified mnemonic. BI32 operand (crS)
Standard branch mnemonics BI32 operand specifies entire 4-bit field simplified mnemonics based BI16 operand specifies 2-bit field. values used, identified BI32, CR1-CR3 used, form LT|GT|EQ|SO used.
Integer record-form instructions update floating-point record-form instructions update CR1, described Table
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Simplified mnemonics instructions
Specifying
Note that version PowerPC architecture numbers bits 0-31 Book numbers them 32-63. However, adjustment necessary code; Book devices, automatically added BI32 BI16 values, shown Table Table Table
Book CR0[0] CR0[1] CR0[2] CR0[3] CR1[0] CR1[1] CR1[2] CR1[3] Negative (LT)-Set when result negative. Positive (GT)-Set when result positive (and zero). Zero (EQ)-Set when result zero. Summary overflow (SO). Copy XER[SO] instruction's completion. Copy FPSCR[FX] instruction's completion. Copy FPSCR[FEX] instruction's completion. Copy FPSCR[VX] instruction's completion. Copy FPSCR[OX] instruction's completion.
fields updated integer floating-point instructions
Bits BI32 BI16 Description
Some simplified mnemonics incorporate only BO32 BO16 fields described Section A.4.2: Eliminating BO32 BO16 operands). these simplified mnemonics used must accessed, BI32 BI16 operand specified either numeric value using symbols Table Compare word instructions (described Section A.6: Compare word simplified mnemonics), floating-point compare instructions, move instructions, others also modify fields, hold values that adhere meanings described Table Table
BI32 BI16 operand settings fields branch comparisons
bits expression operand bi32 bi16 Description Book less than floating-point less than (lt, fl). integer compare instructions: simm (signed comparison) uimm (unsigned comparison). floating-point compare instructions: frb.
crn[0]
cr3+
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BI32 BI16 operand settings fields branch comparisons (continued)
bits expression operand bi32 bi16 Description Book greater than floating-point greater than (gt, fg). integer compare instructions: simm (signed comparison) uimm (unsigned comparison). floating-point compare instructions: frb. equal floating-point equal (eq, fe). integer compare instructions: simm, uimm, floating-point compare instructions: frb. summary overflow floating-point unordered (so, fu). integer compare instructions, this copy xer[so] instruction completion. floating-point compare instructions, both nan.
crn[1]
cr3+
crn[2]
cr3+ so/un so/un) so/un so/un so/un
crn[3]
Only most useful simplified mnemonics found Section A.5: Simplified mnemonics that incorporate BO32 BO16 operands. Unusual cases still coded using standard branch conditional syntax.
operand
symbols shown Table Note that either symbol operand value used syntax used with simplified mnemonic. Table field identification symbols
Symbol (default, eliminated from syntax) BI32[0-1] BI16 Implied Bits 32-35 36-39 40-43 44-47
identify bit, expression which field symbol multiplied then added bit-number-within-CR-field symbol used, (for example, eq).
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Simplified mnemonics instructions
Simplified mnemonics that incorporate BO32 BO16 operands
mnemonics Table allow common BO32 BO16 operand encodings specified part mnemonic, along with link register (LK). There simplified mnemonics unconditional branches, branch link register, branch count register. these, basic mnemonics e_b, e_bl, se_b, se_bl, se_blr, se_blrl, se_bctr, se_bctrl used. Table Branch simplified mnemonics
Update Enabled Branch semantics e_bc Branch condition true Branch condition false Decrement CTR, branch Decrement CTR, branch e_bt e_bf e_bdnz e_bdz se_bc se_bt se_bf e_bcl e_btl e_bfl e_bdnzl e_bdzl Update Enabled
Simplified mnemonics branch instructions that test bits should specify only target. Otherwise, programming error occur.
Table shows syntax basic simplified branch mnemonics Table Branch instructions
Standard mnemonic (e_bl) se_b (se_bl) e_bc (e_bcl) se_bc Branch Link Register Branch Count Register Syntax Simplified mnemonic Syntax
Instruction Branch Branch Conditional
target_addr BO32,BI32,target_add BO16,BI16,target_add
N/A, syntax does include BO32 BO16 e_bx(1) (e_bxl) se_bx1 BI32(2),target_addr BI16 2,target_addr
se_blr (se_blrl) se_bctr (se_bctrl)
N/A, syntax does include BO32 BO16 N/A, syntax does include BO32 BO16
stands symbols Table where applicable. BI32 BI16 numeric value expression shown Table
simplified mnemonics Table that test condition require corresponding first operand examples Section A.5.1: Examples that eliminate BO32 BO16 operands below illustrate). symbols Table used place numeric value.
A.5.1
Examples that eliminate BO32 BO16 operands
simplified mnemonics Table used following examples:
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Decrement branch still nonzero (closure loop controlled count loaded into CTR) (note that bits tested).
e_bdnz target
equivalent
e_bc 2,0,target
Because this instruction does test bit, simplified mnemonic should specify only target operand. Specifying (for example, e_bdnz 0,target e_bdnz cr0,target) considered programming error. Subsequent examples test conditions). Branch condition equal.
e_bt eq,target equivalent e_bc 1,2,target Other equivalents include e_bt 2,target unlikely e_bt eq,target
Same (2), equal condition CR3.
e_bt eq,target equivalent e_bt 14,target would also work
Branch false.
e_bc 1,14,target
15,target equivalent so,target would also work
e_bc 0,15,target
Same (4), link register. This form conditional call.
15,target
equivalent
4,15,target
Table lists simplified mnemonics syntax e_bc se_bc without updating. Table Simplified mnemonics e_bc se_bc without update
e_bc e_bc 1,BI32,target e_bc 0,BI32,target e_bc 2,0,target e_bc 3,0,target Simplified mnemonic e_bt BI32,target
Branch semantics Branch condition true Branch condition false Decrement CTR, branch Decrement CTR, branch
se_bc
Simplified mnemonic
se_bc 1,BI16,target se_bt BI16,target
e_bf BI32,target1 se_bc 0,BI16,target se_bf BI16,target e_bdnz target(2) e_bdz target2
Instructions which B032 either (branch condition true) (branch condition false) depend value alternately coded incorporating condition specified BI32 field, described Section A.5.2: Simplified mnemonics that incorporate conditions (eliminates BO32 BO16 replaces BI32 with crS) Simplified mnemonics branch instructions that test bits should specify only target. Otherwise, programming error occur.
Table provides simplified mnemonics syntax e_bcl. Table Simplified mnemonics e_bcl with update
Branch semantics Branch condition true(1) Branch condition false e_bcl e_bcl 1,BI32,target e_bcl 0,BI32,target Simplified mnemonic e_btl BI32,target e_bfl BI32,target
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Simplified mnemonics instructions Simplified mnemonics e_bcl with update (continued)
Branch semantics e_bcl e_bcl 2,0,target e_bcl 3,0,target Simplified mnemonic e_bdnzl target e_bdzl target
Decrement CTR, branch Decrement CTR, branch
Instructions which B032 either (branch condition true) (branch condition false) depend value alternately coded incorporating condition specified BI32 field. Section A.5.2: Simplified mnemonics that incorporate conditions (eliminates BO32 BO16 replaces BI32 with crS) Simplified mnemonics branch instructions that test bits should specify only target. Otherwise, programming error occur.
A.5.2
Simplified mnemonics that incorporate conditions (eliminates BO32 BO16 replaces BI32 with crS)
mnemonics Table variations branch-if-condition-true (BO32 BO16 branch-if-condition-false (BO32 BO16 encodings. Because these instructions depend CTR, true/false conditions specified either BO32 BO16 combined with test specified BI32 BI16 operand create different simplified mnemonics that eliminates BO32 BO16 operands portion BI32 BI16 operands (BI32[2-3] BI16[0-1]) that specifies four possible test bits. However, simplified mnemonics using BO32 operand, simplified mnemonic cannot specify which four fields (CR0-CR3) test falls, BI32 operand replaced operand. standard codes shown Table used most common combinations branch conditions. ease programming, these codes include synonyms; example, less than equal (le) greater than (ng) achieve same result.
Note:
field symbol, cr0-cr3, used first operand after simplified mnemonic. default, CR0, used, necessary. Table
Code Less than Less than equal (equivalent Equal Greater than equal (equivalent Greater than less than (equivalent equal greater than (equivalent Summary overflow summary overflow Unordered (after floating-point comparison) unordered (after floating-point comparison)
Standard coding branch conditions
Description Equivalent Tested
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Table shows syntax simplified branch mnemonics that incorporate conditions. Here, replaces BI32 operand specify only field (because specific within field part simplified mnemonic. Note that default CR0; specified, used. Table Branch instructions simplified mnemonics that incorporate conditions
Standard mnemonic (e_bl) se_b (se_bl) e_bc (e_bcl) se_bc se_blr (se_blrl) se_bctr (se_bctrl) Syntax Simplified mnemonic e_bx (e_bxl) se_bx1 crS(2),target_addr target_addr Syntax
Instruction Branch Branch Conditional Branch Link Register Branch Count Register
target_addr BO32,BI32,target_addr BO16,BI16,target_addr
stands symbols Table where applicable. numeric value expression shown Table
Table shows simplified branch mnemonics incorporating conditions. Table Simplified mnemonics with comparison conditions
Update Enabled Branch semantics e_bc Branch less than Branch less than equal Branch equal Branch greater than equal Branch greater than Branch less than Branch equal Branch greater than Branch summary overflow Branch summary overflow Branch unordered Branch unordered e_blt e_ble e_beq e_bge e_bgt e_bnl e_bne e_bng e_bso e_bns e_bun e_bnu se_bc se_blt se_ble se_beq se_bge se_bgt se_bnl se_bne se_bng se_bso se_bns se_bun se_bnu e_bcl e_bltl e_blel e_beql e_bgel e_bgtl e_bnll e_bnel e_bngl e_bsol e_bnsl e_bunl e_bnul Update Enabled
Instructions using mnemonics Table indicate condition bit, field. field specified, used. 32-bit instruction forms (denoted with prefix) field symbols defined Table (cr0-cr3) used, shown examples Section A.5.3: Branch simplified mnemonics that incorporate conditions: examples below. Note that 16-bit instruction forms (denoted with prefix) must CR0.
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A.5.3
Branch simplified mnemonics that incorporate conditions: examples
following examples simplified mnemonics shown Table Branch reflects not-equal condition.
e_bne target se_bne target
equivalent equivalent equivalent
e_bc 0,2,target se_bc 0,2,target e_bc 0,14,target
Same condition CR3.
e_bne cr3,target
Branch specifies greater than condition, setting This form conditional call.
e_bgtl cr2,target A.5.4
equivalent
e_bcl 1,9,target
Branch simplified mnemonics that incorporate conditions: listings
Table shows simplified branch mnemonics syntax e_bc se_bc without updating.
Table
Simplified mnemonics e_bc se_bc without comparison conditions updating
e_bc e_bc 1,BI32(1),target e_bc 0,BI32(2),target e_bc 1,BI32(3),target e_bc 0,BI321,target 1,BI322 Simplified mnemonic e_blt crS,target e_ble crS,target e_bng crS,target e_beq crS,target e_bge crS,target e_bnl crS,target e_bc ,target e_bgt crS,target e_bne crS,target e_bso crS,target se_bc 1,BI16 e_bun crS,target e_bns crS,target se_bc e_bnu crS,target se_bc 1,BI16 ,target se_bc 0,BI163,target
Branch semantics Branch less than Branch less than equal Branch greater than Branch equal Branch greater than equal Branch less than Branch greater than Branch equal Branch summary overflow Branch unordered Branch summary overflow
se_bc se_bc 1,BI161,target
Simplified mnemonic se_blt target se_ble target
se_bc
0,BI162,target se_bng target
se_bc 1,BI163,target
se_beq target se_bge target se_bnl target se_bgt target se_bne target se_bso target
se_bc 0,BI161,target
e_bc 0,BI323,target
e_bc 1,BI32(4),target
4,target
se_bun target se_bns target 0,BI164,target se_bnu target
e_bc 0,BI32 Branch unordered
4,target
value BI32 BI16 operand selects CRn[0], bit. value BI32 BI16 operand selects CRn[1], bit.
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value BI32 BI16 operand selects CRn[2], bit. value BI32 BI16 operand selects CRn[3], bit.
Table shows simplified branch mnemonics syntax e_bcl. Table Simplified mnemonics e_bcl with comparison conditions updating
Branch semantics Branch less than Branch less than equal Branch greater than Branch equal Branch greater than equal Branch less than Branch greater than Branch equal Branch summary overflow Branch unordered Branch summary overflow Branch unordered
value BI32 operand selects CRn[0], bit. value BI32 operand selects CRn[1], bit. value BI32 operand selects CRn[2], bit. value BI32 operand selects CRn[3], bit.
e_bcl e_bcl 1,BI32(1),target e_bcl 0,BI32(2),target e_bcl 1,BI32(3),target e_bcl 0,BI321,target e_bcl 1,BI322,target
Simplified mnemonic e_bltl crS,target e_blel crS,target e_bngl crS,target e_beql crS,target e_bgel crS,target e_bnll crS,target e_bgtl crS,target e_bnel crS,target e_bsol crS,target e_bunl crS,target
e_bcl 0,BI323,target e_bcl 1,BI32(4),target
e_bcl 0,BI324,target
e_bnsl crS,target e_bnul crS,target
Compare word simplified mnemonics
compare word instructions, operand indicates word double-word Simplified mnemonics Table eliminate operand word comparisons. Table Word compare simplified mnemonics
Operation Compare Word Immediate Simplified mnemonic e_cmpwi crD,rA,SIMM e_cmpwi cr0,rA,SIMM Compare Word Compare Logical Word Immediate cmpw crD,rA,rB e_cmplwi crD,rA,UIMM e_cmplwi cr0,rA,UIMM Compare Logical Word cmplw crD,rA,rB Equivalent e_cmpi crD,rA,SIMM e_cmp16i rA,SIMM crD,0,rA,rB e_cmpli crD,rA,UIMM e_cmpl16i rA,UIMM cmpl crD,0,rA,rB
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Simplified mnemonics instructions with branch mnemonics, field compare instruction omitted used, shown examples below. Otherwise, target field must specified first operand. following examples word compare mnemonics: Compare with immediate value signed 32-bit integers place result CR0.
e_cmpwi rA,100
equivalent equivalent equivalent
e_cmp16i rA,100 e_cmpi 3,rA,100 cmpl 0,0,rA,rB
Same (1), place results CR4.
e_cmpwi cr3,rA,100 cmplw rA,rB
Compare unsigned 32-bit integers place result CR0.
Trap instructions simplified mnemonics
codes Table most common combinations trap conditions. Table
Code
Standard codes trap instructions
Description Encoding <U(1) >U(2)
Less than Less than equal Equal Greater than equal Greater than less than equal greater than Logically less than Logically less than equal Logically greater than equal Logically greater than Logically less than Logically greater than Unconditional
symbol `<U' indicates unsigned less-than evaluation performed. symbol `>U' indicates unsigned greater-than evaluation performed.
mnemonics Table variations trap instructions, with most useful values represented mnemonic rather than specified numeric operand.
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Trap semantics Trap unconditionally Trap less than Trap less than equal Trap equal Trap greater than equal Trap greater than Trap less than Trap equal Trap greater than Trap logically less than Trap logically less than equal Trap logically greater than equal Trap logically greater than Trap logically less than Trap logically greater than Register trap twlt twle tweq twge twgt twnl twne twng twllt twlle twlge twlgt twlnl twlng
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following examples trap mnemonics shown Table Trap equal
twne rA,rB
Trap unconditionally.
equivalent equivalent
24,rA,rB 31,0,0
trap
Trap instructions evaluate trap condition comparing contents with contents comparison results five conditions that ANDed with operand result trap exception handler invoked. Table these conditions. Table
operand Encoding
ANDed with condition Less than, using signed comparison Greater than, using signed comparison Equal Less than, using unsigned comparison Greater than, using unsigned comparison
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Simplified mnemonics accessing SPRs
mtspr mfspr instructions specify special-purpose register (SPR) numeric operand. Simplified mnemonics provided that represent mnemonic rather than requiring coded numeric operand. pattern mtspr mfspr simplified mnemonics straightforward: replace -spr portion mnemonic with abbreviation (for example XER, SRR0, LR), eliminate SPRN operand, leaving source destination operand, Following examples using simplified mnemonics: Copy contents XER.
mtxer
Copy contents
equivalent equivalent equivalent
mtspr 1,rS mfspr rD,8 mtspr 9,rS
mflr mtctr
Copy contents CTR.
examples above show simplified mnemonics accessing SPRs defined version PowerPC architecture; however, same formula used Book EIS, implementation-specific SPRs, shown following examples: Copy contents CSRR0.
mtcsrr0
Copy contents IVOR0
equivalent equivalent equivalent
mtspr 58,rS mfspr rD,400 mtspr 625,rS
mfivor0 mtmas1
Copy contents MAS1.
There additional simplified mnemonics accessing SPRGs, which supported assemblers. These mnemonics shown Table along with equivalent simplified mnemonic using formula described this section. Table
Simplified mnemonic SPRGs mtsprg n,rS mtspr n,rS mtsprgn,rS mfsprgn Equivalent Simplified mnemonic mfsprg rD,n mfspr rD,272 Equivalent
Additional simplified mnemonics Accessing SPRGs
Move Move from
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Recommended simplified mnemonics
This section describes commonly-used operations (such no-op, load immediate, load address, move register, complement register).
A.9.1
No-Op(nop)
Many instructions coded such that, effectively, operation performed. Additional mnemonics provided preferred forms no-op. implementation performs type run-time optimization related no-ops, preferred forms following:
e_nop se_nop A.9.2 Load Address (la)
equivalent equivalent
e_ori 0,0,0 se_or
mnemonic permits computing value base-displacement operand, using e_add16i instruction that normally requires separate register immediate operands.
e_la rD,d(rA)
equivalent
e_add16i rD,rA,d
e_la mnemonic useful obtaining address variable specified name, allowing assembler supply base register number compute displacement. variable located offset bytes from address assembler directed base references data structure containing following line causes address loaded into
e_la rD,V A.9.3 Move Register (mr)
equivalent
e_add16i rD,rV,dV
Several instructions coded copy contents register another. simplified mnemonic provided signify that computation being performed, merely that data being moved from register another. following instruction copies contents into This mnemonic coded with suffix cause underlying instruction.
rA,rS A.9.4 Complement Register (not)
equivalent
rA,rS,rS
Several instructions coded complement contents register place result into another register. simplified mnemonic allows this operation coded easily. following instruction complements contents places result into This mnemonic coded with suffix cause underlying instruction.
rA,rS A.9.5
equivalent
rA,rS,rS
Move Condition Register (mtcr)
mtcr mnemonic permits copying contents using same syntax mfcr instruction.
mtcr
equivalent
mtcrf 0xFF,rS
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A.10
EIS-Specific simplified mnemonics
This section describes simplified mnemonics used auxiliary processing units (APUs) defined part Book implementation standards (EIS).
A.10.1
Integer Select (isel)
following mnemonics simplify most common variants isel instruction that access CR0: Integer Select Less Than
isellt rD,rA,rB
Integer Select Greater Than
equivalent equivalent equivalent
isel rD,rA,rB,0 isel rD,rA,rB,1 isel rD,rA,rB,2
iselgt rD,rA,rB
Integer Select Equal
iseleq rD,rA,rB
A.11
Comprehensive list simplified mnemonics
Table lists simplified mnemonics. Note that compiler designers implement additional simplified mnemonics listed here.
Table
Simplified mnemonics
Mnemonic e_bc 2,0,target e_bcl 2,0,target e_bc 3,0,target e_bcl 3,BI32,target e_bc 1,BI32(2),target se_bc 1,BI16 ,target e_bcl 1,BI32
2,target
Simplified mnemonic e_bdnz target(1) e_bdnzl target e_bdz target e_bdzl target e_beq crS,target se_beq target e_beql crS,target e_bf BI32,target se_bf BI16,target e_bfl BI32,target e_bge crS,target se_bge target e_bgel crS,target
Instruction Decrement CTR, branch (e_bc without update) Decrement CTR, branch (e_bcl with update) Decrement CTR, branch (e_bc without update) Decrement CTR, branch (e_bcl with update) Branch equal (e_bc without updating) Branch equal (se_bc) Branch equal (e_bcl with updating) Branch condition false (e_bc without update) Branch condition false3 (se_bc) Branch condition false (e_bcl with update) Branch greater than equal (e_bc without updating) Branch greater than equal (se_bc) Branch greater than equal (e_bcl with updating)
e_bc 0,BI32,target se_bc 0,BI16,target e_bcl 0,BI32,target e_bc 0,BI32(4),target se_bc 0,BI164,target e_bcl 0,BI324,target
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Simplified mnemonics instructions Table Simplified mnemonics (continued)
Mnemonic e_bc 1,BI32 ,target se_bc 1,BI165,target e_bcl 1,BI32 ,target e_bc 0,BI325,target se_bc 0,BI165,target e_bcl 0,BI325,target e_bc 1,BI324,target se_bc 1,BI164,target e_bcl 1,BI324,target
3,target
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Simplified mnemonic e_bgt crS,target se_bgt target e_bgtl crS,target e_ble crS,target se_ble target e_blel crS,target e_blt crS,target se_blt target e_bltl crS,target e_bne crS,target se_bne target e_bnel crS,target e_bng crS,target se_bng target e_bngl crS,target e_bnl crS,target se_bnl target e_bnll crS,target e_bns crS,target se_bns target e_bnsl crS,target e_bnu crS,target se_bnu target e_bnul crS,target e_bso crS,target se_bso target e_bsol crS,target e_bt BI32,target se_bt BI16,target e_btl BI32,target
Instruction Branch greater than (e_bc without updating) Branch greater than (se_bc) Branch greater than (e_bcl with updating) Branch less than equal (e_bc without updating) Branch less than equal (se_bc) Branch less than equal (e_bcl with updating) Branch less than (e_bc without updating) Branch less than (se_bc) Branch less than (e_bcl with updating) Branch equal (e_bc without updating) Branch equal (se_bc) Branch equal (e_bcl with updating) Branch greater than (e_bc without updating) Branch greater than (se_bc) Branch greater than (e_bcl with updating) Branch less than (e_bc without updating) Branch less than (se_bc) Branch less than (e_bcl with updating) Branch summary overflow (e_bc without updating) Branch summary overflow (se_bc) Branch summary overflow (e_bcl with updating) Branch unordered (e_bc without updating) Branch unordered (se_bc) Branch unordered (e_bcl with updating) Branch summary overflow (e_bc without updating) Branch summary overflow (se_bc) Branch summary overflow (e_bcl with updating) Branch condition true3 (e_bc without update) Branch condition true3 (se_bc) Branch condition true (e_bcl with update)
e_bc 0,BI32 se_bc
0,BI163,target
e_bcl 0,BI323,target e_bc 0,BI325,target se_bc 0,BI165,target e_bcl 0,BI32 e_bc
5,target
0,BI324,target
se_bc 0,BI164,target e_bcl 0,BI32
4,target
e_bc 0,BI32(6),target se_bc 0,BI166,target e_bcl 0,BI326,target e_bc 0,BI326,target se_bc 0,BI166,target e_bcl 0,BI32 ,target e_bc 1,BI326,target se_bso 1,BI166,target e_bcl 1,BI326,target e_bc 1,BI32,target se_bc 1,BI16,target e_bcl 1,BI32,target
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UM0438 Table Simplified mnemonics (continued)
Mnemonic e_bc 1,BI32 ,target se_bc 1,BI166,target e_bcl 1,BI32 ,target e_rlwinm rA,rS,n,b n,31 e_rlwinm rA,rS,0,n,31 e_rlwinm rA,rS,0,0,31 cmpl crD,0,rA,rB e_cmpli crD,rA,UIMM e_cmpl16i rA,UIMM crD,0,rA,rB e_cmpi crD,rA,SIMM e_cmp16i rA,SIMM e_rlwinm rA,rS,b,0,n
Simplified mnemonics instructions
Simplified mnemonic e_bun crS,target se_bun target e_bunl crS,target e_clrlslwi rA,rS,b,n e_clrlwi rA,rS,n e_clrrwi rA,rS,n cmplw crD,rA,rB e_cmplwi crD,rA,UIMM e_cmplwi cr0,rA,UIMM cmpw crD,rA,rB e_cmpwi crD,rA,SIMM e_cmpwi cr0,rA,SIMM e_extlwi rA,rS,n,b e_extrwi rA,rS,n,b e_inslwi rA,rS,n,b e_insrwi rA,rS,n,b iseleq rD,rA,rB iselgt rD,rA,rB isellt rD,rA,rB e_la rD,d(rA) e_nop se_nop rA,rS e_rotlwi rA,rS,n e_rotrwi rA,rS,n e_slwi rA,rS,n e_srwi rA,rS,n rD,rA,rB sub. rD,rA,rB subo rD,rA,rB subo. rD,rA,rB subc rD,rA,rB subc. rD,rA,rB
Instruction Branch unordered (e_bc without updating) Branch unordered (se_bc) Branch unordered (e_bcl with updating) Clear left shift left word immediate Clear left word immediate Clear right word immediate Compare logical word Compare logical word immediate Compare logical word immediate Compare word Compare word immediate Compare word immediate Extract left justify word immediate
e_rlwinm rA,rS,b n,32 n,31 Extract right justify word immediate e_rlwimi rA,rS,32 b,b,(b Insert from left word immediate e_rlwimi rA,rS,32 n),b,(b Insert from right word immediate isel rD,rA,rB,2 isel rD,rA,rB,1 isel rD,rA,rB,0 e_add16i rD,rA,d e_ori 0,0,0 se_or rA,rS,rS e_rlwinm rA,rS,n,0,31 e_rlwinm rA,rS,32 n,0,31 e_rlwinm rA,rS,n,0,31 e_rlwinm rA,rS,32 n,n,31 subf rD,rB,rA subf. rD,rB,rA subf rD,rB,rA subf. rD,rB,rA subfc rD,rB,rA subfc. rD,rB,rA Integer Select Equal Integer Select Greater Than Integer Select Less Than Load address No-op No-op (Complement register) Rotate left word immediate Rotate right word immediate Shift left word immediate Shift right word immediate Subtract from Subtract from Subtract from Subtract from Subtract from carrying Subtract from carrying
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Simplified mnemonics instructions Table Simplified mnemonics (continued)
Mnemonic subfco rD,rB,rA subfco. rD,rB,rA e_add16i rD,rA,-value e_add2i. rA,-value e_add2is rA,-value e_addi rD,rA,-value e_addic rD,rA,-value e_addic. rD,rA,-value 31,0,0 4,rA,rB 12,rA,rB 8,rA,rB 20,rA,rB 12,rA,rB 1,rA,rB 6,rA,rB 2,rA,rB 6,rA,rB 5,rA,rB 16,rA,rB 24,rA,rB 20,rA,rB 12,rA,rB Instruction Subtract from carrying Subtract from carrying Subtract immediate Subtract operand immediate recorded Subtract operand shifted immediate Subtract immediate Subtract immediate carrying Subtract immediate carrying Trap unconditionally Trap equal Trap greater than equal Trap greater than Trap less than equal Trap logically greater than equal Trap logically greater than Trap logically less than equal Trap logically less than Trap logically greater than Trap logically less than Trap less than Trap equal Trap greater than Trap less than
UM0438
Simplified mnemonic subco rD,rA,rB subco. rD,rA,rB e_sub16i rD,rA,value e_sub2i. rA,value e_sub2is rA,value e_subi rD,rA,value e_subic rD,rA,value e_subic. rD,rA,value trap tweq rA,rB twge rA,rB twgt rA,rB twle rA,rB twlge rA,rB twlgt rA,rB twlle rA,rB twllt rA,rB twlng rA,rB twlnl rA,rB twlt rA,rB twne rA,rB twng rA,rB twnl rA,rB
Simplified mnemonics branch instructions that test should specify one; programming error occur. value BI32 BI16 operand selects CRn[2], bit. Instructions which B032 BO16 either (branch condition true) (branch condition false) depend value alternately coded incorporating condition specified BI32 BI16, described Section A.5.2: Simplified mnemonics that incorporate conditions (eliminates BO32 BO16 replaces BI32 with crS) value BI32 BI16 operand selects CRn[0], bit. value BI32 BI16 operand selects CRn[1], bit. value BI32 BI16 operand selects CRn[3], bit.
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Glossary
Appendix
Glossary
glossary contains alphabetical list terms, phrases, abbreviations used this book. Some terms definitions included glossary reprinted from IEEE Std. 754-1985, IEEE Standard Binary Floating-Point Arithmetic, copyright ©1985 Institute Electrical Electronics Engineers, Inc. with permission IEEE. Note that some terms defined context they used this book.
Architecture detailed specification requirements processor computer system. does specify details processor computer system must implemented; instead provides template family compatible implementations.
Biased exponent exponent whose range values shifted constant (bias). Typically bias provided allow range positive values express range that includes both positive negative values. Big-endian byte-ordering method memory where address word corresponds mostsignificant byte. addressed memory word, bytes ordered (left right) with being most-significant byte. Little-endian.
Cache High-speed memory component containing recently-accessed data and/or instructions (subset main memory).
Denormalized number nonzero floating-point number whose exponent reserved value, usually format's minimum, whose explicit implicit leading significant zero.
Effective address (EA) 64-bit address specified load, store, instruction fetch. This address then submitted translation either physical memory address address.
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Glossary Exponent
UM0438
binary representation floating-point number, exponent component that normally signifies integer power which value raised determining value represented number. also Biased exponent.
General-purpose register (GPR) registers general-purpose register file. These registers provide source operands destination results integer data manipulation instructions. Integer load instructions move data from memory GPRs store instructions move data from GPRs memory.
IEEE standard written Institute Electrical Electronics Engineers that defines operations representations binary floating-point arithmetic. Inexact Loss accuracy arithmetic operation when rounded result differs from infinitely precise value with unbounded range.
Least-significant (lsb) least value address, register, data element, instruction encoding. Little-endian byte-ordering method memory where address word corresponds leastsignificant byte. addressed memory word, bytes ordered (left right) with being most-significant byte. Big-endian.
Mnemonic abbreviated name instruction used coding. Modulo value which lies outside range numbers representable n-bit wide destination type replaced low-order bits two's complement representation Most-significant (msb) highest-order address, registers, data element, instruction encoding.
abbreviation `Not Number'; symbolic entity encoded floating-point format. There types NaNs-signaling NaNs (SNaNs) quiet NaNs (QNaNs).
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UM0438 Normalization.
Glossary
process which floating-point value manipulated such that represented format appropriate precision (single- double-precision). floating-point value representable single- double-precision format, leading implied must
Overflow error condition that occurs during arithmetic operations when result cannot stored accurately destination register(s). example, 32-bit numbers multiplied, result representable bits.
Record bit) instruction encoding. When set, updates condition register (CR) reflect result operation. presence denoted following mnemonic. Reserved field register, reserved field that assigned function. reserved field single bit. handling reserved bits implementation-dependent. Software permitted write value such bit. subsequent reading returns value last written returns undefined value otherwise. RISC (reduced instruction computing) architecture characterized fixed-length instructions with nonoverlapping functionality separate load store instructions that perform memory accesses.
Saturate value which lies outside range numbers representable destination type replaced representable number closest Signaling type that generates invalid operation program exception when specified arithmetic operands. Quiet NaN. Significand component binary floating-point number that consists explicit implicit leading left implied binary point fraction field right. Sticky that when must cleared explicitly.
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Glossary Supervisor mode
UM0438
privileged operation state processor. supervisor mode, software, typically operating system, access control registers access supervisor memory space, among other privileged operations.
Tiny floating-point value that small represented particular precision format, including denormalized numbers; they include
Underflow error condition that occurs during arithmetic operations when result cannot represented accurately destination register. example, underflow happen floating-point fractions multiplied result requires smaller exponent and/or mantissa than single-precision format provide. other words, result small represented accurately. User mode unprivileged operating state processor used typically application software. user mode, software only access certain control registers access only user memory space. privileged operations performed. Also referred problem state.
Word 32-bit data element.
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Revision history
Revision history
Table
Date 1-July-2007
Document revision history
Revision Initial release. Changes
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UM0438
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