STPC Atlas ISA/PCMCIA Mode Evaluation User Manual with ATLASISABD

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STPC Atlas ISA/PCMCIA Mode Evaluation User Manual with ATLASISABD

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ATLASISABD
STPC Atlas ISA/PCMCIA Mode Evaluation User Manual
with ATLASISABD Board Issue October 2001
Information provided believed accurate reliable. However, Microelectronics assumes responsibility consequences such information infringements patents other rights third parties which result from use. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied.
STMicroelectronics
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Motherboard Functional Specification
ATLASISABD GLANCE 1.1.1 STPC 1.1.2 Cache Memory 1.1.3 Main Memory 1.1.4 Slots 1.1.5 Interfaces
UNIFIED MEMORY ARCHITECTURE CORE INTEGRATED CHIPSET FUNCTIONS MEMORY INTERFACE PC-CARD INTERFACE INTERFACE INTERFACE GRAPHICS 1.10TFT
Hardware Installation
JUMPERS 2.1.1 Setting Jumpers 2.1.2 Jumper Switch Setting Symbols DEFAULT JUMPER SETTING. INSTALLATION 2.3.3 Step Installing Memory 2.3.4 Step Clear CMOS Memory 2.3.5 Step Default Jumper Setting BIOS Setup 2.3.6 Step Setting STPC Atlas Speed (S500 2.3.7 Step Setting Clock Speed (S500 2.3.8 Step Selecting Mode (S500 2.3.9 Step Type Selection (J500, J501 J509) 2.3.10Step Unused Switch keys (S500 2.3.11Jumper Setting Summary
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JTAG Facility
INTRODUCTION JTAG CHAIN DESCRIPTION JTAG CONNECTOR DETAILS
Motherboard Resources
SYSTEM ADDRESS MEMORY ADDRESS MAP. ADDRESS. INTERRUPTS CHANNELS
Motherboard Hardware Specification
CONNECTORS CONNECTOR CONNECTION DEFINITIONS 5.2.1 Connectors 5.2.2 Connector 5.2.3 Mouse Connector 5.2.4 Keyboard Connector 5.2.5 Parallel Port Connector 5.2.6 CVBS Video Connectors 5.2.7 S-VHS Video Connector 5.2.8 Digital Video Input Connector 5.2.9 Connectors 5.2.10USB Port Connectors 5.2.11COM (Serial Port) Connectors 5.2.12IDE Connectors 5.2.13ATX Power Supply Connector 5.2.14PC-Card Slot 5.2.15TFT Screen Output 5.2.16TFT Backlight Power Connector 5.2.17JTAG Connector 5.2.18GPIO Connector 5.2.19I2C Connector
ELECTRICAL SPECIFICATIONS
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Technical Support
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Motherboard Functional Specification
Motherboard Functional Specification
ATLASISABD system board high-performance personal computer system based STPC Atlas microprocessor, running with external 14.31818 quartz crystal oscillator.
ATLASISABD Glance
Each physical area board, illustrated board layout block diagram (Figure 1-1), described briefly following paragraphs. functional block schematic diagram board given Figure 1-2.
1.1.1 STPC
Supports STPC Atlas MHz.
1.1.2 Cache Memory
Integrated write back cache. cache subsystem installed.
1.1.3 Main Memory
first bank made using soldered SDRAM memory chips. capacity each these chips default Mbits, these components replaced either Mbit Mbit chips, thanks dual-footprint. second bank made using single DIMM socket which supports single-sided 168-pin DIMM modules.
1.1.4 Slots
32-bit slots. 16-bit slots. PCMCIA Socket Possible combinations: PCMCIA
1.1.5 Interfaces
power supply. Keyboard, Mouse, Parallel Interface, Serial Interfaces. master, slave. Real Time Clock. Boot flash. Disk-On-Chip. interface. SVGA monitor. Video input port (analog digital). Screen Interface. JTAG interface. GPIO connector.
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Motherboard Functional Specification bus. Speaker, Reset button, Power On/Off button. Display BIOS POST code (also helpful software debug).
Dimensions: 28.5 four layer PCB. Mounting: mounting holes.
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Motherboard Functional Specification
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Figure 1-1. Board Layout Block Diagram
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Disk Chip Mouse 8-bit Boot Flash Connector Connector
Micronas
Parallel Port
Serial Ports
Ports
Keyboard
Logic (Post code 80h)
JTAG
Video
Slots exclusive features
Motherboard Functional Specification
JTAG
Figure 1-2. Board Functional Schematic Block Diagram
Issue
PCMCIA Connector PCMCIA
STPC
Atlas
14.318 Quartz
Slots
Connector VCore VCore (2.5
UIDE Connectors SDRAM Connector Soldered SDRAM Bank JTAG
Reset Logic/Button Power Logic/Button
Debug Features Front Panel
Connectors
GPIO
Legend: Function
Connector, Slot Socket
Motherboard Functional Specification
Unified Memory Architecture
STPC Atlas makes tightly coupled Unified Memory Architecture (UMA), where same memory array used main memory graphics frame-buffer. This means reduction total system memory system performances that equal that comparable frame buffer system memory based system, generally much better, higher memory bandwidth allowed attaching graphics engine directly 64-bit processor host interface running speed processor rather than traditional bus.
Core
heart STPC Atlas advanced processor block that includes powerful processor core along with 64-bit SDRAM controller, advanced 64-bit accelerated graphics video controller, high speed local-bus controller Industry standard chip functions (Interrupt controller, UltraDMA Controller, Interval timer bus). STPC Atlas addition, output, Video Input, Local interface, PCMCIA super features including host hub.
Integrated Chipset Functions
`standard' chipset functions (DMA, interrupt controller, timers, power management logic) integrated together with processor core; additional bandwidth functions such communication ports accessed STPC Atlas internal bus. following features directly implemented STPC Atlas: Powerful Processor 64-Bit SDRAM Controller Graphics Controller SVGA Controller RAMDAC Enhanced Graphics Engine Video Input Port Video Pipeline Up-Scaler Video Colour Space Converter Chroma Colour Support Display Controller Compliant Master/Slave/Arbiter Master/Slave Controller 16-Bit Local Interface PCMCIA Interface Controller Ultra DMA-33 Controller Host Interfaces Features PC/AT+ Keyboard Controller PS/2 Mouse Controller
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Motherboard Functional Specification Serial Ports Parallel Port General Purpose I/Os Interface Integrated Peripheral Controller Controller Interrupt Controller Timer/Counters Power Management Unit Watchdog JTAG IEEE1149.1
Memory Interface
STPC Atlas handles memory data directly, controlling from MBytes MBytes. SDRAM controller supports accesses Memory Banks to/from (via host), from to/from CRTC, VIDEO with Video Pipeline (Banks which populated with either single-sided double-sided 72-bit (4-bit parity) memory devices. Parity supported. memory interface comprises soldered memory bank plus DIMM socket single-sided memory modules only. SDRAM controller supports 64-bit wide Memory Banks, with buffered unbuffered SDRAM devices devices. SDRAM devices must support Full Page Mode Type access. STPC Atlas Memory Controller provides various programmable SDRAM parameters allow SDRAM interface optimised different processor speeds, SDRAM speed grades Latency. implements 64-bit single memory subsystem both system well Frame Buffer memory. other words, size DRAM available system reduced size DRAM allocated Frame Buffer.
PC-Card Interface
STPC Atlas configured either PC-Card connection external devices.
Interface
Generates clock from either 14.318 oscillator clock clock Supports programmable extra wait state cycles Supports recovery time back back cycles. Fast Gate Fast reset. Supports single that blocks shares with block BIOS ROM. Supports flash ROM. Supports hidden refresh.
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Motherboard Functional Specification Buffered master cycles reduce bandwidth utilization Host bus.
Interface
main data communication link STPC Atlas chip. STPC Atlas translates appropriate host Memory cycles onto bus. also supports generation Configuration cycles bus. STPC Atlas, agent (host bridge class), fully complies with specification 2.1. chip-set also implements mandatory header registers Type configuration space easy porting aware system BIOS. device contains arbitration function three external devices.
Graphics
Graphics functions controlled through on-chip SVGA controller monitor display produced through graphics display engine. This Graphics Engine tuned work with host provide balanced graphics system with silicon area cost. performs limited graphics drawing operations which include hardware acceleration text, bitblts, transparent blts fills. results these operations change contents on-screen off-screen frame buffer areas SDRAM memory. frame buffer occupy space Mbytes anywhere physical main memory. maximum graphics resolution supported 1280 1024 Million colours refresh rate SVGA compatible. Horizontal timing fields compatible while vertical fields extended accommodate above display resolution. main features Enhanced Graphics Controller listed below: Supports pixel depths 8-bit, 16-bit, 24-bit 32-bit. Full BitBLT implementation raster operations defined Windows. Supports four transparent modes Bitmap Transparency, Pattern Transparency, Source Transparency Destination Transparency. Hardware clipping Fast line draw engine with anti-aliasing. Fast triangle fill engine. Supports 4-bit alpha blended font anti-aliased text display. Complete double buffered registers pipelined operation. 64-bit wide pipelined architecture running MHz. High performance 64-bit windows accelerator. Complete backward compatibility SVGA standards. Hardware acceleration Text (generalized expansion), bitblts fills. long linear Frame Buffer. output analog format, Interlacing supported
1.10
generate output, STPC Atlas extracts digital video stream before
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Motherboard Functional Specification RAMDAC reformats format. height width flat panel programmable through configuration registers size 1024 1024. default, lower resolution images cover only part larger panel. STPC Atlas allows user expand image vertically horizontally text mode inserting programmable blank pixels. allows expansion image vertically horizontally graphics mode replicating pixels. replication times every pixel independently programmable vertical horizontal directions. power supply cable connected board-mounted 10-pin connector using 5-pin female header. signal cable cable suit Molex connector type 52030-3010 equivalent. Molex connector information found Molex site: WWW: http://www.Molex.com PanelLinkand LVDS supported directly externally implemented. PanelLinkis proprietary interconnect protocol defined Silicon Image, Inc. consists transmitter that takes parallel video/graphics data from host graphics controller transmits serially high speed receiver which controls panel. interface designed support connection this control signal PanelLinktransmitter. Given below list devices that known supported. This list only indicative other types used. Manufacturer HAPD HAPD Electronics Sharp Hyunday Part Number HLD1201 HLD1209 NL6448 NL8060AC26-11 LM151X2 LQ64D341 HT15x22 Resolution 800x600 800x600 640x480 800x600 1024x768 640x480 1024x768
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Hardware Installation
Hardware Installation
Installing system board requires configuration switches, setting jumpers attachment connectors. Figure jumper location information.
Jumpers
Jumpers system board provide information your system about installed options system settings.
2.1.1 Setting Jumpers
Configure system board option setting jumpers. Note: When jumper left open, leave plastic jumper attached pins save losing
2.1.2 Jumper Switch Setting Symbols
2-pin jumpers, following symbols used: Close pins with jumper cap.
Open pins without jumper cap.
3-pin jumpers, following symbols used: Close pins with jumper cap.
Close pins with jumper
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Hardware Installation
S500 switches, following symbols used: Push button side switch marking) related entry logical "0". Pull button bottom side switch related entry logical
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Hardware Installation
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Figure 2-1. Jumper Location Diagram
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Hardware Installation
Default Jumper Setting.
Table 2-1. Default Jumper Setting
Jumper J508 J500 J501 J509 J1500 PCMCIA choice default: CMOS clean-up default: Normal mode J1502 J1503 Disk-On-Chip address range default: C8000h-C9FFFh Both jumpers Jumper three jumpers Purpose HCLK/MCLK synchronisation default: synchronisation enabled Setting Jumper
J3302
Board power control default: Switch soft control
System configuration default: S500 HCLK (CPU) clock HCLK/3 Clock Multiplier
Please Note; ower supplies require minimum load least output. this done, there risk that board will start that power supply will regulated.
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Hardware Installation
Installation
main board installation, important that jumper settings correctly. Improper jumper settings cause system instability system hang-up. Please follow installation procedures given below.
2.3.3 Step Installing Memory
main board supports four dual-footprint sockets soldered SDRAM memory devices also single DIMM SDRAM socket. Soldered SDRAM ATLASISABD normally supplied with four 16-bit, 54-pin TSOP(ll)) devices soldered board. required, these could replaced with four 16bit, 50-pin TSOP(ll)) devices with four 16-bit, 54-pin TSOP(ll)) devices. Note: 16-bit, 54-pin TSOP(ll)) devices supported. DIMM Socket second bank memory uses DIMM socket insertion single-sided 168-pin DIMM module. Buffered, buffered registered DIMM modules supported, where type DIMM module fitted dependent type soldered SDRAM fitted. default soldered SDRAM devices, single-sided DIMMS with either chips used. soldered SDRAM devices fitted, DIMM modules with chips only used. soldered SDRAM devices, DIMM modules with chips used. Provision included fitting terminator devices, U709 U710, type PACDN005, needed when DIMM module that does conform SDRAM standard fitted. Note default condition terminators fitted.
2.3.4 Step Clear CMOS Memory
BOARD OPERATING, switch board using PB3301 Power button. Place jumper J1500 seconds then remove (default). Verify that S500 switch configured with default settings described Table 2-1.
2.3.5 Step Default Jumper Setting BIOS Setup
power, keyboard, mouse screen must correctly connected. Switch board pressing PB3301 Power ON/OFF button. When requested screen enter BIOS Setup, press `DEL'. Setup menu `Basic CMOS Configuration'. Configure parameters installed disk(s). Return main menu pressing `ESC'. Choose `Write CMOS Exit' save entries quit BIOS Setup.
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Hardware Installation
2.3.6 Step Setting STPC Atlas Speed (S500
Using S500 switch, keys given Table 2-2, according expected speed. This validated reset Power This speed corresponds HCLK (CPU) clock. devices, core runs twice this speed. Warning: Improper speed setting cause serious damage STPC.
Table 2-2. S500 -4.6 Settings
Setting S500 S500 S500
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Hardware Installation
2.3.7 Step Setting Clock Speed (S500
Using S500 switch, keys given Table Table 2-4, according STPC Atlas HCLK (CPU) speed setup required clock speed. This validated reset Power
Table 2-3. S500 Setting
Setting HCLK HCLK S500
Table 2-4. S500 Setting
Setting clock from clock from S500
2.3.8 Step Selecting Mode (S500
configuration done setting S500 switch, given Table 2-5. core STPC Atlas will then twice HCLK clock specified setting S500 keys This validated after reset Power
Table 2-5. S500 Setting
Setting Mode Mode S500
2.3.9 Step Type Selection (J500, J501 J509)
STPC Atlas using either Bridge redirecting signals PC-Card, given Table 2-6. this stage that choice made.
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Hardware Installation
Table 2-6. J500, J501 J509 Settings
Setting PC-Card J500, J501 J509 Jumpers Jumpers
2.3.10 Step Unused Switch keys (S500
Those switches connected free pads. They either OFF.
2.3.11 Jumper Setting Summary
Table 2-7. Jumper Setting Summary
Jumper S500-1 S500-[2-3] S500-[4-6] S500-[7-8] J508 J500 J501 J509 J1500 CMOS Type Setting Title Clock Mode Clock Frequency Clock Frequency Unused HCLK/MCLK Synchronisation Setting Mode OFF: Mode Table 2-3. Table 2-4. seeTable 2-2. Don't care MCLK HCLK synchronized OFF: MCLK HCLK synchronized OFF: PC-Card Reset CMOS OFF: Normal Mode J1502 OFF: J1503 OFF; C8000h-C9FFFh J1502 J1503 OFF; D8000h-D9FFFh J1502 OFF: J1503 CC000h-CDFFFh J1502 J1503 DC000h-DDFFFh 1-2: Switch Soft Control J3302 Power Control 2-3: Force OFF: Force 1-2: 2-3:
J1502 J1503
Disk-On-Chip Address Range
J3800
Power Supply
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JTAG Facility
JTAG Facility
Introduction
JTAG (Joint Test Action Group) facility complies with requirements IEEE1149.1, common protocol boundary-scan architecture developed into industrial standard. requires special test circuits inputs outputs (boundary-scan) selected semi-conductor components, together with logic control these test circuits. 4-wire serial test combines test circuits into complete test group which controlled test bus. further detailed information, refer publication IEEE Standard Test Access Port Boundary-Scan Architecture, IEEE 1149.1. ATLAS Local Evaluation Board includes JTAG connector (P4000 Table 3-2). This used program Programmable Logic Device (PLD) allows STPC Atlas JTAG debug facilities. Access JTAG chain possible using external equipped with suitable hardware software example, Altera BitBlaster Serial Download Cable Altera Maxplus+II software (see Figure 3-1). further details, visit Altera Internet Website http://www.altera.com
Figure 3-1. Example Test System
10-way Flying Lead with Altera Maxplus+II Software RS-232 Cable
Port
STPC EVALUATION BOARD
Altera
JTAG CONNECTOR
BitBlaster
JTAG Chain Description
There three JTAG components interconnected form JTAG chain. These EPM7064S PLD, VPX3226E Analog-to-Digital Video Decoder STPC Atlas, shown Figure 3-2. required parameters configure correctly JTAG chain given Table 3-1.
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JTAG Facility
STPC JTAG Connector
EPM7064S
VPX3226E
Figure 3-2. JTAG Chain
Table 3-1. JTAG Configuration Parameters STPC Atlas Boundary Scan Length: Instruction Register Length: 0CC15041 1029 bits EPM7064S 070640DD bits VPX3226E 133500D9 bits
JTAG Connector Details
Table 3-2. JTAG Connector (P4000)
Signal Name (Test Data Input) (Test Mode Select) TRST (Test Reset) (Test Data Output) (Test Clock) Connection
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Motherboard Resources
Motherboard Resources
System Address
This section describes mapping memory address spaces. Also covered this section configuration space mapping
Memory Address Map.
Table 4-1. Memory Address
Address Range (Dec) 1024K-16984K 896K-1024K 768K-800K 736K-768K 704K-736K 640K-704K 0K-640K Address Range (Hex) 100000h-1000000h 0E0000h-0FFFFFh 0C0000h-0C7FFFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A0000h-0AFFFFh 0-9FFFFh Size 15960 Description Extended Memory System Bios Graphic Bios Colour Text Memory Mono Chrome Text Memory "Graphics" Memory Conventional Memory
Address
system chip-set implements number registers address space, given following Address Map.
Table 4-2. Address
Address Range (Hex) 0000h-000Fh 0020h-0021h 0022h-0023h 0040h-0043h 0060h 0061h 0064h 0070h 0071h 0078h 0080h-008Fh 00A0h-00A1h 00C0h-00DEh 00F0h 0102h Size (Hex) Bytes Bytes Bytes Bytes Bytes Byte Byte Byte Byte Byte Bytes Bytes Bytes Byte Byte Description Controller (8237) Interrupt Controller (8259) STPC Specific Registers Timer Controller (8254) Keyboard Controller Data Byte Port Ctlr, CMD,STAT Byte Real Time Clock Address Real Time Clock Data General Purpose Page Registers Interrupt Controller (8259) Controller (8237) Reset Numeric Error Setup Register
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Motherboard Resources
Table 4-2. Address
Address Range (Hex) 0170h-0177h 01F0h-01F7h 0278h-027Bh 02F8h-02FFh 0378h-037Fh 03B4h, 03B5h, 03BAh 03D4h, 03D5h, 03DAh 03C0h-03CFh 03F6h 03F7h, bits 03F8h-03FFh 0CF8h 0CFCh-0CFFh 046E8h C000h-C0FFh Size (Hex) Bytes Bytes Bytes Bytes Bytes bytes Bytes Bytes Byte bits Bytes Byte Bytes Byte Bytes Description Secondary Channel Primary Channel Parallel Port Serial Port Parallel Port Registers Registers Registers Command Port Status Port Serial Port Configuration Address Register Configuration Data Registers Add-in mode enable Register Configuration Registers
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Motherboard Resources
Interrupts Channels
Table 4-3. Channels
System Resource Parity Error Reserved, Interval Timer Reserved, Keyboard Buffer Full Reserved, Cascade Interrupt from Interrupt Controller Serial Port Serial Port User available User available Parallel Port Real Time Clock User available (Video) User available User available PS/2 Mouse Port Reserved, Math Coprocessor User available
Table 4-4. Channels
16-bit 16-bit 16-bit Data Width 8-bit 8-bit 8-bit 8-bit System Resource User available User available User available Parallel Port (ECP mode) Reserved, Cascade Channel User Available User Available User Available
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Motherboard Resources
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Motherboard Hardware Specification
Motherboard Hardware Specification
Connectors
following table (Table 5-1) contains full list connectors implemented board. Refer numbered Table given connection details.
Table 5-1. Connectors List
Identification P1300, P1301 P900, P901 P2510 P700 P3100 J3100 P3102 P3109 P2701 P2511 P2500 P2506 P2507 P2100 P2101 P2300 P3300 P3800 P3801 P4000 P3700 P4400 J3300 J3301 Table Table Table 5-11, Table 5-12 Table 5-13 Table 5-18 Table Table Table 5-10 Table Table Table Table Table Table 5-15 Table 5-15 Table 5-16 Table 5-16 Table 5-14 Table 5-17 Table 5-19 Table 5-20 Table 5-21 Table 5-22 Table 5-23 Name Slot (16-bit) Slot PC-Card Slot (PCMCIA) SDRAM socket CVBS Video Input CVBS Video Input Digital Video Input Port S-VHS Video Input Mouse Keyboard Parallel Port Port Port Primary Secondary Ports Power Supply Screen Output Power JTAG GPIO Reset Button Power Button Dual Mini Straight header Straight header Shrouded Straight header Shrouded Straight header Dual connector pins Straight header Straight header Straight header Straight header Straight header Straight header 168-pin DIMM connector CINCH Straight header Straight header Type Pins
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Motherboard Hardware Specification
Connector Connection Definitions 5.2.1 Connectors
Table 5-2. Connector (P1300 P1301)
Signal Name RSTDRV IRQ9 DRQ2 -12V +12V SMEMW# SMEMR# IOW# IOR# DACK3# DREQ3 DACK1# DRQ1 REFRESH# BCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2# BALE MEMCS16# SBHE# Signal Name IOCHCK# IOCHRDY SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10
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Motherboard Hardware Specification
Table 5-2. Connector (P1300 P1301)
Signal Name IOCS16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0# DRQ0 DACK5# DRQ5 DACK6# DRQ6 DACK7# DRQ7 MASTER# Signal Name LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR# MEMW# SD10 SD11 SD12 SD13 SD14 SD15
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Motherboard Hardware Specification
5.2.2 Connector
Table 5-3. Standard Connector (P2701)
Signal Name Green Blue Fuse DDCDAT DDCCLK
5.2.3 Mouse Connector
Table 5-4. Mouse Connector (P2511 upper side)
Signal Name MData MVCC MClk
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Motherboard Hardware Specification
5.2.4 Keyboard Connector
Table 5-5. Keyboard Connector (P2511 lower side)
Signal Name KBData KBVCC KBClk
5.2.5 Parallel Port Connector
Table 5-6. Parallel Connector (P2500)
Signal Name STROBE#1 DP1_0 DP1_1 DP1_2 DP1_3 DP1_4 DP1_5 DP1_6 DP1_7 ACK#1 BUSY1 SLCT1 Signal Name AFD#1 ERROR#1 INIT#1 SLCT IN#1
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Motherboard Hardware Specification
5.2.6 CVBS Video Connectors
Table 5-7. CVBS Video Connector (P3100)
Signal Name COMPOSITE VIDEO
Table 5-8. CVBS Video Connector (J3100)
Signal Name COMPOSITE VIDEO
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Motherboard Hardware Specification
5.2.7 S-VHS Video Connector
Table 5-9. S-VHS Video Connector (P3109)
Signal Name Y_IN C_IN
5.2.8 Digital Video Input Connector
Table 5-10. Digital Video Input Port (P3102)
Signal Name VIP_D0 VIP_D1 VIP_D2 Connected VIP_D3 Connected VIP_D4 Connected VIP_D5 VIP_SCL VIP_D6 VIP_D7 VIP_VCLOCK VIP_VCS VIP_ODD/EVEN# Connected Connected VIP_SDA
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Motherboard Hardware Specification
5.2.9 Connectors
Table 5-11. Connectors (P900 P901)
Signal Name +12V next tables next tables Reserved Reserved Reserved RESET# next tables Reserved AD30 3.3V AD28 AD26 AD24 next tables 3.3V AD22 AD20 AD18 AD16 3.3V FRAME# Signal Name -12V next tables next tables Reserved Reserved PCICLK next tables AD31 AD29 AD27 AD25 3.3V CBE3# AD23 AD21 AD19 3.3V AD17 CBE2# IRDY-
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Motherboard Hardware Specification
Table 5-11. Connectors (P900 P901)
Signal Name TRDY# STOP# 3.3V SDONE SBO# AD15 3.3V AD13 AD11 CBE0# 3.3V Signal Name 3.3V DEVSEL# PCILOCK# PERR# 3.3V SERR# 3.3V CBE1# AD14 AD12 AD10 3.3V
Table 5-12. Connector (P901)
Signal Name PCI_INT1# PCI_INT3# PCI_GNT1# IDSELB (AD31) PCI_REQ1# PCI_INT2# PCI_INT0# Signal Name
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Motherboard Hardware Specification
Table 5-13. Connector (P900)
Signal Name PCI_INT0# PCI_INT2# PCI_GNT0# IDSELA (AD30) PCI_REQ0# PCI_INT1# PCI_INT3# Signal Name
5.2.10 Port Connectors
Table 5-14. Dual Connector (P2300)
Signal Name Data0Data0+ Data1Data1+ Fuse
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Motherboard Hardware Specification
5.2.11 (Serial Port) Connectors
Table 5-15. (Serial Port) Connectors (P2506, P2507)
Signal Name HDCD# HRxD HTxD HDTR# HDSR# HRTS# HCTS# HRI# (SubD P2506) (Header P2507)
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Motherboard Hardware Specification
5.2.12 Connectors
Table 5-16. Connectors (P2100, P2101)
Signal Name RST# DREQ DIOW# DIOR# IOCHRDY DACK# HCS#0 Activity Signal Name HD10 HD11 HD12 HD13 HD14 HD15 IOCS16# HCS#1
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Motherboard Hardware Specification
5.2.13 Power Supply Connector
Table 5-17. Power Supply Connector (P3300)
Signal Name +3.3V -12V Signal Name +3.3V +3.3V POWER GOOD Supply Backup +12V
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Motherboard Hardware Specification
5.2.14 PC-Card Slot
Table 5-18. PC-Card Slot Connector (P2510)
Signal Name D[3] D[4] D[5] D[6] D[7] CE1# A[10] OE#/TCw A[11] A[9] A[8] A[13] A[14] WE#/TCr READY#/BUSY#/IRQ# A[16] A[15] A[12] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D[0] D[1] D[2] Signal Name CD1# D[11] D[12] D[13] D[14] D[15] CE2# VS1# IORD# IOWR# A[17] A[18] A[19] A[20] HDSEL A[22] A[23] A[24] A[25] VS2# RESET WAIT# INPACK# REG# BVD2 BVD1 D[8] D[9] D[10] CD2#
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Motherboard Hardware Specification
5.2.15 Screen Output
Table 5-19. Screen Output Connector (P3800)
Signal Name DCLK FPLINE FPFRAME TFTVCC TFTVCC
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Motherboard Hardware Specification
5.2.16 Backlight Power Connector
Table 5-20. Backlight Power Connector (P3801)
Signal Name TFT_ENVDD12V TFT_ENVDD5V TFT_PWM TFT_VCC Variable voltage
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Motherboard Hardware Specification
5.2.17 JTAG Connector
Table 5-21. JTAG Connector (P4000)
Signal Name TRST TCLK Connection
5.2.18 GPIO Connector
Table 5-22. GPIO Connector (P3700)
Signal Name GPIO_0 GPIO_1 GPIO_13 GPIO_2 GPIO_3 GPIO_14 GPIO_4 GPIO_5 GPIO_15 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10
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Motherboard Hardware Specification
Table 5-22. GPIO Connector (P3700)
Signal Name GPIO_11 GPIO_12
5.2.19 Connector
Table 5-23. Connector (P4400)
Signal Name
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Motherboard Hardware Specification
Electrical Specifications
Power Supply used power this board must have following characteristics.
Table 5-24. Power Supply Characteristics
Voltage +3.3 Precision +/-500
Details Gerber designs available site.
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Motherboard Hardware Specification
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Technical Support
Technical Support
Visit STMicroelectronics Internet World Wide (WWW) product presentation, technical literature product support information. dedicated STPC section available, providing date hardware documentation software tools. updated versions this ATLASISABD User Manual will found this section. Technical questions regarding ATLASISABD Evaluation other STPC related product should addressed your nearest Microelectronics Sales Office. STMicroelectronics address
http://www.st.com/stpc
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Technical Support
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Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. 2000 STMicroelectronics Rights Reserved logo registered trademark STMicroelectronics. other names property their respective owners. STMicroelectronics GROUP COMPANIES Australia Brazil China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A.
Issue This preliminary information product development undergoing evaluation. Details subject change without notice.

STPC Atlas ISA/PCMCIA Mode Evaluation User Manual with ATLASISABD

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