Turbo Plus series Fast Turbo 8032 with programmable logic Fast 8-
|
|
|
Top Searches for this datasheet
UPSD3422 UPSD3433 UPSD3434 UPSD3454
Turbo Plus series Fast Turbo 8032 with programmable logic
Fast 8-bit Turbo 8032 MCU, Advanced core, 4-clocks instruction MIPs peak performance JTAG debug in-system programming 16-bit internal instruction path fetches double-byte instruction single memory cycle Branch cache instruction prefetch queue Dual XDATA pointers with automatic increment decrement Compatible with party 8051 tools Dual Flash memories with memory management Place either memory into 8032 program address space data address space READ-while-WRITE operation inapplication programming EEPROM emulation Single voltage program erase guaranteed erase cycles, 15-year retention Clock, reset, power supply management Flexible 8-level clock divider register Normal, Idle, power-down modes Power-on-reset low-voltage-reset supervisor Programmable watchdog timer Programmable logic, general purpose macrocells logic applications (e.g., shifters, state machines, chip-selects, gluelogic keypads, LCDs) converter Eight channels, 10-bit resolution, Operating voltage source (±10%) devices: sources devices: source
LQFP52 (T), 52-lead, thin, quad, flat
LQFP80 (U), 80-lead, thin, quad, flat
Communication interfaces v2.0 Full Speed (12Mbps) endpoint pairs (In/Out), each endpoint with 64-byte FIFO (supports Control, Intr, Bulk transfer types) Master/Slave controller, 833kHz Master controller, 10MHz UARTs with independent baud rate IrDA potocol: kbaud I/O, tolerant uPSD34xxV Timers interrupts Three 8032 standard 16-bit timers Programmable counter array (PCA), 16bit modules PWM, CAPCOM, timers 8/10/16-bit operation Interrupt sources with external interrupt pins Packages ECOPACK® compliant Device summary
Part number UPSD3422E, UPSD3422EV UPSD3433E, UPSD3433EV UPSD3434E, UPSD3434EV UPSD3454E, UPSD3454EV
Table
Reference uPSD3422 uPSD3433E uPSD3434 uPSD3454
January 2009
1/300
www.st.com
Contents
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Contents
Description descriptions Hardware description Memory organization
Internal memory (MCU module, standard 8032 memory: DATA, IDATA, SFR)
4.1.1 4.1.2 4.1.3 DATA memory IDATA memory memory
External memory (PSD module: program memory, data memory)
4.2.1 4.2.2 4.2.3 Program memory Data memory Memory placement
8032 core performance enhancements
Pre-fetch queue (PFQ) branch cache (BC) example, multi-cycle instructions Aggregate performance
module description 8032 registers
Stack pointer (SP) Data pointer (DPTR) Program counter (PC) Accumulator (ACC) register General purpose registers Program status word (PSW)
7.7.1 7.7.2 Carry flag (CY) Auxiliary carry flag (AC)
2/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 7.7.3 7.7.4 7.7.5 7.7.6
Contents
General purpose flag (F0) Register bank select flags (RS1, RS0) Overflow flag (OV) Parity flag
Special function registers (SFR) 8032 addressing modes
9.10 9.11 Register addressing Direct addressing Register indirect addressing Immediate addressing External direct addressing External indirect addressing Indexed addressing Relative addressing Absolute addressing Long addressing addressing
UPSD34xx instruction summary Dual data pointers
11.1 11.2 Data pointer control register, DPTC (85h) Data pointer mode register, DP(86h)
11.2.1 Firmware example
Debug unit Interrupt system
13.1 Individual interrupt sources
13.1.1 13.1.2 13.1.3 13.1.4 13.1.5 External interrupts Int0 Int1 Timer overflow interrupt Timer overflow interrupt UART0 UART1 interrupt interrupt
3/300
Contents 13.1.6 13.1.7 13.1.8 13.1.9
UPSD3422, UPSD3433, UPSD3434, UPSD3454 interrupt interrupt interrupt interrupt
clock generation
14.1 14.2 MCU_CLK PERIPH_CLK
14.2.1 14.2.2 JTAG interface clock USB_CLK
Power saving modes
15.1 15.2 15.3 Idle mode Power-down mode Reduced frequency mode
Oscillator external components ports module
17.1 port operating modes
17.1.1 17.1.2 17.1.3 17.1.4 GPIO function GPIO output GPIO input Alternate functions
interface
18.1 18.2 18.3 18.4 18.5 PSEN cycles READ WRITE cycles Connecting external devices Programmable timing Controlling
Supervisory functions
19.1 19.2 19.3 External reset input pin, RESET_IN voltage detect, Power-up reset
4/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Contents
19.4 19.5
JTAG debug reset Watchdog timer,
19.5.1 Firmware example
Standard 8032 timer/counters
20.1 20.2 20.3 20.4 20.5 Standard timer SFRs Clock sources SFR, TCON SFR, TMOD Timer Timer operating modes
20.5.1 20.5.2 20.5.3 20.5.4 Mode Mode Mode Mode
20.6
Timer
20.6.1 20.6.2 20.6.3 Capture mode Auto-reload mode Baud rate generator mode
Serial UART interfaces
21.1 UART operation modes
21.1.1 21.1.2 21.1.3 21.1.4 21.1.5 Mode Mode Mode Mode Multiprocessor communications
21.2 21.3
Serial port control registers UART baud rates
21.3.1 21.3.2 Using timer generate baud rates Using timer/counter generate baud rates
21.4 21.5 21.6
More about UART mode More about UART mode More about UART modes
IrDA interface
22.1 Baud rate selection
5/300
Contents
UPSD3422, UPSD3433, UPSD3434, UPSD3454
22.2
Pulse width selection
interface
23.1 23.2 23.3 23.4 23.5 interface main features Communication flow Operating modes arbitration Clock synchronization
23.5.1 23.5.2 Clock sync during arbitration Clock sync during handshaking
23.6 23.7 23.8 23.9
General call address Serial engine (SIOE) interface control register (S1CON) interface status register (S1STA)
23.9.1 Interrupt conditions
23.10 data shift register (S1DAT)
23.10.1 wait condition
23.11 address register (S1ADR) 23.12 Start sample setting (S1SETUP) 23.13 operating sequences
23.13.1 Interrupt service routine (ISR)
(synchronous peripheral interface)
24.1 24.2 24.3 24.4 24.5 24.6 features communication flow Full-duplex operation Bus-level activity registers configuration Dynamic control
interface
25.1 Basic concepts
25.1.1 25.1.2 25.1.3 Communication flow Endpoints Packets
6/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 25.1.4
Contents
Data transfers with host
25.2 25.3
Types transfers
25.2.1 Enumeration
Endpoint FIFOs
25.3.1 25.3.2 25.3.3 25.3.4 25.3.5 25.3.6 Busy (BSY) operation Busy interrupts FIFO pairing Reading writing FIFOs Accessing FIFO control registers, UCON, USIZE Accessing setup command buffer
25.4
registers
25.4.1 25.4.2 25.4.3 device address register Endpoint FIFO pairing interrupts
25.5
Typical connection
Analog-to-digital convertor (ADC)
26.1 Port channel selects
Programmable counter array (PCA) with
27.1 27.2 27.3 27.4 27.5 27.6 27.7 27.8 27.9 block clock selection Operation modes Capture mode Timer mode Toggle mode mode (x8), fixed frequency mode (x8), programmable frequency mode fixed frequency, 16-bit
27.10 mode fixed frequency, 10-bit 27.11 Writing capture/compare registers 27.12 Control register definition 27.13 interrupts
module
7/300
Contents
UPSD3422, UPSD3433, UPSD3434, UPSD3454
28.1
module functional description
28.1.1 28.1.2 28.1.3 28.1.4 28.1.5 28.1.6 28.1.7 28.1.8 28.1.9 8032 address/data/control interface Dual Flash memories Main Flash memory Secondary Flash memory SRAM Runtime control registers, csiop Memory page register Programmable logic (PLDs) decode (DPLD)
28.1.10 general (GPLD) 28.1.11 OMCs 28.1.12 allocator 28.1.13 IMCs 28.1.14 ports 28.1.15 JTAG port 28.1.16 Power management 28.1.17 Security sector protection
28.2
Memory mapping
28.2.1 28.2.2 28.2.3 28.2.4 28.2.5 28.2.6 28.2.7 8032 program address space 8032 data address space (XDATA) Specifying memory with PSDsoft express EEPROM emulation Alternative mapping schemes Memory sector select rules register
28.3 28.4 28.5
module data width Runtime control register definitions (csiop) module detailed operation
28.5.1 28.5.2 28.5.3 28.5.4 28.5.5 28.5.6 28.5.7 Flash memory operation Flash memory instruction sequences Reading Flash memory Read memory contents Reading erase/program status bits Data polling flag (DQ7) Toggle flag (DQ6)
8/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 28.5.8 28.5.9
Contents
Error flag (DQ5) Erase time-out flag (DQ3)
28.5.10 Programming Flash memory 28.5.11 Data polling 28.5.12 Data toggle 28.5.13 Ready/Busy (PC3) 28.5.14 Bypassed unlock sequence 28.5.15 Erasing Flash memory 28.5.16 Flash bulk erase 28.5.17 Flash sector erase 28.5.18 Suspend sector erase 28.5.19 Resume sector erase 28.5.20 Reset Flash 28.5.21 Reset signal applied Flash memory 28.5.22 Flash memory sector protection 28.5.23 Flash memory protection during power-up 28.5.24 module security 28.5.25 PLDs 28.5.26 Turbo PLDs 28.5.27 Decode (DPLD) 28.5.28 General (GPLD) 28.5.29 Output macrocell 28.5.30 allocator 28.5.31 Product term allocator 28.5.32 Loading reading OMCs 28.5.33 mask registers 28.5.34 Input macrocells 28.5.35 ports 28.5.36 General port architecture 28.5.37 Port operating modes 28.5.38 mode 28.5.39 mode 28.5.40 Latched address output mode 28.5.41 Peripheral mode 28.5.42 JTAG mode 28.5.43 Other port capabilities 28.5.44 Port drive options
9/300
Contents
UPSD3422, UPSD3433, UPSD3434, UPSD3454 28.5.45 Drive select registers 28.5.46 Enable registers 28.5.47 Individual port structures 28.5.48 Port structure 28.5.49 Port structure 28.5.50 Port structure 28.5.51 Port structure 28.5.52 Power management 28.5.53 Automatic power-down (APD) 28.5.54 Forced power-down (FDP) 28.5.55 Chip select input (CSI) 28.5.56 non-turbo mode 28.5.57 current consumption 28.5.58 Turbo mode current consumption 28.5.59 Non-turbo mode current consumption 28.5.60 blocking bits 28.5.61 Blocking 8032 control signals 28.5.62 Blocking common clock, CLKIN
28.6
module reset conditions
28.6.1 28.6.2 28.6.3 28.6.4 28.6.5 28.6.6 28.6.7 28.6.8 28.6.9 JTAG JTAG debug JTAG chaining inside package In-system programming 4-pin JTAG (default) 6-pin JTAG (optional) Recommended JTAG connector Chaining UPSD34xx devices Debugging 8032 module JTAG security setting
28.6.10 Initial delivery state
AC/DC parameters Maximum rating parameters Package mechanical information
10/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Contents
Part numbering Important notes
34.1 34.2 34.3 34.4 34.5 34.6 34.7 34.8 34.9 interrupts with idle mode reset interrupt reset Data toggle FIFO accessibility Erroneous resend data packet FIFO pairing operation FIFO pairing operation Missing host retransmission SETUP packet
34.10 JTAG 34.11 Port 5-volt tolerant 34.12 Incorrect code execution when code banks switched 34.13 received data corrupted UART modes
Revision history
11/300
List tables
UPSD3422, UPSD3433, UPSD3434, UPSD3454
List tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Device summary definitions Port type voltage source combinations Register bank select addresses memory with direct address reset value Arithmetic instruction set. Logical instruction Data transfer instruction Boolean variable manipulation instruction Program branching instruction Miscellaneous instruction Notes instruction addressing modes DPTC: data pointer control register (SFR 85h, reset value 00h) DPTC register definition DPTM: data pointer mode register (SFR 86h, reset value 00h) DPregister definition Interrupt summary. interrupt enable register (SFR A8h, reset value 00h) register definition IEA: interrupt enable addition register (SFR A7h, reset value 00h) register definition interrupt priority register (SFR B8h, reset value 00h) register definition IPA: Interrupt Priority Addition register (SFR B7h, reset value 00h) register definition PLLM PLLD values different fOSC frequencies CCON0: clock control register (SFR F9h, reset value 50h) CCON0 register definition CCON1 control register (SFR FAh, reset value 00h) CCON1 register definition module port peripheral status during reduced power modes State 8032 signals during power-down idle modes PCON: power control register (SFR 87h, reset value 00h). PCON register definition port register (SFR 90h, reset value FFh) register definition port register (SFR B0h, reset value FFh) register definition port register (SFR C0h, reset value FFh) register definition P3SFS: Port special function select register (SFR 91h, reset value 00h) P3SFS register definition P1SFS0: Port special function select register (SFR 8Eh, reset value 00h) P1SFS1: Port special function select register (SFR 8Fh, reset value 00h) P1SFS0 P1SFS1 details P4SFS0: Port special function select register (SFR 92h, reset value 00h). P4SFS1: Port special function select register (SFR 93h, reset value 00h). P4SFS0 P4SFS1 details
12/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
List tables
BUSCON: control register (SFR 9Dh, reset value EBh) BUSCON register definition Number MCU_CLK periods required optimize transfer rate WDKEY: Watchdog timer register (SFR AEh, reset value 55h) WDKEY register definition WDRST: Watchdog timer reset counter register (SFR A6h, reset value 00h) WDRST register definition TCON: Timer control register (SFR 88h, reset value 00h) TCON register definition TMOD: Timer mode register (SFR 89h, reset value 00h) TMOD register definition T2CON: Timer control register (SFR C8h, reset value 00h) T2CON register definition Timer/counter operating modes Commonly used baud rates generated from timer2 (T2CON 34h) UART operating modes SCON0: serial port UART0 control register (SFR 98h, reset value 00h) SCON0 register definition SCON1: serial port UART1 control register (SFR D8h, reset value 00h) SCON1 register definition Commonly used baud rates generated from timer IRDACON register definition (SFR CEh, reset value 0Fh). IRDACON register definition Baud rate selection register (SFR xxh, reset value xxh). Baud rate UART#1 IrDA interface Recommended CDIV[4:0] values generate SIRClk (default CDIV[4:0] 0Fh, decimal) Serial control register S1CON (SFR DCh, reset value 00h) S1CON register definition Selection frequency Master mode based fOSC examples S1STA: interface status register (SFR DDh, reset value 00h) S1STA register definition S1DAT: data shift register (SFR DEh, reset value 00h) S1DAT register definition S1ADR: address register (SFR DFh, reset value 00h). S1ADR register definition. S1SETUP: Start condition sample setup register (SFR DBh, reset value 00h) S1SETUP register definition Number samples taken after 1-to-0 transition (Start condition) Start condition hold time S1SETUP examples various speeds oscillator frequencies SPICON0: control register (SFR D6h, reset value 00h). SPICON0 register definition SPICON1: interface control register (SFR D7h, reset value 00h) SPICON1 register definition SPICLKD: prescaler (clock divider) register (SFR D2h, reset value 04h) SPICLKD register definition SPISTAT: interface status register (SFR D3h, reset value 02h) SPISTAT register definition Types packet
13/300
List tables Table Table Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149.
UPSD3422, UPSD3433, UPSD3434, UPSD3454
UPSD34xx supported endpoints. UPSD34xx register map. device address register (UADDR 0E2h, reset value 00h) UADDR register definition Pairing control register (UPAIR 0E3h, reset value 00h) UPAIR register definition global interrupt enable register (UIE0 0E4h, reset value 00h) UIE0 register definition. FIFO interrupt enable register (UIE1 0E5h, reset value 00h) UIE1 register definition. FIFO interrupt enable register (UIE2 0E6h, reset value 00h) UIE2 register definition. FIFO interrupt enable register (UIE3 0E7h, reset value 00h) UIE3 register definition. global interrupt flag register (UIF0 0E8h, reset value 00h). UIF0 register definition FIFO interrupt flag (UIF1 0E9h, reset value 00h). UIF1 register definition FIFO interrupt flag (UIF2 0EAh, reset value 00h) UIF2 register definition FIFO interrupt flag (UIF3 0EBh, reset value 00h) UIF3 register definition control register (UCTL 0ECh, reset value 00h) UCTL register definition endpoint0 status (USTA 0EDh, reset value 00h) USTA register definition endpoint select register (USEL 0EFh, reset value 00h) USEL register definition endpoint control register (UCON 0F1h, reset value 08h) UCON register definition FIFO valid size (USIZE 0F2h, reset value 00h) USIZE register definition FIFO base address high register (UBASEH 0F3h, reset value 00h) UBASEH register definition FIFO base address register (UBASEL 0F4h, reset value 00h) UBASEL register definition setup command index register (USCI 0F5h, reset value 00h) USCI register definition setup command value register (USCV 0F6h, reset value 00h) USCV register definition. ACON register (SFR 97h, reset value 00h) ACON register definition ADCPS register details (SFR 94h, Reset Value 00h) ADAT0 register (SFR 95h, reset value 00h) ADAT1 register (SFR 96h, reset value 00h) PCA0 PCA1 registers CCON2 register definition (SFR 0FBh, reset value 10h) CCON2 register definition CCON3 register definition (SFR 0FCh, reset value 10h) CCON3 register definition PCA0 control register PCACON0 (SFR 0A4h, reset value 00h). PCA0 register definition
14/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table 150. Table 151. Table 152. Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159. Table 160. Table 161. Table 162. Table 163. Table 164. Table 165. Table 166. Table 167. Table 168. Table 169. Table 170. Table 171. Table 172. Table 173. Table 174. Table 175. Table 176. Table 177. Table 178. Table 179. Table 180. Table 181. Table 182. Table 183. Table 184. Table 185. Table 186. Table 187. Table 188. Table 189. Table 190. Table 191. Table 192. Table 193. Table 194. Table 195. Table 196. Table 197. Table 198. Table 199. Table 200. Table 201.
List tables
PCA1 control register PCACON1 (SFR 0BCh, reset value 00h) PCA1 register definition status register PCASTA (SFR 0A5h, reset value 00h) PCASTA register definition TCMMODE0 TCMMODE5 registers, reset value 00h). TCMMODE0 TCMMODE5 register definition TCMMODE register configurations UPSD34xx memory configuration. General pins module statement example generated from PSDsoft express memory register (address csiop offset E2h) Data width different cycles CSIOP registers their offsets hexadecimal) Flash memory instruction sequences Flash memory status definition Main Flash memory protection register definition (address csiop offset C0h) Secondary Flash memory protection/security register definition (csiop offset C2h) DPLD GPLD inputs port data assignments Output macrocell MCELLAB (address csiop offset 20h) Output macrocell MCELLBC (address csiop offset 21h) Output macrocell MCELLAB mask register (address csiop offset 22h) Output macrocell MCELLBC mask register (address csiop offset 23h) Input macrocell port (address csiop offset 0Ah) Input macrocell port (address csiop offset 0Bh) Input macrocell port (address csiop offset 18h) Port operating modes Port configuration setting requirements mode port data register (address csiop offset 00h) mode port data register (address csiop offset 01h) mode port data register (address csiop offset 10h) mode port Data register (address csiop offset 11h) mode port data register (address csiop offset 04h) mode port data register (address csiop offset 05h) mode port data register (address csiop offset 12h) mode port data register (address csiop offset 13h) mode port direction register (address csiop offset 06h) mode port direction register (address csiop offset 07h) mode port direction register (address csiop offset 14h) mode port direction register (address csiop offset 15h) Latched address output, port contro register(address csiop offset 02h)l Latched address output, port contro register (address csiop offset 03h)l Port drive select register (address csiop offset 08h) Port drive select register (address csiop offset 09h) Port drive select register (address csiop offset 16h) Port drive select register (address csiop offset 17h) Port enable register (address csiop offset 0Ch) Port enable register (address csiop offset 0Dh) Port enable register (address csiop offset 1Ah) Port enable register (address csiop offset 1Bh) Power management mode register PMMR0 (address csiop offset B0h) Power management mode register PMMR2 (address csiop offset B4h)
15/300
List tables Table 202. Table 203. Table 204. Table 205. Table 206. Table 207. Table 208. Table 209. Table 210. Table 211. Table 212. Table 213. Table 214. Table 215. Table 216. Table 217. Table 218. Table 219. Table 220. Table 221. Table 222. Table 223. Table 224. Table 225. Table 226. Table 227. Table 228. Table 229. Table 230. Table 231. Table 232. Table 233. Table 234. Table 235. Table 236. Table 237. Table 238. Table 239. Table 240. Table 241.
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Power management mode register PMMR3 (address csiop offset C7h) Function status during power-up reset, warm reset, power-down mode module example, typ. power calculation (turbo mode off) Absolute maximum ratings Operating conditions devices) Operating conditions (3.3 devices) signal letters timing signal behavior symbols timing Major parameters module characteristics. module characteristics (with VDD) module characteristics (with VDD). External READ cycle characteristics device) values External WRITE cycle characteristics device) External clock drive. analog specification transceiver specification CPLD combinatorial timing module) CPLD combinatorial timing module) CPLD macrocell synchronous clock mode timing module). CPLD macrocell synchronous clock mode timing module). CPLD macrocell asynchronous clock mode timing module). CPLD macrocell asynchronous clock mode timing module). Input macrocell timing module) Input macrocell timing module) Program, WRITE erase times modules). Port peripheral data mode READ timing module) Port peripheral data mode READ timing module) Port peripheral data mode WRITE timing module) Port peripheral data mode WRITE timing module) Supervisor reset LVD. timing module) timing module) capacitance LQFP52 52-lead plastic thin, quad, flat package mechanical data LQFP80 80-lead plastic thin, quad, flat package mechanical data Ordering information scheme Order codes Document revision history
16/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
List figures
List figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Block diagram LQFP52 connections LQFP80 connections Functional modules. UPSD34xx memories Comparison UPSD34xx with standard 8032 performance Instruction pre-fetch queue branch cache operation multi-cycle instructions UPSD34xx multi-cycle instructions compared standard 8032 8032 registers Program status word (PSW) register Enabling polling interrupts Clock generation logic Oscillator clock connections module port function routing cell block diagram port cell block diagram port cell block diagram port Connecting external devices using ports address AD[15:0] Connecting external devices using port external latch address AD[15:0] PSEN cycle MCU_CLK Supervisor reset generation Watchdog counter. Timer/counter mode 13-bit counter. Timer/counter mode 8-bit Auto-reload Timer/counter mode 8-bit counters Timer capture mode Timer auto-reload mode. Timer baud rate generator mode UART mode block diagram. UART mode timing diagram UART mode block diagram. UART mode timing diagram UART mode block diagram. UART mode timing diagram UART mode block diagram. UART mode timing diagram IrDA interface Pulse shaping IrDA interface Typical configuration Data transfer interface SIOE block diagram device connection examples full-duplex data exchange receive operation example transmit operation example interface, master mode only. module block diagram
17/300
List figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 100.
UPSD3422, UPSD3433, UPSD3434, UPSD3454
packets transfer example bulk transfers Interrupt transfer Control transfer FIFOs with pairing FIFO pairing example (1/2 paired paired). Typical self powered example 10-bit PCA0 block diagram Timer mode. mode (x8), fixed frequency mode (x8) programmable frequency. module block diagram Memory page register Typical system memory PSDsoft express memory mapping Mapping: split second Flash half. Mapping: Flash code space Mapping: small code data module memory priority register control memories register example corresponding memory example. Data polling flowchart Data toggle flowchart DPLD GPLD DPLD logic array. GPLD: OMC, IMC, port (typical pin, port Detail single allocator Detail single Detail single port (typical ports Simple logic example declarations PSDsoft express simple example Using design assistant PSDsoft Express simple example. Peripheral mode Port structure Port structure Port structure. Port structure. Automatic power-down (APD) unit Power-down mode flowchart JTAG chain UPSD34xx package Recommended 4-pin JTAG connections Recommended 6-pin JTAG connections Recommended JTAG connector Example chaining UPSD34xx devices frequency consumption range) frequency consumption range) Switching waveforms External READ cycle (80-pin device only) External WRITE cycle (80-pin device only). Input output disable enable.
18/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Figure 112. Figure 113. Figure 114.
List figures
Synchronous Clock mode timing Asynchronous RESET Preset. Asynchronous clock mode timing (product term clock). Input macrocell timing (product term clock) Peripheral READ timing Peripheral WRITE timing timing module measurement waveform module float waveform External clock cycle module measurement waveform module measurement load circuit LQFP52 52-lead plastic thin, quad, flat package outline LQFP80 80-lead plastic thin, quad, flat package outline
19/300
Description
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Description
Turbo Plus UPSD34xx Series combines powerful 8051-based microcontroller with flexible memory structure, programmable logic, rich peripheral form ideal embedded controller. core fast 4-cycle 8032 with 4-byte instruction prefetch queue (PFQ) 4-entry fully associative branching cache (BC). connected 16-bit internal instruction path maximize performance, enabling loops code smaller localities execute extremely fast. 16-bit wide instruction path Turbo Plus Series allows double-byte instructions fetched from memory single memory cycle. This keeps average performance near peak performance (peak performance Turbo Plus UPSD34xx MIPS single-byte instructions, average performance will approximately MIPS single- multi-byte instructions). (full speed, 12Mbps) included, providing endpoints, each with 64-byte FIFO maintain high data throughput. Endpoint (control endpoint) uses endpoints directions, remaining eight endpoints allocated either type transfers: Bulk Interrupt. Code development easily managed without hardware in-circuit emulator using serial JTAG debug interface. JTAG also used in-system programming (ISP) little seconds, perfect manufacturing development. 8032 core coupled programmable system device (PSD) architecture optimize 8032 memory structure, offering independent banks Flash memory that placed virtually address within 8032 program data address space, easily paged beyond Kbytes using onchip programmable decode logic. Dual Flash memory banks provide robust solution remote product updates field through in-application programming (IAP). Dual Flash banks also support EEPROM emulation, eliminating need external EEPROM chips. General-purpose programmable logic (PLD) included build endless variety gluelogic, saving external logic devices. configured using software development tool, PSDsoft Express, available from www.st.com/psm, charge. UPSD34xx also includes supervisor functions such programmable watchdog timer low-voltage reset.
Note:
list known limitations UPSD34xx devices, please refer Section Important notes.
20/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure Block diagram
uPSD34xx
16-bit Timer/ Counters External Interrupts Turbo 8032 Core
Description
P3.0:7
Flash memory: Kbyte, Kbyte Kbyte Programmable decode page logic Flash memory: Kbyte SRAM: Kbyte, Kbyte Kbyte
UART0 GPIO, Port (80-pin only) GPIO, Port Generalpurpose programmable logic, macrocells GPIO, Port GPIO, Port GPIO, Port
PA0:7 PB0:7 PD1:2
10-bit Optional IrDA UART1 Encoder/Decoder
SYSTEM
P1.0:7
GPIO, Port
PC0:7
JTAG 8032 Address/Data/Control (80-pin device only) Supervisor: Watchdog low-voltage reset VCC, VDD, GND, Reset, Crystal
16-bit PWM, CAPCOM, timer
P4.0:7 USB+, USB-
GPIO, Port
Dedicated pins
v2.0, Full Speed
FIFOs
AI09695c
21/300
descriptions
UPSD3422, UPSD3433, UPSD3434, UPSD3454
descriptions
Figure LQFP52 connections
P1.6/SPITXD(2)/ADC6 P1.7/SPISEL(2)/ADC7
AVCC/AVREF(3)
RESET_IN
PD1/CLKIN JTAG JTAG DEBUG USB+
P1.5/SPIRXD(2)/ADC5 P1.4/SPICLK(2)/ADC4 P1.3/TXD1(IrDA)(2)/ADC3 P1.2/RXD1(IrDA)(2)/ADC2 P1.1/T2X(2)/ADC1 P1.0/T2(2)/ADC0 VDD(1) XTAL2 XTAL1 P3.7/SCL P3.6/SDA P3.5/C1 P3.4/C0
USB- JTAG JTAG
SPISEL(2)/PCACLK1/P4.7
SPITXD(2)/TCM5/P4.6
TXD1(IrDA)(2)/PCACLK0/P4.3
RXD1(IrDA)(2)/TCM2/P4.2
T2X(2)/TCM1/P4.1
T2(2)/TCM0/P4.0
RXD0/P3.0
TXD0/P3.1
EXTINT0/TG0/P3.2
SPIRXD(2)/TCM4/P4.5
SPICLK(2)/TCM3/P4.4
EXTINT1/TG1/P3.3
AI09696c
applications, must connected source. applications, must connected source. These signals used different ports (Port Port flexibility. Default Port1. AVREF AVCC shared 52-pin package only. channels must AVREF 52-pin package.
22/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure LQFP80 connections
P1.6/SPITXD(3)/ADC6 P1.7/SPISEL(3)/ADC7 P3.2/EXINT0/TG0
descriptions
P3.0/RXD0
P3.1/TXD0
RESET_IN
AVREF
PSEN
AVCC
PD2/CSI P3.3/TG1/EXINT1 PD1/CLKIN JTAG JTAG DEBUG PC4/TERR USB+(1) VDD(2) USB- PC3/TSTAT JTAG SPISEL(2)/PCACLK1/P4.7 SPITXD(2)/TCM5/P4.6 JTAG
P1.5/SPIRXD(3)/ADC5 P1.4/SPICLK(3)/ADC4 P1.3/TXD1(IrDA)(3)/ADC3 P1.2/RXD1(IrDA)(3)/ADC2 P1.1/T2X(3)/ADC1 P1.0/T2(3)/ADC0 VDD(1) XTAL2 XTAL1 P3.7/SCL P3.6/SDA P3.5/C1
SPIRXD(2)/TCM4/P4.5
SPICLK(2)/TCM3/P4.4
TXD1(IrDA)(2)/PCACLK0/P4.3
RXD1(IrDA)(2)/TCM2/P4.2
T2X(2)/TCM1/P4.1
T2(2)/TCM0/P4.0
P3.4/C0
AI09697c
connected USB+ needs pull-up resistor. applications, must connected source. applications, must connected source. These signals used different ports (Port Port flexibility. Default Port1.
23/300
descriptions Table
Port
UPSD3422, UPSD3433, UPSD3434, UPSD3454
definitions
Signal name 80-pin 52-pin In/out No.(1) Function Basic External multiplexed address/data A0/D0 Multiplexed address/data A1/D1 Multiplexed address/data A2/D2 Multiplexed address/data A3/D3 Multiplexed address/data A4/D4 Multiplexed address/data A5/D5 Multiplexed address/data A6/D6 Multiplexed address/data A7/D7 General port General port General port General port General port General port General port General port General port Timer Count input Channel (T2) input (ADC0) Timer Trigger input Channel (T2X) input (ADC1) UART1 IrDA Receive (RxD1) UART IrDA Transmit (TxD1) Clock (SPICLK) Receive (SPIRxD) Transmit (SPITxD) Slave Select (SPISEL) UART0 Receive (RxD0) Channel input (ADC2) Channel input (ADC3) Channel input (ADC4) Channel input (ADC5) Channel input (ADC6) Channel input (ADC7) Alternate Alternate
MCUAD0
MCUAD1
MCUAD2
MCUAD3
MCUAD4
MCUAD5
MCUAD6
MCUAD7
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0
ADC0 ADC1 RxD1 ADC2 TXD1 ADC3 SPICLK ADC4 SPIRxD ADC5 SPITXD ADC6 SPISEL ADC7 RxD0
24/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table
Port
descriptions
definitions (continued)
Signal name TXD0 EXINT0 80-pin 52-pin In/out No.(1) Function Basic General port Alternate UART0 Transmit (TxD0) Alternate
P3.1
P3.2
Interrupt input General port (EXTINT0)/Timer gate control (TG0) Interrupt input General port (EXTINT1)/Timer gate control (TG1) General port Counter input (C0) General port Counter input (C1) General port General port General port serial data (I2CSDA) clock (I2CSCL) Program counter Timer count input array0 PCA0-TCM0 (T2) Timer trigger input (T2X) UART1 IrDA Receive (RxD1) UART1 IrDA Transmit (TxD1)
P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7
INT1 TCM0 TCM1 RXD1 TCM2 TXD1 PCACLK0 SPICLK TCM3 SPIRXD TCM4 SPITXD SPISEL PCACLK1
General port PCA0-TCM1 General port PCA0-TCM2 General port PCACLK0 General port
Program counter clock Array1 PCA1-TCM3 (SPICLK) Receive (SPIRxD) Transmit (SPITxD) Slave Select (SPISEL)
General port PCA1-TCM4 General port PCA1-TCM5 General port PCACLK1 Reference Voltage input ADC. Connect AVREF used. READ signal, external WRITE signal, external PSEN signal, external
AVREF
PSEN
25/300
descriptions Table
Port
UPSD3422, UPSD3433, UPSD3434, UPSD3454
definitions (continued)
Signal name 80-pin 52-pin In/out No.(1) TSTAT TERR Function Basic Address Latch signal, external Active reset input Oscillator input system clock Oscillator output system clock debug unit General port General port General port General port General port General port General port General port General port General port General port General port General port General port General port General port JTAG (TMS) JTAG (TCK) General port General port General port JTAG (TDI) JTAG (TDO) Optional JTAG Status (TSTAT) Optional JTAG Status (TERR) Macrocell output, input PLD, Macrocell output, input PLD, Macrocell output, input Port pins support: Macrocell outputs, inputs, Latched address (A0-A7 A8-A15) Port pins support: Macrocell outputs, inputs, Latched address (A0-A7), Peripheral mode Alternate Alternate
RESET_IN XTAL1 XTAL2 DEBUG JTAGTMS JTAGTCK JTAGTDI JTAGTDO
26/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table
Port
descriptions
definitions (continued)
Signal name 80-pin 52-pin In/out No.(1) Function Basic General port Alternate Alternate PLD, Macrocell output, input Clock input Chip select module
CLKIN
General port
General port pin; pull-up resistor required. module. connect AVCC used. Analog Input module module
USB+ USB-
V-VCC
AVCC
Signal available 52-pin package.
27/300
Hardware description
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Hardware description
UPSD34xx modular architecture built from stacked process. There dice, designated "MCU module" this document, other designated "PSD module" (see Figure page 29). cases, module operates with tolerant I/O. module either die, depending UPSD34xx device described below. module consists fast 8032 core, that operates with clocks instruction cycle, many peripheral system supervisor functions. module provides 8032 with multiple memories (two Flash SRAM) program data, programmable logic address decoding general-purpose logic, additional I/O. module communicates with module through internal address data busses (AD0 AD15) control signals (RD, PSEN, ALE, RESET). There slightly different characteristics each module. I/Os module designated Ports I/Os module designated Ports UPSD34xx devices, module stacked with module. this case, UPSD34xx device must supplied with module module. Ports module ports with tolerance devices (they directly driven external devices they directly drive external devices while producing 2.4V max). Ports module true ports. UPSD34xxV devices, module stacked with module. this case, UPSD34xx device needs supplied with single voltage source both VDD. pins Ports tolerant connected external peripherals devices desired. Ports module ports, which tolerant external devices. Refer Table port type voltage source requirements. 80-pin UPSD34xx devices provide access 8032 address, data, control signals external pins connect external peripheral memory devices. 52-pin UPSD34xx devices provide access 8032 system bus. non-volatile memory configuration portions UPSD34xx device programmed through JTAG interface special programming voltage needed. This same JTAG port also used debugging 8032 core runtime providing breakpoint, single-step, display, trace features. non-volatile security programmed block access JTAG interface security. security defeated only erasing entire device, leaving device blank ready again. Table
Device type UPSD34xx UPSD34xxV
Port type voltage source combinations
module module Ports module (Ports tolerant) (Ports tolerant) Ports module tolerant
28/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure Functional modules
Port UART0, Intr, Timers Port imer, ADC, Port PCA, PWM, UART1 Port
Hardware description
pins
Module
Port Port urbo 8032 Core Dual UARTs Interrupt imer Counters Byte SRAM
Clock Unit
10-bit
Counters
Unit
Transceiver
Pins 3.3V
Dedicated Memory Interface Prefetch, Branch Cache 8-Bit/16-Bit Die-to-Die Enhanced Interface
Page Register
8032 Internal
Ext. Reset Input
DEBUG
Internal Reset
Reset Logic
Reset
Main Flash
Decode
Secondary Flash
Reset SRAM
Module
Internal
CPLD MACROCELLS
Pins 3.3V
uPSD34xx
Port JTAG GPIO
Port A,B,C GPIO
Port GPIO
AI10409
29/300
Memory organization
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Memory organization
8032 core views memory module "internal" memory views memory module "external" memory, Figure Internal memory module consists DATA, IDATA, SFRs. These standard 8032 memories reside bytes SRAM located fixed address space starting address 0000h. External memory module consists four types: main Flash Kbyte, Kbyte, Kbyte), smaller secondary Flash Kbyte), SRAM Kbyte, Kbyte Kbyte), block module control registers called csiop (256 bytes). These external memories reside programmable address ranges, specified using software tool PSDsoft Express. module section this document more details these memories. External memory accessed 8032 separate Kbyte address spaces. address space program memory other address space data memory. Program memory accessed using 8032 signal, PSEN. Data memory accessed using 8032 signals, 8032 needs access more than Kbytes external program data memory, must paging banking) techniques provided page register module.
Note:
When referencing program data memory spaces, nothing with 8032 internal SRAM areas DATA, IDATA, module. Program data memory spaces only relate external memories module. External memory module overlap internal SRAM memory module same physical address range (starting 0000h) without interference because 8032 core does assert signals when accessing internal SRAM. Figure UPSD34xx memories
Internal SRAM module External memory module
Fixed addresses Indirect addressing
Main Flash Bytes SRAM bytes
External memories placed virtually address using software tool PSDsoft Express. SRAM Flash memories placed 8032 Program Space Data Space using PSDsoft Express. memory 8032 data space XDATA.
IDATA
bytes
Direct addressing
Bytes
Secondary Flash
SRAM
AI10410c
DATA
Direct indirect addressing
30/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Memory organization
4.1.1
Internal memory (MCU module, standard 8032 memory: DATA, IDATA, SFR)
DATA memory
first bytes internal SRAM ranging from address 0000h 007Fh called DATA, which accessed using 8032 direct indirect addressing schemes typically used store variables stack. Four register banks, each with registers R7), occupy addresses 0000h 001Fh. Only these four banks enabled time. next locations 0020h 002Fh contain directly addressable locations that used software flags. SRAM locations 0030h above used variables stack.
4.1.2
IDATA memory
next bytes internal SRAM named IDATA range from address 0080h 00FFh. IDATA accessed only through 8032 indirect addressing typically used hold stack well data variables. stack reside both DATA IDATA memories reach size limited only available space combined bytes these memories (since stack accesses always done using indirect addressing, boundary between DATA IDATA does exist with regard stack).
4.1.3
memory
Special function registers (Table page occupy separate physical memory, they logically overlap same bytes IDATA, ranging from address 0080h 00FFh. SFRs accessed only using direct addressing. There active registers used many functions: changing operating mode 8032 core, controlling 8032 peripherals, controlling I/O, managing interrupt functions. remaining unused SFRs reserved should accessed. SFRs both byte- bit-addressable. Bit-addressable SFRs those whose address ends hex.
External memory (PSD module: program memory, data memory)
module four memories: main Flash, secondary Flash, SRAM, csiop. MODULE section more detailed information these memories. Memory mapping module implemented with Decode (DPLD) optionally page register. user specifies decode equations individual segments each memories using software tool PSDsoft Express. This very easy pointand-click process allowing total flexibility mapping memories. Additionally, each memories placed various combinations 8032 program address space 8032 data address space using software tool PSDsoft Express.
31/300
Memory organization
UPSD3422, UPSD3433, UPSD3434, UPSD3454
4.2.1
Program memory
External program memory addressed 8032 using 16-bit program counter (PC) accessed with 8032 signal, PSEN. Program memory present address program space between 0000h FFFFh. After power-up reset, 8032 begins program execution from location 0000h where reset vector stored, causing jump initialization routine firmware. address 0003h, just following reset vector interrupt service locations. Each interrupt assigned fixed interrupt service location program memory. interrupt causes 8032 jump that service location, where commences execution service routine. External Interrupt (EXINT0), example, assigned service location 0003h. EXINT0 going used, service routine must begin location 0003h. Interrupt service locations spaced 8-byte intervals: 0003h EXINT0, 000Bh Timer 0013h EXINT1, forth. interrupt service routine short enough, reside entirely within 8-byte interval. Longer service routines jump instruction somewhere else program memory.
4.2.2
Data memory
External data referred XDATA addressed 8032 using Indirect Addressing 16-bit data pointer register (DPTR) accessed 8032 signals, XDATA present address data space between 0000h FFFFh.
Note:
UPSD34xx dual data pointers (source destination) making XDATA transfers much more efficient.
4.2.3
Memory placement
module architecture allows placement external memories into different combinations program memory data memory spaces. This means main Flash, secondary Flash, SRAM viewed 8032 various combinations program memory data memory defined PSDsoft Express. example this flexibility, applications that require great deal Flash memory data space (large lookup tables extended data recording), larger main Flash memory placed data space smaller secondary Flash memory placed program space. opposite realized different application more Flash memory needed code less Flash memory data. default, SRAM csiop memories module must always reside data memory space they treated 8032 XDATA. main Flash secondary Flash memories reside program space, data space, both. These memory placement choices specified PSDsoft Express programmed into non-volatile sections UPSD34xx, active power-up after reset. possible override these initial settings during runtime In-Application Programming (IAP). Standard 8032 architecture cannot write program memory space prevent accidental corruption firmware. However, this becomes obstacle typical 8032 systems when remote update firmware Flash memory required using IAP. module provides solution remote updates allowing 8032 firmware temporarily "reclassify" Flash memory reside data space during remote update, then returning Flash memory back program space when finished. register (Table page 203) module section this document more details.
32/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
8032 core performance enhancements
8032 core performance enhancements
Before describing performance features UPSD34xx, first look standard 8032 architecture. clock source 8032 creates basic unit timing called machine-cycle, which period clocks standard 8032 MCUs. instruction traditional 8032 MCUs consists byte instructions that execute different combinations machine-cycles. example, there one-byte instructions that execute machine-cycle clocks), one-byte instructions that execute four machine-cycles clocks), two-byte, two-cycle instructions clocks), addition, standard 8032 architecture will fetch bytes from program memory almost every machine-cycle, regardless needs them (dummy fetch). This means onebyte, one-cycle instructions, second byte ignored. These one-byte, one-cycle instructions account half 8032's instructions (126 opcodes). There inefficiencies wasted cycles idle times that eliminated. UPSD34xx 8032 core offers increased performance number ways, while keeping exact same instruction standard 8032 (all opcodes, number bytes instruction, native number machine-cycles instruction identical original 8032). first performance boosted reducing machine-cycle period just clocks compared clocks standard 8032. This shortened machine-cycle improves instruction rate one- two-byte, one-cycle instructions factor three (Figure page compared standard 8051 architectures, significantly improves performance multiple-cycle instruction types. example Figure page shows continuous execution stream one- twobyte, one-cycle instructions. UPSD34xx will yield MIPS peak performance this case while operating clock rate. typical application however, effective performance will lower since programs only one-cycle instructions, special techniques implemented UPSD34xx keep effective MIPS rate close possible peak MIPS rate times. This accomplished with instruction prefetch queue (PFQ), branch cache (BC), 16-bit program memory shown Figure page Figure Comparison UPSD34xx with standard 8032 performance
2-byte, 1-cycle Instructions Instruction Turbo uPSD34xx
Execute instruction pre-fetch next instruction
Instruction
Execute instruction pre-fetch next instruction
Instruction
Execute instruction pre-fetch next instruction
clocks (one machine cycle)
machine cycle
machine cycle
Clock
clocks (one machine cycle)
Instruction Standard 8032
Fetch byte instruction Execute instruction fetch second dummy byte
Dummy byte Ignored (wasted access)
Turbo uPSD34xx executes instructions same amount time that standard 8032 executes only Instruction
AI10411b
33/300
8032 core performance enhancements Figure
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Instruction pre-fetch queue branch cache
Branch code Branch Cache (BC) Branch code Compare
Branch Branch code code Branch Branch code code Branch code Branch code
Load branch address match
Instruction byte 16-bit program memory module
Current branch address Instruction byte
Instruction byte
Address bytes instruction Wait
8032
Address
Wait
Instruction pre-fetch queue (PFQ)
AI10431b
Pre-fetch queue (PFQ) branch cache (BC)
always working minimize idle time inherent 8032 architecture, eliminate wasted memory fetches, maximize memory bandwidth MCU. does this running asynchronously relation MCU, looking ahead pre-fetch bytes (word) code from program memory during idle periods. Only necessary word will fetched dummy fetches like standard 8032). will queue four code bytes advance execution, which significantly optimizes sequential program performance. However, when program execution becomes non-sequential (program branch), typical pre-fetch queue will empty itself reload code, causing stall. Turbo UPSD34xx diminishes this problem using Branch Cache with PFQ. four-way, fully associative cache, meaning that when program branch occurs, branch destination address compared simultaneously with four recent previous branch destinations stored Each four cache entries contain four bytes code related branch. there match), then four code bytes matching program branch transferred immediately simultaneously from PFQ, execution that branch continues with minimal delay. This greatly reduces chance that will stall from empty PFQ, improves performance embedded control systems where quite common branch loop relatively small code localities. default, enabled after power-up reset. 8032 disable runtime desired writing specific (BUSCON). memory module operates with variable wait states depending value specified named BUSCON. example, UPSD34xx device operating crystal frequency requires four memory wait states (equal four clocks). this example, once word code, wait states become transparent full MIPS achieved when program stream consists sequential one- two-byte, machine-cycle instructions shown Figure page (transparent because machine-cycle four clocks which equals memory pre-fetch wait time that also
34/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
8032 core performance enhancements
four clocks). also important understand operation multi-cycle instructions.
example, multi-cycle instructions
look string two-byte, two-cycle instructions Figure page There three instructions executed sequentially this example, instructions Each time divisions figure machine-cycle four clocks, there phases reference this discussion. Each instruction pre-fetched into advance execution MCU. Prior Phase pre-fetched instruction bytes Instruction During Phase one, both bytes loaded into execution unit. Also Phase pre-fetching Instruction (bytes from program memory. Phase processing Instruction internally while pre-fetching Instruction Phase both bytes instruction loaded into execution unit begins pre-fetch bytes next instruction. Phase Instruction processed. UPSD34xx instructions exact scale standard 8032 instructions with regard number cycles instruction. Figure page shows equivalent instruction sequence from example above standard 8032 comparison.
Aggregate performance
stream two-byte, two-cycle instructions Figure page running MHz, UPSD34xx will yield MIPs. stream one- two-byte, one-cycle instructions Figure page same yield MIPs. Effective performance will depend number things: clock frequency; mixture instructions types (bytes cycles) application; amount time empty stalls (mix instruction types misses Branch Cache); operating voltage. UPSD34xx device operates with four memory wait states, device operates with five memory wait states yielding MIPS peak compared MIPs peak device. same number wait states will apply both program fetches data READ/WRITEs unless otherwise specified named BUSCON. general, aggregate performance increase expected over standard 8032 application running same clock frequency. Figure operation multi-cycle instructions
Three 2-byte, 2-cycle Instructions uPSD34xx
Pre-Fetch Inst Pre-Fetch Inst Pre-Fetch next Inst
Inst Byte Inst Byte Inst Byte
Next Inst
Continue Pre-Fetch
4-clock Macine Cycle
Phase Phase Process Phase Phase Process Phase Phase Process Next Inst
Execution
Previous Instruction
Instruction
Instruction
Instruction AI10432
35/300
8032 core performance enhancements Figure
UPSD3422, UPSD3433, UPSD3434, UPSD3454
UPSD34xx multi-cycle instructions compared standard 8032
Three 2-byte, 2-cycle Instructions, uPSD34xx Standard 8032 Clocks Total clocks cycle)
uPSD34xx
Inst
Inst
Inst
Cycle Clocks clocks cycle) 8032 Byte Byte Process Inst Cycle
AI10412
Byte
Byte
Process Inst
Byte
Byte
Process Inst
36/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
module description
module description
This following sections provide detailed description module system functions peripherals, including:
8032 registers Special function registers 8032 addressing modes UPSD34xx instruction summary Dual data pointers Debug unit Interrupt system clock generation Power saving modes Oscillator external components ports interface Supervisory functions Standard 8032 timer/counters Serial UART interfaces IrDA interface interface interface Analog digital converter Programmable counter array (PCA) interface
37/300
8032 registers
UPSD3422, UPSD3433, UPSD3434, UPSD3454
8032 registers
UPSD34xx following 8032 core registers, also shown Figure Figure 8032 registers
R0-R7 DPTR(DPH)
AI06636
Accumulator Register Stack Pointer Program Counter Program Status Word General Purpose Register (Bank0-3) Data Pointer Register
DPTR(DPL)
Stack pointer (SP)
8-bit register which holds current location stack. incremented before value pushed onto stack, decremented after value popped stack. initialized after reset. This causes stack begin location (top stack). avoid overlapping conflicts, user must initialize stack four banks registers used, well stack 8032 memory locations used.
Data pointer (DPTR)
DPTR 16-bit register consisting 8-bit registers, DPH. DPTR register used base register create address indirect jumps, table look-up operations, external data transfers (XDATA). When used addressing, DPTR register used general purpose 16-bit data register. Very frequently, DPTR register used access XDATA using external direct addressing mode. UPSD34xx special registers (DPTC, DPTM) control secondary DPTR register speed memory-to-memory XDATA transfers. Having dual DPTR registers allows rapid switching between source destination addresses (see details Section Dual data pointers page 57).
Program counter (PC)
16-bit register consisting 8-bit registers, PCH. This counter indicates address next instruction program memory fetched executed. reset forces location 0000h, which where reset jump vector stored.
38/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
8032 registers
Accumulator (ACC)
This 8-bit general purpose register which holds source operand receives result arithmetic operations. register also source destination logic data movement operations. instructions, combined with register hold 16-bit operands. referred instruction set.
register
register general purpose 8-bit register temporary data storage also used 16-bit register when concatenated with register with instructions.
General purpose registers
There four banks eight general purpose 8-bit registers R7), only bank eight registers active given time depending setting word (described next). generally used assist manipulating values moving data from memory location another. These register banks physically reside first locations 8032 internal DATA SRAM, starting address 00h. reset, only first bank eight registers active (addresses 07h), stack begins address 08h.
Program status word (PSW)
8-bit register which stores several important bits, flags, that cleared many 8032 instructions, reflecting current state core. Figure page shows individual flags.
7.7.1
Carry flag (CY)
This flag when last arithmetic operation that executed results carry (addition) borrow (subtraction). cleared other arithmetic operations. flag also affected Shift Rotate Instructions.
7.7.2
Auxiliary carry flag (AC)
This flag when last arithmetic operation that executed results carry into (addition) borrow from (subtraction) high-order nibble. cleared other arithmetic operations.
7.7.3
General purpose flag (F0)
This bit-addressable, general-purpose flag under software control.
7.7.4
Register bank select flags (RS1, RS0)
These bits select which bank eight registers used during register accesses (see Table
39/300
8032 registers
UPSD3422, UPSD3433, UPSD3434, UPSD3454
7.7.5
Overflow flag (OV)
flag when: ADD, ADDC, SUBB instruction causes sign change; instruction results overflow (result greater than 255); instruction causes divideby-zero condition. flag cleared ADD, ADDC, SUBB, MUL, instructions other cases. CLRV instruction will clear flag time.
7.7.6
Parity flag
flag eight bits Accumulator odd, cleared even. Table
Register bank select addresses
Register bank 8032 internal data address
Figure Program status word (PSW) register
Carry Flag Auxillary Carry Flag General Purpose Flag Register Bank Select Flags select Bank0-3)
AI06639
Reset Value Parity Flag assigned Overflow Flag
40/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Special function registers (SFR)
Special function registers (SFR)
group registers designated special function register (SFR) shown Table page SFRs control operating modes core also control peripheral interfaces pins module. SFRs accessed only using Direct Addressing method within address range from internal 8032 SRAM. Sixteen addresses address space both byte- bit-addressable. bitaddressable SFRs noted Table possible addresses occupied. remaining unoccupied addresses (designated "RESERVED" Table should written. Reading unoccupied locations will return undefined value.
Note:
There separate control registers module, designated csiop, they described Section module page 191. pins, PLD, other functions module controlled SFRs. SFRs categorized follows:
core registers: PSW, DPTL, DPTH, DPTC, DPMCU module Port registers: P1SFS0, P1SFS1, P3SFS, P4SFS0, P4SFS1 Standard 8032 Timer registers TCON, TMOD, T2CON, TH0, TH1, TH2, TL0, TL1, TL2, RCAP2L, RCAP2H Standard Serial Interfaces (UART) SCON0, SBUF0, SCON1, SBUF1 Power, clock, timing registers PCON, CCON0, CCON1, BUSCON Hardware watchdog timer registers WDKEY, WDRST Interrupt system registers IPA, Prog. Counter Array (PCA) control registers PCACL0, PCACH0, PCACON0, PCASTA, PCACL1, PCACH1, PCACON1, CCON2, CCON3
capture/compare registers CAPCOML0, CAPCOMH0, TCMMODE0, CAPCOML1, CAPCOMH1, TCMMODE2, CAPCOML2, CAPCOMH2, TCMMODE2, CAPCOML3, CAPCOMH3, TCMMODE3,
41/300
Special function registers (SFR)
UPSD3422, UPSD3433, UPSD3434, UPSD3454
CAPCOML4, CAPCOMH4, TCMMODE4, CAPCOML5, CAPCOMH5, TCMMODE5, PWMF0, PMWF1
interface registers SPICLKD, SPISTAT, SPITDR, SPIRDR, SPICON0, SPICON1 interface registers S1SETUP, S1CON, S1STA, S1DAT, S1ADR Analog digital converter registers ACON, ADCPS, ADAT0, ADAT1 IrDA interface register IRDACON interface registers UADDR, UPAIR, WE0-3, UIF0-3, UCTL, USTA, USEL, UCON, USIZE, UBASEH, UBASEL, USCI, USCV
Table
addr (hex) 88(1) 90(1)
memory with direct address reset value
name name <bit address> Reset Reg. value descr. (hex) with link
RESERVED SP[7:0] DPL[7:0] DPH[7:0] RESERVED DPTC DPPCON TCON TMOD P1SFS0 P1SFS1 P3SFS P4SFS0 P4SFS1 P1.7 <97h> P1.6 <96h> P1.5 <95h> <8Dh> <8Ch> MD1[1:0] RCLK1 <8Bh> GATE TCLK1 <8Ah> DPSEL[2:0] MD0[1:0] <89h> IDLE <88h> P1.2 <92h> P1.1 <91h> P1.0 <90h>
Table Table Table Table Table Table Section Table Table Table Table Table
Section Section
SMOD0 SMOD1 <8Fh> GATE <8Eh>
TL0[7:0] TL1[7:0] TH0[7:0] TH1[7:0] P1SFS0[7:0] P1SFS1[7:0] P1.4 <94h> P1.3 <93h>
P3SFS[7:0] P4SFS0[7:0] P4SFS1[7:0]
42/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table
addr (hex) 98(1) PCACL0 PCACH0 EOVF1 INTF4 BUSCON EPFQ WRW1
Special function registers (SFR)
memory with direct address reset value (continued)
name name <bit address> ADCCE ADCPS[2:0] Reset Reg. value descr. (hex) with link ADS[2:0] <9Ch> <9Bh> <9Ah> ADATA[9:8] ADST <99h> ADSF <9h8>
Table Table Table Table Table Section
ADCPS ADAT0 ADAT1 ACON SCON0 SBUF0
ADATA[7:0] AINTF <9Fh> AINTEN <9Eh> ADEN <9Dh>
SBUF0[7:0] RESERVED RESERVED RESERVED WRW0 RDW1 RDW0
Table
RESERVED RESERVED RESERVED RESERVED PCACL0[7:0] PCACH0[7:0] PCA_IDL INTF3 OVF0 INTF2 CLK_SEL[1:0] INTF1 INTF0 <AAh> EI2C <A9h> <A8h>
Table Table Table Table Table Table Table Table Table
PCACON0 EN_ALL EN_PCA A8(1) PCASTA WDRST EADC <AFh> ESPI OVF1 INTF5
WDRST[7:0] EPCA <ADh> <ACh> <ABh>
TCMMOD EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE TCMMOD EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE TCMMOD EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE CAPCOM CAPCOM WDKEY CAPCOM CAPCOML0[7:0] CAPCOMH0[7:0] WDKEY[7:0] CAPCOML1[7:0]
PWM[1:0] PWM[1:0] PWM[1:0]
Table Table
43/300
Special function registers (SFR) Table
addr (hex) B0(1) B8(1) PCACL1 PCACH1 EN_PCA EOVF1 PADC PSPI PPCA <BDh>
UPSD3422, UPSD3433, UPSD3434, UPSD3454
memory with direct address reset value (continued)
name name <bit address> P3.7 <B7h> P3.6 <B6h> P3.5 <B5h> P3.4 <B4h> P3.3 <B3h> P3.2 <B2h> P3.1 <B1h> P3.0 <B0h> Reset Reg. value descr. (hex) with link
Table Table
CAPCOM CAPCOM CAPCOM PWMF0
CAPCOMH1[7:0] CAPCOML2[7:0] CAPCOMH2[7:0] PWMF0[7:0] RESERVED RESERVED <BCh> <BBh> <BAh> PI2C <B9h> <B8h>
Table Table
RESERVED PCACL1[7:0] PCACH1[7:0] PCA_IDL CLK_SEL[1:0] PWM[1:0] PWM[1:0] PWM[1:0] P4.1 P4.0 <C1h> <C0h>
Table
Table Table Table
PCACON1 C0(1)
TCMMOD EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE TCMMOD EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE TCMMOD EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE P4.7 <C7h> P4.6 <C6h> P4.5 <C5h> P4.4 <C4h> P4.3 <C3h> P4.2 <C2h>
44/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table
addr (hex) C8(1) RCAP2L RCAP2H <D7h>
Special function registers (SFR)
memory with direct address reset value (continued)
name name <bit address> Reset Reg. value descr. (hex) with link <CAh> C/T2 CP/RL2 <C9h> <C8h>
Table Table
CAPCOM CAPCOM CAPCOM CAPCOM CAPCOM CAPCOM PWMF1 T2CON <CFh> EXF2 <CEh> RCLK <CDh>
CAPCOML3[7:0] CAPCOMH3[7:0] CAPCOML4[7:0] CAPCOMH4[7:0] CAPCOML5[7:0] CAPCOMH5[7:0] PWMF1[7:0] TCLK <CCh> EXEN2 <CBh>
RESERVED RCAP2L[7:0] RCAP2H[7:0] TL2[7:0] TH2[7:0] IRDA_EN BIT_PULS CDIV4 <D6h> <D5h> CDIV3 CDIV2 <D2h> CDIV1 CDIV0 <D0>
Table Section Section
IRDACON D0(1) D8(1) SPICLKD SPISTAT SPITDR SPIRDR SPICON0 SPICON1 SCON1 SBUF1
RS[1:0] <D4h, D3h> RESERVED
SPICLKD[5:0] BUSY TEISF RORISF
TISF
RISF
Table Table Table
SPITDR[7:0] SPIRDR[7:0] <DE> <DD> SPIEN <DC> SSEL TEIE <DB> FLSB RORIE <DA> <D9> <D8>
Table Table Table Section
SBUF1[7:0] RESERVED SMPL_SET[6:0] ADDR
S1SETUP SS_EN S1CON
Table Table
45/300
Special function registers (SFR) Table
addr (hex) E0(1) F0(1) USEL UCON USIZE UBASEH UBASEL USCI USCV BASEADDR[7:6] UADDR UPAIR UIE0 UIE1 UIE2 UIE3 UIF0 UIF1 UIF2 UIF3 UCTL USTA OUTF
UPSD3422, UPSD3433, UPSD3434, UPSD3454
memory with direct address reset value (continued)
name name <bit address> STOP INTR Reset Reg. value descr. (hex) with link
Table Table Table Section
S1STA S1DAT S1ADR
TX_MD B_BUSY B_LOST ACK_R S1DAT[7:0] S1ADR[7:0]
A[7:0] <bit addresses: E7h, E6h, E5h, E4h, E3h, E2h, E1h, E0h> RESERVED USBADDR[6:0] IN4IE PR3OU PR1OUT PR3IN RSTIE IN3IE SUSPND EOPIE IN2IE IN1IE PR1IN UMIE IN0IE
OUT4IE OUT3IE OUT2IE OUT1IE OUT0IE NAK4IE NAK3IE NAK2IE NAK1IE NAK0IE NAKF IN4F OUT4F NAK4F RSTF IN3F OUT3F NAK3F RCVT SUSPND RESUM EOPF IN2F IN1F IN0F
OUT2F OUT1F OUT0F NAK2F USBEN SETUP NAK1F NAK0F VISIBL WAKEU
RESERVED EP[2:0] USCI[2:0]
Section
B[7:0] <bit addresses: F7h, F6h, F5h, F4h, F3h, F2h, F1h, F0h> ENABLE STALL SIZE[6:0] BASEADDR[15:8] USCV[7:0] RESERVED RESERVED TOGGL
46/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table
addr (hex)
Special function registers (SFR)
memory with direct address reset value (continued)
name name <bit address> PLLM[4] PLLEN UPLLCE DBGCE CPU_ CPUPS[2:0] PLLD[3:0] PCA0CE PCA1CE RESERVED RESERVED RESERVED RESERVED RESERVED PCA0PS[3:0] PCA1PS[3:0] Reset Reg. value descr. (hex) with link
Table Table Table
CCON0 CCON1 CCON2 CCON3
PLLM[3:0]
This addressed individual bits (bit address mode) addressed entire byte (direct address mode).
47/300
8032 addressing modes
UPSD3422, UPSD3433, UPSD3434, UPSD3454
8032 addressing modes
8032 uses different addressing modes listed below:
Register Direct Register indirect Immediate External direct External indirect Indexed Relative Absolute Long
Register addressing
This mode uses contents registers (selected last three bits instruction opcode) operand source destination. This mode very efficient since additional instruction byte needed identify operand. example:
Move contents accumulator
Direct addressing
This mode uses 8-bit address, which contained second byte instruction, directly address operand which resides either 8032 DATA SRAM (internal address range 00h-07Fh) resides 8032 (internal address range 80h-FFh). This mode quite fast since range limit bytes internal 8032 SRAM. example:
Move contents DATA SRAM location into accumulator
Register indirect addressing
This mode uses 8-bit address contained either register indirectly address operand which resides 8032 IDATA SRAM (internal address range 80h-FFh). Although 8032 registers also occupy same physical address range IDATA, SFRs will accessed register Indirect mode. SFRs only accesses using Direct address mode. example:
Move into accumulator contents IDATA SRAM that pointed address contained
48/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
8032 addressing modes
Immediate addressing
This mode uses 8-bits data constant) contained second byte instruction, stores into memory location register indicated first byte instruction. Thus, data immediately available within instruction. This mode commonly used initialize registers SFRs perform mask operations. There also 16-bit version this mode loading DPTR register. this case, bytes following instruction byte contain 16-bit value. example:
DPTR, 1234# Move constant, 40h, into accumulator Move constant, 1234h, into DPTR
External direct addressing
This mode will access external memory (XDATA) using 16-bit address stored DPTR register. There only instructions using this mode both accumulator either receive byte from external memory addressed DPTR send byte from accumulator address DPTR. UPSD34xx special feature alternate contents (source destination) DPTR rapidly implement very efficient memory-to-memory transfers. example:
MOVX @DPTR Move contents accumulator XDATA address contained DPTR Move XDATA accumulator
MOVX @DPTR,
Note:
details Section Dual data pointers page
External indirect addressing
This mode will access external memory (XDATA) using 8-bit address stored either register This fastest access XDATA (least cycles), because only 8-bits available address, this mode limits XDATA size only bytes (the traditional Port 8032 available UPSD34xx, possible write upper address byte). example:
MOVX @R0,A Move into accumulator XDATA that pointed address contained
Note:
This mode supported UPSD34xx.
49/300
8032 addressing modes
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Indexed addressing
This mode used MOVC instruction which allows 8032 read constant from program memory (not data memory). MOVC often used read look-up tables that embedded program memory. final address produced this mode result adding either 16-bit DPTR value contents accumulator. value accumulator referred index. data fetched from final location program memory stored into accumulator, overwriting index value that previously stored there. example:
MOVC @A+DPTR MOVC @A+PC Move code byte relative DPTR into accumulator Move code byte relative into accumulator
Relative addressing
This mode will two's-compliment number stored second byte instruction program counter short jumps within +128 -127 addresses relative program counter. This commonly used looping very efficient since additional cycle needed fetch jump destination address. example:
SJMP Jump bytes ahead program memory) address which SJMP instruction stored. SJMP 1000h, program execution jumps 1034h.
Absolute addressing
This mode will append high-order bits address next instruction low-order bits ACALL AJUMP instruction produce 16-bit jump address. jump will within same Kbyte page program memory first byte following instruction. example:
AJMP 0500h next instruction located address 4000h, resulting jump will made 4500h.
9.10
Long addressing
This mode will 16-bits contained bytes following instruction byte jump destination address LCALL LJMP instructions. example:
LJMP 0500h Unconditionally jump address 0500h program memory
50/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
8032 addressing modes
9.11
addressing
This mode allows setting clearing individual without disturbing other bits within 8-bit value internal SRAM. Addressing only available certain locations 8032 DATA memory. Valid locations DATA addresses addresses whose base address ends with (Example: SFR, base address A8h, each eight bits addressed individually address A8h, A9h, AFh.) example:
SETB individual (Enable Interrupts) inside register,
51/300
UPSD34xx instruction summary
UPSD3422, UPSD3433, UPSD3434, UPSD3454
UPSD34xx instruction summary
Tables through list instructions supported UPSD34xx, including number bytes number machine cycles required implement each instruction. This standard 8051 instruction set. meaning "machine cycles" many 8032 core machine cycles required execute instruction. "native" duration machine cycles memory wait state settings SFR, BUSCON, clock divider selections SFR, CCON0 (i.e. machine cycle typically clocks UPSD34xx). However, individual machine cycle grow duration when either things happen: stall imposed while loading 8032 Pre-Fetch Queue (PFQ); occurrence cache miss Branch Cache (BC) during branch program execution flow.
Section 8032 core performance enhancements page more details. generally speaking, during typical program execution, empty misses, producing very good performance without extending duration machine cycles. Table Arithmetic instruction
Description register direct byte indirect SRAM immediate data register with carry direct byte with carry indirect SRAM with carry immediate data with carry Subtract register from with borrow Subtract direct byte from with borrow Subtract indirect SRAM from with borrow Subtract immediate data from with borrow Increment Increment register Increment direct byte Increment indirect SRAM Decrement Decrement register Decrement direct byte Length/cycles byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle
Mnemonic(1) ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB Direct #data direct #data direct #data direct direct
52/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table Arithmetic instruction (continued)
UPSD34xx instruction summary
Mnemonic(1) DPTR
Description Decrement indirect SRAM Increment Data Pointer Multiply Divide Decimal adjust
Length/cycles byte/1 cycle byte/2 cycle byte/4 cycle byte/4 cycle byte/1 cycle
mnemonics copyrighted ©Intel Corporation 1980.
Table
Logical instruction
Description Logical Instructions Length/cycles
Mnemonic(1)
SWAP
direct #data direct, direct, #data direct #data direct, direct, #data direct #data direct, direct, #data
register direct byte indirect SRAM immediate data direct byte immediate data direct byte register direct byte indirect SRAM immediate data direct byte immediate data direct byte Swap nibbles within Exclusive-OR register Exclusive-OR direct byte Exclusive-OR indirect SRAM Exclusive-OR immediate data Exclusive-OR direct byte Exclusive-OR immediate data direct byte Clear Compliment Rotate left Rotate left through carry Rotate right Rotate right through carry
byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/2 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/2 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/2 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle
mnemonics copyrighted ©Intel Corporation 1980.
53/300
UPSD34xx instruction summary Table
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Data transfer instruction
Description Move register Move direct byte Move indirect SRAM Move immediate data Move register Move direct byte register Move immediate data register Move direct byte Move register direct byte Move direct byte direct Move indirect SRAM direct byte Move immediate data direct byte Move indirect SRAM Move direct byte indirect SRAM Move immediate data indirect SRAM Load Data Pointer with 16-bit constant Length/cycles byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/2 cycle byte/1 cycle byte/1 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/1 cycle byte/2 cycle byte/1 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/1 cycle byte/2 cycle byte/2 cycle byte/1 cycle byte/1 cycle byte/1 cycle
Mnemonic(1) MOVC MOVC MOVX MOVX MOVX MOVX PUSH XCHD direct #data direct #data direct, direct, direct, direct direct, direct, #data @Ri, @Ri, direct @Ri, #data DPTR, #data16
@A+DPTR Move code byte relative DPTR @A+PC
Move code byte relative Move XDATA (8-bit addr) Move XDATA (16-bit addr) Move XDATA (8-bit addr) Move XDATA (16-bit addr) Exchange register with Push direct byte onto stack direct byte from stack Exchange direct byte with Exchange indirect SRAM with Exchange low-order digit indirect SRAM with
@DPTR @Ri, @DPTR, direct direct direct
mnemonics copyrighted ©Intel Corporation 1980. This instruction supported UPSD34xx. Section 9.6: External indirect addressing page
54/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table
UPSD34xx instruction summary
Boolean variable manipulation instruction
Description Clear carry Clear direct carry direct Compliment carry Compliment direct direct carry compliment direct carry direct carry compliment direct carry Move direct carry Move carry direct Jump carry Jump carry Jump direct Jump direct Jump direct clear Length/cycles byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/1 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/1 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle
Mnemonic(1) SETB SETB /bit /bit bit, bit,
mnemonics copyrighted ©Intel Corporation 1980.
Table
Program branching instruction
Description Program Branching Instructions Length/cycles
Mnemonic(1)
ACALL LCALL RETI AJMP LJMP SJMP CJNE CJNE CJNE
addr11 addr16
Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt
byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle byte/2 cycle
addr11 addr16 @A+DPTR direct, #data,
Absolute jump Long jump Short jump (relative addr) Jump indirect relative DPTR Jump zero Jump zero Compare direct byte ACC, jump equal Compare immediate ACC, jump equal
#data, Compare immediate register, jump equal
55/300
UPSD34xx instruction summary Table
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Program branching instruction (continued)
Description Compare immediate indirect, jump equal Decrement register jump zero Decrement direct byte jump zero Length/cycles byte/2 cycle byte/2 cycle byte/2 cycle
Mnemonic(1) CJNE DJNZ DJNZ @Ri, #data, direct,
mnemonics copyrighted ©Intel Corporation 1980.
Table
Miscellaneous instruction
Description Miscellaneous Length/Cycles
Mnemonic(1)
operation
byte/1 cycle
mnemonics copyrighted ©Intel Corporation 1980.
Table
direct #data
Notes instruction addressing modes
Register currently selected register bank. 8-bit address internal 8032 DATA SRAM (locations 7Fh) registers (locations FFh). 8-bit internal 8032 SRAM (locations FFh) addressed indirectly through contents 8-bit constant included within instruction.
#data16 16-bit constant included within instruction. addr16 addr11 16-bit destination address used LCALL LJMP. 11-bit destination address used ACALL AJMP. Signed (two-s compliment) 8-bit offset byte. Direct addressed internal 8032 DATA SRAM (locations 2Fh) registers (88h, 90h, 98h, A8h, B8h, C0h, C8h, D0h, D8h, E0h, F0h).
56/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Dual data pointers
Dual data pointers
XDATA accessed External Direct addressing mode, which uses 16-bit address stored DPTR register. Traditional 8032 architecture only DPTR register. This burden when transferring data between XDATA locations because requires heavy working registers manipulate source destination pointers. However, UPSD34xx data pointers, storing source address other storing destination address. These pointers configured automatically increment decrement after each data transfer, further reducing burden 8032 making this kind data movement very efficient.
11.1
Data pointer control register, DPTC (85h)
default, DPTR register UPSD34xx will behave different than standard 8032 MCU. DPSEL0 register DPTC shown Table selects which "background" data pointer registers (DPTR0 DPTR1) will function traditional DPTR register given time. After reset, DPSEL0 cleared, enabling DPTR0 function DPTR, firmware access DPTR0 reading writing traditional DPTR register addresses 83h. When DPSEL0 set, then DPTR1 register functions DPTR, firmware access DPTR1 through registers 83h. pointer which selected DPSEL0 remains background accessible 8032. DPSEL0 never set, then UPSD34xx will behave like traditional 8032 having only DPTR register. further speed XDATA XDATA transfers, bit, automatically toggle data pointers, DPTR0 DPTR1, each time standard DPTR register accessed MOVX instruction. This eliminates need firmware manually manipulate DPSEL0 between each data transfer. Detailed description register DPTC shown Table Table
DPTC: data pointer control register (SFR 85h, reset value 00h)
DPSEL0
Table
DPTC register definition
Symbol DPSE0 Reserved Manually select data pointer Auto toggle between DPTR0 DPTR1 Reserved DPTR0 selected DPTR DPTR1 selected DPTR Definition
57/300
Dual data pointers
UPSD3422, UPSD3433, UPSD3434, UPSD3454
11.2
Data pointer mode register, DP(86h)
"background" data pointers, DPTR0 DPTR1, configured automatically increment, decrement, stay same after MOVX instruction accesses DPTR register. Only currently selected pointer will affected increment decrement. This feature controlled DPregister defined Table automatic increment decrement function effective only MOVX instruction, MOVC other instruction that uses DTPR register.
11.2.1
Firmware example
8051 assembly code illustrated Table shows transfer block data bytes from XDATA address region another XDATA address region. Auto-address incrementing auto-pointer toggling will used. Table
DPTM: data pointer mode register (SFR 86h, reset value 00h)
MD11 MD10 MD01 MD00
Table
DPregister definition
Symbol DPTR1 mode bits DPTR1 change Reserved Auto Increment Auto Decrement DPTR0 mode bits DPTR0 change Reserved Auto Increment Auto Decrement Definition Reserved
MD[11:10]
MD[01:00]
58/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Dual data pointers
8051 assembly code example
LOOP: MOVX
#COUNT DPTR, #SOURCE_ADDR 85h, #01h 85h, #40h 86h, #0Ah @DPTR
initialize size data block transfer load XDATA source address base into DPTR0 load DPTC access DPTR1 pointer load DPTC access DPTR0 pointer auto toggle load DPto auto-increment both pointers load XDATA byte from source into ACC. after load completes, DPTR0 increments DPTR switches DPTR1 store XDATA byte from destination. after store completes, DPTR1 increments DPTR switches DPTR0 continue until done disable auto-increment disable auto-toggle, back single DPTR mode
DPTR, #DEST_ADDR load XDATA destination address base into DPTR1
MOVX(1)
@DPTR,
DJNZ(1)
LOOP 86h, 85h,
Note:
code loop where data transfer takes place only lines code.
59/300
Debug unit
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Debug unit
8032 module supports run-time debugging through JTAG interface. This same JTAG interface also used In-System Programming (ISP) physical connections described module section, Section 28.6.1: JTAG JTAG debug page 257. Debugging with serial interface such JTAG non-intrusive gain access internal state 8032 core various memories. traditional external hardware emulator cannot completely effective UPSD34xx because Pre-Fetch Queue Branch Cache. nature hide visibility actual program flow through traditional external connections, thus requiring on-chip serial debugging instead. Debugging supported Windows based software tools used 8051 code development from party vendors listed www.st.com/psm. Debug capabilities include:
Halt start execution Reset Single step match breakpoints range breakpoint (inside outside range) Program tracing Read modify core registers, DATA, IDATA, SFR, XDATA, code External debug event pin, input output JTAG debugger access registers, data memory, code memory while executing full speed cycle-stealing. This means "watch windows" displayed periodically updated during full speed operation. Registers data content also modified during full speed operation. There on-chip storage Program Trace data, instead this data scanned from UPSD34xx through JTAG channel run-time host proccessing. such, full speed program tracing possible only when 8032 operating below approximately MIPS performance. Above MIPS, program will real-time while tracing. MIPS performance determined combination choice clock frequency, settings registers BUSCON CCON0. Breakpoints optionally halt MCU, and/or assert external Debug Event pin. Breakpoint definitions qualified with read write operations, also qualified with address code, SFR, DATA, IDATA, XDATA memories. Three breakpoints will compare address, fourth breakpoint compare address also data content. Additionally, fouth breakpoint logically combined (AND/OR) with other three breakpoints. Debug Event configured host generate output pulse external triggering when break condition met. also configured event input breakpoint logic, causing break fallingedge external event signal. used, Debug Event should pulled
Some points regarding JTAG debugger.
60/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Debug unit
described section, Section 28.6.8: Debugging 8032 module page 263. duration pulse, generated when Event configured output, clock cycle. This active-low signal, first edge when event occurs high-to-low. clock Watchdog Timer, ADC, interface stopped breakpoint halt. Watchdog Timer should disabled while debugging with JTAG, else reset will generated upon watchdog time-out.
61/300
Interrupt system
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Interrupt system
UPSD34xx 12-source, priority level interrupt structure summarized Table Firmware assign each interrupt source either high priority writing bits SFRs named, IPA, shown Table interrupt will serviced long interrupt equal higher priority already being serviced. interrupt equal higher priority being serviced, interrupt will wait until finished before being serviced. lower priority interrupt being serviced, will stopped interrupt serviced. When interrupt finished, lower priority interrupt that stopped will completed. interrupt requests same priority level received simultaneously, internal polling sequence determines which request selected service. Thus, within each priority levels, there second priority structure determined polling sequence. Firmware individually enable disable interrupt sources writing bits SFRs named, IEA, shown Table page named contains global disable (EA), which cleared disable interrupts once, shown Table page Figure page illustrates interrupt priority, polling, enabling process. Each interrupt source least interrupt flag that indicates whether interrupt pending. These flags reside bits various SFRs shown Table page interrupt flags latched into interrupt control system beginning each machine cycle, they polled beginning following machine cycle. polling determines flags set, interrupt control system automatically generates LCALL user's Interrupt Service Routine (ISR) firmware stored program memory appropriate vector address.
specific vector address each interrupt sources listed Table page However, this LCALL jump blocked following conditions: interrupt equal higher priority already progress current machine cycle final cycle execution instruction progress current instruction involves write SFRs: IEA, current instruction RETI
Note:
Interrupt flags polled based sample taken previous machine cycle. interrupt flag active cycle denied serviced conditions above, then later active when conditions above finally satisfied, previously denied interrupt will serviced. This means that active interrupts remembered. Every poling cycle new. Assuming listed conditions satisfied, executes hardware generated LCALL appropriate ISR. This LCALL pushes contents onto stack (but does save PSW) loads with appropriate interrupt vector address. Program execution then jumps vector address. Execution precedes ISR. necessary firmware clear pending interrupt flag some interrupt sources, because interrupt flags automatically cleared hardware when called, shown Table page
62/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Interrupt system
interrupt flag cleared after servicing interrupt, unwanted interrupt will occur upon exiting ISR. After interrupt serviced, last instruction executed RETI. RETI informs that longer progress pops bytes from stack loads them into Execution interrupted program continues where left off. Note: must with RETI instruction, RET. will inform interrupt control system that complete, leaving think still progress, making future interrupts impossible. Table Interrupt summary
Flag autocleared hardware? Edge Level Edge Level Enable name Priority name (SFR.bit (SFR.bit position) position) Intr Enabled High Priority Intr Disabled Priority (IE.0) (IP.0)
Flag name (SFR.bit Interrupt Polling Vector position) source priority addr Intr pending interrupt Reserved (high) 0063h External Interrupt INT0 Timer Overflow External Interrupt INT1 Timer Overflow UART0 Timer Overflow
(TCON.1)
0003h
000Bh
(TCON.5)
(IE.1)
(IP.1)
0013h
(TCON.3
(IE.2)
(IP.2)
001Bh 0023h
(TCON.7) (SCON0.0) (SCON0.1) (T2CON.7) EXF2 (T2CON.6) TEISF, RORISF, TISF, RISF (SPISTAT[3:0])
(IE.3) (IE.4)
(IP.3) (IP.4)
002Bh
(IE.5)
(IP.5)
0053h 0033h
ESPI (IEA.6) EUSB (IEA.0) EI2C (IEA.1)
PSPI (IPA.6) PUSB (IPA.0) PI2C (IPA.1) PADC (IPA.7) PPCA (IPA.5) (IPA.4)
0043h INTR (S1STA.5) 003Bh 005Bh AINTF (ACON.7) OFVx, INTFx (PCASTA[0:7]) (SCON1.0) (SCON1.1)
UART1
EADC (IEA.7) EPCA (IEA.5) (IEA.4)
(low) 004Bh
interrupt flag registers UIF0-3.
63/300
Interrupt system
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Figure Enabling polling interrupts
Interrupt Sources Reserved Priority IE/IEA IP/IPA High
INT0 Timer INT1
Timer
UART0
Interrupt Polling Sequence
Timer
UART1
Global Enable
AI07844
13.1
13.1.1
Individual interrupt sources
External interrupts Int0 Int1
External interrupt inputs pins EXTINT0 EXTINT1 (pins 3.3) either edgetriggered level-triggered, depending bits named TCON. When external interrupt generated from edge-triggered (falling-edge) source, appropriate flag (IE0 IE1) automatically cleared hardware upon entering ISR. When external interrupt generated from level-triggered (low-level) source, appropriate flag (IE0 IE1) automatically cleared hardware.
64/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Interrupt system
13.1.2
Timer overflow interrupt
Timer Timer interrupts generated flag bits when there overflow condition respective Timer/Counter register (except Timer Mode
13.1.3
Timer overflow interrupt
This interrupt generated logical flag bits, EXE2. must read flag bits determine cause interrupt.
overflow Timer EXE2 generated falling edge signal external pin, (pin P1.1).
13.1.4
UART0 UART1 interrupt
Each UARTs have identical interrupt structure. each UART, single interrupt generated logical flag bits, (byte received) (byte transmitted). must read flag bits named SCON0 UART0, SCON1 UART1 determine cause interrupt.
13.1.5
interrupt
interrupt four interrupt sources, which logically ORed together when interrupting MCU. must read flag bits determine cause interrupt. flag for: data transmit (TEISF); data receive overrun (RORISF); transmit buffer empty (TISF); receive buffer full (RISF).
13.1.6
interrupt
flag INTR variety conditions occurring interface: received slave address (ADDR flag); received general call address flag); received Stop condition (STOP flag); successful transmission reception data byte.The must read flag bits determine cause interrupt.
13.1.7
interrupt
flag AINTF when A-to-D conversion completed.
13.1.8
interrupt
eight interrupt sources, which logically ORed together when interrupting MCU.The must read flag bits determine cause interrupt.
Each TCMs generate "match capture" interrupt flag bits OFV5.0 respectively. Each 16-bit counters generate overflow interrupt flag bits INTF1 INTF0 respectively.
Tables through Table page have detailed definitions interrupt system SFRs.
65/300
Interrupt system
UPSD3422, UPSD3433, UPSD3434, UPSD3454
13.1.9
interrupt
interrupt multiple sources. must read interrupt flag registers (UIF0-3) determine source interrupt. interrupt activated following four group interrupt sources:
Global: interrupt flag when following events occurs: Reset, Suspend, Resume, Packet; FIFO: interrupt flag when Point FIFO becomes empty; FIFO: interrupt flag when Point FIFO becomes full; FIFO NAK: interrupt flag when Point FIFO ready (in-bound) packet. interrupt enable register (SFR A8h, reset value 00h)
Table
Table
register definition
Symbol Function Global disable bit. interrupts disabled. Each interrupt source individually enabled disabled setting clearing enable bit. modify this bit. used JTAG debugger instruction tracing. Always read write back same value when writing this SFR. Enable Timer Interrupt Enable UART0 Interrupt Enable Timer Interrupt Enable External Interrupt INT1 Enable Timer Interrupt Enable External Interrupt INT0
5(1) 4(1) 3(1)
0(1)
Enable Interrupt, Disable Interrupt.
Table
EADC
IEA: interrupt enable addition register (SFR A7h, reset value 00h)
ESPI EPCA EI2C EUSB
Table
7(1) 6(1)
register definition
Symbol EADC ESPI EPCA Enable Interrupt Enable Interrupt Enable Programmable Counter Array Interrupt Enable UART1 Interrupt Function
66/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table
1(1)
Interrupt system
register definition (continued)
Symbol EUSB
Function Reserved, logic '1.' Reserved, logic '1.' Enable Interrupt Enable Interrupt
Enable Interrupt, Disable Interrupt.
Table
interrupt priority register (SFR B8h, reset value 00h)
Table
register definition
Symbol Reserved Reserved Timer Interrupt priority level UART0 Interrupt priority level Timer Interrupt priority level External Interrupt INT1 priority level Timer Interrupt priority level External Interrupt INT0 priority level Function
3(1)
0(1)
Assigns high priority level, Assigns priority level.
Table
PADC
IPA: Interrupt Priority Addition register (SFR B7h, reset value 00h)
PSPI PPCA PI2C PUSB
Table
7(1) 6(1) 5(1)
register definition
Symbol PADC PSPI PPCA PI2C PUSB Function Interrupt priority level Interrupt priority level Interrupt level UART1 Interrupt priority level Reserved Reserved Interrupt priority level Interrupt priority level
1(1)
Assigns high priority level, Assigns priority level.
67/300
clock generation
UPSD3422, UPSD3433, UPSD3434, UPSD3454
clock generation
Internal system clocks generated clock generation unit derived from signal, XTAL1, shown Figure XTAL1 frequency fOSC, which comes directly from external crystal oscillator device. named CCON0 (Table page controls clock generation unit. There clock signals produced clock generation unit:
MCU_CLK PERIPH_CLK
14.1
MCU_CLK
This clock drives 8032 core Watchdog Timer (WDT). frequency MCU_CLK equal fOSC default, divided much 2048, shown Figure bits CPUPS[2:0] select eight different divisors, ranging from 2048. frequency available immediately after CPUPS[2:0] bits written. final frequency MCU_CLK fMCU. MCU_CLK blocked either bit, IDL, named PCON during Powerdown mode Idle mode respectively. MCU_CLK clock further divided required WDT. details Section Supervisory functions page
14.2
PERIPH_CLK
This clock drives UPSD34xx peripherals except WDT. Frequency PERIPH_CLK always fOSC. Each peripherals independently divide PERIPH_CLK scale appropriately use. PERIPH_CLK runs times except when blocked named PCON during Power-down mode.
14.2.1
JTAG interface clock
JTAG interface Debugging uses externally supplied JTAG clock, coming TCK. This means JTAG interface always available, JTAG Debug interface available when enabled, even during Idle mode Power-down mode. However, since participates JTAG debug process, MCU_CLK halted during Idle Power-down modes, majority debug functions available during these power modes. JTAG debug interface capable executing reset command while these power modes, which will exit back normal operating mode where debug commands available again. CCON0 contains bit, DBGCE, which enables breakpoint comparators inside JTAG Debug Unit when set. DBGCE default after reset, firmware clear this run-time. Disabling these comparators will reduce current consumption module, recommended Debug Unit will used (such production version end-product).
68/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
clock generation
14.2.2
USB_CLK
UPSD34xx dedicated analog phase locked loop (PLL) that configured generate 48MHz USB_CLK clock wide range fOSC frequencies. USB_CLK must 48MHz function properly. enabled after power power lock time clock about 200µs, firmware should wait that much time before enabling USB_CLK setting UPLLCE CCON0 register '1.' disabled Power-down mode, also disabled enabled writing PLLEN CCON0 register. output clock frequency (fUSB_CLK) determined using following formula:
USBCLK PLLM PLLD
where PLLM PLLD multiplier divisor that specified CCON1 register. fOSC, PLLM PLLD range must meet following conditions generate stable USB_CLK: PLLM (binary: [11111] PLLM[4:0] [11110]), PLLD (binary: [1111] PLLD[3:0] [1110]), fOSC/(PLLD+2) must equal greater than 3MHz.
requires 48MHz clock operate correctly. PLLM[4:0] PLLD[3:0] values must selected generate USB_CLK that close 48MHz possible different oscillator frequencies (fOSC). Table lists some PLLM PLLD values that used common fOSC frequencies. Table
fOSC (MHz) 40.0 36.0 33.0 30.0 24.0 16.0 12.0
PLLM PLLD values different fOSC frequencies
PLLM[4:0] decimal binary 10110 00110 11110 01110 10010 11100 11110 10110 11110 11110 PLLD[3:0] decimal binary 1000 0001 1001 0011 0011 0011 0010 0000 0000 1111 fUSB_CLK (MHz) 48.0 48.0 48.0 48.0 48.0 48.0 48.0 48.0 48.0 48.0
69/300
clock generation Figure Clock generation logic
PCON[1]: Power-Down Mode
UPSD3422, UPSD3433, UPSD3434, UPSD3454
CCON[2:0], Clock Pre-Scaler Select
XTAL1 (default)
PCON[0]: IDL, Idle Mode
XTAL1 (fOSC)
XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 /1024 XTAL1 /2048
MCU_CLK (fMCU) (to: 8032, WDT)
Clock Divider PERIPH_CLK (fOSC) (to: TIMER0/1/2, UART0/1, PCA0/1, SPI, I2C, ADC)
USB_CLK
PCON[1] CCON0[6]
AI10433b
Table
PLLM[4]
CCON0: clock control register (SFR F9h, reset value 50h)
PLLEN UPLLCE DBGCE CPUAR CPUPS[2:0]
Table
CCON0 register definition
Symbol PLLM[4] Definition Upper 5-bit PLLM[4:0] Multiplier (Default: PLLM 00h) Enable Disable operation Enable operation (Default condition after reset) Clock Enable clock disabled (Default condition after reset) clock enabled Debug Unit Breakpoint Comparator Enable JTAG Debug Unit comparators disabled JTAG Debug Unit comparators enabled (Default condition after reset)
PLLEN
UPLLCE
DBGCE
70/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table
clock generation
CCON0 register definition (continued)
Symbol Definition Automatic Clock Recovery There change CPUPS[2:0] when interrupt occurs. Contents CPUPS[2:0] automatically become 000b whenever interrupt occurs. MCUCLK Pre-Scaler 000b: fMCU fOSC (Default after reset) 001b: fMCU fOSC/2 010b: fMCU fOSC/4 011b: fMCU fOSC/8 100b: fMCU fOSC/16 101b: fMCU fOSC/32 110b: fMCU fOSC/1024 111b: fMCU fOSC/2048
CPUAR
CPUPS
Table
CCON1 control register (SFR FAh, reset value 00h)
PLLM[3:0]
PLLD[3:0]
Table
CCON1 register definition
Symbol Definition Lower bits 5-bit PLLM[4:0] Multiplier (Default after reset: PLLM 00h) PLLM[4] CCON0 register. 4-bit Divider (Default after reset: PLLD
PLLM[3:0] PLLD[3:0]
71/300
Power saving modes
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Power saving modes
UPSD34xx combination die, modules, each module having current consumption characteristics. This section describes reduced power modes module. Section 28.1.16: Power management page reduced power modes module. Total current consumption combined modules determined specifications this document. module three software-selectable modes reduced power operation.
Idle mode Power-down mode Reduced frequency mode
15.1
Idle mode
Idle mode will halt 8032 core while leaving peripherals active (Idle mode blocks MCU_CLK only). lowest current consumption this mode, recommended disable unused peripherals, before entering Idle mode (such Debug Unit breakpoint comparators). following functions remain fully active during Idle mode (except disabled settings).
External Interrupts INT0 INT1 Timer Timer Timer Supervisor reset from: LVD, JTAG Debug, External RESET_IN_, Interface UART0 UART1 Interfaces Interface Programmable Counter Array Interface
interrupt generated these peripherals, reset generated from supervisor, will cause Idle mode exit 8032 will resume normal operation. output state pins ports remain unchanged during Idle mode. enter Idle mode, 8032 executes instruction named PCON, shown Table page This last instruction executed normal operating mode before Idle mode activated. Once Idle mode, status entirely preserved, there changes PSW, ACC, SFRs, DATA, IDATA, XDATA. following factors related Idle mode exit:
Activation enabled interrupt will cause cleared hardware, terminating Idle mode. interrupt serviced, following Return from Interrupt instruction (RETI), next instruction executed will which follows instruction that PCON SFR. After reset from supervisor, cleared, Idle mode terminated, restarts after three machine cycles.
72/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Power saving modes
15.2
Power-down mode
Power-down mode will halt 8032 core peripherals (Power-down mode blocks MCU_CLK, USB_CLK, PERIPH_CLK). This lowest power state module. When module also placed Power-down mode, lowest total current consumption combined achieved UPSD34xx. Section 28.1.16: Power management page module section details also place module Power-down mode. sequence 8032 instructions important when placing both modules into Power-down mode. instruction that sets named PCON (Table page last instruction executed prior module going into Power-down mode. Once Power-down mode, on-chip oscillator circuitry clocks stopped. SFRs, DATA, IDATA, XDATA preserved. Power-down mode terminated only reset from supervisor, originating from RESET_IN_ pin, Low-Voltage Detect circuit (LVD), JTAG Debug reset command. Since clock active during Power-down mode, possible supervisor generate reset. Table page summarizes status pins peripherals during Idle Power-down modes module. Table page shows state 8032 address, data, control signals during these modes.
15.3
Reduced frequency mode
8032 consumes less current when operating lower clock frequency. reduce clock frequency run-time writing three bits, CPUPS[2:0], named CCON0 described Table page These bits effectively divide clock frequency (fOSC) coming from external crystal oscillator device. clock division range from 1/2048, resulting frequency fMCU. This clock division does affect peripherals, except WTD. clock driving same clock driving 8032 core shown Figure page firmware reduce clock frequency run-time consume less current when performing tasks that time critical, then restore full clock frequency required perform urgent tasks. Returning full clock frequency done automatically upon interrupt, CPUAR named CCON0 (the interrupt will force CPUPS[2:0] 000). This excellent conserve power using frequency clock until event occurs that requires full performance. Table page details CPUAR. Specifications this document estimate current consumption based clock frequency.
Note:
Some bits PCON shown Table page related power control.
73/300
Power saving modes Table
Mode
UPSD3422, UPSD3433, UPSD3434, UPSD3454 module port peripheral status during reduced power modes
Ports Maintain data Maintain data SPI, I2C, UART0,1 Active Disabled PCA, Timer 0,1,2 Active Disabled INT0,1 Active Disabled Supervisory
Idle Powerdown
Active Disabled
Active Disabled
Active(1) Disabled
Watchdog Timer active during Idle mode. Other supervisor functions active: LVD, external reset, JTAG Debug reset.
Table
Mode Idle Power-down
State 8032 signals during power-down idle modes
PSEN_ AD0-7 A8-15
Table
SMOD0
PCON: power control register (SFR 87h, reset value 00h)
SMOD1 RCLK1 TCLK1
Table
PCON register definition
Symbol Function Baud Rate Double (UART0) doubling Doubling (See Section 21.3: UART baud rates page details.) Baud Rate Double UART (UART1) doubling Doubling (See Section 21.3: UART baud rates page details.) Reserved Only power-on reset sets this (cold reset). Warm reset will this bit. Cleared zero with firmware only power-on reset generated Supervisory circuit (see Section 19.3: Power-up reset page details). Received Clock Flag (UART1) (See Table page flag description.) Transmit Clock Flag (UART1) (See Table page flag description)
SMOD0
SMOD1
RCLK1 TCLK1
74/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Table
Power saving modes
PCON register definition (continued)
Symbol Function Activate Power-down mode Power-down mode Enter Power-down mode Activate Idle mode Idle mode Enter Idle mode
75/300
Oscillator external components
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Oscillator external components
oscillator circuit UPSD34xx devices single stage, inverting amplifier Pierce oscillator configuration. internal circuitry between pins XTAL1 XTAL2 basically inverter biased transfer point. Either external quartz crystal ceramic resonator used feedback element complete oscillator circuit. Both operated parallel resonance. Ceramic resonators lower cost, typically have wider frequency tolerance than quartz crystals. Alternatively, external clock source from oscillator other active device drive UPSD34xx oscillator circuit input directly, instead using crystal resonator. minimum frequency quartz crystal, ceramic resonator, external clock source 3MHz used. minimum 8MHz used. maximum 40MHz cases. This frequency fOSC, which divided internally described Section clock generation page XTAL1 high gain amplifier input, XTAL2 output. drive UPSD34xx device externally from oscillator other active device, XTAL1 driven XTAL2 left open-circuit. This external source should drive logic voltage level below, logic high 0.7V above, VCC. XTAL1 input tolerant. Most quartz crystals range 25MHz operate third overtone frequency mode. external tank circuit XTAL2 output oscillator circuit needed achieve third overtone frequency, shown Figure page Without this circuit, crystal will oscillate fundamental frequency mode that about desired overtone frequency.
Note:
Figure page crystals which specified operate fundamental mode (not overtone mode) need circuit components. Since quartz crystals ceramic resonators have their characteristics based their manufacturer, wise also consult manufacturer's recommended values external components.
76/300
UPSD3422, UPSD3433, UPSD3434, UPSD3454 Figure Oscillator clock connections
XTAL1 (in) XTAL2 (out)
Oscillator external components
Crystal resonator usage
XTAL (fOSC)
XTAL (fOSC) Ceramic resonator Crystal, fundamental mode (3-40MHz) Crystal, overtone mode (25-40MHz)
15-33
None None
None None
Direct drive
XTAL1 (in)
XTAL2 (out)
External ocsillator active clock source
connect
AI09198c
77/300
ports module
UPSD3422, UPSD3433, UPSD3434, UPSD3454
ports module
module three 8-bit ports: Port Port Port module four other ports: Port This section describes only ports module. ports will function bidirectional general-purpose (GPIO), port pins have alternate functions assigned run-time writing specific SFRs. default operating mode (during after reset) three ports GPIO input mode. Port pins that have external connection will float because each internal weak pull-up (~150 VCC. ports tolerant, meaning they driven/pulled externally without damage. pins Port have higher current capability than pins Ports Three additional ports (only 80-pin UPSD34xx devices) dedicated bring 8032 address, data, control signals external pins. port, named MCUAD[7:0], eight multiplexed address/data bidirectional signals. third port control outputs: read, write, program fetch, address latch. These ports typically used connect external parallel peripherals memory devices, they used GPIO. Notice that eight upper address signals come pins port. high-order address signals required external pins (MCU addresses A[15:8]), then these address signals brought needed output pins Address mode pins module ports. module section, "Section 28.5.40: Latched address output mode page details. Figure page represents flexibility function routing controlled SFRs. Each pins
Other recent searches
XP04315 - XP04315 XP04315 Datasheet
TA75307 - TA75307 TA75307 Datasheet
MP1410 - MP1410 MP1410 Datasheet
IHLP-5050CE-07 - IHLP-5050CE-07 IHLP-5050CE-07 Datasheet
APTM50DHM75T - APTM50DHM75T APTM50DHM75T Datasheet
2SD849 - 2SD849 2SD849 Datasheet
1673650000 - 1673650000 1673650000 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
