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INTRODUCTION CORE ADDRESSING MODES ASSEMBLY TOOLCHAIN STVD7 DEBUGGER HARDWARE TOOLS PERIPHERALS ST-REALIZER TOOLCHAINS
PURPOSE OBJECTIVES
Purpose
improve your knowledge standard peripherals
Objectives
List main features most standard peripherals Optimize their Develop efficient code either Assembly language using these peripherals application environment quick start Demonstrate peripherals performance using INDART demo board support
PORTS Optional features:
8-Bit CORE Accu Index Index Program Data bytes Data EEprom PORT 16-bit timer Peripheral Peripheral Interrupt Controller Test/Vpp Reset Oscillator Power Supply Watchdog Timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
Optional
PORTS
Overview
I/Os individually software configurable using different registers:
DDR: Data Direction Register Data Register Option Register
ST72254: multifunction bidirectional lines
Standard I/Os (sink 5mA) High Current I/Os (PA0-PA7 sink 20mA) Analog Inputs (PC0-PC5) alternate Functions pins (for Timers, I2C) I/Os set-up Interrupt inputs
PORT
Safe transition
Mode Floating input Input pull- with/without interrupt Output Open-Drain Output Push-Pull
Reset State
PORT Basic structure
Read Write DDRi Data Direction Register
Write
Latch Data Output Input
Ouput
Read Input
Software selectable configuration HIGH FLEXIBILITY software board layout
PORT
Settings electrical behaviour
Configuration given when external Hardware connected pins
Input Floating Written Read
Floating Floating
Input Pull_up
Ouput Open Drain
Floating
Ouput Push-Pull
EXTERNAL INTERRUPTS
Edge/level selection Edge/level selection Interrupt generation Interrupt source Negative edge only Positive edge only Positive Negative edge Negative edge level Positive edge high level Latched Latched Latched Latched Latched Interrupt Source Interrupt Controller Interrupt Source
Miscellaneous Register
PORT Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT
n-chi peri
(see table below) PULL-UP table below)
ALTERNATE ENABLE
PULL-UP ONDITIO
implemented
N-BUFFER CMOS HMIT TRIG
table below) ANALO INPUT
ALTERNATE INPUT
Comb on-ch riph eral
EXTERNAL ERRUPT REQUEST
SENSITIVITY SELECTIO
BITS Refer Port onfig uratio
vice cific informa
PROGRAMMING TIPS
Port
convertion
Each used cell must configured floating input (i.e. without pull-up resistors) before activating analog input mode (which usual default state)
Alternate function
signal coming from on-chip peripheral output port. this case, automatically configured output mode. signal coming from input on-chip peripheral. this case, must configured Input without interrupt (Floating Input).
PROGRAMMING TIPS
Port
Open Drain Outputs used driving where several devices connected same line avoid conflicts: lines pulled high impedance) They wired together parallel increase current drive capability (I2C connections typically). Voltages driving Analog Input should always stay within absolute maximum ratings (Vss-0.3V Vdd+0.3V) Pull-up resistors typically deliver 50µA under toggling time output will approximately 30ns 50pF load
Ports Configuration Example
PBDR7 PBDRO
PBDR
PBDDR7 PBDDRO
Fill dedicated port registers order have following configuration: PB0:PB2
Push-Pull Output (high level)
PB3,PB4
Floating Input
Input with Interrupt
PBDDR
PBOR7 PBORO
Push-Pull Output (low level)
Ouput (High Impedance)
PBOR
Ports Configuration Example
PBDR7 PBDR0
Fill dedicated port registers order have following configuration: PB0:PB2
Push-Pull Output (high level)
PBDR
PBDDR7 PBDDR0
PB3,PB4
Floating Input
Input with Interrupt
PBDDR
PBOR7 PBOR0
Push-Pull Output (low level)
Ouput (High Impedance)
PBOR
8-Bit CORE Accu Index Index
EEPROM Data Optional features:
PORT 16-bit timer Peripheral Peripheral
Interrupt Controller Test/Vpp Reset Oscillator
Program Data bytes Data EEprom
Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Power Supply Watchdog Timer
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
Optional
EEPROM
Overview
Eeprom features:
Used store volatile data devices, multi-cycle write access, EEPROM cannot execute code (time access: cycle instead devices (XFlash), code executed EEPROM data.
parallel writing allows program bytes
Write cycle Write Erase cycles cycles Data retention years
EEPROM Block Diagram
INTERRUPT REQUEST
FALLING EDGE DETECTOR
HIGH VOLTAGE PUMP
EEPCR RESERVED E2ITE E2LAT E2PGM DECODER
EEPROM MEMORY MATRIX BITS
ADDRESS
ADDRESS DECODER
32*8 BITS DATA LATCHES
E2ITE disabled enabled E2LAT read mode write mode E2PGM prog finished started start programming
DATA MULTIPLEXER
BUFFER DATA
EEPROM Programming Cycle
Read operation possible INTERNAL PROGRAMMING VOLTAGE
Write data latches
Read operation allowed
Erase cycle
Write cycle
Tprog
E2LAT
E2PGM
INTERRUPT REQUEST
Interrupt vector fetch
PROGRAMMING TIPS
EEPROM
write done programming e2prom control register:
Step E2LAT order select write mode Step write bytes with MSbits common Step E2PGM start programming cycle Step wait E2PGM reset programming cycle
read performed read only memory: software overhead required halt instruction reset immediatly stop eeprom operation. wait mode effect
EEPROM
Programming mode
read memory location, E2LAT must cleared program EEPROM
BSET EEPCR, #E2LAT VARIABLE_i, E2LAT Write locations with same address
BSET EEPCR, #E2ITE Enable interrupts needed BSET EEPCR, #E2PGM Start programming .wait BTJT EEPCR, #E2PGM, wait Wait write cycle
8-Bit CORE
CONVERTER Optional features:
PORT 16-bit timer Peripheral Peripheral
Accu Index Index Program Data bytes Data EEprom
Interrupt Controller Test/Vpp Reset Oscillator
Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Power Supply Watchdog Timer
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
Optional
CONVERTER
Overview
8-Bit 10-Bit depending device:
8-Bit ST72254, ST72334, ST7Lite0 10-Bit ST7Lite2, ST7Lite3, ST7Lite1B, ST7UltraliteS, ST72264, ST72344, ST72521,ST7262
Conversion based successive approximations with sample hold circuitry analog channels Conversion time frequency (fADC=4MHz):
8-bit 10-Bit 3.5µs 7.5µs (but Fadc 2MHz) depending devices
Integrated op-amp zoom function (Lite family):
Gain: Range: [0-250mV] [0-430mv] depending devices
CONVERTER
Overview
ADON (ADC on/off bit) allows reduce power consumption. COCO indicates that conversion completed Special features:
Amplifier zooming (ST7Lite family) conversion interrupt generation (ST7Hub) Average Speed adjustment shot mode (ST7262)
CONVERTER
Overview
consumption modes
Wait mode doesn't affect Halt mode stops Conversion results analog input voltage Conversion linear analog voltage input VREF: converted result overflow indication) analog voltage input VSS: converted result underflow indication) voltage reference configuration: VREF VSSA available: 0.7xVDD VREF 5.5V with decoupling capacitors. VREF VSSA pins available: connection done internally
CONVERTER
Block diagram
AIN0 AIN1 SAMPLE HOLD ANALOG DIGITAL CONVERTER Fadc Fcpu Speed ADON Slow
(Control Status Register)
AIN15 AIN16
(Data Register High)
(Data Register Low)
CONVERTER PROGRAMMING TIPS
Procedure: Step Configure used analog input input floating mode pull-up, interrupt Step Select channel converted using bits CH[3:0] register ADON Step Wait until COCO set. continuous conversion performed Step Read data registers. reach best accuracy, impedance seen analog input must lower than 10Kohm.
CONVERTER TYPE DEVICE
ST7Lite0 TYPE ERROR (LSB) INPUTS 8-Bit 10-Bit 10-Bit 10-Bit 10-Bit ST7Lite2 ST7F264 ST7F324 ST7F521
CONVERTER SUMMARY
Which types ADC?
8-Bit 10-Bit
What configuration analog input pin?
used analog input must configured input floating mode pull-up, interrupt).
Which indicates completion conversion?
COCO bit. hardware cleared software.
What conversion time 10-Bit ADC?
conversion time 7.5µs fADC=2MHz some devices 3.5µs some others fADC=4MHz.
Configuration Example
SPEED ADON
ADCCSR
Fill ADCCSR register order have analog conversion AIN4 with fCPU/2 (Refer ST7Lite0 datasheet).
Configuration Example
COCO
ADON
ADCDR
tested
Fill ADCCSR register order have analog conversion AIN4 with fCPU/2 (Refer ST7Lite0 datasheet).
Exercise
Purpose
familiar with peripheral manipulation
Objectives
Step Convert analog input display conversion result PA[0:4] PB[0:2] with MSB. Step Convert analog input display follows: 1.5V 1.5V 3.5V 3.5V
Refer Training Manual: Exercise P.26/30
ANALOG COMPARATOR Optional features:
8-Bit CORE PORT Accu Index Index Program Data bytes Data EEprom 16-bit timer Peripheral Peripheral Interrupt Controller Test/Vpp Reset Oscillator Power Supply Watchdog Timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
Optional
Analog comparator
Features (lite1b device):
External internal reference voltage (1.2V fixed internal bandgap voltage levels between 3.2V 0.2V with 0.2V step) Output available externally possibility connect internally break function 12-bit ARTimer COMPIN+ also connected AIN0 COMPIN- AIN4 COMPIN+ COMPIN- then COMPOUT=0 COMPIN+ COMPIN- then COMPOUT=1 Stabilization time 500ns CINV invert comparator output (COMPOUT) Dedicated interrupt output change
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
PORT
Optional features:
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
16-bit timer Peripheral Peripheral
Interrupt Controller Test/Vpp Reset Oscillator
Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Power Supply Watchdog Timer
Optional
features
Division been removed from formula devices features: parity control reduced power consumption mode
devices flash) Other devices
ST72311 ST72511 ST72532 ST72334 ST72314 ST72124 ST72589 ST72389 ST7263 ST7285 ST72171 ST72121 ST72331 ST7226x ST7232x ST72521 ST7262 ST7263B ST7234x
Overview
Full duplex, asynchronous communication, pins (RDI TDO) Dual baud rate generator (maximum speed 500kHz 500000 bauds)
Fcpu bits bits Fcpu
Programmable word length
Noise, overrun frame error detection Parity control (new devices only!) Reduced power consumption mode (new devices only!)
Overview
Muting functions multiprocessor configurations Receiver wake function most significant idle line Interrupt sources with flags
Transmit data register empty Transmission complete Received data ready read Overrun error detected Parity error (new devices only!)
Flags without interrupt
Noise flag Framing error
Serial data format
8-bit word length
Data frame
Start
Possible parity
Stop
Idle frame Break frame
Extra
9-bit word length
Data frame
Start
Possible parity
Stop
Idle frame Break frame
Extra
Sampling Data Format
Time Data Sampled values Sampling Time Received value Flag
Each time
Divided clock Sampled times 8th, 10th count clock
flag sampling equal reception still available
Block Diagram
Data Register Transmit data register Receive data register
Transmit shift register
Receive shift register
Transmit rate Control Transmit Control Wake-Up Unit Receive Control
Receive rate Control
Control register
Status Register
fcpu
Control Register Interrupt Control
Removed devices
Clock selection
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
ETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
ERPR
EXTENDED RECEIVER PRESCALER REGISTER
EXTENDED PRESCALER RECEIVER RATE CONTROL EXTENDED PRESCALER
TRANSMITTER RATE CONTROL
TRANSMITTER CLOCK
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
Removed devices
RECEIVER CLOCK
RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR
Configurable Baud Rate (1/2)
devices
Conventional Baud Rate Generation Fcpu Extended Baud Rate Generation Fcpu
ETPR
Fcpu
Fcpu
ERPR
Others devices
Conventional Baud Rate Generation Fcpu Extended Baud Rate Generation Fcpu
ETPR
Fcpu Fcpu
ERPR
Configurable Baud Rate (2/2) devices
SCT2:SCT0 SCP1,SCP0 ETPR Baud rate 2400 4800 9600 19200 38400 38400 57600
Values given fCPU =8MHz
Other devices
SCT2:SCT0 SCP1,SCP0 ETPR Baud rate 1200 2400 4800 9600 19200 38400 57600
Values given fCPU =8MHz
Configuration Example
WAKE
SCICR1
TCIE ILIE
SCICR2
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
SCIBRR
Fill registers order configure cell
word reception 9600 Bauds word transmission 1200 Bauds Interrupt generation when RDRF (reception flag)
fCPU 8MHz
Configuration Example
SCID WAKE
SCICR1
TCIE
ILIE
SCICR2
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
SCIBRR
Fill registers order configure cell
word reception 9600 Bauds word transmission 1200 Bauds Interrupt generation when RDRF (reception flag)
fCPU 8MHz
8-Bit CORE
Serial Peripheral Interface Optional features:
PORT Accu Index Index Program Data bytes Data EEprom 16-bit timer Peripheral Peripheral
Interrupt Controller Test/Vpp Reset Oscillator
Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Power Supply Watchdog Timer
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
Optional
Overview (1/2)
cell allows full duplex synchronous serial communication between devices Main features:
Full duplex, wire synchronous transfers Master: frequency available. rates Slave mode: rates (Slave Select) also configurable through software (MISCR2 SPICSR Xflash HDFlash devices)
clock programmable: polarity phase
Overview (2/2)
Interrupt sources with flags
Data transfer: data transfer completed Overrun error: SPIF cleared (new devices only!) Fault flag: fault master mode detected
Flag without interrupt
Write collision: access SPIDR during transmission
Master-Slave communication
Master
8-bit Shift Register MISO MISO
Slave
8-bit Shift Register
MOSI
MOSI
Clock Generator
Block diagram
SPIDR
MISO MOSI
8-Bit Shift Register
SPIF WCOL
Read Read Buffer
Internal request
SPISR
MODF
Write STATE CONTROL
MISCR2
SPIOD
MASTER CONTROL
SPIE
SPICR
SPR2- MSTR CPOL CPHA SPR1 SPR0
SERIAL CLOCK GENERATOR
Single master configuration
Slave MOSI MISO Slave MOSI MISO Slave MOSI MISO Slave MOSI MISO
MOSI MISO Master
Configuration Example
SPIE
SPR2
MSTR
CPOL
CPHA
SPR1
SPRO
SPICR
Fill SPICR register order configure cell
Master mode Serial clock 5OOKHz (fCPU=8MHz) Sampling edge High level after clock signal interrupt generation
Configuration Example
SPIE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
SPICR
Fill SPICR register order configure cell Master mode Serial clock 5OOKHz (fCPU=8MHz) Sampling edge High level after clock signal interrupt generation
8-Bit CORE Accu Index Index
PORT
Optional features:
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
16-bit timer Peripheral Peripheral
Program Interrupt Controller Test/Vpp Reset Oscillator Power Supply Watchdog Timer Data bytes Data EEprom
Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Optional
Overview
cell provides specific sequencing, protocol, arbitration timing order reduce much possible software overhead Polling Management Interrupt Driven Cell Main features:
Multi Master capability Interrupt generation Standard mode 100kHz) Fast mode 400kHz) 7-bit 10-bit addressing
Protocol
START CONDITION
STOP CONDITION
Master Mode
Transfer Sequencing
7-bit Master Transmitter
Address DATA1 DATA2 DATA
7-bit Master Receiver
Address DATA1 DATA2 DATA
EV5: EVF=1, SB=1, cleared reading register followed writing register. EV6: EVF=1, cleared reading register followed writing register (for example PE=1). EV7: EVF=1, BTF=1, cleared reading register followed reading register. EV8: EVF=1, BTF=1, cleared reading register followed writing register.
Send master Send slave
Slave Mode
Transfer Sequencing
7-bit Slave Receiver
Address DATA1 DATA2 DATA
7-bit Slave Transmitter
Address DATA1 DATA2 DATA
EV1: EVF=1, ADSL=1, cleared reading register. EV2: EVF=1, BTF=1, cleared reading register followed reading register. EV3: EVF=1, BTF=1, cleared reading register followed writing register. EV4: EVF=1, STOPF=1, cleared reading register.
Send master Send slave
Clock Control
CLOCK CONTROL REGISTER (CCR)
FM/SM
FM/SM :Fast standard mode Standard mode Fast mode CC6-CC0 7bit clock divider
Standard Mode
Fast Mode
Fscl
Fcpu (2x[CC6.CC0]+2)
Fcpu Fscl= (3x[CC6.CC0]+2)
Block Diagram
DATA REGISTER (DR)
DATA CONTROL
DATA SHIFT REGISTER
COMPARATOR
ADDRESS REGISTER (OAR1) ADDRESS REGISTER (OAR2)
CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR) STATUS REGISTER (SR1) STATUS REGISTER (SR2)
CONTROL LOGIC
INTERRUPT
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
16-bit TIMER Optional features:
PORT 16-bit timer Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Interrupt Controlle Test/Vpp Reset Oscillator
Power Supply Watchdog Timer
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
Optional
16-bit TIMER
Overview
16-bit free running counter driven software configurable prescaler different modes:
Input capture pins): latch value counter after transition ICAPi Output compare pins): control output waveform indicate when period time over pulse: generation pulse when external event occurs PWM: generation signal with frequency pulse length software (OCR1 OCR2)
16-bit TIMER
Overview
timer clock provided
internal clock with configurable ratio external source: Fext must times slower than internal clock Fmax=2Mhz)
Timer clock Fcpu/4 Fcpu/2 Fcpu/8 External
16-bit TIMER
Block diagram
INTERNAL MCU-PERIPHERAL INTERFACE HIGH BYTE HIGH BYTE HIGH BYTE HIGH BYTE BYTE BYTE BYTE BYTE CLOCK 8-BIT BUFFER 16-BIT FREE RUNNING COUNTER COUNTER ALTERNATE REGISTER BYTE EXEDG
EXCLK
OUTPUT COMPARE REGISTER
OUTPUT COMPARE REGISTER
INPUT CAPTURE REGISTER
INPUT CAPTURE REGISTER
16-Bit INTERNAL TIMER
EDGE DETECT CIRCUIT EDGE DETECT CIRCUIT ICAP1
OVERFLOW DETECT CIRCUIT
OUTPUT COMPARE CIRCUIT
ICAP2
LATCH
OCMP1
STATUS REGISTER
ICF1
OCF1
ICF2
OCF2
LATCH
OCMP2
ICIE
OCIE
TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL2
OC1E OC2E
IEDG2 EXEDG
CONTROL REGISTER
CONTROL REGISTER
TIMER INTERNAL INTERRUPT
16-bit TIMER
Input capture
Captures counter value upon input signal edge detection Allows external pulse length measurement Internal safety process case critical interrupts timing
Timer Counter Register
ICAP1A
Edge Detector
Input Capture Register Software Maskable Interrupt Request
16-bit TIMER
Input capture
ICAP1 (Control Register ICAP2 EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1 ICIE IEDG1 (Status Register) IC2R IC1R ICF1 ICF2
16-BIT 16-BIT FREE RUNNING COUNTER
(Control Register IEDG2
16-bit TIMER
Output compare
Event generation (Interrupt request/bit toggling) whenever compare register matches counter Indicates period time elapsed controls output waveform Internal safety process case critical interrupts timing
Timer Counter Register Match? Output Compare Register Software Maskable Interrupt Request Pulse generation
16-bit TIMER
Output compare
16-BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT
OC1E OC2E
(Control Register (Control Register OCIE OLVL2 OLVL1 Latch Latch OCF1 OCF2 OCMP1
OCMP2
16-bit OC1R
16-bit OC2R
(Status Register)
16-bit TIMER
Real Time Clock
each Interrupt Routine Register content updated. There shift time (the counter never reset externally).
FREE RUNNING COUNTER VALUE
FFFFh
OCR+T
0000h
Timer
Timer
time
16-bit TIMER
pulse mode
Generation pulse synchronized with external event Allows Phase Locked Loop Generation Input Capture event counter reset timer output toggled Output compare event timer output toggled timer waits next Input Capture event
16-bit TIMER
pulse mode
Free running counter initialized FFFCh
When external event occurs ICAP1
OLVL2 level applied OCMP1 When free running counter reaches OC1R register value
OLVL1 level applied OCMP1
16-bit TIMER
pulse mode
FREE RUNNING COUNTER VALUE FFFFh FFFCh
Compare
0000h time
ICAP1
Input Capture Timer input
time
OCMP1
Ouput Compare Timer output
time
16-bit TIMER
mode
Automatic generation Pulse Width Modulated signal Period pulse length software:
first Output Compare Register OC1R contains length pulse second Output Compare Register OCR2 contains period pulse
Resolution steps (fCPU MHz): accuracy duty cycle
TIMER
mode
Free running counter initialized FFFCh
When free running counter reaches OC2R register value
OLVL2 level applied OCMP1 ICF1
When free running counter reaches OC1R register value
OLVL1 level applied OCMP1
TIMER
mode
FREE RUNNING COUNTER VALUE
Tmax Ttimer 65535
FFFFh FFFCh
Compare Compare
0000h time
OCMP1
Ouput Compare Timer output
OLVL2= OLVL1=0
time
PROGRAMMING TIPS
16-bit timer
Define Input capture pins inputs through corresponding Data Direction Register Read first then
counter buffered during read counter read accesses buffered value access high byte disables corresponding timer function until byte accessed Disable interrupts during word access
Writing counter resets timer FFFCh
write access valid (CLR TACLR TACLR,A)
PROGRAMMING TIPS 16-bit timer
Clearing status performed read access status register followed access (read write) byte corresponding register alternate counter register always matching counter alternate counter register when want clear Timer Overflow Flag interrupt generated compare when active, ICF1 every period generates interrupt aware that implicit reading performed emulator might clear status flags
PROGRAMMING TIPS
16-bit timer
buffered ACLR buffered
Read
ACHR
others Instructions
Read
ACLR
Returns buffered value Clear Returns ACLR buffered value Reset counter FFFCh Clear Reset counter FFFCh
Write
ACLR
Timer Configuration Example
ICIE OCIE TOIE FOLVL2 FOLVL1 OLVL2 IEDG1 OLVL1
TACR1
OC1E OC2E IEDG2 EXED
TACR2
Fill Timer registers order generate real time clock using interrupt strategy timer clock (fCPU 8MHz).
interrupt generated every using Output compare1. OCMP1 toggled every period
What value TAOC1HR TAOC1LR every period?
Timer Configuration Example
ICIE OCIE TOIE FOLVL2 FOLVL1 OLVL2 IEDG1 OLVL1
TACR1
OC1E
OC2E
IEDG2
EXED
TACR2
Fill Timer registers order generate real time clock using interrupt strategy timer clock (fCPU 8MHz).
interrupt generated every using Output compare1. OCMP1 toggled every period
What value TAOCIHR TAOC1LR every period? 5ms/1µs =5000 0x13
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
Lite Timers Optional features:
PORT 16-bit timer Peripheral Peripheral
Interrupt Controller Test/Vpp Reset Oscillator
Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Power Supply Watchdog Timer
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
Optional
Lite Timers Overview
(Lite0,Ultralite):
free running 8-bit (Lite0) 13-bit upcounter (Ultralite): timebase period (@Fosc=8MHz, overflow when counter reaches $F9) Maskable timebase interrupt Input capture with dedicated interrupt (wake from Halt capability) Watchdog: timeout @Fosc=8MHz, (WDGD) avoid reset. reset forced setting WDGRF bit. enabled through WDGE (software WDG) through option byte (hardware WDG).
(Lite1b,Lite2,Lite3):
free running 8-bit upcounters: with timebase other with programmable timebase period from 1.024ms steps (@Fosc=8MHz) maskable timebase interrupts Input capture with dedicated interrupt (wake from Halt capability)
8-Bit CORE
8-bit Auto Reload Timer Optional features:
PORT 16-bit timer Peripheral Peripheral
Accu Index Index Program Data bytes Data EEprom
Interrupt Controller Test/Vpp Reset Oscillator
Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Power Supply Watchdog Timer
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
Optional
Overview 8-bit ARTimer
Programmable Timer frequency (Fcounter) External Clock counter event capability independant signals (same frequency) Output compare timebase Interrupts Input capture Channels with Interrupts Timer implemented ST72171, ST72511R, ST72311R, ST72F521,ST7FLITE0,ST7FLITEUS
8-bit ARTimer
Fcounter definition
Finput could Fcpu Fext. Fext Fcpu/2. Counter incremented rising edge Finput.
Fcounter Finput Finput Finput Finput Finput Finput Finput Finput /128 Finput= 8MHz 8MHz 4MHz 2MHz 1MHz 500KHz 250KHz 125KHZ 62.5KHZ
Fcounter division Finput, acccording prescaler driven CC2-CC0 bits Control Register.
8-bit ARTimer
Autoreload Ouputs
Counter value
DCRx Duty Cycle Register
set, Interrupt generation
Auto Reload Register
PWMx Output
bit=1 bit=1
Time
Time DCRx Value ARR-1 PWMx (OPx=1) Level 1pulse Tcounter High Level
8-bit ARTimer
Input Capture
Interrupt generation CIEx Fcounter Counter Register ARTICx Input Capture ICRx Input Capture Register
bit=1
8-bit ARTimer
Programming Tips
Clearing OVF(Overflow) performed reading register. Clearing (Capture Flag performed reading ICRx register. HALT mode, Input capture Interrupt used wake ST7. HALT mode, Overflow Interrupt used wake ST7, external clock (Fext) used. (external event detector mode). aware that implicit reading performed emulator might clear status flags.
8-Bit CORE
12-bit Auto Reload Timers Optional features:
PORT 16-bit timer Peripheral Peripheral Accu Index Index Program Data bytes Data EEprom
Interrupt Controller Test/Vpp Reset Oscillator
Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Power Supply Watchdog Timer
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
Optional
Overview (1/2) 12-bit ARTimers
(lite0,ultralite):
external pins, clock Fcpu comes from Lite timer Maskable overflow interrupt signal generator (programmable duty cycle, polarity control, maskable compare interrupt, freq range 2kHz-4MHz Fcpu=8MHz) Output compare function
(lite2):
external pins independent outputs: BREAK (force break condition outputs) programmable duty cycle output mode, polarity control, maskable compare interrupt, freq range 2kHz-4MHz Fcpu=8MHz) 12-bit Input Capture function (ATIC pin): rising falling edge Maskable overflow interrupts Output compare function
Overview (2/2) 12-bit ARTimers
AT3: Dual Auto reload timer (lite3, lite1b)
external pins 12-bit upcounters! independent outputs: BREAK (force break condition outputs) programmable duty cycle output mode, polarity control, maskable compare interrupt, freq range 2kHz-4MHz Fcpu=8MHz), Dead time generation (for Half Bridge driving mode) 12-bit Input Capture function (ATIC LTIC pin): rising falling edge, long range input capture feature (Lite timer clock feds timer, signal LTIC: 20-bit cascaded) Maskable overflow interrupts Output Compare function
SPGA
Software Programmable Gain Amplifier
8-Bit CORE Accu Index Index PORT 16-bit timer Peripheral Peripheral Program Interrupt Controller Test/Vpp Reset Oscillator Power Supply Watchdog Timer Data bytes Data EEprom Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Optional features:
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
Optional
Software Programable Gain Amplifier OVERVIEW
Integrated RAIL RAIL OpAmp Internal programmable Gain Integrated reference voltage sources, dependent independent (Band-Gap). OpAmp Outputs internally connected input Interupt flag comparator mode Power on/off active power modes capability with PWM/ART output
SPGA
Block Diagram
SPGA1
NS1[2:0] bits OA1NIN AGND G1[2:0] bits
/16R R=2K
Programmable gain Op-Amp
VR1E, PS1[1:0] bits OA1PIN
R3=2K
Channel
OA1O
VR1[2:0] bits
Band Reference Voltage
(1.2V)
OA1V
8-Step Reference Voltage OA1IE Interrupt
Reference voltages: *1.2V, independant steps, dependant
Analog (Amplifier digital (Comparator) output
SPGA MODES
NS1[2:0] bits
OA1NIN
AGND R=2K VR1E, PS1[1:0] bits
G1[2:0] bits
Programmable gain Value
Channel
Inverter Inverter
OA1PIN
R3=2K VR1[2:0] bits
OA1O
OA1V OA1IE
Band Reference Voltage (1.2V)
8-Step Reference
Voltage
Interrupt
NS1[2:0] bits
OA1NIN
AGND R=2K VR1E, PS1[1:0] bits
G1[2:0] bits /16R
Channel
OA1PIN
R3=2K VR1[2:0] bits
OA1O
OA1V OA1IE
Band Reference Voltage (1.2V)
8-Step Reference Voltage
Interrupt
OPAMP MODES
Comparator mode
NS1[2:0] bits OA1NIN AGND /16R R=2K VR1E, PS1[1:0] bits OA1PIN R3=2K OA1O Band Reference Voltage (1.2V) VR1[2:0] bits 8-Step Reference Voltage OA1IE G1[2:0] bits
Channel
selectables positive input
Interrupt
SPGA MODES
NS1[2:0] bits OA1NIN AGND /16R R=2K PWM0R OA1PIN VR1E, PS1[1:0] bits R3=2K VR1[2:0] bits DDA/8 8-Step Reference Voltage AVCL=1 G1[2:0] bits
Channel Analog output sink
OA1IE Interrupt
External Capacitor
Band Reference Voltage (1.2V) Internal Resistor
Channel PWM0
8-bit PWM/ARTimer
Channel
8-Bit Digital Analog Converter
Op-Amps characteristics comparison
general purpose Rail Rail Consumption (mA) Output current (mA) Noise(nv*sqr(Hz)) Offset voltage (mV) Slow rate (v/us) Power supply range(v) ST72C171 (I/O) TS922 audio performance (I/O)
8-Bit CORE Accu Index Index Program Data bytes Data EEprom
PORT 16-bit timer Peripheral Peripheral
Optional features:
EEPROM converter Analog Comparator 16-bit Timer Lite Timers 8-bit Auto Reload Timer 12_bit ARtimers Programmable OpAmp
Interrupt Controller Test/Vpp Reset Oscillator
Peripheral Peripheral Peripheral Peripheral Peripheral Peripheral
Power Supply Watchdog Timer
Optional
High Networks
ENTERTAINMENT
AUDIO VIDEO speed 2.0B kbps Door
Module Radio Audio Power TVModule Car-Phone Navigation VideoBox Door Module Trunk Module Cond DoomControl Contr. Pannel. Light Front Wiper Left UART Node Node Wiper
BODY
COMFORT ACCESS
POWER-TRAIN
TRACTION STABILITY
Door Module Door Module Driver-Seat
Dashboard Gateway
Sensor Gearbox
Pass.-Seat Backseat Central Airbag Light Rear Immobiliser
Very high speed 100M
DIAGNOSIS ISO9141 10kbps
Traction
High speed CAN2.0B kbps 1Mbps
High Lights
Asynchronous Serial Communication Protocol Based
Multi-master concept CSMA/CA (Carrier Sense Multiple Access Collision Avoid) Message priority Object oriented communication node addressing, content identification Realtime capability message transfer latency System wide message consistence Error detection management mechanism
Topology
Sensor Signals Actuator Signals
Node Node Node
Controller differential voltage twisted wire Mbps
Transceiver
CANH
CANL
Standard Extended Frames
bits Arbitration Field Identifier Data, bytes bits bits bits Idle Control Field 0.64 bits Data Field Field bits Interframe space
IDE=0
delimiter slot
delimiter
2.0A (standard format: identifier)
bits Control Field 0.64 bits Data Field Data, bytes Field bits bits Interframe space bits
Arbitration Field Identifier Identifier
bits
IDE=1
delimiter slot
delimiter
2.0B (extended format: identifier)
Standard Extended Implementations
Implementation 2.0B Passive 2.0B Active
Standard send receive Extended check acknowledge Extended send receive
(destructive (destructive
(compliant)
2.0B passive active nodes cohabit same network
Characteristics
Wired-AND
Levels Recessive Dominant
Dominant Prevail
node node node recessive dominant
Access Arbitration
Node Node Node Node
Arbitration Phase Remainder Transmit Request
Node Node Node recessive dominant
Error Detection Transmitter
Error
Based "write verify" principle each sent read back transmitter values differ error detected Except during arbitration phase
Acknowledge Error
receiver considering frame correct acknowledge otherwise signal detected error with Error Frame transmitter missing acknowledge supposes only active node network
Error Detection Receiver
Error
transmitter
Stuff Error
More than identical bits detected
Error
received calculated values different
Form Error
fixed format bits correct delimiter delimiter Frame
Fault Confinement
Reset configuration Error Active blocks successive recessive bits
Error Passive
Basic Full
Full controller Many buffers (e.g. Sophisticated message filtering Dedicated Larger silicon (buffer size, filtering) Typical: body
Basic controller Tx/Rx buffers (e.g. Simple identifier filtering More overhead Less silicon
Typical: Engine management
Filters Possible Implementations
FULL Buffer allocation static based message Messages copied (automatic reply capability) Interesting great number buffers
Buffer
BASIC Buffer allocation dynamic based avalaibility Messages must copied (more load)
Match Filter
Buffer
Decreasing Priority
Buffer
Match Filter
Buffer
Buffer
Match Filters
Buffer
Cell Block Diagram
INTERNAL INTERFACE
Buffer Buffer Buffer Bytes Bytes Bytes
Filter Filter Bytes Bytes
PAGE CKDIV
BCDL
8-bit Shift Reg. CTRL STAT
passive Engine
Features
Comply with 2.0B passive specification Speed: 1MBits/s Basic capability with:
prioritized object messages data bytes each) acceptance filters match don't care)
Flexibility Full baud rate timing control
Buffers useable transmit receive buffers
Other Features
Optimized buffer flip-flopping capability transmission
Real-time performance minimum load Deterministic transfers Solves inner priority inversion problem with extra hardware
power mode Extensive interrupt scheme
Separate signalling successful transfers errors maskable sources: Rx123, error, error, overrun
Buffer Pagination
Saves address space
registers mapped onto addresses
Interrupt Status Interrupt Control Control Status Baud Rate Prescaler Timing Page Selection
Allows more efficient addressing mode
memory indirection
PAGED PAGES REGS PAGED REGS REGISTERS PAGED REGS PAGED REGS DIAGNOSIS, MESSAGE BUFFERS, ACCEPTANCE FILTERS
Page Mapping
Page LAST 10-BYTE BUFFER RESERVED RESERVED
CTRL STATUS
Page
Page
Page
Page FILTER
10-BYTE BUFFER
10-BYTE BUFFER FILTER
TEST REG.
ERROR COUNTERS
RESERVED
CTRL STATUS
RESERVED
CTRL STATUS
RESERVED
Buffer-dedicated Control Status Register (BCSR)
Reduces requirements reactiveness
Dual mapping interupt flags BCSR
same code handles buffer
Sleep Mode Wake
Software controlled power mode (RUN cleared)
Prescaler protocol engine stopped Need resynchronization
Automatic power mode after recessive bits
Protocol engine stopped need resynchronization (idle mode)
Wake-up upon reception dominant Possible wake pulse generation when leaving stand-by
Cell Certification
Validated with Bosch model patterns Certification going with expert third party (c&s)
Protocol compliance test according Bosch specifications interface test Cell robustness behaviour
Final silicon certification targeted 1Q99
ST725xx Kits
Development ST7MDT2-DVP2
Available User software development debugging Easy connection high speed node/network Compatible widespread Vector tools
Demonstration Board
Available Software functions controlled Visual
Visual
Intuitive discover exercice passive cell Existing network traffic monitoring messages generator function
VisualCAN Snapshot
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