SST39WF400B Organized 256K Single Voltage Read Write Operations 1

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SST39WF400B Organized 256K Single Voltage Read Write Operations 1

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Mbit (x16) Multi-Purpose Flash
SST39WF400B
Organized 256K Single Voltage Read Write Operations 1.65-1.95V Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption (typical values MHz) Active Current: (typical) Standby Current: (typical) Sector-Erase Capability Uniform KWord sectors Block-Erase Capability Uniform KWord blocks Fast Read Access Time Latched Address Data Fast Erase Word-Program Sector-Erase Time: (typical) Block-Erase Time: (typical) Chip-Erase Time: (typical) Word-Program Time: (typical) Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Flash EEPROM Pinouts command sets Packages Available 48-ball TFBGA (6mm 8mm) 48-ball WFBGA (4mm 6mm) Micro-Package 48-ball XFLGA (4mm 6mm) Micro-Package non-Pb (lead-free) devices RoHS compliant
PRODUCT DESCRIPTION
SST39WF400B 256K CMOS Multi-Purpose Flash (MPF) manufactured with proprietary, high-performance CMOS SuperFlash technology. split-gate cell design thick-oxide tunneling injector attain better reliability manufacturability compared alternate approaches. SST39WF400B writes (Program Erase) with 1.65-1.95V power supply. This device conforms JEDEC standard assignments memories. SST39WF400B features high-performance Word-Programming which provides typical Word-Program time µsec. uses Toggle Data# Polling detect completion Program Erase operation. On-chip hardware software data protection schemes protect against inadvertent writes. Designed, manufactured, tested wide spectrum applications, SST39WF400B offered with guaranteed typical endurance 100,000 cycles. Data retention rated greater than years. SST39WF400B suited applications that require convenient economical updating program, configuration, data memory. system applications, this significantly improves performance reliability, while lowering power consumption. inherently uses less
©2008 Silicon Storage Technology, Inc. S71370-01-000 7/08
energy during Erase Program than alternative flash technologies. When programming flash device, total energy consumed function applied voltage, current, time application. given voltage range, SuperFlash technology uses less current program shorter erase time; therefore, total energy consumed during Erase Program operation less than alternative flash technologies. These devices also improve flexibility while lowering cost program, data, configuration storage applications. SuperFlash technology provides fixed Erase Program times independent number Erase/Program cycles that have occurred. Consequently, system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. meet surface mount requirements, SST39WF400B offered 48-ball TFBGA, 48-ball WFBGA, 48-ball XFLGA packages. Figures assignments Table descriptions.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit (x16) Multi-Purpose Flash SST39WF400B
Device Operation
Commands, which used initiate memory operation functions device, written device using standard microprocessor write sequences. command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first.
Sector-/Block-Erase Operation
SST39WF400B offers both Sector-Erase BlockErase modes which allow system erase device sector-by-sector, block-by-block, basis. sector architecture based uniform sector size KWord. Initiate Sector-Erase operation executing six-byte command sequence with Sector-Erase command (30H) sector address (SA) last cycle. Block-Erase mode based uniform block size KWord. Initiate Block-Erase operation executing six-byte command sequence with Block-Erase command (50H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. End-of-Erase operation determined using either Data# Polling Toggle methods. Figures timing waveforms. commands issued during Sector- Block-Erase operation ignored.
Read
Read operation SST39WF400B controlled OE#; both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Figure
Word-Program Operation
SST39WF400B programmed word-by-word basis. sector where word exists must fully erased before programming. Programming accomplished three steps: Load three-byte sequence Software Data Protection. Load word address word data. During Word-Program operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. Initiate internal Program operation after rising edge fourth CE#, whichever occurs first. Once initiated, Program operation will completed within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored.
Chip-Erase Operation
SST39WF400B provides Chip-Erase operation, which allows user erase entire memory array state. This useful when entire device must quickly erased. Initiate Chip-Erase operation executing six-byte command sequence with Chip-Erase command (10H) address 5555H last byte sequence. Erase operation begins with rising edge sixth CE#, whichever occurs first. During Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored.
©2008 Silicon Storage Technology, Inc.
S71370-01-000
7/08
Mbit (x16) Multi-Purpose Flash SST39WF400B
Write Operation Status Detection
optimize system write cycle time, SST39WF400B provides software means detect completion Program Erase write cycle. software detection includes status bits-Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. completion nonvolatile Write asynchronous with system; therefore, either Data# Polling Toggle read occur simultaneously with completion Write cycle. this occurs, system erroneous result, i.e., valid data appear conflict with either DQ6. prevent spurious rejection event erroneous result, software routine must include loop read accessed location additional times. both Reads valid, then device completed Write cycle, otherwise rejection valid.
Toggle valid after rising edge fourth CE#) pulse Program operation. Sector-, Blockor Chip-Erase, Toggle valid after rising edge sixth CE#) pulse. Figure Toggle timing diagram Figure flowchart.
Data Protection
SST39WF400B provides both hardware software features protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: pulse less than will initiate write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.0V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Data# Polling (DQ7)
When SST39WF400B internal Program operation, attempt read will produce complement true data. Once Program operation complete, will produce true data. Although have valid data immediately following completion internal Write operation, remaining data outputs still invalid. Valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read will produce `0'. Once internal Erase operation complete, will produce `1'. Data# Polling valid after rising edge fourth CE#) pulse Program operation. Sector-, Block-, Chip-Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling timing diagram Figure flowchart.
Software Data Protection (SDP)
SST39WF400B provides JEDEC approved Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. This group devices shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15DQ8 VIH, other value, during command sequence.
Common Flash Memory Interface (CFI)
SST39WF400B contains information that describes characteristics device, supports both original Query mode implementation compatibility with existing devices, well general Query mode. enter Query mode, system must write three-byte sequence, same Product Entry command, with (CFI Query command) address 5555H last byte sequence.
Toggle (DQ6)
During internal Program Erase operation, consecutive attempts read will produce alternating `1's `0's, i.e., toggling between `0'. When Program Erase operation complete, will stop toggling device ready next operation.
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
Data Sheet enter general Query mode, system must write one-byte sequence using Entry command with address 55H. Once device enters Query mode, system read data addresses given Tables through system must write Exit command return Read mode from Query mode.
Product Identification Mode Exit/ Mode Exit
return standard Read mode, exit Software Product Identification mode issuing Software Exit command sequence. Software Exit command reset SST39WF400B Read mode after inadvertent transient condition that causes device behave abnormally. Software Exit/CFI Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform, Figure flowchart.
Product Identification
Product Identification mode identifies device SST39WF400B manufacturer SST. This mode accessed software operations. Software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Table software operation, Figure Software Entry Read timing diagram, Figure Software Entry command sequence flowchart. TABLE Product Identification Table
Address Manufacturer's Device SST39WF400B 0001H 272EH
T1.0 1370
Data 00BFH
0000H
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
X-Decoder
SuperFlash Memory
Memory Address
Address Buffer Latches Y-Decoder
DQ15
1370 B1.0
Control Logic
Buffers Data Latches
FIGURE Functional Block Diagram
VIEW (balls facing down)
SST39WF400B
DQ10 DQ11
DQ12 DQ13 DQ14 DQ15
1370 48-wfbga P02.0
FIGURE Assignments 48-Ball WFBGA 48-Ball XFLGA
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
VIEW (balls facing down)
SST39WF400B
DQ15
DQ14 DQ13 DQ12 DQ10 DQ11
1370 48-tfbga P01.0
FIGURE Assignments 48-ball TFBGA TABLE Description
Symbol AMS1-A0 DQ15-DQ0 Name Address Inputs Data Input/output Functions provide memory addresses. During Sector-Erase AMS-A11 address lines will select sector. During Block-Erase AMS-A15 address lines will select block. output data during Read cycles receive input data during Program cycles. Data internally latched during Program cycle. outputs tri-state when high. activate device when low. gate data output buffers. control Program operations. provide power supply voltage: Unconnected pins.
T2.0 1370
Chip Enable Output Enable Write Enable Power Supply Ground Connection
1.65-1.95V SST39WF400B
Most significant address SST39WF400B
TABLE Operation Modes Selection
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode Table
T3.0 1370
DOUT High High DOUT High DOUT
Address Sector Block address, Chip-Erase
VIH, other value.
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
Data Sheet TABLE Software Command Sequence
Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Query Entry5 General Query Mode Software Exit7/ Exit Software Exit7/ Exit Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H Data2 2AAAH 5555H
T4.0 1370
Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data2
Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H Data2
Write Cycle Addr1 5555H 5555H 5555H Data2 Data
Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data2
Write Cycle Addr1 SAX4
Data2
5555H
Software Entry5,6 5555H
Address format A14-A0 (Hex), Addresses AMS-A15 VIH, other value, Command sequence. Most significant address SST39WF400B DQ15-DQ8 VIH, other value, Command sequence Program word address Sector-Erase; uses AMS-A11 address lines Block-Erase; uses AMS-A15 address lines device does remain Software Product mode powered down. With AMS-A1 Manufacturer's 00BFH, read with SST39WF400B Device 272EH, read with Both Software Exit operations equivalent
TABLE Query Identification String1 SST39WF400B
Address Data 0051H 0052H 0059H 0001H 0007H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string "QRY"
Primary command Address Primary Extended Table Alternate command (00H none exists) Address Alternate extended Table (00H none exits)
T5.0 1370
Refer publication more details.
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
Data Sheet TABLE System Interface Information SST39WF400B
Address Data 0016H 0020H 0000H 0000H 0005H 0000H 0005H 0007H 0001H 0000H 0001H 0001H Data (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (00H pin) (00H pin) Typical time Word-Program Typical time size buffer program (00H supported) Typical time individual Sector/Block-Erase Typical time Chip-Erase Maximum time Word-Program times typical Maximum time buffer program times typical Maximum time individual Sector/Block-Erase times typical Maximum time Chip-Erase times typical
T6.0 1370
TABLE Device Geometry Information SST39WF400B
Address Data 0013H 0001H 0000H 0000H 0000H 0002H 007FH 0000H 0010H 0000H 0007H 0000H 0000H 0001H Data Device size Byte (0013H KByte) Flash Device Interface description; 0001H x16-only asynchronous interface Maximum number byte multi-byte write (0000H supported) Number Erase Sector/Block sizes supported device Sector Information Number sectors; 256B sector size) sectors (007FH 127) Bytes KByte/sector (0010H Block Information Number blocks; 256B block size) blocks (0007H Bytes KByte/block (0100H 256)
T7.1 1370
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Voltage Ground Potential -0.5V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Solder Reflow Temperature 260°C seconds Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
Operating Range
Range Commercial Industrial Ambient Temp +70°C -40°C +85°C 1.65-1.95V 1.65-1.95V
Conditions Test
Input Rise/Fall Time Output Load Figures
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
Power-Up Specifications
functionalities specifications specified ramp rate faster than 1.8V less than ms). addition, ramp rate slower than recommended. Table Figure more information. TABLE Recommended System Power-up Timings
Symbol TPU-READ1 TPU-WRITE1 Parameter Read Operation Write Operation Minimum Units
T8.0 1370
This parameter measured only initial qualification after design process change that could affect this parameter.
TPU-READ
1370 F37.1
FIGURE Power-Up Reset Diagram
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
Characteristics
TABLE Operating Characteristics, 1.65-1.95V1
Limits Symbol Parameter Power Supply Current Read Program Erase Standby Current2 Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage VDD-0.1 0.8VDD 0.2VDD Units Test Conditions Address input=VILT/VIHT, MHz, VDD=VDD CE#=VIL, OE#=WE#=VIH, I/Os open CE#=WE#=VIL, OE#=VIH CE#=VDD, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T9.0 1370
Typical conditions Active Current shown front page data sheet average values 25°C (room temperature), 1.8V. 100% tested. maximum SST39WF400B commercial grade devices. maximum SST39WF400B industrial grade devices. SST39WF400B commercial industrial devices, typical
TABLE Capacitance 25°C, MHz, other pins open)
Parameter CI/O
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T10.0 1370
CIN1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Reliability Characteristics
Symbol NEND1,2 TDR1 ILTH1 Parameter Endurance Data Retention Latch Minimum Specification 10,000 Units Cycles Years Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T11.0 1370
This parameter measured only initial qualification after design process change that could affect this parameter. NEND endurance rating qualified 10,000 cycle minimum whole device. sector- block-level rating would result higher minimum specification.
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
Characteristics
TABLE Read Cycle Timing Parameters
Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change Units
T12.0 1370
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Program/Erase Cycle Timing Parameters
Symbol TOES TOEH TWPH1 TCPH1 TSCE
Parameter Word-Program Time Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Pulse Width Pulse Width Pulse Width High Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Sector-Erase Block-Erase Chip-Erase
Units
TIDA1
T13.0 1370
This parameter measured only initial qualification after design process change that could affect this parameter.
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
ADDRESS AMS-0 TCLZ HIGH-Z TOLZ TOHZ TCHZ HIGH-Z
DQ15-0
DATA VALID
DATA VALID
1370 F03.0
Note: Most significant address SST39WF400B
FIGURE Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 5555 DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA)
1370 F04.0
2AAA
5555
ADDR
TWPH
Note: Most significant address SST39WF400B VIH, other value.
FIGURE Controlled Program Cycle Timing Diagram
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 5555 DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA)
1370 F05.0
2AAA
5555
ADDR
TCPH
Note: Most significant address SST39WF400B VIH, other value.
FIGURE Controlled Program Cycle Timing Diagram
ADDRESS AMS-0 TOEH TOES
DATA
DATA#
DATA#
DATA
1370 F06.0
Note: Most significant address SST39WF400B
FIGURE Data# Polling Timing Diagram
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
ADDRESS AMS-0 TOEH TOES
READ CYCLES WITH SAME OUTPUTS 1370 F07.0
Note: Most significant address SST39WF400B
FIGURE
0-1: Toggle Timing Diagram
SIX-BYTE CODE CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
1370 F08.0
Note: This device also supports controlled Chip-Erase operation signals interchangeable long minimum timings met. (See Table Most significant address SST39WF400B VIH, other value.
FIGURE Controlled Chip-Erase Timing Diagram
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
SIX-BYTE CODE BLOCK-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
1370 F09.0
Note: This device also supports controlled Block-Erase operation signals interchangeable long minimum timings met. (See Table Most significant address SST39WF400B VIH, other value.
FIGURE Controlled Block-Erase Timing Diagram
SIX-BYTE CODE SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
1370 F10.0
Note: This device also supports controlled Sector-Erase operation signals interchangeable long minimum timings met. (See Table Most significant address SST39WF400B VIH, other value.
FIGURE Controlled Sector-Erase Timing Diagram
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
THREE-BYTE SEQUENCE SOFTWARE ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
TWPH DQ15-0 XXAA XX55 XX90
1370 F11.0
TIDA
00BF Device
Note: Device 272FH SST39WF400B VIH, other value.
FIGURE Software Entry Read
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555
TWPH DQ15-0 XXAA XX55 XX98
1370 F12.0
TIDA
Note: VIH, other value.
FIGURE Query Entry Read
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ15-0
XXAA
XX55
XXF0 TIDA
TWHP
1370 F13.0
Note: VIH, other value.
FIGURE Software Exit/CFI Exit
VIHT INPUT VILT
1370 F14.0
REFERENCE POINTS
OUTPUT
test inputs driven VIHT (VDD) logic VILT (VSS) logic `0'. Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE Input/Output Reference Waveforms
TESTER
1370 F15.0
FIGURE Test Load Example
©2008 Silicon Storage Technology, Inc. S71370-01-000 7/08
Mbit (x16) Multi-Purpose Flash SST39WF400B
Start
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XXA0H Address: 5555H
Load Word Address/Word Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
Note:
VIH, other value.
1370 F16.0
FIGURE Word-Program Algorithm
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read word
Read
Program/Erase Completed
Read same word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
1370 F17.0
FIGURE Wait Options
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
Query Entry Command Sequence
Software Entry Command Sequence
Software Exit/CFI Exit Command Sequence
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXF0H Address:
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Wait TIDA
Load data: XX98H Address: 5555H
Load data: XX90H Address: 5555H
Load data: XXF0H Address: 5555H
Return normal operation
Wait TIDA
Wait TIDA
Wait TIDA
Read data
Read Software
Return normal operation
Note:
VIH, other value.
1370 F18.0
FIGURE Software ID/CFI Command Flowcharts
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
Chip-Erase Command Sequence Load data: XXAAH Address: 5555H
Sector-Erase Command Sequence Load data: XXAAH Address: 5555H
Block-Erase Command Sequence Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX10H Address: 5555H
Load data: XX30H Address:
Load data: XX50H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
Note:
VIH, other value.
1370 F19.0
FIGURE Erase Command Sequence
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
PRODUCT ORDERING INFORMATION
400B XXXX Environmental Attribute non-Pb Package Modifier balls balls possible positions) Package Type TFBGA (0.8mm pitch, 8mm) XFLGA (0.5mm pitch, 6mm) WFBGA (0.5mm pitch, 6mm) Temperature Range Commercial +70°C Industrial -40°C +85°C Minimum Endurance 10,000 cycles Read Access Speed Device Density Mbit Voltage 1.65-1.95V Product Series Multi-Purpose Flash
Environmental suffix denotes non-Pb solder. non-Pb solder devices "RoHS Compliant".
Valid combinations SST39WF400B SST39WF400B-70-4C-B3KE SST39WF400B-70-4C-D1QE SST39WF400B-70-4C-Y1QE SST39WF400B-70-4I-B3KE SST39WF400B-70-4I-D1QE SST39WF400B-70-4I-Y1QE
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2008 Silicon Storage Technology, Inc.
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Mbit (x16) Multi-Purpose Flash SST39WF400B
PACKAGING DIAGRAMS
VIEW
8.00 0.20
BOTTOM VIEW
5.60 0.80 0.45 0.05 (48X)
0.80 CORNER 4.00 6.00 0.20
SIDE VIEW
1.10 0.10
CORNER
SEATING PLANE 0.35 0.05
0.12
Note:
Complies with JEDEC Publication MO-210, variant 'AB-1', although some dimensions more stringent. linear dimensions millimeters. Coplanarity: 0.12 Ball opening size 0.38 0.05 48-tfbga-B3K-6x8-450mic-4
FIGURE 48-Ball Thin-Profile, Fine-Pitch Ball Grid Array (TFBGA) Package Code:
VIEW
6.00 ±0.08
BOTTOM VIEW
5.00 0.50 0.29 ±0.05 (48X)
CORNER
4.00 ±0.08
2.50
INDICATOR
0.50
DETAIL
0.52 max. 0.48 nom.
SIDE VIEW
0.05
SEATING PLANE
0.10 ±0.02
Note:
Complies with JEDEC Publication MO-207, variant CZB-4, dimensions except bump height much less. linear dimensions millimeters. Coplanarity: 0.08 ball present position gold-colored indicator present. Bump width interface package body surface 0.29 48-xflga-D1Q-4x6-32mic-5-2.0
FIGURE 48-Ball Extremely Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) Package Code:
©2008 Silicon Storage Technology, Inc. S71370-01-000 7/08
Mbit (x16) Multi-Purpose Flash SST39WF400B
VIEW
6.00 ±0.08
BOTTOM VIEW
5.00 0.50 0.32 ±0.05 (48X)
CORNER
4.00 ±0.08
2.50
INDICATOR
0.50
DETAIL
0.61 ±0.10
SIDE VIEW
0.08
SEATING PLANE
0.23 ±0.06 Note: Complies with JEDEC Publication MO-207, variant CZB-4, dimensions except nominal ball width larger. linear dimensions millimeters. Coplanarity: 0.08 ball present position gold-colored indicator present. Ball width interface package body surface 0.29
48-wfbga-Y1Q-4x6-320mic-5-2.0
FIGURE 48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) Package Code:
TABLE Revision History
Number Description Date 2008 2008
Initial release data sheet Updated Table page
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2008 Silicon Storage Technology, Inc. S71370-01-000 7/08

SST39WF400B Organized 256K Single Voltage Read Write Operations 1

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