The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284 Flash Organizatio


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



Mbit Burst Mode Concurrent SuperFlash ComboMemory
SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Flash Organization: PSRAM Organization: Mbit: 512k Mbit: Single Voltage Read Write Operations 1.7V 1.95V Program, Erase Read Bottom Boot Block Protection Bottom Boot Protection SST34WA32x3 Boot Protection SST34WA32x4 Multiplexed Data/Address reduced count A15-A0 multiplexed DQ15-DQ0 Addresses latched AVD# control input when BEF# Power Consumption (Typical) Standby Current: Flexible Flash Memory Organization Banks (512 Uniform KWord blocks Uniform Sectors (2KWord) entire memory array Concurrent Flash Memory Operation Read While Program (RWP) Read While Erase (RWE) Erase-Suspend/Erase-Resume Capability Read while Erase-Suspend Program while Erase-Suspend Read while Program during Erase-Suspend Industry Standard interface compatible Flash Synchronous Burst Mode Read MHz/66 MHz) Continuous, Sequential Linear Burst 8/16/32-words with Wrap-Around Burst 8/16/32-words without Wrap-Around Burst Burst Access Time: 13.5 ns/11.5 Asynchronous Random Address Access: PSRAM Burst Mode Read/Write Access MHz/66 MHz) Continuous, Sequential Linear Burst 4/8/16-words with Wrap-Around Burst 4/8/16-words without Wrap-Around Burst Burst Access Time: 13.5 ns/11.5 Asynchronous Random Address Access: Fast Program Erase (Typical) Word Program Time: Sector/Block Erase Time: Chip Erase Time: Expanded Block Locking blocks locked Power-up block locked/unlocked software Flash Security 128-bit unique factory preset 128-word non-erasable, lockable User-programmed bits ("OTP-like") End-of-Write Detection Data# Polling Toggle Packages Available 56-ball VFBGA 8mm) Superior Reliability Endurance sector: 1,000,000 cycles (typical) Greater than years Data Retention non-Pb (lead-free) devices RoHS compliant
PRODUCT DESCRIPTION
SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284 Mbit Mbit x16) ComboMemory devices which integrate Mbit flash with either Mbit PSRAM Mbit PSRAM multi-chip package (MCP). These devices utilize single 1.8V supply support burst mode access address data multiplex architecture. Combo Memory devices feature KWord uniform multi-bank flash memory architecture that consists four banks that contain individually-erasable blocks sectors increased flexibility. Either bottom bank, consists standard KWord blocks four parameter KWord blocks added granularity. remaining three banks each contain uniform KWord blocks. Each KWord block further divided into sixteen uniform KWord sectors. bank read while another bank being erased programmed, with zero latency. addition, these devices provide Erase-Suspend mode during which data programmed read from, sector block that being erased.
©2007 Silicon Storage Technology, Inc. S71358-01-000 11/07
SST34WA32A3/32A4/3283/3284 support synchronous Burst mode Read from address location flash memory array; Burst mode Read Write from address location PSRAM. Burst modes allow devices Read Write sequential data with significantly shorter latency delays than during random read write. protect against inadvertent write, flash memory bank offers expanded Block Locking scheme. Each block individually locked, bottom KWord parameter blocks each boot block individually locked finer granularity. addition, 136-words Security included flash memory, increases system design security. Designed, manufactured, tested applications requiring power small form factor SST34WA32A3/32A4/3283/3284 offered extended temperature with small footprint package meet board space constraints requirement. Figure assignments.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. ComboMemory trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
DEVICE OPERATION
SST34WA32A3/32A4/3283/3284 control operation either flash PSRAM memory bank using BEF# BES#. When BEF# low, flash bank activated Read, Program, Erase operation. When BES# low, PSRAM activated Read Write operation. assert BEF# BES# same time. bank enable signals asserted, contention will result device suffer permanent damage.
Concurrent Read/Write Operation multi-bank architecture flash memory this device allows zero latency Concurrent Read/Write operation whereby user read from bank flash while programming erasing another bank. With this operation user read system code bank while updating data another bank. unique feature SST34WA32A3/32A4/3283/3284 ability Read during Erase-Suspend even while Programming another bank. This feature designed respond interrupt requests during concurrent operation. Table Current Read/Write State. TABLE Concurrent Read/Write State
Current Operation Bank Read Read Write Write Operation Operation Possible Operation Other Bank Operation Write Read Operation Read Write
T2.0 1358
Flash Memory
Various commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences. Table page command sequence each function. flash memory SST34WA32A3/32A4/3283/3284 Auto Power mode which puts device "near stand-by" mode after data been accessed with valid Read operation. This reduces flash active read current. Auto Power mode reduces current consumption flash memory stand-by level. flash memory exits Auto Power mode with address flash control signal transition; therefore, there access time penalty Read cycles.
Note: purposes this table, "Write" means perform Sector/Block Word-Program operations applicable appropriate bank.
TABLE Critical Parameters
Critical Parameters Values Units 13.5 11.5
T1.0 1358
Random Address Access Time Synchronous Access Time MHz) Synchronous Access Time MHz)
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information Asynchronous Read default configuration flash memory power-up, after hardware reset RST# pin, Asynchronous Read. read data from flash memory array, system must assert valid address A/DQ15- A/DQ0 A20-A16, while AVD# BEF# VIL. During read, remains Asynchronous Read, rising edge AVD# latches address, driven VIL. data appears DQ15-A/DQ0. details, Figure Since memory array divided into four banks, each bank remains enabled read access until command register contents altered. Address access time (TACC) equal delay from stable addresses valid output data. chip enable access time (TCE) delay from stable addresses stable BEF# valid data outputs. output enable access time (TOE) delay from falling edge valid data output. internal state machine read array data upon device power-up after hardware reset. This ensures that spurious alteration memory content occurs during power transition. Burst Mode Read (Synchronous) SST34WA32A3/32A4/3283/3284 flash memory default configuration power-up after reset Asynchronous Read. However, configured operate Synchronous Read mode with continuous, sequential linear burst operation linear burst operation 16-, 32-words length with wrap-around. Before setting flash memory configuration Burst Mode, determine number wait states initial word access time (TIACC) desired Burst mode- continuous with, without, wrap-around. WAIT States power flash memory SST34WA32A3/32A4/ 3283/3284 defaults asynchronous read operation. device automatically enabled burst mode first rising edge input, while AVD# held addresses latched first rising edge CLK. Prior activating clock signal, system determines many wait states desired initial word (TIACC) each burst session. system then writes Configuration Register command sequence. device automatically delays RY/BY# needed number clock cycles data ready. Refer details "Handshaking Feature" section. initial word output Data TIACC after active edge first cycle. Each successive clock cycle automatically increments addresses counter. Subsequent words output Data TBACC after active edge each successive clock cycle. return device Asynchronous Read mode, either drive BEF# drive RST# VIL.
Power-up/ Hardware Reset
Asynchronous Read Mode Only
Active edge when AVD#
BEF# RST#
Synchronous Read Mode Only
1358 F01.0
FIGURE Synchronous/Asynchronous State Diagram
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information 16-, 32-Words Linear Burst Mode with WrapAround flash memory SST34WA32A3/32A4/3283/3284 device supports synchronous read operation with Linear Burst mode pre-determined word length with wrap-around. Groups words read this defined Table 32-words Linear Burst mode operation, starting address linear burst sequence address written device. Each successive clock cycle automatically increments address counter until address group reached. Once address reached, address wraps back first address selected group continues incrementing from there. example 8-word linear Burst mode with WrapAround follows: starting address 8-word mode words group start 10H, group 17H), address range read would 10H-17H, burst sequence would -12H -13H RY/BY# will indicate when valid data present data bus.
TABLE 16-, 32-Words Linear Burst Mode Wrap-Around Groups
Group Size Address Ranges
words words words
00000H 00007H 00000H 0000FH 00000H 0001FH
00008H 0000FH 00010H 0001FH 00020H 0003FH
00010H 00017H 00020H 0002FH 00040H 0005FH
(A)1 (B)1 (C)1 1FH)
T3.0 1358
multiple 00008H, multiple 00010H, multiple 00020H.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information 8-16-32-Words Linear Burst Mode without WrapAround SST34WA32A3/32A4/3283/3284 flash memory supports synchronous read operation with Linear Burst mode that does wrap around. fixed number words predefined 16-, 32-words read from consecutive addresses starting with initial word, which written device. Once fixed number words read completely, Burst Read operation stops RY/BY# output goes low. There group limitation there with Linear Burst with Wrap-Around. Table group definitions. example 8-word linear Burst mode without WrapAround follows: 8-word length Burst Read, starting address written device 39h, burst sequence would 39-3A-3B-3C-3D-3E-3F-40h, read operation will terminated 40h. similar fashion, 16-word 32-word modes begin their burst sequence starting address written device, Continuously Read predefined word length, words. operation similar Continuous Burst, will stop operation fixed word length. device crosses first 32-word address boundary during burst read, latency occur before data appears next address RY/BY# pulsing low. burst read start address 8-word boundary aligned latency does occur. host system crosses bank boundary, device will react same manner Continuous Burst. Continuous Linear Burst Mode flash memory SST34WA32A3/32A4/3283/3284 supports synchronous read operation with continuous, sequential linear Burst mode read. When this mode, Addresses automatically incremented linearly with every successive clock active edge. device reaches Highest Memory Location Address (FFFFFH), will continue continuous, sequential linear Burst read operation wrapping around Address 00000H. Burst operation will continue sequentially until another address latched AVD# pin, until BEF# driven VIH, until RST# driven VIL. When address latched AVD# with active edge CLK, burst read will start with initial address. continuous, sequential linear burst read sequence crosses bank boundary into bank that performing Programming Erasing operation, device will provide status information. Once system completed status read operation, device completed Program/Erase Operation, system allowed start burst read operation. this case address needs latched AVD# pin.
©2007 Silicon Storage Technology, Inc. S71358-01-000 11/07
synchronous, continuous, sequential, linear read array, latency output data occur when burst sequence crosses first 32-word address boundary. burst read start address 8-word boundary aligned delay does occur. burst read start address mis-aligned 8-word boundary, delay occurs once burst-mode read sequence. RY/BY# signal will indicate this delay system. Burst Register flash memory SST34WA32A3/32A4/3283/3284 defaults Asynchronous Read power-up. However, configured operate Synchronous Read Mode with continuous, sequential linear burst operation linear burst operation 16-, words length with wrap-around. Burst Register used configure type read access flash memory will perform setting desired Mode Burst (continuous wrap-around) number wait states initial word access time (TIACC). user Burst Register with Burst Register Command. Burst Register will retain information until reset RST# after PowerUp. Burst Register Command initiated executing three-cycle command sequence. last cycle, Data C0H, address bits A11-A0 555H, address bits A17-A12 code latched, shown Table Upon power-up hardware reset using RST# pin, device will default state. Burst Register cannot changed device Programming, Erasing, Sector Lock/Unlock mode.
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Burst Mode Configuration Command
Function Address Value values wait states initial word wait states initial word wait states initial word wait states initial word wait states initial word (default) Reserved Reserved values Continuous burst (default) 8-word linear burst 16-word linear burst 32-word linear burst linear burst with wrap-around (default) linear burst without wrap-around
T4.0 1358
Programmable Initial WAIT State
Burst Mode Type
Note: Device will default state after Hardware Reset (via RST# pin) after Power-Up.
Burst Suspend/Resume
Burst Suspend Resume feature allows system temporarily suspend synchronous burst operation flash memory during initial access, before data available, after device reading data. When burst operation suspended, previously latched internal data current state retained. Burst Suspend occurs when BEF# asserted, deasserted, de-asserted. must halted VIL. resume burst access, reasserted, afterwards restarted. Subsequent edges resume burst sequence where suspended. When Burst Suspend enabled flash will enter power mode, which current consumption reduced typically 1mA. RY/BY# pin, which controlled BEF#, will remain active placed into high-impedance state when de-asserted.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Writing Commands
SST34WA32A3/32A4/3283/3284 accept address data information form program commands. write command, system needs drive BEF#, VIL. addresses latched rising edge AVD# while keeping VIH, data latched rising edge while keeping
acceleration mode return read mode. first cycle contains data 90h, second cycle contains data 00h.
Eight-Word Program
Eight Word Program command provided fast data programming. room temperature normal VDD, command only enabled when Supervoltage (11.4V 12V). Eight Word Program Operation initiated with command then host provides eight consecutive data words. Eight Word program Asynchronous operation signal ignored. system drives BEF# Initial address latched rising edge first AVD# pulse while keeping high. Data latched rising edge each pulse while keeping high. Figure timings. Initial address AINI must 8-words boundary aligned otherwise part will force boundary alignment. Each subsequent pulse will automatically increment address word from AINI AINI user must issue data words programmed when Eight Word Program Mode.
Word-Program Operation
SST34WA32A3/32A4/3283/3284 programmed word-by-word basis. Before programming, erase sector programmed. Program operation accomplished three phases. First, Software Data Protection initiated using three-word load sequence. Next, word address word data loaded. Finally, internal Program operation initiates after rising edge fourth WE#. Program operation completes within SST34WA32A3/32A4/3283/3284 features programming acceleration mode faster programming. Once device enters programming acceleration mode, only write cycles required program word, instead four cycles required standard program command sequence. During Program operation, only valid reads within bank being programmed status reads (DQ7 Data# Polling DQ2/DQ6 Toggle Bits). commands issued during internal Program operation ignored. When Program Operation complete, bank will return Read Array Mode. Program operation timing diagram flowchart, Figure Figure
Standby Mode
SST34WA32A3/32A4/3283/3284 flash memory enter Standby mode when both BEF# RST# inputs held device requires standard access time (TCE) read access before ready read data.
Auto Power Mode
flash memory these devices have Auto Lower Power mode which puts near standby mode. Asynchronous read mode, this happens when addresses remain stable within TACC after data accessed with valid Read operation. This reduces flash active Read current typically. While BEF# low, device exits Auto Power mode with address transition control signal transition used initiate another flash Read cycle, with access time penalty. While Auto Power mode, output data latched always available system. synchronous read mode, after AVD# falling edge, flash memory automatically enters Auto Power mode when there active edge within TACC+ 60ns. flash memory exits Auto Power mode with active edge.
Programming Acceleration Operation
programming acceleration makes programing faster than using standard program command sequence because reduces standard four-cycle process cycles. unlock cycles initiates programming acceleration command sequence which followed third write cycle containing programming acceleration command. chip enters programming acceleration mode. program this mode, two-cycle programming acceleration program command sequence that required. first cycle contains programming acceleration command, A0h; second cycle contains program address data. Likewise, additional data programmed. initial unlock cycles required standard program command sequence eliminated. This reduces total programming time. Table programming acceleration command sequence requirements. system issues two-cycle programming acceleration reset command sequence exit programming
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Memory Architecture
flash memory SST34WA32A3/32A4/3283/3284 features 4-bank, KWord uniform multi-bank architecture. Either bottom bank consists standard KWord blocks four parameter KWord blocks added granularity. remaining three banks each contain uniform KWord blocks. KWord blocks further divided into uniform KWord sectors, respectively. Each block sector individually erased greater flexibility. device's unique bank architecture, allows reads from bank while another bank being erased (RWE) programmed (RWP). device also supports Erase-Suspend mode that allows programming data other sector block other than being erase-suspended. also read data memory sector block other than being erased during Erase-Suspend operation. Suspend operations cannot nested because system needs complete resume previously suspended operation before operation suspended.
Erase-Suspend, Erase-Resume Operations
Erase-Suspend command temporarily suspends Sector/Block-Erase operation which allows data read from memory location, programmed into sector block that suspended Erase operation. operation executed issuing EraseSuspend one-word command, B0H. device automatically enters Erase-Suspend Read Mode within TES, after Erase-Suspend command issued. Valid data read from sector block that suspended from Erase operation. Reading address location within erase-suspended sectors blocks will output toggling `1'. Table Write Operation Status, details. While Erase-Suspend mode, Word-Program operations allowed sectors blocks, with exception sector block selected Erase-Suspend. Word Program operation attempted suspended sector block, command rejected Program operation performed. system also issue Software Entry command during Erase-Suspend. After system issued Software Exit command, device automatically reverts Read Mode. resume Sector/Block-Erase operation that suspended, system must issue Erase-Resume command. operation executed issuing EraseResume one-word command, 30H, address last word sequence. erase operation being suspended re-suspended after resume, cumulative erase time needed greater than erase time non-suspended erase operation. accumulative erase time needed become very long hold time from Erase-Resume next EraseSuspend operation, TERH, less than 330µs. Erase-Resume command will ignored until program operations initiated during Erase-Suspend complete. Erase-Suspend Program Resume operations have influence program operation. Table details Suspend-Resume Concurrent operations
Sector/Block-Erase Operation
Sector/Block-Erase operation allows system erase device sector-by-sector block-by-block basis. SST34WA32A3/32A4/3283/3284 offers SectorErase Block-Erase modes. sector architecture based uniform sector size KWord. Block-Erase mode erases either regular KWord blocks smaller KWord Parameter Blocks. Sector-Erase operation initiated executing six-word command sequence with Sector-Erase command (50H) sector address (SA) last cycle. Block-Erase operation initiated executing six-word command sequence with Block-Erase command (30H) block address (BA) last cycle. Sector Block address latched during sixth cycle, either rising edge AVD# falling edge cycle, whichever occurs last, while command (30H/50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. End-of-Erase operation determined using either Data# Polling Toggle methods. Figure timing waveforms Figure flowchart.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Erase-Suspend Concurrent Banks State
Current Operation Bank Sector/Block-Erase-Suspend Sector/Block-Erase-Suspend Sector/Block-Erase-Suspend Sector/Block-Erase-Suspend Sector/Block-Erase-Suspend Sector/Block-Erase-Suspend Possible Operation Same Bank Read other Sector/Block within same Bank Read other Sector/Block within same Bank Program other Sector/Block within same Bank Program other Sector/Block within same Bank Operation Operation Possible Operation Other Concurrent Bank Operation Program Sector/Block Operation Read Sector/Block Read Sector/Block Program Sector/Block
T5.0 1358
Chip-Erase Operation
SST34WA32A3/32A4/3283/3284 provides ChipErase operation which allows user erase entire flash memory array state. This quick erase entire flash memory. initiate Chip-Erase execute six-word command sequence with ChipErase command, 10H, address 555H last word sequence. Erase operation begins with rising edge sixth WE#. During Erase operation, only valid reads Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored, including EraseSuspend Command. held VIL, more blocks locked, Chip Erase Operation disabled.
Ready (RY/BY#)
RY/BY# dedicated status output that indicates valid output data A/DQ15-A/DQ0 during synchronous burst reads. When RY/BY# asserted (RY/BY# VOH), output data valid read. When RY/BY# de-asserted (RY/BY# VOL), system will wait until re-asserted before expecting next word data. conditions cause RY/BY# output low: during initial access while burst mode, when device Continuous Burst Mode address crosses first word boundary. asynchronous, non-burst mode, RY/BY# does indicate valid invalid output data. Instead, RY/BY# when BEF# VIL, RY/BY# Hi-Z when BEF# VIH.
Write Operation Status Detection
SST34WA32A3/32A4/3283/3284 optimizes system flash Write cycle time providing software means detect completion Program Write cycle Erase Write cycle. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of- Write detection mode, which enabled after rising edge WE#, initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling (DQ7), Toggle (DQ6) Read simultaneous with completion Write cycle. this occurs, system will erroneous result. example, valid data appear conflict with either DQ6. order prevent spurious rejection when erroneous result occurs, software routine must include loop read accessed location additional time. both Reads indicate completion, then Write cycle completed.
Data# Polling (DQ7)
When SST34WA32A3/32A4/3283/3284 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth pulse Program operation. Sector/ Block Chip-Erase, Data# Polling valid after rising edge sixth pulse. Figure Data# Polling timing diagram Figure flowchart.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Toggle Bits (DQ6 DQ2)
During internal Program Erase operation, consecutive attempts read will produce alternating `1's `0's. example, toggling between `0'. When internal Program Erase operation complete, will stop toggling. device then ready next operation. Sector-, Block-, Chip-Erase, toggle (DQ6) valid after rising edge sixth pulse. will Read operation attempted Erase-Suspended Sector/Block. Program operation initiated sector/block selected Erase-Suspend mode, will toggle. additional Toggle available DQ2, which used conjunction with check whether particular sector being actively erased erase-suspended. Table shows detailed status information. Toggle (DQ2) valid after rising edge last pulse Write operation. Figure Toggle timing diagram Figure flowchart. TABLE Write Operation Status
Status Normal Standard Operation Program Standard Erase EraseSuspend Mode Read from Erase-Suspended Sector/Block Read from Non- EraseSuspended Sector/Block Program DQ7# Toggle Toggle Toggle Toggle Toggle
Data Protection
SST34WA32A3/32A4/3283/3284 provides both hardware software features protect flash memory data from inadvertent writes.
Hardware Data Protection
device provides following protection features prevent inadvertent writes flash memory: Noise/Glitch Protection: BEF# pulse less than will initiate write cycle. Power Up/Down Detection: Write operation inhibited when less than VLKO. Write Inhibit Mode: Forcing low, BEF# high, high will inhibit Write operation. This prevents inadvertent writes during power-up powerdown. When brought Supervoltage Eight Word Program command enabled. this case blocks temporarily unprotected regardless Block Locking Register. only device operation available when Eight Word Programming, must held above during other operations. Eight Word Programming provided fast data programming manufacturing environment. device will return normal operations when voltage each block locking status will depend Block Locking Register value (this value that each block before application ACC). must left floating unconnected. When brought sectors locked. should other conditions chip operations.
Data
Data
Data
Data
DQ7#
Toggle
T6.0 1358
Note: Note: DQ7, require valid address when reading status information. When Erase-Suspend Mode system read either synchronously (Burst) asynchronously.
SST34WA32A3/32A4/3283/3284 provides hardware block protection which protects KWords Blocks (SST34WA32x3), and/or BA65 BA66 (SST34WA32x4) flash memory. stands Block Address. KWord blocks, located bottom blocks, protected when held VIL. Program Erase operation these blocks disabled independently using Block Locking Register Status. user disable hardware protection outermost blocks driving VIH. this case, Protection Status outermost Blocks will revert what indicated corresponding Block Locking Registers. will latched specific time program erase sequence. prevent write outermost blocks, must held last write cycle sequence. example, write cycle program sequence write cycle erase sequence. using
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information programming acceleration feature, program cycle after programming acceleration command written, must held cycle. held Chip Erase Operation disabled. should pull-up state used. Software Block Locking prevent accidental data programming erasing, Block Lock command used. KWord main blocks parameter blocks independently locked. locked block able programmed erased. After Power-Up, blocks locked. Changing state-of-lock block done using Block Lock/Unlock Command (60H). Table third cycle address must point Block locked/unlocked. status Address will specify block must locked (A6=VIL) unlocked (A6=VIH). After third cycle, state-of-lock additional Blocks same Bank modified. Reading state-of-lock each block achieved using Read Block Locking Register command with TABLE Block Locking Register Data
Reserved Bits BLR[15:1] 000000000000000 000000000000000 Write-Lock bit: BLR[0] Code 0000H 0001H Lock Status Full Access Write Locked (Default State Power-Up)
T7.0 1358
address parameter that within block address space details, Table This command will read Block Locking Register. Block Locking Register 0000H Block Unlocked, 0001H Block Locked. Read Block Locking Register command written bank which either Read Mode EraseSuspend-Read mode. Only bank time switched Read Block Locking Register mode. return selected bank Read Mode, Erase-Suspend Read Mode, Software Exit/Block Locking Exit Command must issued system. Table internally ORed with Block Locking register. When low, blocks hardware write protected regardless state Write-Lock corresponding Block Locking registers. Clearing WriteProtect register when will have functional effect, even though register indicate that block longer locked. After third cycle, state-of-lock additional Blocks same Bank modified.
Note: default read status blocks upon power-up write-locked ("01H"). After power-up, when power supply (VDD) valid, register alterable.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Hardware Reset (RST#)
RST# provides hardware method reset flash memory devices read array data. When RST# held least in-progress operation will terminate flash memory will return Read Array mode. When internal Program/Erase operation progress, minimum period required after RST# driven high before valid Read take place. interrupted Erase operation must reinitiated after flash memory resumes normal operation mode ensure data integrity. RST# asynchronous input signal which aborts on-going Erase Program operation resets flash memory Read Array mode within time TReadyw. RST# asserted during flash Read Operation, required time reset device TReady. this point outputs tri-stated, device ignores Read/Write operations duration RST# pulse. RST# reset operation will also reset Flash Burst Configuration register Asynchronous Read Mode flash memory Read Array mode. Exit command return Read mode Erase-Suspend Read mode from Query mode.
Security
SST34WA32A3/32A4/3283/3284 device offers 136word Security space. Secure space divided into segments-one 8-word, 128-bit factory programmed segment 128-word user programmed segment. first segment programmed locked with unique 128-bit number. user segment left un-programmed customer program desired. program user segment Security Security Word-Program command required. Check end-of-write status Security reading toggle bits. Data# Polling detect end-ofwrite. Once programming complete, must locked using User Program Lock-Out, which disables future corruption this space. Neither segment-user factory programmed-can erased, regardless whether locked. Secure space queried executing threeword command sequence with Enter command (88H) address 555H last byte sequence. exit this mode, Exit command should executed. Refer Table more details. Security space located addresses 000000H 0000FFH. Factory programmed segment located addresses 000000H 000007H. User segment located address 000080H 0000FFH. Security Locked/Unlocked status read Address 000007FH. Table User Segment Security Unlocked. When `0', User Segment Security Locked. Once Query Security Command executed, system read Security space with normal Read cycles using valid address range 0000000H 00000FFH. Table more details.
Software Data Protection (SDP)
SST34WA32A3/32A4/3283/3284 provides JEDEC approved Software Data Protection scheme data alteration operations flash memory, such Program Erase. single word Program operation requires inclusion three-word sequence. three-word load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations; instance, during system power-up power-down. Erase operation requires inclusion six-word sequence. These devices shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device read mode within TRC. contents DQ15DQ8 VIH, other value, during command sequence.
TABLE Security Valid Range
Common Flash Memory Interface (CFI)
SST34WA32A3/32A4/3283/3284 contains information describe characteristics flash memory. order enter Query mode, system must write word command three-word sequence, with 98H- Query command-to address 555H last word sequence. Once device enters Query mode, system read data addresses given Tables through System write entry command when device Read Array mode also when device Product Identification Mode. system must write
©2007 Silicon Storage Technology, Inc.
Security Segment Factory Programmed User Programmed Locked/ Unlocked Status
Start Address 000000H 000080H 00007FH
Address 000007H 0000FFH
T8.0 1358
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Product Identification
Product Identification mode identifies devices manufacturer. software operation details Table Software Entry command sequence flowchart Figure Product Identification Mode (PIM) entered issuing unlock cycles. This must followed third cycle that contains Bank Address using A19) Product Identification Mode command. After this third cycle, addressed Bank enters Product Identification Mode. system read manufacturer Device number times without re-issuing command sequence. Product Identification command written bank that either Read Mode Erase-Suspend Read Mode. Product Identification Command cannot written while device Programming Erasing another bank. system addresses different Bank, memory array data read from device following normal Asynchronous Read operation. subsequent data will made available device Synchronous Mode. system must issue Software Exit command order return Bank previously Product Identification Mode into Read mode Erase-Suspend Read mode. TABLE Product Identification
Address Manufacturer's Device SST34WA32A3/3283 SST34WA32A4/3284 BKX0001H BKX0001H 975BH 975AH
T9.0 1358
Handshaking Feature
device equipped with handshaking feature that brings fastest initial latency this burst mode flash memory simply monitoring RY/BY# signal from device determine when initial word burst data ready read. this handshaking mode, microprocessor does need register number initial wait clocks. device will indicate when initial word burst data valid rising edge RY/BY# after goes low. handshaking feature used burst mode performance optimization, then host system must appropriate number wait states flash device depending clock frequency. "Configuration Register Command" section more information.
Power-up/Power-down Sequencing
There restrictions sequencing during powerup power-down. Setting RST# level required during entire power sequence until respective supplies reach their operating voltages. Once reach their respective operating voltages, setting RST# level allowed.
Data 00BFH
BKX0000H
Note: Bank Address, using A19.
Product Identification Mode Mode Security Block Locking Exit
order return device standard Read Array Mode, Software Product Identification Security Block Locking Modes must exited. Exit accomplished issuing Software Product Identification Security Block Locking Modes Exit command sequence, which returns device Read mode. This command also used reset device Read Array Mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Software Product Identification Security Block Locking Query/Exit command cannot executed concurrent Program/ Erase operations. Table software command code, Figure flowchart.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
RD/BY# Buffer
RD/BY#
A/DQ15-A/DQ0
Detector Input/Output Buffers Y-Gating RST# State Control Command Register Data Latch Erase Voltage Generator Voltage Generator Y-Decoder Amax Burst State Control Burst Address Counter
1358 B01.0
Cell Matrix
X-Decoder
Timer
BEF#
Chip Enable Output Enable Logic
Address Latch A/DQ15-A/DQ0 Amax -A16
AVD#
FIGURE Flash Memory Functional Block Diagram
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE SST34WA32A3/3283, Mbit Concurrent SuperFlash Multi-Bank Memory Organization
Bank Block BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA21 BA22 BA23 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BA37 BA38 BA39 BA40 BA41 BA42 Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE SST34WA32A3/3283, Mbit Concurrent SuperFlash Multi-Bank Memory Organization
Bank Block BA43 BA44 BA45 BA46 BA47 BA48 BA49 BA50 BA51 BA52 BA53 BA54 BA55 BA56 BA57 BA58 BA59 BA60 BA61 BA62 BA63 BA64 BA65 BA66 Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Address Range 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh
T10.0 1358
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE SST34WA32A4/3284, Mbit Concurrent SuperFlash Multi-Bank Memory Organization
Bank Block BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA21 BA22 BA23 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BA37 BA38 BA39 BA40 BA41 BA42 Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE SST34WA32A4/3284, Mbit Concurrent SuperFlash Multi-Bank Memory Organization
Bank Block BA43 BA44 BA45 BA46 BA47 BA48 BA49 BA50 BA51 BA52 BA53 BA54 BA55 BA56 BA57 BA58 BA59 BA60 BA61 BA62 BA63 BA64 BA65 BA66 Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Address Range 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F9FFFh 1FA000h-1FBFFFh 1FC000h-1FDFFFh 1FE000h-1FFFFFh
T11.0 1358
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
PSRAM
Self-Initialization power-up PSRAM, self-initialization process begins. During initialization VDDQ must simultaneously applied BES# must remain High. Selfinitialization requires 150µs after VDDQ stable above 1.7V. After completion self-initialization, default settings Configuration Register (BCR) Refresh Configuration Register (RCR) configured device ready normal operation.
1.7V VDD, VDDQ TPUS 150µs Device Initialization
1358 F55.0
latency. This requires controller monitor WAIT refresh cycle conflicts. Fixed latency improves performance lower clock frequencies sending first data word after worst case access delay. this feature when controller cannot monitor WAIT. When burst initiates, WAIT asserted; then deasserted when data transferred into, memory. Stopping High suspends Bursts. While burst suspended, another device uses data then must driven High disable outputs. Otherwise, remain Low. During burst suspend, WAIT remains active other devices share WAIT connection controller. resume burst, drive Low. After valid data available bus, restarted. refresh cycle limits time that BES# stay low. BES# remains burst suspend longer than TBEPS, then BES# must driven High burst restarted with BES# AVD# cycle. Table details PSRAM operation Burst mode.
Device ready normal operation
FIGURE Power-Up Initialization Timing
Asynchronous Mode
device configuration power-up Asynchronous Random Read. read data from PSRAM memory array, system must assert valid address multiplexed address/data while BES# AVD# VIL. During read, remains VIH, rising edge AVD# latches address, driven VIL. data appears A/DQ15 A/DQ0 after TBES. write data, drive BES#, WE#, LBS#/UBS# while valid address asserted multiplexed address/data bus. Driving AVD# latches address drives data onto bus. "don't care" state during Asynchronous Random Write mode, override OE#. terminate Write operation, deassert BES#, WE#, LBS#/UBS#. Table details PSRAM operation during Asynchronous mode.
Mixed Mode
Mixed mode combines synchronous Read Asynchronous Write seamlessly interface with legacy burst mode flash memory controllers; supported when configured synchronous operation. Hold entire sequence asynchronous Write. Latch target address using AVD#. When transitioning between mixed more fixed latency enabled, BES# driven High. BES# must exceed TBEPS. WAIT WAIT output connects RY/BY# SST34WA32A3/32A4/3283/3284 internally. This signal coordinates transactions synchronous multiple memory systems. After Read Write initiated, WAIT activates because burst mode, PSRAM requires additional time before transferring data. Reads, WAIT active until valid data output; Writes, WAIT indicated when data accepted. Data burst progresses successive rising clock edges when WAIT inactive. Until first data valid, BES# must remain asserted. prevent data corruption, bring BES# High during initial latency. Read launches during on-chip refresh when using variable initial access latency (BCR[14] WAIT
S71358-01-000 11/07
Burst Mode
High-speed, synchronous PSRAM Read Write enabled burst mode operation. access address latches next clock after AVD# BES# driven low. Read Write indicated during first clock rising edge. Fixed-length bursts 16-words continuous, bursts selected BCR. Latency number clock cycles before initial data transferred between processor PSRAM, BCR. Initial Read latency configured either fixed variable; however, Write latency always fixed. achieve minimum latency high clock frequencies, configure Burst PSRAM variable
©2007 Silicon Storage Technology, Inc.
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information prevents collision. When collision occurs, WAIT asserts until refresh complete. Read continues normally once refresh complete. During asynchronous Read Write, ignore asserted WAIT. Using PSRAM burst mode with fixed latency (BCR[14] does require WAIT monitoring. WAIT will indicate when valid data available start burst row. However, when WAIT monitored, controller must stop burst access boundaries.
Temperature Compensated Refresh
on-chip temperature sensor automatically regulates refresh rate according operating temperature. Temperature compensated refresh (TCR) continually adjusts refresh rate ensures that sufficient refreshes occur various temperatures.
Deep Power-Down
system does require storage provided PSRAM, Deep Power-down (DPD) disables refresh related activities; however, will corrupt stored data. After re-enabling refresh activity, device requires initialize before normal operations resume. During this time, current consumption higher than during specified standby levels, considerably lower than active current specification. enable DPD, Write using CRES software access sequence. starts when BES# driven High; disabled next time BES# driven remains least 10ns.
Processor READY
Other WAIT Device
Burst Pseudo SRAM WAIT
Other WAIT Device External Pull-Up/ Pull-Down Resistor
1358 F52.0
FIGURE WAIT Configuration
LBS#/UBS#
Byte-wide data transfers accomplished LBS# UBS# enable signals. During Read, enabled bytes driven A/DQs disabled bytes A/DQs into High-Z state. Disabled bytes transferred during Write, their values unchanged. During asynchronous Write, data latched rising edge first occurrence either BES#, WE#, LBS#/UBS#. data will receive transmit data when both LBS# UBS# disabled (High) during operation; however, long BES# remains Low, device remains active mode.
Standby Mode
After completion Read Write, when address control inputs static extended period, PSRAM enters Standby mode when BES# driven High. Standby, power consumption reduced level necessary perform DRAM refresh. Standby continues until change address PSRAM control input occurs.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Amax-A16
Address Decode Logic BES# AVD# CRES LBS# UBS# Wait Configuration Register (BCR) Control Logic Refresh Configuration Register (RCR)
DRAM Memory Array A/DQ7-A/DQ0 Input/ Output Buffers A/DQ15-A/DQ8
1358 F51.1
FIGURE PSRAM Functional Block Diagram
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
PSRAM Configuration Registers
SST34WA32A3/32A4/3283/3284 features PSRAM configuration registers: Configuration Register (BCR) Refresh Configuration Register (RCR). Register Read/Program using CRES When control register enable (CRES) input High, access registers either asynchronous synchronous mode. When CRES Low, access PSRAM array with either Read Write operation. Values written configuration registers using addresses Amax During synchronous Write, LBS# UBS# Don't Care values latched rising edge either AVD#, BES#, WE#, depending which occurs first. SST34WA32A3/32A4, when 10b, accessed; when 00b, accessed A17-A16 must SST34WA3283/3284, when A18-A17 00b, accessed; when A18-A17 01b, accessed must During reads, register bits output A/DQ15-0 address inputs other than SST34WA32A3/32A4, SST34WA3283/
3284, Don't Care. completion Read Write operation register, immediately execute Read memory array. must during register Read Program using CRES. Register Read/Program using Software Method software method disable enable Deep Power-down mode (bit RCR). Read Program RCR, first issue Read Configuration Register sequence then issue Configuration Register sequence, while CRES Don't Care. Both Read Configuration Register sequence Configuration sequence require four read write cycles which performed asynchronous mode. read cycles followed write cycle address-a unique address location-indicates whether next operation read write. During third cycle, write 000h access 001h access BCR, next cycle. configuration register written read from, during fourth cycle. Software Read/Program timings asynchronous write read timings. identical
Amax-A16 BES# LBS#/UBS# AVD# A/DQ15-A/DQ0
Address
Address
Address
Address
Address
Address
Address
Note1
Address
Note2
Read Cycle
Read Cycle
Write Cycle
Write Cycle
1358 F03.0
program last write cycle, A/DQ15-A/DQ0 must `0001h' `0000' respectively. Configuration Data Only Configuration Register(BCR) Refresh Configuration Register (RCR) modified. control signals BES#, OE#, WE#, LBS# UBS#, must toggled shown above figure.
FIGURE Configuration Register Software Method
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Amax-A16 BES# LBS#/UBS# AVD# A/DQ15-A/DQ0
Address
Address
Address
Address
Address
Address
Address
Note2
Address
Note3
Read Cycle
Read Cycle
Write Cycle
Read Cycle
1358 F04.0
highest order address location modified during this operation. read BCR, RCR, last read cycle, A/DQ15-A/DQ0 must `0001h' `0000h' respectively. Configuration Data Out. control signals BES#, OE#, WE#, LBS# UBS#, must toggled shown above figure.
FIGURE Read Configuration Register Software Method
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Configuration Register
A/DQ15
Operating Mode
A/DQ14
Initial Latency
A/DQ[13:11]
Latency Counter
A/DQ10
WAIT Polarity
A/DQ9 Reserved
A/DQ8
A/DQ[7:6] A/DQ[5:4] Reserved Drive
Strength
A/DQ[3]
A/DQ[2:0]
T12.0 1358
Burst wrap length apply both READ WRITE operations.
Symbol Operating Mode
Initial Latency
Latency Counter
WAIT Polarity
Drive Strength
Reserved
Function Operating Mode Synchronous Burst Access Mode Asynchronous Access Mode (default) Initial Access Latency Variable (default) Fixed Latency Counter 000b: Reserved 001b: Reserved 010b: Code 011b: Code (default) 100b: Reserved 101b: Reserved 110b: Reserved 111b: Reserved WAIT Polarity Active Active HIGH (default) WAIT Configuration Asserted during delay Asserted data cycle before delay (default) Output Impedance 00b: Full Drive (default) 01b: Reserved 10b: 11b: Reserved Burst Wrap Burst wraps within burst length Burst wrap (default) Burst Length 001b: words 010b: words 011b: words 111b: Continuous burst (default) Others: Reserved Must
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Refresh Configuration Register Mapping
A/DQ[15:5] Reserved A/DQ4 A/DQ[3:0] Reserved
T13.0 1358
Symbol
Function Deep Power Down Enable Disable (default) Must
Reserved
TABLE Sequence Burst Length
Starting Address Decimal
0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14
Burst Wrap BCR[3] Wrap
4-Word Burst Length Linear
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
8-Word Burst Length Linear
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
16-Word Burst Length Linear
Continuous Burst Linear
0-1-2-3-4-5-6-. 1-2-3-4-5-6-7-. 2-3-4-5-6-7-8-. 3-4-5-6-7-8-9-. 4-5-6-7-8-9-10-. 5-6-7-8-9-10-11-. 6-7-8-9-10-11-12-. 7-8-9-10-11-12-13-. 14-15-16-17-18-19-20-. 15-16-17-18-19-20-21-. 30-31-32-33-34-. 31-32-33-34-35-. 0-1-2-3-4-5-6-. 1-2-3-4-5-6-7-. 2-3-4-5-6-7-8-. 3-4-5-6-7-8-9-. 4-5-6-7-8-9-10-. 5-6-7-8-9-10-11-. 6-7-8-9-10-11-12-. 7-8-9-10-11-12-13-. 14-15-16-17-18-19-20-. 15-16-17-18-19-20-21-. 30-31-32-33-34-35-36-. 31-32-33-34-35-36-37-.
T14.0 1358
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
DESCRIPTION
RY/BY# VDDQ AVD# LBS# UBS# RST# BEF#
VSSQ
A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8
A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VDDQ A/DQ1 A/DQ0
BES# CRES
FIGURE Assignments 56-ball VFBGA (6mm
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Descriptions
Symbol -A16 A/DQ15-A/DQ0 BEF# RST# RY/BY# AVD# Name Address Inputs Functions provide memory addresses.
Multiplexed Address/Data Sixteen least-significant Addresses multiplexed with Data Input/output. outputs tri-state when BEF# high. Flash Memory Enable Output Enable Write Enable Hardware Reset Ready Output Clock Address Valid Input Write Protect Power Supply activate flash memory bank when BEF# low. gate data output buffers control Write operations reset return flash memory Read mode RY/BY# signal when Flash memory selected. WAIT signal when PSRAM selected. increment internal address counter (after initial output delay) when part Burst Mode. required asynchronous mode. indicate device that valid Address present Address protect unprotect bottom KWord outermost sectors) flash memory bank from Erase Program operation. Supervoltage (11.4V 12V) input enable eight word programming flash memory bank. When locks sectors. Should other conditions. provide power Input/Output Buffers. provide 1.7-1.95V power supply voltage. VDDQ need shorted together application circuit. VSSQ need shorted together application circuit. Unconnected pins Don't make connection these pins. When high, Write operations load Refresh configuration register, configuration register Device register. Activate PSRAM when low. Gates data lower byte data during write operation Data gated from lower part selected address during read operation. Gates data upper byte data during write operation Data gated from upper part selected address during read operation.
T15.1 1358
VDDQ VSSQ CRES BES# LBS# UBS#
Power Supply Power Supply Ground Ground Power Supply Connection Reserve future Configuration Register Enable (PSRAM) PSRAM Memory Enable Lower Byte Control (PSRAM) Upper Byte Control (PSRAM)
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Flash Operation Mode Selection
Mode Asynchronous Read Program Erase BEF#1 AVD# Pulse Pulse Pulse CLK2 A/DQ15-0 Sector block address, XXH2 Chip-Erase Table Table RST#
Standby Write Inhibit Hardware Reset Product Identification Mode (Manufacturer) Product Identification Mode (Device)
High I/O/ DOUT High DOUT High Manufacturer's (00BFH) Device (xxxxH)
Table Table
T16.0 1358
BEF# BES# cannot same time. Default Clock Active edge rising edge. VIH, other value. Device SST34WA32x3 975BH SST34WA32x4 975AH.
TABLE Flash Burst Mode Selection
Mode Load Starting Burst Address Automatic Address Advance during Burst Read BEF#1 AVD# Pulse Pulse Active Edge Active Edge Active Edge Active Edge DOUT High High High High Address RST#
T17.0 1358
Terminate Current Burst Read (with BEF#) Terminate Current Burst Read with RST# Terminate Current Burst Read Start Burst Read Burst Suspend
BEF# BES# cannot same time. VIH, other value.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE PSRAM Operation Mode Selection Asynchronous
Mode1 Word Read Lower Byte Read Upper Byte Read Word Write Lower Byte Write Upper Byte Write Output Disable/ Operation Deep Power-Down3 Standby Assert going BES#2 AVD# UBS# LBS# CRES Amax Address Valid Address Valid Address Valid Address Valid Address Valid Address Valid A/DQ7-0 A/DQ15-8
Address in/Data Valid Address Data Valid High-Z High-Z Address Data Valid
Address in/Data Valid Address Data Valid Data Valid Data Valid Address Data Valid
High-Z High-Z High-Z
T18.0 1358
clock signal (CLK) must remain asynchronous operating mode. BEF# BES# cannot same time. device enters Deep Power-Down mode driving chip Enable Signal, BES#, from High with `0'. device remains Deep Power-Down mode until BES# goes again held TCW. Device reading programming registers CRES controlled method software method.
TABLE PSRAM Operation Burst Mode
Mode Initial Burst Read Subsequent Burst Read Initial Burst Write Subsequent Burst Write Operation Standby Deep Power-Down CLK1 rising rising rising rising rising BES#2 AVD# UBS#/ LBS# High-Z Low-Z WAIT CRES Amax Address Valid Address Valid A/DQ10-0 Address Valid Data Valid Address Valid Data Valid High-Z High-Z High-Z
T19.0 1358
Configuration Register output during initial burst operation (read write). following read write operations similar subsequent burst operations. BES# must held equivalent single-word burst operation BEF# BES# cannot same time.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Software Command Sequence
Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Suspend Resume Block Lock/ Unlock5 Write Cycle Addr1 555H 555H 555H 555H XXXH XXXH XXXH Data2 XXXH 2AAH 2AAH 2AAH 2AAH BLAX6 BKX55 555H 555H 555H SIWA8 Data 0000H Table Table Write Cycle Addr 2AAH 2AAH 2AAH 2AAH Data Write Cycle Addr 555H 555H 555H 555H Data Write Cycle Addr 555H 555H 555H Data Data 2AAH 2AAH 2AAH SAX4 Write Cycle Addr Data Write Cycle Addr Data
BAX4 555H
Read Block Lock- 555H Register Entry/Query Security User Security Program User Security Program LockOut Software Entry9, Query Entry Software Exit11/CFI Exit/ Exit Query Entry cycles) 555H 555H 555H
555H BKX55H
2AAH
BKX55
Table Table
555H
2AAH 2AAH
BKX55 555H
Software Exit/ 555H Exit/ Security Exit cycles) Burst Mode Configuration Register Eight Word Program Programming Acceleration Mode Entry Programming Acceleration Program14 555H
2AAH
CRX55 5H12
A0H13 Table Table Cycle Seq. Cycle Seq. 2AAH 555H
555H
Data
Programming Acceleration Program Reset15
T20.0 1358
Address format A11-A0 (Hex) Addresses A12-A20 VIH, other value, Command sequence SST34WA32A3/32A4/3283/3284.
©2007 Silicon Storage Technology, Inc. S71358-01-000 11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
DQ15-DQ8 VIH, other value, Command sequence Program Word address. Sector-Erase; uses A20-A11 address lines Block-Erase; uses A20-A13 address lines indicates Block Locking Register Data: 0000H Block Unlocked, 0001H Block Locked. BLAX indicates Address Block Locked/Unlocked; uses -A13 address lines. This composed Block Address (BA) either Unlock Lock. With A20-A8 Security information read with A7-A0 Factory Unique read Address Range: 000000H 000007H (128-bit). This segment always locked SST. User read Address range: 000080H 0000FFH (128-words). Lock Status User Segment read with 00007FH. Unlocked: Locked: SIWA: Security Program Word Address: User written Address range: 000080H 0000FFH (128-words). device does remain Software Product Identification mode Powered Down. With A18-A1 A20-A19 (Bank Address), address Bank that being switched Software Mode: Manufacturer 00BFH, read with SST34WA32x3 Device 975BH, read with SST34WA32x4 Device 975AH, read with Both Software Exit operations equivalent. Burst Mode Configuration Register Value A17-A12 (see Programmable WAIT State Configuration Section). Eight Word Program command only executed Supervoltage must Supervoltage before "A0H" command issued order enable Eight Words Program Command. Programming Acceleration command sequence required prior this command sequence. Programming Acceleration Reset command required return normal read mode when chip Programming Acceleration mode.
TABLE Eight Word Program Software Command Sequence
Cycle Address1 XXXXH3 XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH Data2 DATA DATA DATA DATA DATA DATA DATA DATA Comment Eight Word Program Command Will program "DATA Address Will program "DATA Address Will program "DATA Address Will program "DATA Address Will program "DATA Address Will program "DATA Address Will program "DATA Address Will program "DATA Address
T21.1358
Address format A11-A0 (Hex). Addresses A12- VIH, other value, Command sequence SST34WA32A3/32A4/3283/3284. DQ15-DQ8 VIH, other value, Command sequence. VIH, other value. Program Word Address first word programmed. Eight-Word Program Mode must 8-word boundary aligned (A0=A1=A2=0).
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Software Read Block Locking Registers
Command Sequence Software Entry: Manufacturer Software Entry: Device Software Entry: Read Block Locking Status Cycle (Write) Addr1 555H Data2 Cycle (Write) Addr 2AAH Data Cycle (Write) Addr BKX555H3 Data Cycle (Read) Addr BKXX00 Data 00BFH
555H
2AAH
BKX555H
BKXX01
xxxxH4
555H
2AAH
BKX555H3
BAXX02
BLR5
T22.0 1358
Address format A11-A0 (Hex). Addresses A12-A20 VIH, other value, Command sequence SST34WA32A3/32A4/3283/3284. DQ15-DQ8 VIH, other value, Command sequence. indicates Bank Address: uses A20-A19 address lines. indicates Address Block Locked/Unlocked; uses A20-A13 address lines. This composed Block Address (BAX). SST34WA32x3 975BH SST34WA32x4 975AH indicates Block Locking Register Data: 0000H Block Unlocked, 0001H Block Locked.
TABLE Query Identification String1
Address Data 0051H 0052H 0059H 0001H 0007H 0040H 0000H 0000H 0000H 0000H 0000H
T23.0 1358
Description Query Unique ASCII string "QRY"
Primary command Address Primary Extended Table Alternate command (00H none exists) Address Alternate extended Table (00H none exits)
Refer publication more details.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE System Interface Information
Address Data 0017H 0019H 00B4H 00C0H 0003H 0000H 0004H 0005H 0001H 0000H 0001H 0001H Description (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (00H pin) (00H pin) Typical time Word-Program Typical time size buffer program (00H supported) Typical time individual Sector/Block-Erase Typical time Chip-Erase Maximum time Word-Program times typical Maximum time buffer program times typical Maximum time individual Sector/Block-Erase times typical Maximum time Chip-Erase times typical
T24.1 1358
TABLE Device Geometry Information SST34WA32x3
Address Data 0016H 0001H 0000H 0000H 0000H 0002H 0003H 0000H 0040H 0000H 003EH 0000H 0000H 0001H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
T25.1 1358
Description Device size Bytes (16H MByte) Flash Device Interface description; 0001H x16-only asynchronous interface Maximum number bytes multi-byte write 2N(00H supported) Number Erase Block sizes supported device Block Information Number blocks; 256B block size) blocks Bytes KBytes/block Block Information Number blocks; 256B block size) blocks 100H Bytes KByte/block
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Device Geometry Information SST34WA32x4
Address Data 0016H 0001H 0000H 0000H 0000H 0002H 003EH 0000H 0000H 0001H 0003H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
T26.1 1358
Description Device size Bytes (16H MByte) Flash Device Interface description; 0001H x16-only asynchronous interface Maximum number bytes multi-byte write 2N(00H supported) Number Erase Block sizes supported device Block Information Number blocks; 256B block size) blocks 100H Bytes KByte/block Block Information Number blocks; 256B block size) blocks Bytes KBytes/block
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Primary Vendor-Specific Extended Query
Address Data 0050H 0052H 0049H 0031H 0033H 0005H Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) Required, Required Silicon Technology (Bits 5-2) 0001 0.18 Erase-Suspend Supported, Read Only, Read Write Block Protect Supported, Number blocks group Sector Temporary Unprotect Supported, Supported Sector Protect/Unprotect scheme Supported, Supported Simultaneous Operation Number Sectors banks except boot bank Burst Mode Type Supported, Supported Page Mode Type Supported, Word Page, Word Page (Acceleration) Supply Minimum Supported, D7-D4: Volt, D3-D0: (Acceleration) Supply Maximum Supported, D7-D4: Volt, D3-D0: Top/Bottom Boot Sector Flag Bottom Boot Device, Boot Device Program Suspend. supported Bank Organization: Number banks Bank Region Information. Number blocks bank Bank Region Information. Number blocks bank Bank Region Information. Number blocks bank Bank Region Information. Number blocks bank
T27.1 1358
Description Query Unique ASCII string "PRI"
0002H 0001H 0000H 0005H 0018H 0001H 0000H 00B4H 00C0H 00XXH 0000H 0004H 0013H (SST34WA32x3) 0010H (SST34WA32x4) 0010H 0010H 0010H (SST34WA32x3) 0013H (SST34WA32x4)
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature under Bias. -55°C +125°C Storage Temperature -65°C +125°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Voltage Ground Potential -0.5V +14V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Solder Reflow Temperature1 260°C seconds Output Short Circuit Current2
Please consult factory latest information. Outputs shorted more than second. more than output shorted time.
Operating Range
Range Ambient Temp -20°C +85°C 1.7V-1.95V
Extended Conditions Test
Input Rise/Fall Time Output Load Figures
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Characteristics
TABLE Operating Characteristics 1.7-1.95V
Limits Symbol Parameter Flash Asynchronous Read PSRAM Asynchronous Read/Write Program Erase Concurrent Read/Write IDDB Flash Active Burst Read Current PSRAM Initial Access, Burst Read/Write PSRAM Continuous Burst Write Standby Current Freq Units Test Conditions BEF#=VIL, OE#=WE#=VIH, Array background 55AAH BEF#=VIH, BES#=VIL BEF#=WE#=VIL, OE#=ACC=VIH BEF#=VIL, OE#=VIH BEF#=VIL, OE#=VIH, WE#=VIH, Array background 55AAH BEF#=VIH, BES#=VIL, VIH, Array background BEF#=VIH, BES#=VIL, WE#=VIL, BEF#= -0.1V BES# VDD-0.1V RST#= -0.1V other inputs= 0.1V VDD-0.1V =GND VDD, VDD=VDD VOUT =GND VDD, VDD=VDD VDD=VDD Max, ACC=VH VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD IOL=0.2 VDD=VDD Min, BCR[5:4]=01b IOH=-0.2 VDD=VDD Min, BCR[5:4]=01b 1.8V
T28.0 1358
VOLF VOHF VOLS VOHS VLKO
Input Leakage Current Output Leakage Current Supervoltage Current Eight-Word Program Input Voltage Input High Voltage Flash Output Voltage Flash Output High Voltage PSRAM Output Voltage PSRAM Output High Voltage Supervoltage Eight-Word Program Flash Lock-Out Voltage 0.8VDD 11.4 VDD-0.1
0.2VDD
TABLE Capacitance 25°C, Mhz, other pins open)
Parameter CI/O1 CIN1 Description Capacitance Input Capacitance Test Condition VI/O Maximum
T29.0 1358
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Reliability Characteristics
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Minimum Specification 100,000 Units Cycles Years Test Method JEDEC Standard JEDEC Standard A103 JEDEC Standard
S71358-01-000 11/07
©2007 Silicon Storage Technology, Inc.
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Reliability Characteristics
Symbol Parameter Minimum Specification Units Test Method
T30.0 1358
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Flash Synchronous/Burst Read (54MHz/66MHz) Cycle Timing Parameters 1.7-1.95V1
Symbol TIACC TBACC TACS TACH TBDH TCEZ TOEZ TCES TRACC TRY/BY#S TAVDS TAVDH TAVDO TCKA TOECH TAAH Parameter Initial Access time Burst Access Time, Valid Clock Output Delay Address Setup Time CLK2 Address Hold Time from CLK2 Data Hold Time from Next Clock Cycle Data Valid (OE# RY/BY# Valid) BEF# High-Z High-Z BEF# Setup Time RY/BY# Access Time from RY/BY# Setup Time AVD# setup time AVD# hold time from AVD# High Access Resume Hold time from burst-suspend Address Hold Time from Rising Edge AVD# 13.5 13.5 11.5 13.5 11.5
T31.1358
11.5 11.5 Units
87.5 13.5
100% tested. Test Conditions: Output Load: VDD: 30pF Input Pulse Levels: 0.0V Input: Input Rise Fall Times: Timing measurements reference level Output:
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Flash Asynchronous Read Cycle Timing Parameters 1.7-1.95V
Symbol TACC TAVDP TAAS TAAH TOEH TOEZ TCEZ Parameter Access Time from BEF# Asynchronous Access AVD# Time Address Setup Time Rising Edge AVD# Address Hold Time from Rising Edge AVD# Data Valid Output Enable Hold Time from high (Read Operation) Output Enable Hold Time from high (Toggle Data Poll) Output Enable High-Z2 BEF# High-Z2 Time1 13.5 11.5 Units
T32.0 1358
Asynchronous Access Time from last either stable addresses falling edge AVD# 100% tested
TABLE PSRAM Asynchronous Read Cycle Timing Parameters1 1.7-1.95V
Symbol TACCS TAAVDS TAAHS TAASS TBYAS TBYHZS TBYLZS TBEPS TBEWS TBES TBVS TBHZS TBLZS TOES TOHZS TOLZS TRCS TVPLS TVPHS Parameter Address Access time AVD# Access Time Address Hold from AVD# High Address Setup AVD# High LBS#/UBS# Access Time LBS#/UBS# Disable A/DQ High-z LBS#/UBS# Enable Low-z Output BES# Pulse Width BES# WAIT Valid BES# Access Time BES# AVD# HIGH BES# High A/DQ WAIT High-z BES# Low-z Output Valid Output High A/DQ High-z Low-z Output Read Cycle Time AVD# Pulse Width AVD# Pulse Width High Units
T33.1358
tests performed with outputs configured default setting full drive strength (BCR[5:4]=00B).
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE PSRAM Burst Read Cycle Timing Parameters1 1.7-1.95V
Symbol TACCS TAAVDS TIACCS TBACCS TAAHS TOES TBPHS TBEPS TBEWS TBEAS TBESS THDS TBHZS TCWS TBDHS TOHZS TOLZS TSPS Parameter Address Access Time (Fixed Latency) AVD# Access Time (Fixed Latency) Initial Access Time (Variable Latency)2 Burst Access Time (CLK Output Delay) Address Hold from AVD# HIGH (Fixed Latency) Valid Output BES# HIGH between Subsequent Burst MIxed Model Operations3 BES# Pulse Width3 BES# AVD# WAIT Valid BES# Access Time (Fixed Latency) BES# Setup Time Active Edge Hold Time from Active Edge BES# High A/DQ WAIT High-Z Output WAIT Valid Output HOLD from High A/DQ High-Z Output Low-Z Output Setup Time Active Edge Units
T34.0 1358
tests performed with outputs configured default setting full drive strength (BCR[5:4]=00B). Values valid TCLK (Min.) with refresh collision. refresh opportunity must provided every TBEPS. refresh opportunity satisfied either following conditions: clocked BES# HIGH, BES# HIGH longer than 15ns.
TABLE PSRAM Asynchronous WRITE Cycle Timing Parameters1 1.7-1.95V
Symbol TASTS TAAHS TAASS TAWS TBYWS TBEWS TBPHS TBVS TBWS TDHS TDSS TBHZS TBLZS TOEWS TVPLS TVPHS Parameter Address Setup Time Address Hold from AVD# HIGH Address Setup AVD# HIGH Address Valid Write LBS#/UBS# Select Write BES# AVD# WAIT Valid BES# HIGH between Subsequent Asynchronous Operations BES# AVD# HIGH BES# Write Data Hold from Write Time Data Write Setup Time BES# High WAIT High-Z Output BES# Low-Z Output Write Low-Z Output AVD# Pulse Width AVD# Pulse Width High
S71358-01-000
Units
11/07
©2007 Silicon Storage Technology, Inc.
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE PSRAM Asynchronous WRITE Cycle Timing Parameters1 1.7-1.95V
Symbol TVWS TWCS TODWS TWPLS TWPHS TWRS TAWS Parameter AVD# Setup Write Write Cycle Time Write A/DQ High-Z Output Write Pulse Width Low2 Write Pulse Width High Write Recovery Time AVD# High Write Enable Units
T35.0 1358
tests performed with outputs configured default setting full drive strength (BCR[5:4]=00B). time must limited from TBPHS TBEPS (10µs)
TABLE PSRAM Burst WRITE Cycle Timing Parameters1 VDD= 1.7-1.95V
Symbol TAVS TAAHS TBPHS TBEPS TBEWS TBESS THDS TBHZS TCAVDS TCWS TSPS Parameter Address AVD# setup time2 Address Hold from AVD# High (Fixed Latency) BES# High between Subsequent Burst Mixed Mode Operations3 BES# Pulse Width3 BES# WAIT Valid BES# Setup Active Edge Hold Time from Active Edge BES# High WAIT High-Z Output Last Clock AVD# (Fixed Latency) Clock WAIT Valid Setup Time Activate Edge Units
T36.0 1358
tests performed with outputs configured default setting full drive strength (BCR[5:4]=00B). TAVS required TBESS 20ns. refresh opportunity must provided every TBEPS. refresh opportunity satisfied either following conditions: clocked BES# HIGH, BES# HIGH longer than 15ns.
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Program/Erase Cycle Timing Parameters1 1.7-1.95V
Symbol TAVDP TCLAH TGHWL TWPH TSRW TAHWL TIDA TSCE TERH TVLHT Parameter Word-Program Time Write Cycle Time Units
T37.0 1358
AVD# Time BEF# AVD# High Data Setup Time Data Hold Time Read Recovery Time before Write BEF# Hold Time Pulse Width Pulse Width High Latency Between Read Write Operations BEF# Time AVD# High Software Access Exit Time Sector Erase Time Block Erase Time Chip Erase Time Erase-Suspend Latency Time Erase-Resume Hold Time next Erase-Suspend Rise time Supervoltage Voltage Transition Time
100% tested.
TABLE Power Timings1
Symbol TPU-READ TPU-WRITE TRSTH
100% tested.
Parameter Power-up Read Operation Power-up Write Operation RST# Hold Time after VDD/VDDQ setup
Minimum
units
T38.0 1358
TABLE Flash Hardware Reset
Symbol TREADYW TREADY TRPD
100% tested.
Parameter RST# Read Mode (During Embedded Algorithm)1 RST# Read Mode (NOT During Embedded RST# Pulse Width RST# High Time Before Read RST# Stand-By Mode Algorithm)1
Units
T39.0 1358
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Advance Information TABLE Clock Input Parameters1
Symbol FCLK TCLK TCHCL TCHLH Parameter Frequency Period High Time from Time from Fall Rise Time from High Time from 18.5 Units
T40.0 1358
100% tested.
BEF#
TOEH
TACC
TOEZ
Valid
A/DQ15-A/DQ0
A20-A16
TAAH TAAS AVD# TAVDP
Note: Read Address, Read Data.
1358 F11.0
FIGURE Flash Asynchronous Mode Read
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCES
BEF#
TAVDS
15.2 typ. MHz)
TCEZ
AVD#
TAVDH TAVDO TACS TAAH TBDH
TACH TBACC
A/DQ15 A/D0
TIACC
TOEZ
TRACC
RY/BY#
TRD/BY# 1358 F9.0
FIGURE Flash Synchronous Burst Mode Read
TCES
BEF#
18.5 MHZ)
TAVDS
AVD#
TAAH TACS TBDH
TACH TBACC
A/DQ15 A/DQ0
TIACC
TRACC
RY/BY#
TRD/BY# 1358 F10.0
Note: Figure assumes seven wait states initial access, clock, automatic detect synchronous read. d0-d7 data waveform indicate order data within given 8-word address range, from lowest highest. Data will wrap around within words, non-stop unless RESET# asserted low, AVD# locks another address. device will output RD/BY# with valid data.
FIGURE Flash 8-Word Linear Burst with Wrap-Around
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
AVD#
A20-A16 TOECH A/DQ15-A/DQ0
RY/BY#
BEF#
1358 F21.0
FIGURE Flash Burst Suspend
Program Command Sequence (last cycles) Read Status Data
TCLAH TAVDP AVD#
A20-A16 TAAS A/DQ15-A/DQ0
555h
TAAH
Progress
Complete
BEF# TAHWL TPU-READ
1358 F12.0
TWPH
Note: Program Address, Program Data, Valid Address reading status bits. Progress" "Complete" refer status program operation. Amax don't care during command sequence cycles. don't care. Addresses latched rising edge AVD.
FIGURE Flash Program Operation Timings
©2007 Silicon Storage Technology, Inc. S71358-01-000 11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Erase Command Sequence (last cycles)
Read Status Data
TAVDP
AVD#
TCLAH
SA/BA
Block Erase Chip Erase
A20-A16 TAAS TAAH A/DQ15-A/DQ0
2AAh
555h Chip Erase
SA/BA
Progress
Complete
BEF#
TPU-READ
1358 F13.0
TWPH TSE/TBE/TSCE
Note: sector address Sector Erase. block address Block Erase. Address bits don't care during cycles command sequence.
FIGURE Flash Chip/Block/Sector Erase Command Sequence
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TPU-READ
TVLHT AVD# TAAS TAAH A20-A16
AINI
A/DQ15-A/DQ0
555h
AINI
Data
Data
Data
Data
Data
BEF#
1358 F8.0
FIGURE Flash Eight Words Programming
AVD# BEF# TOEH TACC A20-A16
TCEZ
TOEZ
A/DQ15-A/DQ0
Status Data
Status Data
1358 F14.0
Note: Valid Address. Read cycles required determine status. When Embedded Algorithm operation complete, Data# Polling will output true data. AVD# must toggle between data reads.
FIGURE Flash Data# Polling Timings (During Embedded Algorithms)
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
AVD# BEF# TOEH TACC A20-A16
TCEZ
TOEZ
A/DQ15-A/DQ0
Status Data
Status Data
1358 F15.0
Note: Valid Address. Read cycles required determine status. When Embedded Algorithm operation complete, Data# Polling will output true data. AVD# must toggle between data reads.
FIGURE Flash Toggle Timings (During Embedded Algorithms)
Address boundary occurs every words, beginning address 00001Fh (00003Fh, 00005Fh, etc.). Address 000000H also boundary crossing.
Address (hex) AVD# (stays high)
TRACC RY/BY# latency
A/DQ15-A/DQ0
1358 F17.0
Note: indicates which clock triggers output. example, triggers D30. figure shows that device does cross bank when performing erase program operation. latency with boundary crossing happens 32-word boundary.
FIGURE Flash Latency with Boundary Crossing
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
C253 Address (hex) AVD# 3FFFD (stays high)
C254 3FFFE
C255 3FFFF
C256 40000
C257 40001
RY/BY# A/DQ15-A/DQ0
(stays high) D253 D254 D255 Read Status
BEF#/OE#
(stays low)
1358 F18.0
Note: Cxxx indicates which clock triggers Dxxx output. example, C253 triggers D253. figure shows that device cross bank when performing erase program operation.
FIGURE Flash Boundary Crossing into Program/Erase Bank
A/DQ15-A/DQ0
AVD#
Rising edge next clock cycle following last wait state triggers next burst data
Total number clock cycles following AVD# falling edge
Number clock cycles programmed Wait State Decoding Addresses: A14, A13, "101" programmed, total A14, A13, "100" programmed, total A14, A13, "011" programmed, total A14, A13, "010" programmed, total A14, A13, "001" programmed, total
1358 F19.0
Note: Figure assumes address. address boundary, active clock edge rising, wait state `101.'
FIGURE Example Flash WAIT State Insertion
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Last Cycle Program Sector Erase Copmmand Sequence
Read status least cycles) same bank and/or array data from other bank
Begin another write program command sequence
BEF#
TOEH TGHWL
TWPH TACC TOEZ TOEH
A/DQ15-A/DQ0
PA/SA
PD/50h
TSRW
555h
A20-A16
PA/SA TAAS
AVD#
TAAH
1358 F20.0
Note: Breakpoints waveforms indicate that system alternately read array data from "non-busy bank" while checking status program erase operation "busy" bank. system should read status twice ensure valid information.
FIGURE Flash Back-to-Back Read/Write Cycle Timings
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCHLH TCLK TSPS Amax-A16
Valid Address
TCHLH
TSPS THDS AVD# TBEPS TBESS BES# TOES TSPS TSPS LBS#/UBS# TBEWS WAIT High-Z TBACCS
Valid Address Valid Output
THDS TBHZS
TIACCS
TOHZS
TOLZS THDS
THDS
TCWS High-Z TBDHS
A/DQ15-A/DQ0
High-Z
READ Burst Identified (WE# HIGH)
1358 F23.0
FIGURE PSRAM Single-Access Burst Read Variable Latency
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCLK TSPS Amax-A16
Valid Address
TCHLH TCHLH
TSPS THDS AVD# TBEPS TBESS BES# TOES
TBPHS THDS
TIACCS
TBHZS
TSPS TSPS LBS#/UBS# TBEWS WAIT High-Z TBACCS A/DQ15-A/DQ0 High-Z
Valid Address Valid Output
TOLZS THDS
TOHZS
THDS
TCWS High-Z TBDHS
Valid Output Valid Output Valid Output
READ Burst Identified (WE# HIGH)
1358 F24.0
Note: Non-default settings Latency code (three clocks); WAIT active LOW; WAIT asserted during delay.
FIGURE PSRAM 4-Word Burst Read Operation Variable Latency
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCLK TSPS Amax-A16
Valid Address
TCHLH
TSPS AVD#
TACCS TAAHS THDS TAAVDS TBESS THDS TBHZS
BES# TBES TOES
TOHZS
TSPS TSPS LBS#/UBS# TBEWS WAIT High-Z TBACCS A/DQ15-A/DQ0
Valid Address Valid Output
TOLZS THDS
THDS
TCWS High-Z TBDHS
READ Burst Identified (WE# HIGH)
1358 F25.0
Note:
Non-default setting: Fixed Latency; Latency code three (four clocks); WAIT active LOW; WAIT asserted during delay.
FIGURE PSRAM Single-Access burst Read Fixed Latency
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCLK TSPS Amax-A16
Valid Address
TCHLH TCHLH
TSPS AVD#
TAAHS TACCS
THDS TAAVDS TBESS BES# TBES TOES
TBEPS THDS
TBPHS
TBHZS
TSPS
TOLZS THDS
TOHZS
TSPS
THDS
LBS#/UBS#
TBEWS
TCWS High-Z TBACCS TBDHS
Valid Output Valid Output Valid Output Valid Output
WAIT
High-Z
A/DQ15-A/DQ0
High-Z
Valid Address
READ Burst Identified (WE# HIGH)
1358 F26.0
Note: Non-default setting: Fixed Latency; Latency code (three clocks); WAIT active LOW; WAIT asserted during delay.
FIGURE PSRAM 4-Word Burst Read fixed Latency
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCLK TSPS Amax-A16
Valid Address
TCHLH
Note
Valid Address
TSPS THDS AVD# TBESS TBEPS TBPHS
BES# TOES TSPS TOLZS THDS TSPS LBS#/UBS# TBEWS WAIT Hi-Z Hi-Z TBACCS A/DQ15-A/DQ0 Hi-Z
Valid Address
Valid Output
Note
TBHZS
TOHZS
TOHZS
THDS
TBDHS
Valid Output Valid Output Valid Output
TOES TOLZS
Valid Output Valid Valid Output Output
1358 F27.0
Note: Non-default settings READ burst suspend: Fixed Variable latency; latency code (three clocks); WAIT active LOW; WAIT asserted during delay. During Burst Read Suspend operations, Clock signal must stopped (Low). must static with LOW-to-HIGH transitions during burst suspend. stay during burst suspend. LOW. A/DQ[15:0] will continue output valid data.
FIGURE PSRAM Read Burst Suspend
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCLK Amax-A16
AVD#
LBS#/UBS#
BES#
Note
TBHZS TBHZS HIGH-Z TCWS A/DQ15-A/DQ0
Valid Output Valid Output
WAIT
(A8-A0: 7Fh)
1358 F28.0
Note: Non-default settings continuous burst READ, BCR[8] WAIT active LOW; WAIT asserted during delay. cross boundaries. BES# must remain longer than TBEPS. Bank Enable signal, BES# must High before third Clock cycle after WAIT signal goes Low.
FIGURE PSRAM Continuous Burst Read with Output Delay BCR[8] variable latency end-ofrow condition
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCLK Amax-A16
ADV#
LBS#/UBS#
BES#
Note
TCWS WAIT TBHZS TBHZS
HIgh-Z
A/DQ15-A/DQ0
Valid Output
Valid Output
(A8-A0: 7Fh)
1358 F29.0
Note: Default settings continuous burst READ, BCR[8] WAIT active LOW; WAIT asserted data cycle before delay. cross boundaries. BES# must remain longer than TBEPS. Chip Enable signal, BCR8 were BES# would have before fourth Clock cycle after WAIT signal goes Low.
FIGURE PSRAM Continuous Burst Read with Output Delay BCR[8] variable latency end-ofrow condition
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Amax-A16 TVPHS
Valid Address TAASS TVPLS TAAHS TVWS
AVD# TBVS TBWS TAWS BES# TBYWS LBS#/UBS# TASTS TWPHS TDSS A/DQ15-A/DQ0 High-Z TBEWS WAIT High-Z Valid Address TDHS TWPLS TWPHS
Valid Input TBHZS High-Z
1358 F30.0
Note: Data Inputs Hi-Z BES# high, When BES# Low, (device selected). must remain Low, longer than TBYWS. Write operation controlled BES#, LBS#/UBS#, WE#, whichever de-asserted first.
FIGURE PSRAM Asynchronous Write Using AVD#
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TWCS Amax-A16 Valid Address TAWS AVD# TBWS BES# TBPHS TWRS
LBS#/UBS# TWPHS TDSS A/DQ15-A/DQ0 High-Z Valid Address TDHS
Valid Input TBHZS
WAIT
High-Z TBEWS
High-Z
1358 F31.0
FIGURE PSRAM BES# Controlled Asynchronous Write
TWCS Amax-A16 Valid Address TAWS AVD# TBVS BES# TAWS TBYWS LBS#/UBS# TASTS TWPHS TDSS A/DQ15-A/DQ0 High-Z TBEWS WAIT High-Z Valid Address TDHS TWPLS TWRS
Valid Input TBHZS High-Z
1358 F32.0
FIGURE PSRAM Controlled Asynchronous Write
©2007 Silicon Storage Technology, Inc. S71358-01-000 11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCHLH TCLK TSPS Amax-A16 TAVS3 TSPS THDS AVD# TAVS3 LBS#/UBS# TBESS BES# THDS TBEPS TBPHS TSPS THDS
Valid Address
TCHLH
TAAHS TCAVDS
TSPS THDS TBEWS WAIT High-Z Note TSPS A/DQ15-A/DQ0 High-Z
Valid Address D[1]
TCWS
TBHZS High-Z THDS
D[2] D[3] D[0]
READ Burst Identified (WE# LOW)
1358 F33.0
Notes: Non-default settings burst WRITE operation fixed latency mode: Fixed latency; latency code (three clocks); WAIT active LOW; WAIT asserted during delay: burst length four; burst wrap enabled. WAIT asserts cycles both fixed latency. Latency Code (BCR[13:11]). TAVS required TBESS 20ns.
FIGURE PSRAM Burst Write Fixed Latency
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCLK Amax-A16
AVD#
LBS#/UBS#
BES#
Note
TCWS WAIT TSPS
TBHZS
TBHZS High-Z
THDS
Valid Input
A/DQ15-A/DQ0
Valid Input
(A6-A0: 7Fh)
1358 F34.0
Notes: Default settings continuous burst WRITE, BCR[8] WAIT active LOW. WAIT asserted data cycle before delay. BES# must remain longer than TBEPS. Chip Enable signal, BES# must High before fourth Clock cycle after WAIT signal goes Low. BCR[8] were BES# would have before third Clock cycle after WAIT signal goes Low.
FIGURE PSRAM Continuous Burst Write with Output Delay BCR[8] end-of-row Condition
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCLK TSPS Amax-A16
Valid Address Valid Address
TSPS
TSPS THDS AVD#
TCAVDS3
TSPS THDS
TSPS THDS LBS#/UBS# THDS TBESS TBPHS Note
TBESS BES#
TSPS THDS TBDHS WAIT High-Z THDS
D[0] D[1] D[2] D[3]
THDS TSPS
TOES
TOHZS
High-Z
TSPS A/DQ15-A/DQ0
Valid Address
TBACCS
High-Z
High-Z
Valid Output
Valid Output
Valid Output
Valid Output
1358 F35.0
Notes: Non-default settings burst WRITE followed burst READ: Fixed latency; latency code (three clocks); WAIT active LOW; WAIT asserted during delay. refresh opportunity must provided every TBEPS. refresh opportunity satisfied either following conditions: clocked BES# HIGH, BES# HIGH longer than 15ns. BES# stay between burst READ burst WRITE operations, BES# must remain longer than TBEPS. burst interrupt diagrams cases where BES# stays between bursts. Only fixed latency requires TCAVDS.
FIGURE PSRAM Burst Write Followed Burst Read
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCLK TSPS Amax-A16
Valid Address
READ Burst interrupted with READ WRITE. Note
TSPS
Valid Address
TSPS THDS AVD#
TSPS THDS
THDS TBESS BES# TSPS THDS TCWS TSPS THDS TBEPS (Note
WAIT
High-Z TBEWS
High-Z
Cycle READ
TOES
TOHZS
LBS#/UBS#
Cycle READ
TBACCS A/DQ15-A/DQ0
Cycle READ
Valid Address
High-Z
Valid Output
TBDHS High-Z
TBDHS
Valid Output Valid Output Valid Output Valid Output
TBACCS
Cycle WRITE
LBS#/UBS#
Cycle WRITE
TSPS A/DQ15-A/DQ0
Cycle WRITE
High-Z
D[0]
THDS
D[1] D[2] D[3]
1358 F36.0
Notes: Non-default settings burst READ interrupted burst READ WRITE: Fixed latency code (three clocks); WAIT active LOW; WAIT asserted during delay. Burst interrupt shown first allowable clock (i.e., after first data received controller). BES# stay between burst operations, BES# must remain longer than TBEPS.
FIGURE PSRAM Burst Read Interrupted Burst Read Write
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCLK TSPS Amax-A16
Valid Address
WRITE Burst interrupted with WRITE READ. Note
TSPS
Valid Address
TAAHS
TCAVDS TSPS THDS
TAAHS THDS
AVD# TSPS TBESS BES# TSPS THDS TCWS WAIT High-Z TBEWS
Cycle WRITE
TBEPS (Note
THDS
TSPS THDS
High-Z
LBS#/UBS#
Cycle WRITE
TSPS A/DQ15-A/DQ0
Cycle WRITE
Valid Address
THDS
D[0] D[1] D[2] D[3]
D[0]
TOES
Cycle READ
TOHZS
TSPS LBS#/UBS#
Cycle READ
THDS
TBDHS A/DQ15-A/DQ0 High-Z
High-Z
Cycle READ
Valid Output
Valid Output
Valid Output
Valid Output
TBACCS
1358 F37.0
Notes: Non-default settings burst WRITE interrupted burst WRITE READ fixed latency mode: Fixed latency; latency code (three clocks); WAIT active LOW; WAIT asserted during delay. Burst interrupt shown first allowable clock (i.e., after first data word written). BES# stay between burst operations, BES# must remain longer than TBEPS.
FIGURE PSRAM Burst Write Interrupted Burst Write Read Fixed Latency
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCLK
TWCS Amax-A16
Valid Address
TWCS
Valid Address
TSPS
Valid Address
TAASS TAAHS TAWS TVPHS TVPLS TVWS AVD# TSPS TBVS BYWS LBS#/UBS# TASTS TBWS BES#
TWRS THDS
TSPS
THDS
TBESS TBPHS
Note
TWPLS TASTS TWPHS WAIT TDSS A/DQ15-A/DQ0
Hi-Z
Valid Address Data
Valid
TWCS TSPS
THDS
TOHZS
TBEWS
TOES
High-Z
TBACCS
Data Valid Address
TBDHS
Valid Output Valid Output Valid Output Valid Output
High-Z
TDHS
1358 F38.0
Notes: Non-default settings asynchronous WRITE followed burst READ: Fixed variable latency; latency code (three clocks); WAIT active LOW; WAIT asserted during delay. When transitioning between asynchronous variable-latency burst operations, BES# must HIGH. BES# stay when transitioning fixed-latency burst READs. refresh opportunity must provided every TBEPS. refresh opportunity satisfied either following conditions: clocked BES# HIGH, BES# HIGH longer than 15ns.
FIGURE PSRAM Asynchronous Write Followed Burst Read
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
TCLK TSPS Amax-A16
Valid Address Valid Address
TAASS TAAHS THDS TSPS AVD# THDS TBESS
TVWS TVPHS TVPLS
TBPHS
TAWS TASTS
TBHZS
Note
BES# TOES
TBWS
TSPS TOLZS THDS TOHZS TASTS TWPLS TWPHS
TSPS THDS LBS#/UBS# TBEWS WAIT
High-Z
TBYWS
TCWS
High-Z
TBEWS
TBHZS
TBACCS A/DQ15-A/DQ0
High-Z
Valid Address READ Burst Identified (WE# HIGH) Valid Output
TBDHS
Valid Address
TDSS
Valid Input
TDHS
1358 F39.0
Notes: Non-default settings burst READ followed asynchronous WRITE using AVD#: Fixed latency; latency code (three clocks); WAIT active LOW; WAIT asserted during delay. When transitioning between asynchronous variable-latency burst operations, BES# must HIGH. BES# stay when transitioning from fixed-latency burst READs; asynchronous operation begins falling edge AVD#. refresh opportunity must provided every TBEPS. refresh opportunity satisfied either following conditions: clocked BES# HIGH, BES# HIGH longer than 15ns.
FIGURE PSRAM Burst Read Followed Asynchronous Write Using AVD#
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Amax-A16
Valid Address
Valid Address
Valid Address
TAASS TAAHS TVPHS TVPLS AVD# TBVS LBS#/UBS# TBWS BES#
TAWS TVWS
TWRS TACCS
TBYWS
TBYLZS
TBYHZS
TBPHS
Note
TBHZS
TBLZS TASTS TWPLS TASTS TWCS TWPHS TOLZS TOES TOHZS
WAIT TODWS A/DQ15-A/DQ0
Valid Add. Data Valid Add. Data Valid Address Valid Output
TDHS Note:
TDSS
1358 F40.0
When configured synchronous mode (BCR[15] BES# must remain HIGH least (TBPHS) schedule appropriate refresh interval. Otherwise, TBPHS only required after BES#-controlled WRITEs.
FIGURE PSRAM Asynchronous Write Followed Asynchronous Read
VDD/VDDQ
TRSTH
RST#
1358 F41.0
FIGURE Power Diagram
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Reset Timings during Embedded Algorithms
BEF#,
RST# TReady
Reset Timings during Embedded Algorithms
BEF#, TReadyw
RST#
1358 F42.0
FIGURE Flash Reset Timings
TCLK TCH/L TCHCL TCHLH
1358 F43.0
FIGURE Clock Input Waveform
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
1358 F44.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1VDD) logic `0.' Measurement reference points inputs outputs (0.5VDD) (0.5VDD). Input rise fall times 10%-90% <5ns. Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE Flash Input/Output Reference Waveforms
TESTER
1358 F45.0
FIGURE Flash Test Load Example
INPUT VDD/2 TEST POINTS VDD/2 OUTPUT
1358 F53.0
Note: test inputs driven logic logic `0.' Measurement reference points inputs outputs VDD/2 VDD/2. Input rise fall times 10%-90% <1.6ns.
FIGURE PSRAM Input/Output Reference Waveforms
TEST POINT
30pF VDD/2
1358 F54.0
Note: test performed with outputs configured default setting full drive strength (BCR[5:4]=00b).
FIGURE PSRAM Test Load Example
©2007 Silicon Storage Technology, Inc. S71358-01-000 11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Start
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XXA0H Address: 555H
Load Word Address/Word Data Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
1358 F46.0
Note: VIH, other value.
FIGURE Flash Word-Program Algorithm
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read word
Read
Program/Erase Completed
Read same word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
1358 F47.0
FIGURE Flash WAIT Options
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Query Entry Command Sequence Load data: XXAAH Address: 555H
Query Entry Command Sequence Load data: XXAAH Address: 555H
Software Product Entry Command Sequence Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX98H Address: 555H
Load data: XX88H Address: 555H
Load data: XX90H Address: 555H
Wait TIDA
Wait TIDA
Wait TIDA
Read data
Read
Read Software
1358 F48.0
Note: VIH, other value.
FIGURE Flash Software ID/CFI Entry Command Flowcharts
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Software Exit/CFI Exit/Sec Exit Command Sequence Load data: XXAAH Address: 555H Load data: XXF0H Address:
Load data: XX55H Address: 2AAH
Wait TIDA
Load data: XXF0H Address: 555H
Return normal operation
Wait TIDA
Return normal operation
1358 F49.0
Note: VIH, other
FIGURE Flash Software ID/CFI Exit Command Flowcharts
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
Chip-Erase Command Sequence Load data: XXAAH Address: 555H
Sector-Erase Command Sequence Load data: XXAAH Address: 555H
Block-Erase Command Sequence Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX10H Address: 555H
Load data: XX50H Address:
Load data: XX30H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
1358 F50.0
Note: VIH, other value.
FIGURE Flash Erase Command Sequence
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
PRODUCT ORDERING INFORMATION
Device SST34WA32 XSpeed Suffix1 Suffix2 Environmental Attribute non-Pb Package Modifier balls Package Type VFBGA (6mm 0.92mm, 0.3mm ball size) Temperature Range Extended -20°C +85°C Minimum Endurance 5=100,000 cycles Read Access Speed Boot Block Protection Bottom Boot Block Boot Block PSRAM Density Mbit PSRAM Mbit PSRAM Flash Density Function ADMux, Burst Mode Voltage 1.7-1.95V Product Series Concurrent SuperFlash PSRAM ComboMemory
Environmental suffix denotes non-Pb solder. non-Pb solder devices "RoHS Compliant".
Valid combinations SST34WA32A3 SST34WA32A3-70-5E- MVNE Valid combinations SST34WA32A4 SST34WA32A4-70-5E- MVNE Valid combinations SST34WA3283 SST34WA3283-70-5E- MVNE Valid combinations SST34WA3284 SST34WA3284-70-5E- MVNE Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2007 Silicon Storage Technology, Inc. S71358-01-000 11/07
Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 SST34WA32A4 SST34WA3283 SST34WA3284
PACKAGE DIAGRAMS
VIEW
8.00 ±0.08
CORNER
BOTTOM VIEW
6.50 4.50 0.50
INDICATOR
0.30 ±0.05 (56X)
4.50
6.00 ±0.08
0.50
2.50
DETAIL
SIDE VIEW
0.08
SEATING PLANE
0.21 0.05
Note:
Although many dimensions similar those JEDEC Publication MO-225, this specific package registered. linear dimensions millimeters. Coplanarity: 0.08 Ball opening size 0.25 0.05
56-fbga-MVN-6x8-1.0
FIGURE 56-Ball Very Fine-pitch Ball Grid Array (VFBGA) Package Code: TABLE Revision History
Number Description Date 2007 2007
Initial Release Removed Partial Array Refresh section, page Edited Table page
©2007 Silicon Storage Technology, Inc.
S71358-01-000
11/07

Other recent searches


Xilinx - Xilinx   Xilinx Datasheet
XAPP928 - XAPP928   XAPP928 Datasheet
Digital - Digital   Digital Datasheet
Display - Display   Display Datasheet
Panel - Panel   Panel Datasheet
Reference - Reference   Reference Datasheet
Design - Design   Design Datasheet
Using - Using   Using Datasheet
LVDS - LVDS   LVDS Datasheet
Application - Application   Application Datasheet
Note - Note   Note Datasheet
TS9001 - TS9001   TS9001 Datasheet
MSP430F413 - MSP430F413   MSP430F413 Datasheet
IDT72V10081 - IDT72V10081   IDT72V10081 Datasheet
IDT72V11081 - IDT72V11081   IDT72V11081 Datasheet
IDT72V12081 - IDT72V12081   IDT72V12081 Datasheet
IDT72V13081 - IDT72V13081   IDT72V13081 Datasheet
IDT72V14081 - IDT72V14081   IDT72V14081 Datasheet
DFG1C - DFG1C   DFG1C Datasheet
BL-R2131A - BL-R2131A   BL-R2131A Datasheet
APTGF90SK60TG - APTGF90SK60TG   APTGF90SK60TG Datasheet
AN2013 - AN2013   AN2013 Datasheet
AD7545 - AD7545   AD7545 Datasheet
2SK2267 - 2SK2267   2SK2267 Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive