SST34WA3203 SST34WA3204 Organized Single Voltage Read Write Opera

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

SST34WA3203 SST34WA3204 Organized Single Voltage Read Write Opera

Datasheet Thumbnail

Top Searches for this datasheet

Mbit Burst Mode Concurrent SuperFlash Memory
SST34WA3203 SST34WA3204
Organized Single Voltage Read Write Operations 1.7V 1.95V Program, Erase Read Bottom Boot Block Protection Bottom Boot Protection SST34WA3203 Boot Protection SST34WA3204 Multiplexed Data Address reduced count A15-A0 multiplexed DQ15-DQ0 Addresses latched AVD# control input when BEF# Power Consumption (Typical) Standby Current: Auto Power Mode: Flexible Memory Organization Banks (512 Uniform KWord blocks Uniform Sectors (2KWord) entire memory array Concurrent Memory Operation Read While Program (RWP) Read While Erase (RWE) Erase-Suspend/Erase-Resume Capability Read while Erase-Suspend Program while Erase-Suspend Read while Program during Erase-Suspend Synchronous Burst Mode Read MHz/66 MHz) Continuous, Sequential Linear Burst 8/16/32-words with Wrap-Around Burst 8/16/32-words without Wrap-Around Burst Burst Access Time: 13.5 ns/11.5 Asynchronous Random Address Access: Industry Standard interface compatible Fast Program Erase (Typical) Word Program Time: Sector/Block Erase Time: Chip Erase Time: Expanded Block Locking blocks locked Power-up block locked/unlocked software Flash Security 128-bit unique factory preset 128-word non-erasable, lockable User-programmed bits ("OTP-like") End-of-Write Detection Data# Polling Toggle Packages Available 44-ball VFBGA 8mm) Superior Reliability Endurance sector: 1,000,000 cycles (typical) Greater than years Data Retention non-Pb (lead-free) devices RoHS compliant
PRODUCT DESCRIPTION
SST34WA3203 SST34WA3204 Mbit Mbit x16) Flash memory devices with Burst Mode data access that utilize single supply. When super voltage (11.4V 12V) applied pin, eight word programming enabled faster manufacturingenvironment programming. devices feature KWord uniform multi-bank architecture that consists four banks. boot block, either bottom block, consists standard KWord blocks four parameter KWord blocks added granularity. remaining banks each contain uniform KWord blocks. Each KWord block further divided into sixteen uniform KWord sectors. Blocks sectors individually erasable increased flexibility. bank read while another bank being erased programmed, with zero latency. SST34WA3203/3204 support Erase-Suspend mode during which data programmed read from, sector block that being erased. SST34WA3203/3204 support synchronous Burst mode Read from address location memory array. Burst mode allows sequential data reading with significantly shorter latency delays than during random
©2007 Silicon Storage Technology, Inc. S71340-02-000 10/07
read, including 16-, 32-words continuous without wrap-around. devices offer expanded Block Locking scheme data protection against writes. Each block individually locked. Additionally, bottom KWord parameter blocks individually locked finer granularity bottom boot blocks. 136-words Security included devices, increases system design security. Security divided into segments: 8-word, 128-bit segment factory programmed with Unique 128word segment that programmed locked user. When locked, user programmable bits programmed never erased. Designed, manufactured, tested applications requiring power small form factor SST34WA3203/3204 offered extended temperature with small footprint package meet board space constraints requirement. Figure assignments.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. ComboMemory trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Device Operation
Commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences. SST34WA3203/3204 device also Auto Power mode which puts device "near standby" mode after data been accessed with valid Read operation. This reduces active read current. Auto Power mode reduces typical Stand-By level. device exits Auto Power mode with address control signal transition; therefore, there access time penalty Read cycles.
Asynchronous Read
default configuration power-up, after hardware reset RST# pin, Asynchronous Read. read data from memory array, system must assert valid address A/DQ15-A/DQ0 A20-A16, while AVD# BEF# VIL. During read, remains Asynchronous Read, rising edge AVD# latches address, driven VIL. data appears A/DQ15-A/DQ0. details, Figure Since memory array divided into four banks, each bank remains enabled read access until command register contents altered. Address access time (TACC) equal delay from stable addresses valid output data. chip enable access time (TCE) delay from stable addresses stable BEF# valid data outputs. output enable access time (TOE) delay from falling edge valid data output. internal state machine read array data upon device power-up after hardware reset. This ensures that spurious alteration memory content occurs during power transition.
TABLE Critical Parameters
Critical Parameters Values Units 13.5 11.5
T1.0 1340
Random Address Access Time Synchronous Access Time MHz) Synchronous Access Time MHz)
Concurrent Read/Write Operation
multi-bank architecture this device allows zero latency Concurrent Read/Write operation whereby user read from bank while programming erasing another bank. With this operation user read system code bank while updating data another bank. unique feature SST34WA3203/3204 ability Read during Erase-Suspend even while Programming another bank. This feature designed respond interrupt requests during concurrent operation. Table Current Read/Write State. TABLE Concurrent Read/Write State
Current Operation Bank Read Read Write Write Operation Operation Possible Operation Other Bank Operation Write Read Operation Read Write
T2.0 1340
Burst Mode Read (Synchronous)
SST34WA3203/3204 default configuration powerup after reset Asynchronous Read. However, configured operate Synchronous Read mode with continuous, sequential linear burst operation linear burst operation 16-, 32-words length with wraparound. Before setting device configuration Burst Mode, determine number wait states initial word access time (TIACC) desired Burst mode- continuous with, without, wrap-around.
Note: purposes this table, "Write" means perform Sector/Block Word-Program operations applicable appropriate bank.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification Wait States power SST34WA3203/3204 defaults asynchronous read operation. device automatically enabled burst mode first rising edge input, while AVD# held clock cycle address latched first rising edge CLK. Prior activating clock signal, system determines many wait states desired initial word (TIACC) each burst session. system then writes Configuration Register command sequence. device automatically delays RY/BY# needed number clock cycles data ready. Refer details "Handshaking Feature" section. initial word output Data TIACC after active edge first cycle. Each successive clock cycle automatically increments addresses counter. Subsequent words output Data TBACC after active edge each successive clock cycle. return device Asynchronous Read mode, either drive BEF# drive RST# VIL,.
Power-up/ Hardware Reset
Asynchronous Read Mode Only
Active edge when AVD#
BEF# RST#
Synchronous Read Mode Only
1340 F01.1
FIGURE Synchronous/Asynchronous State Diagram 16-, 32-Words Linear Burst Mode with WrapAround SST34WA3203/3204 device supports synchronous read operation with Linear Burst mode predetermined word length with wrap-around. Groups words read this defined Table 32-words Linear Burst mode operation, starting address linear burst sequence address written device. Each successive clock cycle automatically increments address counter until address group reached. Once address reached, address wraps back first address selected group continues incrementing from there. example 8-word linear Burst mode with WrapAround follows: starting address 8-word mode words group start 10H, group 17H), address range read would 10H-17H, burst sequence would -12H -13H RY/BY# will indicate when valid data present data bus.
TABLE 16-, 32-Words Linear Burst Mode Wrap-Around Groups
Group Size Address Ranges
words words words
00000H 00007H 00000H 0000FH 00000H 0001FH
00008H 0000FH 00010H 0001FH 00020H 0003FH
00010H 00017H 00020H 0002FH 00040H 0005FH
(A)1 (B)1 (C)1 1FH)
T3.0 1340
multiple 00008H, multiple 00010H, multiple 00020H.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification 8-16-32-Words Linear Burst Mode without WrapAround SST34WA3203/3204 device supports synchronous read operation without Linear Burst mode. fixed number words predefined 16-, 32-words read from consecutive addresses starting with initial word, which written device. Once fixed number words read completely, Burst Read operation stops RY/BY# output goes low. There group limitation there with Linear Burst with Wrap-Around. Table group definitions. example 8-word linear Burst mode without WrapAround follows: 8-word length Burst Read, starting address written device 39h, burst sequence would 39-3A-3B-3C-3D-3E-3F-40h, read operation will terminated 40h. similar fashion, 16-word 32-word modes begin their burst sequence starting address written device, Continuously Read predefined word length, words. operation similar Continuous Burst, will stop operation fixed word length. device crosses first 32-word address boundary during burst read, latency occur before data appears next address RY/BY# pulsing low. burst read start address 8-word boundary aligned latency does occur. host system crosses bank boundary, device will react same manner Continuous Burst. Continuous Linear Burst Mode SST34WA3203/3204 device supports synchronous read operation with continuous, sequential linear Burst mode read. When this mode, Addresses automatically incriminated linearly with every successive clock active edge. device reaches Highest Memory Location Address (FFFFFH), will continue continuous, sequential linear Burst read operation wrapping around Address 00000H. Burst operation will continue sequentially until another address latched AVD# pin, until BEF# driven VIH, until RST# driven VIL. When address latched AVD# with active edge CLK, burst read will start with initial address. continuous, sequential linear burst read sequence crosses bank boundary into bank that performing Programming Erasing operation, device will provide status information. Once system completed status read operation, device completed Program/Erase Operation, system allowed start burst read operation. this case address needs latched AVD# pin. synchronous, continuous, sequential, linear read array, latency output data occur when burst sequence crosses first 32-word address boundary. burst read start address 8-word boundary aligned delay does occur. burst read start address mis-aligned 8-word boundary, delay occurs once burst-mode read sequence. RY/BY# signal will indicate this delay system. Burst Register SST34WA3203/3204 defaults Asynchronous Read power-up. However, configured operate Synchronous Read Mode with continuous, sequential linear burst operation linear burst operation 16-, words length with wrap-around. Burst Register used configure type read access memory will perform setting desired Mode Burst (continuous wrap-around) number wait states initial word access time (TIACC). user Burst Register with Burst Register Command. Burst Register will retain information until reset RST# after PowerUp. Burst Register Command initiated executing three-cycle command sequence. last cycle, Data C0H, address bits A11-A0 555H, address bits A17-A12 code latched, shown Table Upon power-up hardware reset using RST# pin, device will default state. Burst Register only changed Read Erase Suspend mode.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Burst Mode Configuration Command
Function Address Value values wait states initial word wait states initial word wait states initial word wait states initial word wait states initial word (default) Reserved Reserved values Continuous burst (default) 8-word linear burst 16-word linear burst 32-word linear burst linear burst with wrap-around (default) linear burst without wrap-around
T4.0 1340
Programmable Initial Wait State
Burst Mode Type
Note: Device will default state after Hardware Reset (via RST# pin) after Power-Up.
Burst Suspend/Resume
Burst Suspend Resume feature allows system temporarily suspend synchronous burst operation during initial access, before data available, after device reading data. When burst operation suspended, previously latched internal data current state retained. Burst Suspend occurs when BEF# asserted, deasserted, de-asserted. must halted VIL. resume burst access, reasserted, afterwards restarted. Subsequent edges resume burst sequence where suspended. When Burst Suspend enabled device will enter power mode, which current consumption reduced typically 1mA. RY/BY# pin, which controlled BEF#, will remain active placed into high-impedance state when de-asserted.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Writing Commands
SST34WA3203/3204 accept address data information form program commands. write command, system needs drive BEF#, VIL. addresses latched rising edge AVD# while keeping VIH, data latched rising edge while keeping
acceleration mode return read mode. first cycle contains data 90h, second cycle contains data 00h.
Eight-Word Program
Eight Word Program command provided fast data programming. room temperature normal VDD, command only enabled when Supervoltage (11.4V 12V). Eight Word Program Operation initiated with command then host provides eight consecutive data words. Eight Word program Asynchronous operation signal ignored. system drives BEF# Initial address latched rising edge first AVD# pulse while keeping high. Data latched rising edge each pulse while keeping high. Figure timings. Initial address AINI must 8-words boundary aligned otherwise part will force boundary alignment. Each subsequent pulse will automatically increment address word from AINI AINI user must issue data words programmed when Eight Word Program Mode.
Word-Program Operation
SST34WA3203/3204 programmed word-byword basis. Before programming, erase sector programmed. Program operation accomplished three phases. First, Software Data Protection initiated using three-word load sequence. Next, word address word data loaded. Finally, internal Program operation initiates after rising edge fourth WE#. Program operation completes within SST34WA3203/3204 features programming acceleration mode faster programming. Once device enters programming acceleration mode, only write cycles required program word, instead four cycles required standard program command sequence. During Program operation, only valid reads within bank being programmed status reads (DQ7 Data# Polling DQ2/DQ6 Toggle Bits). commands issued during internal Program operation ignored. When Program Operation complete, bank will return Read Array Mode. Program operation timing diagram flowchart, Figure Figure
Standby Mode
SST34WA3203/3204 enter Standby mode when both BEF# RST# inputs held device requires standard access time (TCE) read access before ready read data.
Auto Power Mode
These devices have Auto Lower Power mode which puts near standby mode. Asynchronous read mode, this happens when addresses remain stable within TACC after data accessed with valid Read operation. This reduces active Read current typically. While BEF# low, device exits Auto Power mode with address transition control signal transition used initiate another Read cycle, with access time penalty. While Auto Power mode, output data latched always available system. synchronous read mode, after AVD# falling edge, device automatically enters Auto Power mode when there active edge within TACC+ 60ns. device exits Auto Power mode with active edge.
Programming Acceleration Operation
programming acceleration makes programing faster than using standard program command sequence because reduces standard four-cycle process cycles. unlock cycles initiates programming acceleration command sequence which followed third write cycle containing programming acceleration command. chip enters programming acceleration mode. program this mode, two-cycle programming acceleration program command sequence that required. first cycle contains programming acceleration command, A0h; second cycle contains program address data. Likewise, additional data programmed. initial unlock cycles required standard program command sequence eliminated. This reduces total programming time. Table programming acceleration command sequence requirements. system issues two-cycle programming acceleration reset command sequence exit programming
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Memory Architecture
SST34WA3203/3204 features 4-bank,512 KWord uniform multi-bank architecture. four banks, bottom banks contain standard KWord blocks four parameter KWord blocks added granularity. remaining three banks each contain uniform KWord blocks. KWord blocks further divided into uniform KWord sectors, respectively. Each block sector individually erased greater flexibility. device's unique bank architecture, allows reads from bank while another bank being erased (RWE) programmed (RWP). device also supports Erase-Suspend mode that allows programming data other sector block other than being erase-suspended. also read data memory sector block other than being erased during Erase-Suspend operation. Suspend operations cannot nested because system needs complete resume previously suspended operation before operation suspended.
Erase-Suspend, Erase-Resume Operations
Erase-Suspend command temporarily suspends Sector/Block-Erase operation which allows data read from memory location, programmed into sector block that suspended Erase operation. operation executed issuing EraseSuspend one-word command, B0H. device automatically enters Erase-Suspend Read Mode within TES, after Erase-Suspend command issued. Valid data read from sector block that suspended from Erase operation. Reading address location within erase-suspended sectors blocks will output toggling `1'. Table Write Operation Status, details. While Erase-Suspend mode, Word-Program operations allowed sectors blocks, with exception sector block selected Erase-Suspend. Word Program operation attempted suspended sector block, command rejected Program operation performed. system also issue Software Entry command during Erase-Suspend. After system issued Software Exit command, device automatically reverts Read Mode. resume Sector/Block-Erase operation that suspended, system must issue Erase-Resume command. operation executed issuing EraseResume one-word command, 30H, address last word sequence. erase operation being suspended re-suspended after resume, cumulative erase time needed greater than erase time non-suspended erase operation. accumulative erase time needed become very long hold time from Erase-Resume next EraseSuspend operation, TERH, less than 330µs. Erase-Resume command will ignored until program operations initiated during Erase-Suspend complete. Erase-Suspend Program Resume operations have influence program operation. Table details Suspend-Resume Concurrent operations.
Sector/Block-Erase Operation
Sector/Block-Erase operation allows system erase device sector-by-sector block-by-block basis. SST34WA3203/3204 offers Sector-Erase Block-Erase modes. sector architecture based uniform sector size KWord. Block-Erase mode erases either regular KWord blocks smaller KWord Parameter Blocks. Sector-Erase operation initiated executing six-word command sequence with Sector-Erase command (50H) sector address (SA) last cycle. Block-Erase operation initiated executing six-word command sequence with Block-Erase command (30H) block address (BA) last cycle. Sector Block address latched during sixth cycle, either rising edge AVD# falling edge cycle, whichever occurs last, while command (30H/50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. End-of-Erase operation determined using either Data# Polling Toggle methods. Figure timing waveforms Figure flowchart.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Erase-Suspend Concurrent Banks State
Current Operation Bank Sector/Block-Erase-Suspend Sector/Block-Erase-Suspend Sector/Block-Erase-Suspend Sector/Block-Erase-Suspend Sector/Block-Erase-Suspend Sector/Block-Erase-Suspend Possible Operation Same Bank Read other Sector/Block within same Bank Read other Sector/Block within same Bank Program other Sector/Block within same Bank Program other Sector/Block within same Bank Operation Operation Possible Operation Other Concurrent Bank Operation Program Sector/Block Operation Read Sector/Block Read Sector/Block Program Sector/Block
T5.0 1340
Chip-Erase Operation
SST34WA3203/3204 provides Chip-Erase operation which allows user erase entire memory array state. This quick erase entire device. initiate Chip-Erase execute six-word command sequence with Chip-Erase command, 10H, address 555H last word sequence. Erase operation begins with rising edge sixth WE#. During Erase operation, only valid reads Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored, including Erase-Suspend Command. held VIL, more blocks locked, Chip Erase Operation disabled.
Ready (RY/BY#)
RY/BY# dedicated status output that indicates valid output data A/DQ15-A/DQ0 during synchronous burst reads. When RY/BY# asserted (RY/BY# VOH), output data valid read. When RY/BY# de-asserted (RY/BY# VOL), system will wait until re-asserted before expecting next word data. conditions cause RY/BY# output low: during initial access while burst mode, when device Continuous Burst Mode address crosses first word boundary. asynchronous, non-burst mode, RY/BY# does indicate valid invalid output data. Instead, RY/BY# when BEF# VIL, RY/BY# Hi-Z when BEF# VIH.
Write Operation Status Detection
SST34WA3203/3204 optimizes system Write cycle time providing software means detect completion Program Write cycle Erase Write cycle. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-ofWrite detection mode, which enabled after rising edge WE#, initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling (DQ7), Toggle (DQ6) Read simultaneous with completion Write cycle. this occurs, system will erroneous result. example, valid data appear conflict with either DQ6. order prevent spurious rejection when erroneous result occurs, software routine must include loop read accessed location additional time. both Reads indicate completion, then Write cycle completed.
Data# Polling (DQ7)
When SST34WA3203/3204 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth pulse Program operation. Sector/ Block Chip-Erase, Data# Polling valid after rising edge sixth pulse. Figure Data# Polling timing diagram Figure flowchart.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Toggle Bits (DQ6 DQ2)
During internal Program Erase operation, consecutive attempts read will produce alternating `1's `0's. example, toggling between `0'. When internal Program Erase operation complete, will stop toggling. device then ready next operation. Sector-, Block-, Chip-Erase, toggle (DQ6) valid after rising edge sixth pulse. will Read operation attempted Erase-Suspended Sector/Block. Program operation initiated sector/block selected Erase-Suspend mode, will toggle. additional Toggle available DQ2, which used conjunction with check whether particular sector being actively erased erase-suspended. Table shows detailed status information. Toggle (DQ2) valid after rising edge last pulse Write operation. Figure Toggle timing diagram Figure flowchart. TABLE Write Operation Status
Status Normal Standard Operation Program Standard Erase EraseSuspend Mode Read from Erase-Suspended Sector/Block Read from Non- EraseSuspended Sector/Block Program DQ7# Toggle Toggle Toggle Toggle Toggle
Data Protection
SST34WA3203/3204 provides both hardware software features protect nonvolatile data from inadvertent writes.
Hardware Data Protection
devise provides following protection features prevent inadvertent writes: Noise/Glitch Protection: BEF# pulse less than will initiate write cycle. Power Up/Down Detection: Write operation inhibited when less than 0.9V. Write Inhibit Mode: Forcing low, BEF# high, high will inhibit Write operation. This prevents inadvertent writes during power-up powerdown. When brought Supervoltage Eight Word Program command enabled. this case, blocks temporarily unprotected regardless Block Locking Register. only device operation available when Eight Word Programming, must held above during other operations. Eight Word Programming provided fast data programming manufacturing environment. device will return normal operations when voltage each block locking status will depend Block Locking Register value (this value that each block before application ACC). must left floating unconnected. When brought device locked. should normal operations.
Data
Data
Data
Data
DQ7#
Toggle
T6.0 1340
SST34WA3203/3204 provides hardware block protection which protects KWords Blocks (SST34WA3203), and/or BA65 BA66 (SST34WA3204). stands Block Address specified Table KWord blocks, located bottom blocks, protected when held VIL. Program Erase operation these blocks disabled independently using Block Locking Register Status. user disable hardware protection outermost blocks driving VIH. this case, Protection Status outermost Blocks will revert what indicated corresponding Block Locking Registers. will latched specific time program erase sequence. prevent write outermost blocks, must held last write cycle sequence. example, write cycle program sequence write cycle erase sequence. using programming acceleration feature, program
Note: Note: DQ7, require valid address when reading status information. When Erase-Suspend Mode system read either synchronously (Burst) asynchronously.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification cycle after programming acceleration command written, must held cycle. held Chip Erase Operation disabled. should pulled into high state used. Software Block Locking prevent accidental data programming erasing, Block Lock command used. KWord main blocks parameter blocks independently locked. locked block able programmed erased. After Power-Up, blocks locked. Changing state-of-lock block done using Block Lock/Unlock Command (60H). Table third cycle address must point Block locked/unlocked. status Address will specify block must locked (A6=VIL) unlocked (A6=VIH). After third cycle, state-of-lock additional Blocks same Bank modified. Reading state-of-lock each block achieved using Read Block Locking Register command with TABLE Block Locking Register Data
Reserved Bits BLR[15:1] 000000000000000 000000000000000 Write-Lock bit: BLR[0] Code 0000H 0001H Lock Status Full Access Write Locked (Default State Power-Up)
T7.0 1340
address parameter that within block address space details, Table This command will read Block Locking Register. Block Locking Register 0000H Block Unlocked, 0001H Block Locked. Read Block Locking Register command written bank which either Read Mode EraseSuspend-Read mode. Only bank time switched Read Block Locking Register mode. return selected bank Read Mode, Erase-Suspend Read Mode, Software Exit/Block Locking Exit Command must issued system. Table internally ORed with Block Locking register. When low, blocks hardware write protected regardless state Write-Lock corresponding Block Locking registers. Clearing WriteProtect register when will have functional effect, even though register indicate that block longer locked. After third cycle, state-of-lock additional Blocks same Bank modified.
Note: default read status blocks upon power-up write-locked ("01H"). After power-up, when power supply (VDD) valid, register alterable.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Hardware Reset (RST#)
RST# provides hardware method resetting devices read array data. When RST# held least in-progress operation will terminate device will return Read Array mode. When internal Program/Erase operation progress, minimum period required after RST# driven high before valid Read take place. interrupted Erase operation must reinitiated after device resumes normal operation mode ensure data integrity. RST# asynchronous input signal which aborts on-going Erase Program operation resets device Read Array mode within time TReadyw. RST# asserted during Read Operation, required time reset device TReady. this point outputs tri-stated, device ignores Read/ Write operations duration RST# pulse. RST# reset operation will also reset Burst Configuration register Asynchronous Read Mode part Read Array mode. current consumption when RST# held 0.2V, reduced Stand-By values. mode Erase-Suspend Read mode from Query mode.
Security
SST34WA3203/3204 device offers 136-word Security space. Secure space divided into segments-one 8-word, 128-bit factory programmed segment 128-word user programmed segment. first segment programmed locked with unique 128-bit number. user segment left unprogrammed customer program desired. program user segment Security Security Word-Program command required. Check end-of-write status Security reading toggle bits. Data# Polling detect end-ofwrite. Once programming complete, must locked using User Program Lock-Out, which disables future corruption this space. Neither segment-user factory programmed-can erased, regardless whether locked. Secure space queried executing threeword command sequence with Enter command (88H) address 555H last byte sequence. exit this mode, Exit command should executed. Refer Table more details. Security space located addresses 000000H 0000FFH. Factory programmed segment located addresses 000000H 000007H. User segment located address 000080H 0000FFH. Security Locked/Unlocked status read Address 000007FH. Table User Segment Security Unlocked. When `0', User Segment Security Locked. Once Query Security Command executed, system read Security space with normal Read cycles using valid address range 0000000H 00000FFH. Table more details.
Software Data Protection (SDP)
SST34WA3203/3204 provides JEDEC approved Software Data Protection scheme data alteration operations, such Program Erase. single word Program operation requires inclusion three-word sequence. three-word load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations; instance, during system power-up power-down. Erase operation requires inclusion six-word sequence. These devices shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device read mode within TRC. contents DQ15- VIH, other value, during command sequence.
TABLE Security Valid Range
Security Segment Factory Programmed User Programmed Locked/ Unlocked Status Start Address 000000H 000080H 00007FH
T8.0 1340
Common Flash Memory Interface (CFI)
SST34WA3203/3204 contains information describe characteristics device. order enter Query mode, system must write word command three-word sequence, with 98H- Query command-to address 555H last word sequence. Once device enters Query mode, system read data addresses given Tables through System write entry command when device Read Array mode also when device Product Identification Mode. system must write Exit command return Read
©2007 Silicon Storage Technology, Inc.
Address 000007H 0000FFH
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Product Identification
Product Identification mode identifies devices manufacturer. software operation details Table Software Entry command sequence flowchart Figure Product Identification Mode (PIM) entered issuing unlock cycles. This must followed third cycle that contains Bank Address using A19) Product Identification Mode command. After this third cycle, addressed Bank enters Product Identification Mode. system read manufacturer Device number times without re-issuing command sequence. Product Identification command written bank that either Read Mode Erase-Suspend Read Mode. Product Identification Command cannot written while device Programming Erasing another bank. system addresses different Bank, memory array data read from device following normal Asynchronous Read operation. subsequent data will made available device Synchronous Mode. system must issue Software Exit command order return Bank previously Product Identification Mode into Read mode Erase-Suspend Read mode. TABLE Product Identification
Address Manufacturer's Device SST34WA3203 SST34WA3204 BKX0001H BKX0001H 975BH 975AH
T9.0 1340
Handshaking Feature
device equipped with handshaking feature that brings fastest initial latency this burst mode flash memory simply monitoring RY/BY# signal from device determine when initial word burst data ready read. this handshaking mode, microprocessor does need register number initial wait clocks. device will indicate when initial word burst data valid rising edge RY/BY# after goes low. handshaking feature used burst mode performance optimization, then host system must appropriate number wait states flash device depending clock frequency. Table more information.
Power-up/Power-down Sequencing
There restrictions sequencing during powerup power-down. Setting RST# level required during entire power sequence until respective supplies reach their operating voltages. Once reach their respective operating voltages, setting RST# level allowed.
Data 00BFH
BKX0000H
Note: Bank Address, using A19.
Product Identification Mode Mode Security Block Locking Exit
order return device standard Read Array Mode, Software Product Identification Security Block Locking Modes must exited. Exit accomplished issuing Software Product Identification Security Block Locking Modes Exit command sequence, which returns device Read mode. This command also used reset device Read Array Mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Software Product Identification Security Block Locking Query/Exit command cannot executed concurrent Program/ Erase operations. Table software command code, Figure flowchart.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
RD/BY# Buffer
RD/BY#
A/DQ15-A/DQ0
Detector Input/Output Buffers Y-Gating RST# State Control Command Register Data Latch Erase Voltage Generator Voltage Generator Y-Decoder Amax Burst State Control Burst Address Counter
1340 B01.0
Cell Matrix
X-Decoder
Timer
BEF#
Chip Enable Output Enable Logic
Address Latch A/DQ15-A/DQ0 Amax -A16
AVD#
FIGURE Logic Diagram
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE SST34WA3203, Mbit Concurrent SuperFlash Multi-Bank Memory Organization
Bank Block BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA21 BA22 BA23 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BA37 BA38 BA39 BA40 BA41 BA42 Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE SST34WA3203, Mbit Concurrent SuperFlash Multi-Bank Memory Organization
Bank Block BA43 BA44 BA45 BA46 BA47 BA48 BA49 BA50 BA51 BA52 BA53 BA54 BA55 BA56 BA57 BA58 BA59 BA60 BA61 BA62 BA63 BA64 BA65 BA66 Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Address Range 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh
T10.0 1340
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE SST34WA3204, Mbit Concurrent SuperFlash Multi-Bank Memory Organization
Bank Block BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA21 BA22 BA23 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BA37 BA38 BA39 BA40 BA41 BA42 Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE SST34WA3204, Mbit Concurrent SuperFlash Multi-Bank Memory Organization
Bank Block BA43 BA44 BA45 BA46 BA47 BA48 BA49 BA50 BA51 BA52 BA53 BA54 BA55 BA56 BA57 BA58 BA59 BA60 BA61 BA62 BA63 BA64 BA65 BA66 Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Address Range 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F9FFFh 1FA000h-1FBFFFh 1FC000h-1FDFFFh 1FE000h-1FFFFFh
T11.0 1340
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
DESCRIPTION
VIEW (balls facing down)
RY/BY#
VDDQ AVD# RST# BEF# VSSQ
A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 A/DQ9 A/DQ8
A/DQ15 A/DQ14 VSSQ A/DQ5 A/DQ4 A/DQ11 A/DQ10 VDDQ A/DQ1 A/DQ0
1340 44-vfbga P01.0
FIGURE Assignments 44-ball FBGA
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Descriptions
Symbol -A16 A/DQ15-A/DQ0 BEF# RST# RY/BY# AVD# VDDQ VSSQ Name Address Inputs Functions provide memory addresses.
Multiplexed Address/Data Sixteen least-significant Addresses multiplexed with Data Input/output. outputs tri-state when BEF# high. Chip Enable Output Enable Write Enable Hardware Reset Ready Output Clock Address Valid Input Write Protect Power Supply Power Supply Power Supply Ground Ground Power Supply Connection VSSQ need shorted together application circuit. Unconnected pins
T12.1 1340
activate device when BEF# low. gate data output buffers control Write operations reset return device Read mode output status Burst Read. "Low" Data Valid, "High" Data Valid increment internal address counter (after initial output delay) when part Burst Mode. required asynchronous mode. indicate device that valid Address present Address protect unprotect bottom KWord outermost sectors) from Erase Program operation. Supervoltage (11.4V 12V) input enable eight word programming. When locks sectors. Should other conditions. provide power Input/Output Buffers. provide 1.7-1.95V power supply voltage. VDDQ need shorted together application circuit.
TABLE Operation Mode Selection
Mode Asynchronous Read Program Erase BEF# AVD# Pulse Pulse Pulse CLK1 A/DQ15-0 Sector block address, XXH2 Chip-Erase Table Table RST#
Standby Write Inhibit Hardware Reset Product Identification Mode (Manufacturer) Product Identification Mode (Device)
High I/O/ DOUT High DOUT High Manufacturer's (00BFH) Device (xxxxH)
Table Table
T13.0 1340
Default Clock Active edge rising edge. VIH, other value. Device SST34WA3203 975BH SST34WA3204 975AH.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Burst Mode Selection
Mode Load Starting Burst Address Automatic Address Advance during Burst Read BEF# AVD# Pulse Pulse CLK1 Active Edge Active Edge Active Edge Active Edge DOUT High High High High Address RST#
T14.0 1340
Terminate Current Burst Read (with BEF#) Terminate Current Burst Read with RST# Terminate Current Burst Read Start Burst Read Burst Suspend
Address Latch reset BEF# going high, there need wait pulse reset
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Software Command Sequence
Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Block Lock/ Unlock5 Write Cycle Addr1 555H 555H 555H 555H XXXH XXXH XXXH Data2 XXXH 2AAH 2AAH 2AAH 2AAH BLAX6 BKX55 BKX8 555H 555H 555H SIWA9 Data 0000H Table Table Write Cycle Addr 2AAH 2AAH 2AAH 2AAH Data Write Cycle Addr 555H 555H 555H 555H Data Write Cycle Addr 555H 555H 555H Data Data 2AAH 2AAH 2AAH SAX4 Write Cycle Addr Data Write Cycle Addr Data
BAX4 555H
Read Block Lock- 555H Register Entry/Query Security User Security Program User Security Program LockOut Software Entry10, Query Entry Software Exit8,
11/CFI Exit/Sec
555H 555H 555H
555H
2AAH
BKX55 5H12
Table Table
BKXX55H
Exit Query Entry cycles) 555H 2AAH 2AAH BKX55 555H
Software Exit/ 555H Exit/ Security Exit cycles) Burst Mode Configuration Register Eight Word Program Programming Acceleration Mode Entry 555H
2AAH
CRX55 5H14
A0H15 Table Table Cycle Seq. Cycle Seq. 2AAH 555H
555H
Programming Acceleration Program16 Programming Acceleration Program Reset17
Data
T15.0 1340
Address format A11-A0 (Hex) Addresses A12-A20 VIH, other value, Command sequence SST34WA3203/3204.
©2007 Silicon Storage Technology, Inc. S71340-02-000 10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
DQ15-DQ8 VIH, other value, Command sequence Program Word address. Sector-Erase; uses A20-A11 address lines Block-Erase; uses A20-A13 address lines indicates Block Locking Register Data: 0000H Block Unlocked, 0001H Block Locked. BLAX indicates Address Block Locked/Unlocked; uses -A13 address lines. This composed Block Address (BA) either Unlock Lock. With A20-A8 Security information read with A7-A0 Factory Unique read Address Range: 000000H 000007H (128-bit). This segment always locked SST. User read Address range: 000080H 0000FFH (128-words). Lock Status User Segment read with 00007FH. Unlocked: Locked: indicates Bank Address: uses -A19 address lines. SIWA: Security Program Word Address: User written Address range: 000080H 0000FFH (128-words). device does remain Software Product Identification mode Powered Down. With A18-A1 A20-A19 (Bank Address), address Bank that being switched Software Mode: Manufacturer 00BFH, read with SST34WA3203 Device 975BH, read with SST34WA3204 Device 975AH, read with users never lock after programming, programmed over previously unprogrammed bits (data=1) using mode again (the programmed bits cannot reversed "1"). Valid Word-Addresses User Security from 000080H 0000FFH. Both Software Exit operations equivalent. Burst Mode Configuration Register Value A17-A12 (see Programmable Wait State Configuration Section). Eight Word Program command only executed Supervoltage must Supervoltage before "A0H" command issued order enable Eight Words Program Command. Programming Acceleration command sequence required prior this command sequence. Programming Acceleration Reset command required return normal read mode when chip Programming Acceleration mode.
TABLE Eight Word Program Software Command Sequence
Cycle Address1 XXXXH3 XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH Data2 DATA DATA DATA DATA DATA DATA DATA DATA Comment Eight Word Program Command Will program "DATA Address Will program "DATA Address Will program "DATA Address Will program "DATA Address Will program "DATA Address Will program "DATA Address Will program "DATA Address Will program "DATA Address
T16.1340
Address format A11-A0 (Hex). Addresses A12- VIH, other value, Command sequence SST34WA3203/3204. DQ15-DQ8 VIH, other value, Command sequence. VIH, other value. Program Word Address first word programmed. Eight-Word Program Mode must 8-word boundary aligned (A0=A1=A2=0).
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Software Read Block Locking Registers
Command Sequence Software Entry: Manufacturer Software Entry: Device Software Entry: Read Block Locking Status Cycle (Write) Addr1 555H Data2 Cycle (Write) Addr 2AAH Data Cycle (Write) Addr BKX555H3 Data Cycle (Read) Addr BKXX00 Data 00BFH
555H
2AAH
BKX555H
BKXX01
xxxxH4
555H
2AAH
BKX555H3
BAXX02
BLR5
T17.0 1340
Address format A11-A0 (Hex). Addresses A12-A20 VIH, other value, Command sequence SST34WA3203/3204. DQ15-DQ8 VIH, other value, Command sequence. indicates Bank Address: uses A20-A19 address lines. indicates Address Block Locked/Unlocked; uses A20-A13 address lines. This composed Block Address (BAX). SST34WA3203 975BH SST34WA3204 975AH indicates Block Locking Register Data: 0000H Block Unlocked, 0001H Block Locked.
TABLE Query Identification String1,
Address Data 0051H 0052H 0059H 0001H 0007H 0040H 0000H 0000H 0000H 0000H 0000H
T18.0 1340
Description Query Unique ASCII string "QRY"
Primary command Address Primary Extended Table Alternate command (00H none exists) Address Alternate extended Table (00H none exits)
Refer publication more details. Must same when Query Entry mode.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE System Interface Information1
Address Data 0017H 0019H 00B4H 00C0H 0003H 0000H 0004H 0005H 0001H 0000H 0001H 0001H Description (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (00H pin) (00H pin) Typical time Word-Program Typical time size buffer program (00H supported) Typical time individual Sector/Block-Erase Typical time Chip-Erase Maximum time Word-Program times typical Maximum time buffer program times typical Maximum time individual Sector/Block-Erase times typical Maximum time Chip-Erase times typical
T19.1 1340
Must same when Query Entry mode.
TABLE Device Geometry Information SST34WA32031
Address Data 0016H 0001H 0000H 0000H 0000H 0002H 0003H 0000H 0040H 0000H 003EH 0000H 0000H 0001H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
T20.1 1340
Description Device size Bytes (16H MByte) Flash Device Interface description; 0001H x16-only asynchronous interface Maximum number bytes multi-byte write 2N(00H supported) Number Erase Block sizes supported device Block Information Number blocks; 256B block size) blocks Bytes KBytes/block Block Information Number blocks; 256B block size) blocks 100H Bytes KByte/block
Must same when Query Entry mode
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Device Geometry Information SST34WA32041
Address Data 0016H 0001H 0000H 0000H 0000H 0002H 003EH 0000H 0000H 0001H 0003H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
T21.1 1340
Description Device size Bytes (16H MByte) Flash Device Interface description; 0001H x16-only asynchronous interface Maximum number bytes multi-byte write 2N(00H supported) Number Erase Block sizes supported device Block Information Number blocks; 256B block size) blocks 100H Bytes KByte/block Block Information Number blocks; 256B block size) blocks Bytes KBytes/block
Must same when Query Entry mode.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Primary Vendor-Specific Extended Query1
Address Data 0050H 0052H 0049H 0031H 0033H 0005H Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) Required, Required Silicon Technology (Bits 5-2) 0001 0.18 Erase-Suspend Supported, Read Only, Read Write Block Protect Supported, Number blocks group Sector Temporary Unprotect Supported, Supported Sector Protect/Unprotect scheme Supported, Supported Simultaneous Operation Number Sectors banks except boot bank Burst Mode Type Supported, Supported Page Mode Type Supported, Word Page, Word Page (Acceleration) Supply Minimum Supported, D7-D4: Volt, D3-D0: (Acceleration) Supply Maximum Supported, D7-D4: Volt, D3-D0: Top/Bottom Boot Sector Flag Bottom Boot Device, Boot Device Program Suspend. supported Bank Organization: Number banks Bank Region Information. Number blocks bank Bank Region Information. Number blocks bank Bank Region Information. Number blocks bank Bank Region Information. Number blocks bank
T22.1 1340
Description Query Unique ASCII string "PRI"
0002H 0001H 0000H 0005H 0018H 0001H 0000H 00B4H 00C0H 00XXH 0000H 0004H 0013H (SST34WA3203) 0010H (SST34WA3204) 0010H 0010H 0010H (SST34WA3203) 0013H (SST34WA3204)
Must same when Query Entry mode.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature under Bias. -55°C +125°C Storage Temperature -65°C +125°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Voltage Ground Potential -0.5V +14V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Solder Reflow Temperature1 260°C seconds Output Short Circuit Current2
Please consult factory latest information. Outputs shorted more than second. more than output shorted time.
Operating Range
Range Ambient Temp -20°C +85°C 1.7V-1.95V
Extended Conditions Test
Input Rise/Fall Time Output Load Figures
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Characteristics
TABLE Operating Characteristics 1.7-1.95V
Symbol
Parameter Active Current Asynchronous Read Program Erase Concurrent Read/Write
Freq
Limits Units
Test Conditions
BEF#=VIL, OE#=WE#=VIH, Array background 55AAH BEF#=WE#=VIL, OE#=ACC=VIH BEF#=VIL, OE#=VIH BEF#=VIL, OE#=VIH, WE#=VIH, Array background 55AAH BEF#= 0.1V RST#= -0.1V other inputs= 0.1V VDD-0.1V BEF#= 0.1V RST#= -0.1V OE#= -0.1V WE#= -0.1V other inputs= 0.1V VDD-0.1V =GND VDD, VDD=VDD VOUT =GND VDD, VDD=VDD VDD=VDD Max, ACC=VH VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD 1.8V
T23.0 1340
IDDB
Active Burst Read Current Standby Current
IALP2
Auto Power Current
VLKO
Input Leakage Current Output Leakage Current Supervoltage Current Eight-Word Program Input Voltage Input High Voltage Output Voltage Output High Voltage Supervoltage Eight-Word Program Lock-Out Voltage VDD-0.1 11.4
Address input VILT/VIHT, VDD=VDD Device enters Auto Power Mode when addresses stable TACC 60ns.
TABLE Capacitance 25°C, Mhz, other pins open)
Parameter CI/O1 CIN1 Description Capacitance Input Capacitance Test Condition VI/O Maximum
T24.0 1340
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Reliability Characteristics
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Minimum Specification 100,000 Units Cycles Years Test Method JEDEC Standard JEDEC Standard A103 JEDEC Standard
T25.0 1340
This parameter measured only initial qualification after design process change that could affect this parameter.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Synchronous/Burst Read (54MHz/66MHz) Cycle Timing Parameters 1.7-1.95V1
Symbol TIACC TBACC TACS TACH TBDH TCEZ TOEZ TCES TRACC TRY/BY#S TAVDS TAVDH TAVDO TCKA TOECH TAAH Parameter Initial Access time Burst Access Time, Valid Clock Output Delay Address Setup Time CLK2 Address Hold Time from CLK2 Data Hold Time from Next Clock Cycle Data Valid (OE# RY/BY# Valid) BEF# High-Z High-Z BEF# Setup Time RY/BY# Access Time from RY/BY# Setup Time AVD# setup time AVD# hold time from AVD# High Access Resume Hold time from burst-suspend Address Hold Time from Rising Edge AVD# 13.5 13.5 11.5 13.5 11.5 87.5 13.5 11.5 11.5 Units
T26.1340
100% tested. Test Conditions: Output Load: VDD: 30pF Input Pulse Levels: 0.0V Input: Input Rise Fall Times: Timing measurements reference level Output:
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Asynchronous Read Cycle Timing Parameters 1.7-1.95V
Symbol TACC TAVDP TAAS TAAH TOEH TOEZ TCEZ Parameter Access Time from BEF# Asynchronous Access AVD# Time Address Setup Time Rising Edge AVD# Address Hold Time from Rising Edge AVD# Data Valid Output Enable Hold Time from high (Read Operation) Output Enable Hold Time from high (Toggle Data Poll) Output Enable High-Z2 BEF# High-Z2 Time1 13.5 11.5 Units
T27.0 1340
Asynchronous Access Time from last either stable addresses falling edge AVD# 100% tested
TABLE Program/Erase Cycle Timing Parameters1
Symbol TAVDP TCLAH TGHWL TWPH TSRW TAHWL TIDA TSCE TERH TVLHT Parameter Word-Program Time Write Cycle Time Units
T28.0 1340
AVD# Time BEF# AVD# High Data Setup Time Data Hold Time Read Recovery Time before Write BEF# Hold Time Pulse Width Pulse Width High Latency Between Read Write Operations BEF# Time AVD# High Software Access Exit Time Sector Erase Time Block Erase Time Chip Erase Time Erase Suspend Latency Time Erase-Resume Hold Time next Erase-Suspend Rise time Supervoltage Voltage Transition Time
100% tested.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Power Timings1
Symbol TPU-READ TPU-WRITE TRSTH
100% tested.
Parameter Power-up Read Operation Power-up Write Operation RST# Hold Time after VDD/VDDQ setup
Minimum
units
T29.0 1340
TABLE Hardware Reset
Symbol TREADYW TREADY TRPD
100% tested.
Parameter RST# Read Mode (During Embedded Algorithm)1 RST# Read Mode (NOT During Embedded RST# Pulse Width RST# High Time Before Read RST# Stand-By Mode Algorithm)1
Units
T30.0 1340
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Clock Input Parameter1
Symbol FCLK TCLK TCHCL TCHLH Parameter Frequency Period High Time from Time from Fall Rise Time from High Time from 18.5 Units
T31.0 1340
100% tested.
BEF# TOEH
TACC
TOEZ
Valid
A/DQ15-A/DQ0
A20-A16
TAAS AVD# TAVDP
TAAH
Note: Read Address, Read Data.
1340 F11.0
FIGURE Asynchronous Mode Read
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
TCES BEF# TAVDS AVD# TAVDH TAVDO TACS TACH A/DQ15 A/D0 TIACC RY/BY# TAAH
15.2 typ. MHz)
TCEZ
TBDH
TBACC
TOEZ
TRACC
TRD/BY#
1340 F9.0
FIGURE Synchronous Burst Mode Read
TCES BEF#
MHZ)
TAVDS AVD# TACS DQ15 A/DQ0 TACH
TIACC
TAAH
TBDH
TBACC
RY/BY# TRD/BY#
1340 F10.0
TRACC
Note: Figure assumes seven wait states initial access, clock, automatic detect synchronous read. d0-d7 data waveform indicate order data within given 8-word address range, from lowest highest. Data will wrap around within words, non-stop unless RESET# asserted low, AVD# locks another address. device will output RD/BY# with valid data.
FIGURE 8-Word Linear Burst with Wrap-Around
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
AVD#
A20-A16 TOECH A/DQ15-A/DQ0
RY/BY#
BEF#
1340 F21.2
FIGURE Burst Suspend
Program Command Sequence (last cycles)
Read Status Data
TCLAH TAVDP AVD#
A20-A16 TAAS A/DQ15-A/DQ0
555h
TAAH
Progress
Complete
BEF# TAHWL TPU-READ
TWPH
1340 F12.0
Note: Program Address, Program Data, Valid Address reading status bits. Progress" "Complete" refer status program operation. Amax don't care during command sequence cycles. don't care. Addresses latched rising edge AVD.
FIGURE Program Operation Timings
©2007 Silicon Storage Technology, Inc. S71340-02-000 10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Erase Command Sequence (last cycles)
Read Status Data
TAVDP AVD# TCLAH A20-A16 TAAS TAAH A/DQ15-A/DQ0
2AAh SA/BA SA/BA
555h Chip Erase Block Erase Chip Erase
Progress
Complete
BEF#
TPU-READ
1340 F13.2
TWPH
TSE/TBE/TSCE
Note: sector address Sector Erase. block address Block Erase. Address bits don't care during cycles command sequence.
FIGURE Chip/Block/Sector Erase Command Sequence
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
TAAH
TVLHT AVD#
TAAS
A20-A16
AINI
A/DQ15-A/DQ0 BEF#
555h
AINI
Data
Data
Data
Data
Data
1340 F8.0
FIGURE Eight Words Programming
AVD# BEF# TOEH TACC A20-A16
TCEZ
TOEZ
A/DQ15-A/DQ0
Status Data
Status Data
1340 F14.0
Note: Valid Address. Read cycles required determine status. When Embedded Algorithm operation complete, Data# Polling will output true data. AVD# must toggle between data reads.
FIGURE Data# Polling Timings (During Embedded Algorithms)
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
AVD# BEF# TOEH TACC A20-A16
TCEZ
TOEZ
A/DQ15-A/DQ0
Status Data
Status Data
1340 F15.0
Note: Valid Address. Read cycles required determine status. When Embedded Algorithm operation complete, Data# Polling will output true data. AVD# must toggle between data reads.
FIGURE Toggle Timings (During Embedded Algorithms)
Address boundary occurs every words, beginning address 00001Fh (00003Fh, 00005Fh, etc.). Address 000000H also boundary crossing.
Address (hex) AVD# (stays high)
TRACC RY/BY# latency
A/DQ15-A/DQ0
1340 F17.0
Note: indicates which clock triggers output. example, triggers D30. figure shows that device does cross bank when performing erase program operation. latency with boundary crossing happens 32-word boundary.
FIGURE Latency with Boundary Crossing
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
C253 Address (hex) AVD# 3FFFD (stays high)
C254 3FFFE
C255 3FFFF
C256 40000
C257 40001
RY/BY#
(stays high) D253 D254 D255 Read Status
A/DQ15-A/DQ0
BEF#/OE#
(stays low)
1340 F18.0
Note: Cxxx indicates which clock triggers Dxxx output. example, C253 triggers D253. figure shows that device cross bank when performing erase program operation.
FIGURE Boundary Crossing into Program/Erase Bank
A/DQ15-A/DQ0
AVD#
Rising edge next clock cycle following last wait state triggers next burst data
Total number clock cycles following AVD# falling edge
Number clock cycles programmed Wait State Decoding Addresses: A14, A13, "101" programmed, total A14, A13, "100" programmed, total A14, A13, "011" programmed, total A14, A13, "010" programmed, total A14, A13, "001" programmed, total
1340 F19.0
Note: Figure assumes address. address boundary, active clock edge rising, wait state `101.'
FIGURE Example Wait State Insertion
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Last Cycle Program Sector Erase Copmmand Sequence
Read status least cycles) same bank and/or array data from other bank
Begin another write program command sequence
BEF#
TOEH TWPH A/DQ15-A/DQ0
PA/SA PD/50h
TGHWL
TACC
TOEZ
TOEH
555h
TSRW A20-A16
PA/SA
TAAS AVD# TAAH
1340 F20.0
Note: Breakpoints waveforms indicate that system alternately read array data from "non-busy bank" while checking status program erase operation "busy" bank. system should read status twice ensure valid information.
FIGURE Back-to-Back Read/Write Cycle Timings
VDD/VDDQ
TRSTH
RST#
1340 F23.1
FIGURE Power Diagram
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Reset Timings during Embedded Algorithms
BEF#,
RST# TReady
Reset Timings during Embedded Algorithms
BEF#, TReadyw
RST#
1340 F24.0
FIGURE Reset Timings
TCLK
TCH/L
TCHCL
TCHLH
1340 F25.1
FIGURE Clock Input Waveform
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
1340 F26.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1VDD) logic `0.' Measurement reference points inputs outputs (0.5VDD) (0.5VDD). Input rise fall times 10%-90% <5ns. Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE Input/Output Reference Waveforms
TESTER
1340 F27.0
FIGURE Test Load Example
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Start
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XXA0H Address: 555H
Load Word Address/Word Data Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
1340 F28.0
Note: VIH, other value.
FIGURE Word-Program Algorithm
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read word
Read
Program/Erase Completed
Read same word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
1340 F29.0
FIGURE Wait Options
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Query Entry Command Sequence Load data: XXAAH Address: 555H
Query Entry Command Sequence Load data: XXAAH Address: 555H
Software Product Entry Command Sequence Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX98H Address: 555H
Load data: XX88H Address: 555H
Load data: XX90H Address: 555H
Wait TIDA
Wait TIDA
Wait TIDA
Read data
Read
Read Software
1340 F30.0
Note: VIH, other value.
FIGURE Software ID/CFI Entry Command Flowcharts
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Software Exit/CFI Exit/Sec Exit Command Sequence Load data: XXAAH Address: 555H Load data: XXF0H Address:
Load data: XX55H Address: 2AAH
Wait TIDA
Load data: XXF0H Address: 555H
Return normal operation
Wait TIDA
Return normal operation
1340 F31.0
Note: VIH, other value.
FIGURE Software ID/CFI Exit Command Flowcharts
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Chip-Erase Command Sequence Load data: XXAAH Address: 555H
Sector-Erase Command Sequence Load data: XXAAH Address: 555H
Block-Erase Command Sequence Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX10H Address: 555H
Load data: XX50H Address:
Load data: XX30H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
1340 F32.0
Note: VIH, other value.
FIGURE Erase Command Sequence
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
PRODUCT ORDERING INFORMATION
Device SST34WA32 XSpeed Suffix1 Suffix2 Environmental Attribute non-Pb Package Modifier balls Package Type VFBGA (6mm 0.92mm, 0.3mm ball size) Temperature Range Extended -20°C +85°C Minimum Endurance 5=100,000 cycles Read Access Speed Boot Block Protection Bottom Boot Block Boot Block PSRAM Density zero PSRAM Flash Density Voltage 1.7-1.95V Product Series Concurrent SuperFlash with Burst
Environmental suffix denotes non-Pb solder. non-Pb solder devices "RoHS Compliant".
Valid combinations SST34WA3203 SST34WA3203-70-5E- MVJE Valid combinations SST34WA3204 SST34WA3204-70-5E- MVJE Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
PACKAGE DIAGRAMS
VIEW
8.00 ±0.08
BOTTOM VIEW
6.50 0.50 0.05 (44X)
6.00 ±0.08
3.50
0.50
CORNER INDICATOR
DETAIL
0.92 0.08
SIDE VIEW
0.08
SEATING PLANE
0.21 0.06
Note:
Although many dimensions similar those JEDEC Publication MO-225, this specific package registered. linear dimensions millimeters. Coplanarity: 0.08 Ball opening size 0.25 0.05
44-fbga-MVJ-6x8-0.0
FIGURE 44-Ball Very Fine-pitch Ball Grid Array (VFBGA) Package Code:
©2007 Silicon Storage Technology, Inc.
S71340-02-000
10/07
Mbit Burst Mode Concurrent SuperFlash Memory SST34WA3203 SST34WA3204
Preliminary Specification TABLE Revision History
Number Description Date 2007 2007
Initial Release Changed globally. Changed Table Note page Moved bank labels Table Changed Program-/Erase-Suspend Erase-Suspend Table Changed Program-/Erase-Resume Erase-Resume Table Changed BAx555H BKx555H Table Changed 0008H 0010H places Table Changed "Program-/Erase-Suspend" "Erase-Suspend" Table Corrected Product Ordering Information-Package Type/Package Modifier. Updated "Wait States" page Changed "ACC Pin" "WP# Pin" page Added reference "Handshaking Feature" page Added footnote Tables
2007
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2007 Silicon Storage Technology, Inc. S71340-02-000 10/07

SST34WA3203 SST34WA3204 Organized Single Voltage Read Write Opera

Top Searches for this datasheet

Other recent searches