SST34HF324G SST34HF324G32Mb Dual-Bank Flash SRAM ComboMemory
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory
SST34HF324G
SST34HF324G32Mb Dual-Bank Flash SRAM ComboMemory
Data Sheet
FEATURES:
Flash Organization: Mbit: 24Mbit 8Mbit Concurrent Operation Read from Write SRAM while Erase/Program Flash SRAM Organization: Mbit: 256K Single 2.7-3.3V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: (typical values MHz) Active Current: Flash (typical) SRAM (typical) Standby Current: (typical) Hardware Sector Protection (WP#) Protects outer most sectors KWord) smaller bank holding unprotects holding high Hardware Reset (RST#) Resets internal state machine reading data array Sector-Erase Capability Uniform KWord sectors Block-Erase Capability Uniform KWord blocks Read Access Time Flash: SRAM: Erase-Suspend Erase-Resume Capabilities Latched Address Data Fast Erase Word-Program (typical): Sector-Erase Time: Block-Erase Time: Chip-Erase Time: Word-Program Time: Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Command Packages Available 48-ball LFBGA (6mm 8mm) non-Pb (lead-free) devices RoHS compliant
PRODUCT DESCRIPTION
SST34HF324G ComboMemory integrates CMOS flash memory bank with 256K CMOS SRAM memory bank multi-chip package (MCP). This device fabricated using proprietary, high-performance CMOS SuperFlash technology incorporating split-gate cell design thick-oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST34HF324G ideal applications such cellular phones, devices, PDAs, other portable electronic devices power small form factor system. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore, system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. SST34HF324G devices offer guaranteed endurance 10,000 cycles. Data retention rated greater than years. With high-performance Program operations, flash memory banks provide typical
©2007 Silicon Storage Technology, Inc. S71310-02-EOL 12/07
Word-Program time µsec. protect against inadvertent flash write, SST34HF324G devices contain on-chip hardware software data protection schemes. flash SRAM operate independent memory banks with respective bank enable signals. memory bank selection done bank enable signals. SRAM bank enable signal, BES#, selects SRAM bank. flash memory bank enable signal, BEF#, used with Software Data Protection (SDP) command sequence when controlling Erase Program operations flash memory bank. memory banks superimposed same memory address space where they share common address lines, data lines, which minimize power consumption area. Table memory organization. Designed, manufactured, tested applications requiring power small form factor, SST34HF324G offered both commercial extended temperatures small footprint package meet board space constraint requirements. Figure assignments.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. ComboMemory trademark Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
Device Operation
SST34HF324G BES# BEF# control operation either flash SRAM memory bank. When BEF# low, flash bank activated Read, Program Erase operation. When BES# SRAM activated Read Write operation. BEF# BES# cannot level same time. bank enable signals asserted, contention will result device suffer permanent damage. address, data, control lines shared flash SRAM memory banks which minimizes power consumption loading. device goes into standby when BEF# BES# bank enables raised VIHC (Logic High) when BEF# high.
Flash Program Operation
These devices programmed word-by-word basis. Before programming, must ensure that sector which being programmed fully erased. Program operation accomplished three steps: Software Data Protection initiated using three-byte load sequence. Address data loaded. During Program operation, addresses latched falling edge either BEF# WE#, whichever occurs last. data latched rising edge either BEF# WE#, whichever occurs first. internal Program operation initiated after rising edge fourth BEF#, whichever occurs first. Program operation, once initiated, will completed typically within Figures BEF# controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored.
Concurrent Read/Write Operation
SST34HF324G provide unique benefit being able read from write SRAM, while simultaneously erasing programming flash. This allows data alteration code executed from SRAM, while altering data flash. following table lists valid states. Concurrent Read/Write State Table
Flash Program/Erase Program/Erase SRAM Read Write
device will ignore commands when Erase Program operation progress. Note that Product Identification commands SDP; therefore, these commands will also ignored while Erase Program operation progress.
Flash Sector- /Block-Erase Operation
These devices offer both Sector-Erase Block-Erase operations. These operations allow system erase devices sector-by-sector block-by-block) basis. sector architecture based uniform sector size KWord. Block-Erase mode based uniform block size KWord. Sector-Erase operation initiated executing six-byte command sequence with Sector-Erase command (50H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (30H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. commands issued during Block- SectorErase operation ignored except Erase-Suspend Erase-Resume. Figures timing waveforms.
Flash Read Operation
Read operation SST34HF324G controlled BEF# OE#, both have system obtain data from outputs. BEF# used device selection. When BEF# high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either BEF# high. Refer Read cycle timing diagram further details (Figure
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
Flash Chip-Erase Operation
SST34HF324G provide Chip-Erase operation, which allows user erase sectors/blocks state. This useful when device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 555H last byte sequence. Erase operation begins with rising edge sixth BEF#, whichever occurs first. During Erase operation, only valid read Toggle Bits Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling (DQ7) Toggle (DQ6) read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. Flash Data# Polling (DQ7) When device internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth BEF#) pulse Program operation. Sector-, Block-, Chip-Erase, Data# Polling valid after rising edge sixth BEF#) pulse. Figure Data# Polling (DQ7) timing diagram Figure flowchart. Toggle Bits (DQ6 DQ2) During internal Program Erase operation, consecutive attempts read will produce alternating "1"s "0"s, i.e., toggling between When internal Program Erase operation completed, will stop toggling. device then ready next operation. toggle valid after rising edge fourth BEF#) pulse Program operations. Sector-, Block-, Chip-Erase, toggle (DQ6) valid after rising edge sixth BEF#) pulse. will Read operation attempted Erase-suspended Sector/Block. Program operation initiated sector/block selected Erase-Suspend mode, will toggle. additional Toggle available DQ2, which used conjunction with check whether particular sector being actively erased erase-suspended. Table shows detailed status information. Toggle (DQ2) valid after rising edge last BEF#) pulse Write operation. Figure Toggle timing diagram Figure flowchart.
Flash Erase-Suspend/-Resume Operations
Erase-Suspend operation temporarily suspends Sector- Block-Erase operation thus allowing data read from memory location, program data into sector/block that suspended Erase operation. operation executed issuing one-byte command sequence with Erase-Suspend command (B0H). device automatically enters read mode within after Erase-Suspend command been issued. Valid data read from sector block that suspended from Erase operation. Reading address location within erase-suspended sectors/blocks will output toggling "1". While Erase-Suspend mode, Program operation allowed except sector block selected Erase-Suspend. resume Sector-Erase Block-Erase operation which been suspended, system must issue Erase-Resume command. operation executed issuing one-byte command sequence with Erase Resume command (30H) address one-byte sequence.
Flash Write Operation Status Detection
SST34HF324G provides software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation.
©2007 Silicon Storage Technology, Inc.
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet TABLE Write Operation Status
Status Normal Operation Standard Program Standard Erase EraseSuspend Mode Read From Erase Suspended Sector/ Block Read From Non-Erase Suspended Sector/ Block Program DQ7# Toggle Toggle Toggle Toggle Toggle
Hardware Reset (RST#)
RST# provides hardware method resetting device read array data. When RST# held least TRP, in-progress operation will terminate return Read mode (see Figure 17). When internal Program/Erase operation progress, minimum period TRHR required after RST# driven high before valid Read take place (see Figure 16). Erase operation that been interrupted needs reinitiated after device resumes normal operation mode ensure data integrity. Figures timing diagrams. Software Data Protection (SDP) SST34HF324G provide JEDEC standard Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. SST34HF324G shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15DQ8 "Don't Care" during command sequence.
Data
Data
Data
DQ7#
Toggle
Toggle
T1.0 1310
Note: DQ7, DQ6, require valid address when reading status information.
Data Protection
SST34HF324G provide both hardware software features protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: BEF# pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, BEF# high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Hardware Block Protection
SST34HF324G provide hardware block protection which protects outermost KWord Bank block protected when held low. Figure BlockProtection location. user disable block protection driving high thus allowing erase program data into protected sectors. must held high prior issuing write command remain stable until after entire Write operation completed.
©2007 Silicon Storage Technology, Inc.
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12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
Product Identification
Product Identification mode identifies device SST34HF324G manufacturer SST. This mode accessed software operations only. hardware device Read operation, which typically used programmers cannot used this device because shared lines between flash SRAM multi-chip package. Therefore, application high voltage damage this device. Users software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Tables software operation, Figure Software Entry Read timing diagram Figure Entry command sequence flowchart. TABLE Product Identification
ADDRESS Manufacturer's Device SST34HF324G
Note: Bank Address (A20-A18)
SRAM Operation
With BES# BEF# high, SST34HF324G operates either 256K CMOS SRAM, with fully static operation requiring external clocks timing strobes. When BES# BEF# high, memory banks deselected device enters standby. Read Write cycle times equal. control signals UBS# LBS# provide access upper data byte lower data byte. Table SRAM Read Write data byte control modes operation. SRAM Read SRAM Read operation SST34HF324G controlled BES#, both have with high system obtain data from outputs. BES# used SRAM bank selection. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram, Figure further details. SRAM Write SRAM Write operation SST34HF324G controlled BES#, both have system write SRAM. During Word-Write operation, addresses data referenced rising edge either BES# whichever occurs first. write time measured from last falling edge BES# first rising edge BES# WE#. Refer Write cycle timing diagrams, Figures further details.
DATA 00BFH 7353H
T2.0 1310
BK0000H BK0001H
Product Identification Mode Exit order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read mode. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
A20-
Address Buffers
SuperFlash Memory (Bank
RST# BEF# LBS# UBS# BES#
SuperFlash Memory (Bank
Control Logic Buffers DQ15
Address Buffers
Mbit SRAM
1310 B1.0
FIGURE Functional Block Diagram
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet TABLE Dual-Bank Memory Organization
SST34HF324G Block BA63 BA62 BA61 BA60 BA59 BA58 BA57 Bank BA56 BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 Bank BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 Block Size Address Range 3FC000H-3FFFFFH 3F0000H-3FBFFFH 3E0000H-3EFFFFH 3D0000H-3DFFFFH 3C0000H-3CFFFFH 3B0000H-3BFFFFH 3A0000H-3AFFFFH 390000H-39FFFFH 380000H-38FFFFH 370000H-37FFFFH 360000H-36FFFFH 350000H-35FFFFH 340000H-34FFFFH 330000H-33FFFFH 320000H-32FFFFH 310000H-31FFFFH 300000H-30FFFFH 2F0000H-2FFFFFH 2E0000H-2EFFFFH 2D0000H-2DFFFFH 2C0000H-2CFFFFH 2B0000H-2BFFFFH 2A0000H-2AFFFFH 290000H-29FFFFH 280000H-28FFFFH 270000H-27FFFFH 260000H-26FFFFH 250000H-25FFFFH 240000H-24FFFFH 230000H-23FFFFH 220000H-22FFFFH 210000H-21FFFFH 200000H-20FFFFH 1F0000H-1FFFFFH 1E0000H-1EFFFFH 1D0000H-1DFFFFH 1C0000H-1CFFFFH 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH 180000H-18FFFFH 170000H-17FFFFH 160000H-16FFFFH Address Range 1FE000H-1FFFFFH 1F8000H-1FDFFFH 1F0000H-1F7FFFH 1E8000H-1EFFFFH 1E0000H-1E7FFFH 1D8000H-1DFFFFH 1D0000H-1D7FFFH 1C8000H-1CFFFFH 1C0000H-1C7FFFH 1B8000H-1BFFFFH 1B0000H-1B7FFFH 1A8000H-1AFFFFH 1A0000H-1A7FFFH 198000H-19FFFFH 190000H-197FFFH 188000H-18FFFFH 180000H-187FFFH 178000H-17FFFFH 170000H-177FFFH 168000H-16FFFFH 160000H-167FFFH 158000H-15FFFFH 150000H-157FFFH 148000H-14FFFFH 140000H-147FFFH 138000H-13FFFFH 130000H-137FFFH 128000H-12FFFFH 120000H-127FFFH 118000H-11FFFFH 110000H-117FFFH 108000H-10FFFFH 100000H-107FFFH 0F8000H-0FFFFFH 0F0000H-0F7FFFH 0E8000H-0EFFFFH 0E0000H-0E7FFFH 0D8000H-0DFFFFH 0D0000H-0D7FFFH 0C8000H-0CFFFFH 0C0000H-0C7FFFH 0B8000H-0BFFFFH 0B0000H-0B7FFFH
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet TABLE Dual-Bank Memory Organization (Continued)
SST34HF324G Block BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 Bank BA11 BA10 Block Size Address Range 150000H-15FFFFH 140000H-14FFFFH 130000H-13FFFFH 120000H-12FFFFH 110000H-11FFFFH 100000H-10FFFFH 0F0000H-0FFFFFH 0E0000H-0EFFFFH 0D0000H-0DFFFFH 0C0000H-0CFFFFH 0B0000H-0BFFFFH 0A0000H-0AFFFFH 090000H-09FFFFH 080000H-08FFFFH 070000H-07FFFFH 060000H-06FFFFH 050000H-05FFFFH 040000H-04FFFFH 030000H-03FFFFH 020000H-02FFFFH 010000H-01FFFFH 000000H-00FFFFH Address Range 0A8000H-0AFFFFH 0A0000H-0A7FFFH 098000H-09FFFFH 090000H-097FFFH 088000H-08FFFFH 080000H-087FFFH 078000H-07FFFFH 070000H-077FFFH 068000H-06FFFFH 060000H-067FFFH 058000H-05FFFFH 050000H-057FFFH 048000H-04FFFFH 040000H-047FFFH 038000H-03FFFFH 030000H-037FFFH 028000H-02FFFFH 020000H-027FFFH 018000H-01FFFFH 010000H-017FFFH 008000H-00FFFFH 000000H-007FFFH
T3.0 1310
VIEW (balls facing down)
SST34HF324G
UBS# DQ15 DQ14 DQ13 DQ12 DQ10 DQ11 BEF#
1310 48-lfbga P1a.0
RST# LBS#
BES#
FIGURE Assignments 48-ball LFBGA (6mm 8mm)
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet TABLE Description
Symbol AMS1 DQ15-DQ0 Name Address Inputs Data Inputs/Outputs Functions provide Flash address, A20-A0. provide SRAM address, A17-A0 output data during Read cycles receive input data during Write cycles. Data internally latched during flash Erase/Program cycle. outputs tri-state when OE#, BES#, BEF# high. activate Flash memory bank when BEF# activate SRAM memory bank when BES# gate data output buffers control Write operations enable DQ15-DQ8 enable DQ7-DQ0 protect unprotect bottom KWord sectors) from Erase Program operation Reset return device Read mode 2.7-3.3V Power Supply
T4.0 1310
BEF# BES# UBS# LBS# RST#
Flash Memory Bank Enable SRAM Memory Bank Enable Output Enable Write Enable Upper Byte Control (SRAM) Lower Byte Control (SRAM) Write Protect Reset Ground Power Supply
Most Significant Address
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet TABLE Operational Modes Selection SRAM
Mode Full Standby Output Disable BEF#1 Flash Read Flash Write Flash Erase SRAM Read BES#1,2 SRAM Write Product Identification3
OE#2
WE#2
LBS#2
UBS#2
DQ15-0 HIGH-Z HIGH-Z HIGH-Z DOUT DOUT HIGH-Z DOUT HIGH-Z HIGH-Z HIGH-Z HIGH-Z DOUT DOUT DOUT HIGH-Z HIGH-Z
DQ15-8 HIGH-Z HIGH-Z HIGH-Z DQ15-8=HIGH-Z DQ15-8=HIGH-Z DOUT DOUT HIGH-Z HIGH-Z
Manufacturer's Device
T5.0 1310
apply BEF# BES# same time VIH, other value. Software mode only With A20-A18 VIL; Manufacturer's BFH, read with A0=0, SST34HF324G Device 7353H, read with A0=1
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet TABLE Software Command Sequence
Command Sequence Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Software Entry5 Write Cycle Addr1
555H 555H 555H 555H XXXXH XXXXH 555H 555H
Write Cycle Addr1
2AAH 2AAH 2AAH 2AAH
Write Cycle Addr1
555H 555H 555H 555H
Write Cycle Addr1
555H 555H 555H
Write Cycle Addr1
2AAH 2AAH 2AAH
Write Cycle Addr1
SAX4
Data2
Data2
Data2
Data2
Data
Data2
Data2
555H
2AAH 2AAH
BKX6 555H 555H
Software Exit Software Exit
T6.0 1310
Address format A10-A0 (Hex), Addresses A20-A11 VIH, other value, command sequence. DQ15-DQ8 VIH, other value, command sequence Program word address Sector-Erase; uses A20-A11 address lines Block-Erase; uses A20-A15 address lines Bank address; uses A20-A15 address lines device does remain Software Product Identification mode powered down. A20-A18
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Operating Temperature -20°C +85°C Storage Temperature -65°C +125°C Voltage Ground Potential -0.5V VDD+0.3V Transient Voltage (<20 Ground Potential -1.0V VDD+1.0V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Solder Reflow Temperature: 260°C seconds Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
Operating Range
Range Commercial Extended Ambient Temp +70°C -20°C +85°C 2.7-3.3V 2.7-3.3V
Conditions Test
Input Rise/Fall Time Output Load Figures
©2007 Silicon Storage Technology, Inc.
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet TABLE Operating Characteristics (VDD VDDF VDDS 2.7-3.3V)
Limits Symbol IDD1 Parameter Active Current Read Flash SRAM Concurrent Operation Write2 Flash SRAM ILIW VILC VIHC Standby Current Reset Current Input Leakage Current Input Leakage Current RST# Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Flash SRAM Output Voltage Flash SRAM Output High Voltage Units Test Conditions Address input VILT/VIHT, MHz, VDD=VDD Max, open OE#=VIL, WE#=VIH BEF#=VIL, BES#=VIH BEF#=VIH, BES#=VIL BEF#=VIH, BES#=VIL WE#=VIL BEF#=VIL, BES#=VIH, OE#=VIH BEF#=VIH, BES#=VIL Max, BEF#=BES#=VIHC RST#=GND VIN=GND VDD, VDD=VDD WP#=GND VDD, VDD=VDD RST#=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T7.0 1310
VDD-0.3 VDD-0.2
Figure active while Erase Program progress.
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet TABLE Recommended System Power-up Timings
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T8.0 1310
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Capacitance 25°C, Mhz, other pins open)
Parameter CI/O1
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T9.0 1310
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Flash Reliability Characteristics
Symbol NEND TDR1 ILTH1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T10.0 1310
This parameter measured only initial qualification after design process change that could affect this parameter.
©2007 Silicon Storage Technology, Inc.
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
CHARACTERISTICS
TABLE SRAM Read Cycle Timing Parameters
Symbol TRCS TAAS TBES TOES TBYES TBLZS1 TOLZS1 TBYLZS1 TBHZS
Parameter Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time UBS#, LBS# Access Time BES# Active Output Output Enable Active Output UBS#, LBS# Active Output BES# High-Z Output Output Disable High-Z Output
Units
T11.0 1310
TOHZS1 TBYHZS TOHS
UBS#, LBS# High-Z Output Output Hold from Address Change
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM Write Cycle Timing Parameters
Symbol TWCS TBWS TAWS TASTS TWPS TWRS TBYWS TODWS TOEWS TDSS TDHS Parameter Write Cycle Time Bank Enable End-of-Write Address Valid End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time UBS#, LBS# End-of-Write Output Disable from Output Enable from High Data Set-up Time Data Hold from Write Time Units
T12.0 1310
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet TABLE Flash Read Cycle Timing Parameters 2.7-3.3V
Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1
Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time BEF# Active Output Active Output BEF# High High-Z Output High High-Z Output Output Hold from Address Change RST# Pulse Width RST# High Before Read RST# Read
Units
T13.0 1310
TRHR1,2
1,2,3
This parameter measured only initial qualification after design process change that could affect this parameter. package only This parameter applies Sector-Erase, Block-Erase Program operations. This parameter does apply Chip-Erase.
TABLE Flash Program/Erase Cycle Timing Parameters
Symbol TOES TOEH TWPH TDH1 TIDA TSCE
Parameter Program Time Address Setup Time Address Hold Time BEF# Setup Time BEF# Hold Time High Setup Time High Hold Time BEF# Pulse Width Pulse Width Pulse Width High BEF# Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Erase-Suspend Latency Bus# Recovery Time Sector-Erase Block-Erase Chip-Erase
Units
TCPH1
T14.1 1310
This parameter measured only initial qualification after design process change that could affect this parameter.
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
TRCS ADDRESSES AMSS-0 TAAS BES# TBES TBLZS TOLZS UBS#, LBS# TBYLZS DQ15-0 DATA VALID
1310 F02.0
TOHS
TBHZS TOES TOHZS TBYES TBYHZS
Note: AMSS Most Significant Address AMSS SST34HF324G
FIGURE SRAM Read Cycle Timing Diagram
TWCS ADDRESSES AMSS3-0
TAWS
TASTS
TWPS
TWRS
TBWS
BES#
UBS#, LBS# TODWS DQ15-8, DQ7-0
NOTE
TBYWS TDSS TOEWS TDHS
NOTE
1310 F03.0
VALID DATA
Note: High during Write cycle, outputs will remain high impedance. BES# goes coincident with after goes low, output will remain high impedance. BES# goes high coincident with before goes high, output will remain high impedance. Because signals output state this time, input signals reverse polarity must applied. AMSS Most Significant SRAM Address AMSS SST34HF324G
FIGURE SRAM Write Cycle Timing Diagram (WE# Controlled)
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
TWCS ADDRESSES AMSS3-0 TWPS TBWS BES# TAWS TASTS UBS#, LBS# TDSS DQ15-8, DQ7-0
NOTE
TWRS
TBYWS
TDHS
NOTE
1310 F04.0
VALID DATA
Note: High during Write cycle, outputs will remain high impedance. Because signals output state this time, input signals reverse polarity must applied. AMSS Most Significant SRAM Address AMSS SST34HF324G
FIGURE SRAM Write Cycle Timing Diagram (UBS#, LBS# Controlled)
ADDRESS A20-0 BEF# TCLZ DATA VALID TOLZ
TOHZ
TCHZ HIGH-Z DATA VALID
1310 F05.0
DQ15-0
HIGH-Z
FIGURE Flash Read Cycle Timing Diagram
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Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
ADDRESS A20-0 BEF# TCS? DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: VIH, other value.
1310 F06.0
ADDR
TWPH
VALID
FIGURE Flash Controlled Program Cycle Timing Diagram
ADDRESS A20-0 BEF# XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: VIH, other value.
1310 F07.0
ADDR
TCPH
TCS? DQ15-0
VALID
FIGURE Flash BEF# Controlled Program Cycle Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
ADDRESS A20-0 BEF# TOEH TOES
DATA
DATA#
DATA#
DATA
1310 F08.0
FIGURE Flash Data# Polling Timing Diagram
ADDRESS A20-0 BEF# TOEH
READ CYCLES WITH SAME OUTPUTS
1310 F09.0 VALID DATA
FIGURE Flash Toggle Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
SIX-BYTE CODE CHIP-ERASE ADDRESS A20-0
TSCE
BEF#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
VALID
1310 F10.0
Note: This device also supports BEF# controlled Chip-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table 14.) VIH, other value.
FIGURE Flash Controlled Chip-Erase Timing Diagram
SIX-BYTE CODE BLOCK-ERASE ADDRESS A20-0 BEF#
XXAA XX55 XX80 XXAA XX55 XX30
DQ15-0
VALID
1310 F11.0
Note: This device also supports BEF# controlled Block-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table 14.) Block Address VIH, other value.
FIGURE Flash Controlled Block-Erase Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
SIX-BYTE CODE SECTOR-ERASE ADDRESS A20-0 BEF#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
1310 F12.0
Note: This device also supports BEF# controlled Sector-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table 14.) Sector Address VIH, other value.
FIGURE Flash Controlled Sector-Erase Timing Diagram
Three-Byte Sequence Software Entry 0000 0001
ADDRESSES
BEF#
TWPH DQ15-0 XXAA XX55 XX90 00BF
Device
1310 F13.0
TIDA
Note: VIH, other value. Device 7353H SST34HF324G
FIGURE Flash Software Entry Read
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESSES
DQ15-0
XXAA
XX55
XXF0 TIDA
TWPH
1310 F14.0
Note: VIH, other value.
FIGURE Flash Software Exit
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
RY/BY# RST#
BEF#/OE# TRHR
1310 F15.0
FIGURE RST# Timing (when internal operation progress)
RY/BY#
RST# BEF#
1310 F16.0
FIGURE RST# Timing (during Sector- Block-Erase operation)
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
VIHT INPUT? VILT
1310 F17.0
REFERENCE POINTS
OUTPUT
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE Input/Output Reference Waveforms
TESTER
1310 F18.0
FIGURE Test Load Example
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
Start
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XXA0H Address: 555H
Load Address/Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
1310 F19.0
Note: VIH, other value.
FIGURE Program Algorithm
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read byte/word
Read
Program/Erase Completed
Read same byte/word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
1310 F20.0
FIGURE Wait Options
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
Software Product Entry Command Sequence
Software Exit Command Sequence
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX90H Address:
Load data: XXF0H Address: 555H
Wait TIDA
Wait TIDA
Read Software
Return normal operation
1310 F21.0
Note: VIH, other value.
FIGURE Software Product Command Flowcharts
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
Chip-Erase Command Sequence Load data: XXAAH Address: 555H
Sector-Erase Command Sequence Load data: XXAAH Address: 555H
Block-Erase Command Sequence Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX10H Address: 555H
Load data: XX30H Address:
Load data: XX50H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
1310 F22.0
Note: VIH, other value.
FIGURE Erase Command Sequence
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2 XXXX Package Attribute non-Pb Package Modifier balls Package Type LFBGA (6mm 1.4mm, 0.45mm ball size) Temperature Range Commercial +70°C Extended -20°C +85°C Minimum Endurance =10,000 cycles Read Access Speed Version Flash RST# SRAM SRAM Density Mbit Flash Density 32Mbit Voltage 2.7-3.3V Product Series Dual-Bank Flash SRAM ComboMemory
SST34HF324G
Environmental suffix denotes non-Pb solder. non-Pb solder devices "RoHS Compliant".
Valid combinations SST34HF324G SST34HF324G-70-4C-L3KE SST34HF324G-70-4E-L3KE
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2007 Silicon Storage Technology, Inc.
S71310-02-EOL
12/07
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF324G
Data Sheet
PACKAGING DIAGRAMS
VIEW
8.00 0.20
BOTTOM VIEW
5.60 0.80 0.45 0.05 (48X)
0.80 CORNER 4.00 6.00 0.20
CORNER 1.30 0.10
SIDE VIEW
SEATING PLANE 0.35 0.05
0.12
Note:
Except total height dimension, complies with JEDEC Publication MO-210, variant 'AB-1', although some dimensions more stringent. linear dimensions millimeters. Coplanarity: 0.12 Ball opening size 0.38 0.05
48-lfbga-L3K-6x8-450mic-5
48-ball Low-profile, Fine-pitch Ball Grid Array (LFBGA) Package Code: TABLE Revision History
Number Description Date 2006 2007 2007
Initial Release Changed `Program Time: `Word-Program Time: page Features Edited Product Description page valid combinations this data sheet. Replacement part SST34HF3244 (S71335)
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2007 Silicon Storage Technology, Inc. S71310-02-EOL 12/07
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