06-05-18 Raymond Monnin SHEET SHEET STATUS SHEETS PMIC SHEET

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06-05-18 Raymond Monnin SHEET SHEET STATUS SHEETS PMIC SHEET

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REVISIONS DESCRIPTION Update drawing current requirements. Editorial changes throughout. Boilerplate update part five year review. DATE (YR-MO-DA) 01-05-01 APPROVED Raymond Monnin
06-05-18
Raymond Monnin
SHEET SHEET STATUS SHEETS PMIC SHEET
PREPARED Jeff Bowling
DEFENSE SUPPLY CENTER COLUMBUS
STANDARD MICROCIRCUIT DRAWING
THIS DRAWING AVAILABLE DEPARTMENTS AGENCIES DEPARTMENT DEFENSE
CHECKED Jeff Bowling APPROVED Michael Frye
COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, NON-VOLATILE STATIC MONOLITHIC SILICON
DRAWING APPROVAL DATE 94-02-16
AMSC
REVISION LEVEL
SIZE SHEET
CAGE CODE 67268
5962-92324
DSCC FORM 2233
5962-E461-06
SCOPE Scope. This drawing documents product assurance class levels consisting high reliability (device classes space application (device class choice case outlines lead finishes available reflected Part Identifying Number (PIN). When available, choice Radiation Hardness Assurance (RHA) levels reflected PIN. PIN. shown following example:
5962
92324
Federal stock class designator
designator (see 1.2.1)
Device type (see 1.2.2)
Device class designator (see 1.2.3)
Case outline (see 1.2.4)
Lead finish (see 1.2.5)
Drawing number 1.2.1 designator. Device classes marked devices meet MIL-PRF-38535 specified levels marked with appropriate designator. Device class marked devices meet MIL-PRF-38535, appendix specified levels marked with appropriate designator. dash indicates non-RHA device. 1.2.2 Device type(s). device type(s) identify circuit function follows: Access Time Store Cycle Recall Cycle
Device type
Generic number 11C68 11C68 11C68 11C68 11C68 11C68
Circuit function NVSRAM NVSRAM NVSRAM NVSRAM NVSRAM NVSRAM
Endurance 10,000 cycles 10,000 cycles 10,000 cycles 100,000 cycles 100,000 cycles 100,000 cycles
1.2.3 Device class designator. device class designator single letter identifying product assurance level follows: Device class Device requirements documentation Vendor self-certification requirements MIL-STD-883 compliant, nonJAN class level microcircuits accordance with MIL-PRF-38535, appendix Certification qualification MIL-PRF-38535
1.2.4 Case outline(s). case outline(s) designated MIL-STD-1835 follows: Outline letter Descriptive designator CDIP3-T28 GDIP4-T28 CQCC3-N28 Terminals Package style Dual -line Rectangular leadless chip carrier
1.2.5 Lead finish. lead finish specified MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class
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DSCC FORM 2234
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Absolute maximum ratings. Supply voltage range (VCC) Voltage (0-7) with outputs high state Input voltage operating range (VIH, VIL) Storage temperature range Maximum power dissipation (PD) Maximum output current Lead temperature (soldering) Junction temperature (TJ) Thermal resistance, junction case (jc): Data retention Endurance store cycles non-volatile array) Recommended operating conditions. Supply voltage range (VCC) +4.5 +5.5 Case operating temperature range (TC) -55°C +125°C Input voltage, range (VIL) -0.5 inputs Input voltage, high range (VIH) VCC+0.5 inputs APPLICABLE DOCUMENTS Government specification, standards, handbooks. following specification, standards, handbooks form part this drawing extent specified herein. Unless otherwise specified, issues these documents those cited solicitation contract. DEPARTMENT DEFENSE SPECIFICATION MIL-PRF-38535 Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. -0.6 -0.5 (VCC -0.6 -65°C +150°C 300°C 175°C MIL-STD-1835 Years nonvolatile array (minimum) 1.2.2
DEPARTMENT DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 List Standard Microcircuit Drawings. Standard Microcircuit Drawings.
(Copies these documents available online http://assist.daps.dla.mil from Standardization Document Order Desk, Robbins Avenue, Building Philadelphia, 19111-5094.)
Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels affect reliability. This stress rating only, functional operation device conditions above those indicated operational sections this specification implied. voltages referenced (ground). Maximum junction temperature shall exceeded except allowable short duration burn-in screening conditions accordance with method 5004 MIL-STD-883.
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Non-Government publications. following documents form part this document extent specified herein. Unless otherwise specified, issues documents issues documents cited solicitation. ELECTRONICS INDUSTRIES ALLIANCE (EIA) JEDEC Standard EIA/JESD Latch-Up Test. (Applications copies should addressed Electronics Industries Association, 2500 Wilson Boulevard, Arlington, 22201; http://www.jedec.org.) (Non-Government standards other publications normally available from organizations that prepare distribute documents. These documents also available through libraries other informational services.) Order precedence. event conflict between text this drawing references cited herein, text this drawing takes precedence. Nothing this document, however, supersedes applicable laws regulations unless specific exemption been obtained. REQUIREMENTS Item requirements. individual item requirements device classes shall accordance with MIL-PRF-38535 specified herein modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. individual item requirements device class shall accordance with MIL-PRF-38535, appendix non-JAN class level devices specified herein. Design, construction, physical dimensions. design, construction, physical dimensions shall specified MIL-PRF-38535 herein device classes MIL-PRF-38535, appendix herein device class 3.2.1 Case outlines. case outlines shall accordance with 1.2.4 herein. 3.2.2 Terminal connections. terminal connections shall specified figure 3.2.3 Truth table. truth table shall specified figure 3.2.4 Functional tests. Various functional tests used test this device contained appendix. test patterns cannot implemented test equipment limitations, alternate test patterns accomplish same results shall allowed. device class alternate test patterns shall maintained under document revision level control manufacturer shall made available preparing acquiring activity upon request. device classes alternate test patterns shall under control device manufacturer's Technology Review Board (TRB) accordance with MIL-PRF-38535 shall made available preparing acquiring activity upon request. Electrical performance characteristics postirradiation parameter limits. Unless otherwise specified herein, electrical performance characteristics postirradiation parameter limits specified table shall apply over full case operating temperature range. Electrical test requirements. electrical test requirements shall subgroups specified table IIA. electrical tests each subgroup defined table Marking. part shall marked with listed herein. addition, manufacturer's also marked. packages where marking entire number feasible space limitations, manufacturer option marking "5962-" device. product using this option, designator shall still marked. Marking device classes shall accordance with MIL-PRF-38535. Marking device class shall accordance with MIL-PRF-38535, appendix 3.5.1 Certification/compliance mark. certification mark device classes shall "QML" required MIL-PRF-38535. compliance mark device class shall required MIL-PRF-38535, appendix
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Certificate compliance. device classes certificate compliance shall required from QML-38535 listed manufacturer order supply requirements this drawing (see 6.6.1 herein). device class certificate compliance shall required from manufacturer order listed approved source supply MIL-HDBK-103 (see 6.6.2 herein). certificate compliance submitted DSCC-VA prior listing approved source supply this drawing shall affirm that manufacturer's product meets, device classes requirements MIL-PRF-38535 herein device class requirements MIL-PRF-38535, appendix herein. Certificate conformance. certificate conformance required device classes MIL-PRF-38535 device class MIL-PRF-38535, appendix shall provided with each microcircuits delivered this drawing. Notification change device class device class notification DSCC-VA change product (see herein) involving devices acquired this drawing required change that affects this drawing. Verification review device class device class DSCC, DSCC's agent, acquiring activity retain option review manufacturer's facility applicable required documentation. Offshore documentation shall made available onshore option reviewer. 3.10 Microcircuit group assignment device class Device class devices covered this drawing shall microcircuit group number (see MIL-PRF-38535, appendix 3.11 Endurance. reprogrammability test shall completed part vendor's reliability monitors. This reprogrammability test shall done initial characterization after design process changes which affect reprogrammability device. methods procedures vendor specific, shall guarantee number program/erase endurance cycles listed section herein over full military temperature range. vendor's procedure shall kept under document control shall made available upon request acquiring preparing activity, along with test data. 3.12 Data retention. data retention stress test shall completed part vendor's reliability monitors. This test shall done initial characterization after design process changes which affect data retention. methods procedures vendor specific, shall guarantee number years listed section herein over full military temperature range. vendor's procedure shall kept under document control shall made available upon request acquiring preparing activity, along with test data.
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TABLE Electrical performance characteristics. Conditions -55°C +125°C IOUT unless otherwise specified Inputs Inputs Addresses cycling tAVAV
Test
Symbol
Group subgroups
Device type
Limits
Unit
Input leakage current (any input) High impedance output leakage current Input logic voltage Input logic voltage Output logic voltage Output logic voltage current
ICC1
current during store cycle current (standby, cycling input levels) current (standby, stable CMOS input levels) Input capacitance
ICC2
0.2V); other inputs (VCC
ICC3
VIH; others cycling
ICC4
(VCC others (VCC 0.2V) 25°C, 4.4.1e VOUT 25°C, 4.4.1e 4.4.1c
Output capacitance
COUT
Functional test
footnotes table.
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TABLE Electrical performance characteristics Continued. Conditions -55°C +125°C IOUT
Test
Symbol
Group subgroups
Device type
Limits
Unit
Chip enable access time
tELQV
unless otherwise specified READ CYCLES figures
Read cycle time
tAVAV
Address access time
tAVQV
Output enable data valid
tOLQV
Output hold after address change Chip enable output active Chip disable output inactive Output enable output active Output disable output inactive Chip enable power active Chip disable power standby Write recovery time
tAXQX tELQX tEHQZ
tOLQX tOHQZ
tELPU tEHPD tWHQV
WRITE CYCLES Write cycle time tAVAV figures
Write pulse width
tWLWH tWLEH
footnotes table.
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TABLE Electrical performance characteristics Continued. Conditions -55°C +125°C IOUT unless otherwise specified figures
Test
Symbol
Group subgroups
Device type
Limits
Unit
Chip enable write
tELWH tELEH tDVWH tDVEH tWHDX tEHDX tAVWH tAVEH tAVWL tAVEL tWHAX tEHAX tWLQZ tWHQX
Data set-up write Data hold after write Address set-up write Address set-up start write Address hold after write Write enable output disable Output active after write Store/recall initiation cycle time Chip enable output inactive Store cycle time
STORE/RECALL CYCLE figures
tAVAV
tELQZ
tSTORE tRECALL tAVEL
Recall cycle time Address set-up chip enable footnotes table.
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TABLE Electrical performance characteristics Continued. Conditions -55°C +125°C IOUT unless otherwise specified figures
Test
Symbol
Group subgroups
Device type
Limits
Unit
Chip enable pulse 12/, width Chip disable address change
tELEH
tEHAX
ICC1 dependent output loading cycle rate. specified values obtained with outputs unloaded. Bringing will produce standby current levels until nonvolatile cycle progress timed out. Figure ICC2 current required duration store cycle (tSTORE) once store begun. These parameters tested part initial device characterization, after design process change that might affect that parameter. These parameters tested part screening, guaranteed limits specified Table Read Cycles high entire cycle. device continuously selected with low. Measured ±200 from steady state output voltage. when goes low, outputs remain high impedance state. Once software STORE RECALL cycle initiated, completes automatically, ignoring inputs. Note that STORE cycles, RECALL cycles, aborted (STORE inhibit). RECALL cycle initiated automatically power when exceeds tRECALL measured from point which exceeds Noise trigger multiple read cycles from same address abort address sequence. pulse width less than tELQV, greater than equal tELEH, then data valid pulse. However, STORE RECALL will still initiated.
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Device types Case outlines Terminal number
Terminal symbol
FIGURE Terminal connections.
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(HEX) 0000 1555 0AAA 1FFF 1010 0F0F 0000 1555 0AAA 1FFF 1010 0F0E
MODE Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile recall
Output high Output data Input data Output data Output data Output data Output data Output data Output high Output data Output data Output data Output data Output data Output high
POWER Standby Active Active Active
ICC2 Active
consecutive addresses must order listed (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) STORE cycle, (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) RECALL cycle. must high during consecutive cycles. figure
state assumes that VIL. Initiation operation nonvolatile cycles depend state
FIGURE Truth table.
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TEST CONDITIONS
TEST CONDITION Input pulse levels Input rise fall time Input timing reference levels Output reference levels
VALUES 1.5V 1.5V
voltages referenced (ground). FIGURE Output load circuits.
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Read cycle (see notes
Read cycle (see notes
Notes: device continuously selected with low. READ CYCLE must high entire cycle.
Figure Timing waveforms.
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Write cycle controlled (see note)
Write cycle controlled (see note)
Note: must during address transitions.
Figure Timing waveforms continued.
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Store inhibit automatic power-up recall
Store/recall cycle (see note
Notes: read cycles high entire cycle. device continuously selected with low.
must high when during address sequence order initiate nonvolatile cycle. either high throughout. Addresses through found mode selection table. Address determines whether device performs STORE RECALL.
Figure Timing waveforms continued.
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VERIFICATION Sampling inspection. device classes sampling inspection procedures shall accordance with MIL-PRF-38535 modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. device class sampling inspection procedures shall accordance with MIL-PRF-38535, appendix Screening. device classes screening shall accordance with MIL-PRF-38535, shall conducted devices prior qualification technology conformance inspection. device class screening shall accordance with method 5004 MIL-STD-883, shall conducted devices prior quality conformance inspection. 4.2.1 Additional criteria device class Burn-in test, method 1015 MIL-STD-883. Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1015. +125°C, minimum. Interim final electrical test parameters shall specified table herein.
4.2.2 Additional criteria device classes burn-in test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. burn-in test circuit shall maintained under document revision level control device manufacturer's Technology Review Board (TRB) accordance with MIL-PRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1015 MIL-STD-883. Interim final electrical test parameters shall specified table herein. Additional screening device class beyond requirements device class shall specified MIL-PRF-38535, appendix
Qualification inspection device classes Qualification inspection device classes shall accordance with MIL-PRF-38535. Inspections performed shall those specified MIL-PRF-38535 herein groups inspections (see 4.4.1 through 4.4.4). Conformance inspection. Technology conformance inspection classes shall accordance with MIL-PRF-38535 including groups inspections specified herein. Quality conformance inspection device class shall accordance with MIL-PRF-38535, appendix specified herein. Inspections performed device class shall those specified method 5005 MIL-STD-883 herein groups inspections (see 4.4.1 through 4.4.4). 4.4.1 Group inspection. Tests shall specified table herein. Subgroups table method 5005 MIL-STD-883 shall omitted. device class subgroups tests shall sufficient verify truth table. device classes subgroups shall include verifying functionality device.
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(latch-up) tests shall measured only initial qualification after design process changes which affect performance device. device class procedures circuits shall maintained under document revision level control manufacturer shall made available preparing activity acquiring activity upon request. device classes procedures circuits shall under control device manufacturer's accordance with MIL-PRF-38535 shall made available preparing activity acquiring activity upon request. Testing shall pins, five devices with zero failures. Latch-up test shall considered destructive. Information contained JEDEC Standard EIA/JESD used reference. Subgroup (CIN COUT measurements) shall measured only initial qualification after process design changes which affect input output capacitance. Capacitance shall measured between designated terminal frequency MHz. Sample size devices with failures, input output terminals tested.
TABLE IIA. Electrical test requirements. Line Test requirements Subgroups accordance with MIL-STD-883, method 5005, table Device class required Required required Required Subgroups accordance with MIL-PRF-38535, table III) Device class Device class Required Required 4**,
Interim electrical parameters (see 4.2) Static burn-in (method 1015) Same line Dynamic burn-in (method 1015) Same line Final electrical parameters (see 4.2) Group test requirements (see 4.4) Group end-point electrical parameters (see 4.4) Group end-point electrical parameters (see 4.4) Group end-point electrical parameters (see 4.4)
4**,
4**,
Blank spaces indicate tests applicable. subgroups combined when using high-speed testers. Subgroups functional tests shall verify truth table. indicates applies subgroup 4.4.1e. indicates delta limit (see table IIB) shall required where specified, delta values shall computed with reference previous interim electrical parameters (see line 4.4.1d.
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TABLE IIB. Delta limits +25°C. Parameter ICC4 standby IIL, Device types ±10% value table ±10% value table
above parameter shall recorded before after required burn-in life tests determine delta.
4.4.2 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.2.1 Additional criteria device class Steady-state life test conditions, method 1005 MIL-STD-883: Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1005 MILSTD-883. +125°C, minimum. Test duration: 1,000 hours, except permitted method 1005 MIL-STD-883.
4.4.2.2 Additional criteria device classes steady-state life test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. test circuit shall maintained under document revision level control device manufacturer's accordance with MIL-PRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified method 1005 MIL-STD883. 4.4.3 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.4 Group inspection. Group inspection required only parts intended marked radiation hardness assured (see herein). End-point electrical parameters shall specified table herein. device classes devices test vehicle shall subjected radiation hardness assured tests specified MIL-PRF-38535 level being tested. device class devices shall subjected radiation hardness assured tests specified MIL-PRF-38535, appendix level being tested. device classes must meet postirradiation end-point electrical parameter limits defined table +25°C ±5°C, after exposure, subgroups specified table herein.
Delta measurements device classes Delta measurements, specified table IIA, shall made recorded before after required burn-in screens steady-state life tests determine delta compliance. electrical parameters measured, with associated delta limits listed table IIB. device manufacturer may, option, either perform delta measurements within hours after burn-in perform final electrical parameter tests, subgroups
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PACKAGING Packaging requirements. requirements packaging shall accordance with MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class NOTES Intended use. Microcircuits conforming this drawing intended Government microcircuit applications (original equipment), design applications, logistics purposes. 6.1.1 Replaceability. Microcircuits covered this drawing will replace same generic device covered contractor prepared specification drawing. 6.1.2 Substitutability. Device class devices will replace device class devices. Configuration control SMD's. proposed changes existing SMD's will coordinated with users record individual documents. This coordination will accomplished using Form 1692, Engineering Change Proposal. Record users. Military industrial users should inform Defense Supply Center Columbus (DSCC) when system application requires configuration control which SMD's applicable that system. DSCC will maintain record users this list will used coordination distribution changes drawings. Users drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. Comments. Comments this drawing should directed DSCC-VA Columbus, Ohio 43218-3990, telephone (614) 692-0547. Abbreviations, symbols, definitions. abbreviations, symbols, definitions used herein defined MIL-PRF-38535, MIL-HDBK-1331 follows: COUT Input terminal capacitance. Output terminal capacitance. Ground zero voltage potential. Supply current. Input high current. Input current. Case temperature. Ambient temperature Ground zero voltage potential. Latch-up over-voltage
6.5.1 Timing limits. table timing values shows either minimum maximum limit each parameter. Input requirements specified from external system point view. Thus, address setup time shown minimum since system must supply least that much time (even though most devices require it). other hand, responses from memory specified from device point view. Thus, access time shown maximum since device never provides data later than that time.
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6.5.2 Waveforms. Waveform symbol Input MUST VALID CHANGE FROM CHANGE FROM DON'T CARE CHANGE PERMITTED Output WILL VALID WILL CHANGE FROM WILL CHANGE FROM CHANGING STATE UNKNOWN HIGH IMPEDANCE
Sources supply. 6.6.1 Sources supply device classes Sources supply device classes listed QML-38535. vendors listed QML-38535 have submitted certificate compliance (see herein) DSCC-VA have agreed this drawing. 6.6.2 Approved sources supply device class Approved sources supply class listed MIL-HDBK-103. vendors listed MIL-HDBK-103 have agreed this drawing certificate compliance (see herein) been submitted accepted DSCC-VA.
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APPENDIX FUNCTIONAL ALGORITHMS SCOPE A.1.1 Scope. Functional algorithms test patterns which define exact sequence events used verify proper operation random access memory (RAM). Each algorithm serves specific purpose testing device. understood that manufacturers have same test equipment; therefore, becomes responsibility each manufacturer guarantee that test patterns described herein followed closely possible, equivalent patterns used that serve same purpose. Each manufacturer should demonstrate that this condition will met. Algorithms shall applied device topologically pure fashion. This appendix mandatory part specification. information contained herein intended compliance. APPLICABLE DOCUMENTS. This section applicable this appendix. ALGORITHMS A.3.1 Algorithm (pattern A.3.1.1 Checkerboard, checkerboard-bar. Step Step Step Step Load memory with checkerboard data pattern incrementing from location maximum. Read memory, verifying output checkerboard pattern incrementing from location maximum. Load memory with checkerboard-bar pattern incrementing from location maximum. Read memory, verifying output checkerboard-bar pattern incrementing from location maximum.
A.3.2 Algorithm (pattern A.3.2.1 March. Step Step Step Step Step Step Step Step Step Step Step Step Step Step Step Step Step Step Load memory with background data, incrementing from minimum maximum address locations (all "0's"). Read data location Write complement data location Read complement data location Repeat steps through incrementing X-fast sequentially each location array. Read complement data maximum address location. Write data maximum address location. Read data maximum address location. Repeat steps through decrementing X-fast sequentially each location array. Read data location Write complement data location Read complement data location Repeat steps through decrementing X-fast sequentially each location array. Read complement data maximum address location. Write data maximum address location. Read data maximum address location. Repeat steps through incrementing X-fast sequentially each location array. Read background data from memory, decrementing X-fast from maximum minimum address locations.
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SRAM APPENDIX Continued. APPENDIX A.3.3 Algorithm (pattern A.3.3.1 March. Step Step Step Step Step Step Step Step Step Step Load memory with background data, incrementing from minimum maximum address locations (all "0's"). Read data location Write complement data location Read complement data location Repeat steps through incrementing Y-fast sequentially each location array. Read complement data maximum address location. Write data maximum address location. Read data maximum address location. Repeat steps through decrementing X-fast sequentially each location array. Read data location
A.3.3.1 March Continued. Step Step Step Step Step Step Step Step Write complement data location Read complement data location Repeat steps through decrementing Y-fast sequentially each location array. Read complement data maximum address location. Write data maximum address location. Read data maximum address location. Repeat steps through incrementing X-fast sequentially each location array. Read background data from memory, decrementing Y-fast from maximum minimum address locations.
A.3.4 Algorithm (pattern A.3.4.1 CEDES deselect checkerboard, checkerboard-bar. Step Step Step Step Step Step Load memory with checkerboard data pattern incrementing from location maximum. Deselect device, attempt load memory with checkerboard-bar data pattern incrementing from location maximum. Read memory, verifying output checkerboard pattern incrementing from location maximum. Load memory with checkerboard-bar pattern incrementing from location maximum. Deselect device, attempt load memory with checkerboard data pattern incrementing from location maximum. Read memory, verifying output checkerboard-bar pattern incrementing from location maximum.
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STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 06-05-18 Approved sources supply 5962-92324 listed below immediate acquisition information only shall added MIL-HDBK-103 QML-38535 during next revision. MIL-HDBK-103 QML-38535 will revised include addition deletion sources. vendors listed below have agreed this drawing certificate compliance been submitted accepted DSCC-VA. This information bulletin superseded next dated revision MIL-HDBK-103 QML-38535. DSCC maintains online database current sources supply
Standard microcircuit drawing 5962-9232401MXA 5962-9232401MYA 5962-9232402MXA 5962-9232402MYA 5962-9232403MXA 5962-9232403MYA 5962-9232404MXA 5962-9232404MXC 5962-9232404MYA 5962-9232405MXA 5962-9232405MXC 5962-9232405MYA 5962-9232406MXA 5962-9232406MXC 5962-9232406MYA
Vendor CAGE number 0HMW2 0HMW2 0HMW2 0HMW2 0HMW2 0HMW2 0HMW2 0HMW2 0HMW2
Vendor similar STK11C68-C55M STK11C68-L55M STK11C68-C45M STK11C68-L45M STK11C68-C35M STK11C68-L35M STK11C68-5K55M STK11C68-5C55M STK11C68-5L55M STK11C68-5K45M STK11C68-5C45M STK11C68-5L45M STK11C68-5K35M STK11C68-5C35M STK11C68-5L35M
lead finish shown each representing hermetic package most readily available from manufacturer listed that part. desired lead finish listed contact vendor determine availability. Caution. this number item acquisition. Items acquired this number satisfy performance requirements this drawing. available from approved source supply.
Vendor CAGE number 0HMW2
Vendor name address Simtek Corporation 4250 Buckingham Colorado Springs, 80907 7270
information contained herein disseminated convenience only Government assumes liability whatsoever inaccuracies information bulletin.

06-05-18 Raymond Monnin SHEET SHEET STATUS SHEETS PMIC SHEET

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