LC8213 Image Data Compression/Expansion Processor Overview

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LC8213 Image Data Compression/Expansion Processor Overview

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Ordering number:ENN*4605
LC8213
Image Data Compression/Expansion Processor
Overview
LC8213 that compresses (codes) expands (decodes) binary image data used facsimiles, etc. This LC8213 used office automation equipment such G3/G4 facsimiles, image file systems, digital photocopiers, workstations. coding method based (Modified Huffman), (Modified Relative Element Address Designate), (Modified coding methods regulated CCITT T.6.
Package Dimensions
unit:mm 3174-QIP80E
[LC8213]
23.2 20.0 0.15 0.35
17.2
14.0
Features
CCITT coding methods. Compatible with facsimiles. main scanning direction pixels Max. bits. Line skip mode. 8/16 image memory bus, 8-bit bus. Transfer data between image memory bus. transfer function between image memory device. System clock Max. 20MHz. CMOS power dissipation.
3.0max
21.6
SANYO QIP80E
Specifications
Absolute Maximum Ratings 25°C,
Parameter Maximum supply voltage Input/output voltage Allowable power dissipation Operating temperature Storage temperature Resistance against solder heat Manual solder Reflow Symbol Topr Tstg seconds seconds Ta70°C Conditions Ratings +7.0 +0.3 +125 Unit
SANYO products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO representative nearest before using SANYO products described contained herein such applications. SANYO assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges,or other parameters) listed products specifications SANYO products described contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
80101TN (KT)/82093JN (KOTO) No.4605-1/10
15.6
LC8213
Allowable Operating Ranges +70°C,
Parameter Supply voltage Input voltage range Symbol Conditions Ratings Unit
Characteristics +70°C, 5.5V
Parameter Input high-level voltage Input low-level voltage Input leakage current Output high-level voltage Output low-level voltage Output leakage current Oscillation frequency Supply current Symbol fOSC compatible compatible VIN=VSS, IOH=- IOL=3mA During high impedance output +100 Conditions Ratings Unit
Characteristics Clock Reset Timing
Parameter Clock cycle time Clock low-level width Clock high-level width Reset pulse width Symbol tCLK tCKL tCKH tRSTW Conditions Ratings 6tCLK Unit
Interface
Parameter Address setup time Address hold time Read pulse width Read data delay time Read data hold time Write pulse width Write data setup time Write data hold time DACK setup time DACK hold time DREQ delay time Symbol tDAS tDAH tDRQ
2tCLK
Conditions
Ratings
Unit
No.4605-2/10
LC8213
Image Memory Interface
Parameter delay time delay time delay time delay time Control signal valid delay time Control signal invalid delay time MRD, IORD delay time MRD, IORD delay time MWR, IOWR delay time MWR, IOWR delay time UDE, delay time UDE, delay time MDEN delay time MDEN delay time Address valid delay time Address hold time Read data setup time Read data hold time Write data delay time Write data hold time BREQ delay time (for IDREQ BREQ delay time IDACK delay time (for BACK IDACK delay time (for IDACK delay time delay time delay time READY setup time READY hold time Symbol tAEL tAEH tASH tASL tRWV tRWH tRDL tRDH tWRL tWRH tDEL tDEH tMDL tMDH tMAV tDSR tDHR tDDW tDHW tBRH tBRL tDACD tDACL tDACH tDTCH tDTCL tRDYS tRDYH
3tCLK
Conditions
Ratings
2tCLK 4tCLK
13tCLK
Unit
Block Diagram
No.4605-3/10
LC8213
interface This interface circuit with general purpose 8-bit CPU. operation mode set, etc., accessing interface register parameter register. Sequence controller Each block controlled coded decoded process algorithm. Coding section change points pixels detected judged, code each mode generated. coded data transferred data FIFO (EFIFO) 8-bit 4-word coding. Decoding section coded data each mode judged reproduced pixel data generated. coded data transferred data FIFO (DFIFO) decoding. Image memory interface Reading writing image memory control transfer image memory performed. Assignment Input Output Bidirectional Power connected
name IREQ DREQ DACK
Type
name TEST3 TEST2 TEST1 TEST0 BREQ BACK IDREQ IDACK MDEN IORD IOWR READY MA23 MA22 MA21 MA20 MA19 MA18 MA17
Type
name MA16 MA/MD15 MA/MD14 MA/MD13 MA/MD12 MA/MD11 MA/MD10 MA/MD9 MA/MD8 MA/MD7 MA/MD6 MA/MD5 MA/MD4 MA/MD3 MA/MD2 MA/MD1 MA/MD0
Type
RESET TEST4
No.4605-4/10
LC8213
Descriptions Interface
name IREQ Descriptions Chip select access LC8213 (low active). Read. when read LC8213 register. Write. when write LC8213 register. Address input when accesses LC8213.
states
Bidirectional 8-bit data
DREQ
DACK
Interrupt request signal CPU. reading INTR (interrupt request register) find cause interruption. IREQ when reads INTR. request signal external controller. This will following cases. Data exists EFIFO during coding processes. empty space exists DFIFO during decoding processes. DBUF read/write during data transfer between image memory bus. acknowledge signal from external controller. DACK during coding decoding, EFIFO DFIFO will accessed. DBUF will accessed DACK during data transfer between image memory bus.
Image Memory Interface
name MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA/MD15 MA/MD14 MA/MD13 MA/MD12 MA/MD11 MA/MD10 MA/MD9 MA/MD8 MA/MD7 MA/MD6 MA/MD5 MA/MD4 MA/MD3 MA/MD2 MA/MD1 MA/MD0 MDEN IORD IOWR BREQ BACK IDREQ IDACK READY states High-order 8-bit address image memory. Descriptions
states
Low-order 16-bit address 16-bit data image memory.
states states states states states states
This when LC8213 master image memory. AEN="H", MA/MD, MRD, MWR, IORD, IOWR, will output. This signal indicates that address being output MA/MD15 MA/MD0. This signal indicates that LC8213 using MA/MD15 MA/MD0 data buses. This signal indicates that high-order bits data being used. This signal indicates that low-order bits data being used. This when data being read image memory. This when data being written into image memory. This when data being read device. This when data being written into device. This signal used LC8213 request usage rights from image memory bus. Input signal allowing LC8213 image memory bus. Input signal used device request from LC8213. acknowledge signal from LC8213. This signal used delay read/write signal when using speed image memory device. This signal indicates that transfer been completed.
No.4605-5/10
LC8213
Others
name RESET TEST0 TEST1 TEST2 TEST3 TEST4 External clock (Max. 20MHz) Reset testing This normally fixed "L". Descriptions
Power supply
Explanation Function Coding method coding method follows CCITT T.4, coding methods that standard facsimiles. Processing mode maximum lines processing set, processing block possible. Processing line also possible. coding decoding FIFOs built-in, coding decoding performed alternately several lines time. When coding, LC8213 reads image data order from start address image memory register. This data coded written into coding FIFO. When number lines have been processed, interrupted. When decoding, LC8213 reads coded data from decoding FIFO, reproduces image data, writes into image memory. When number lines have been processed decoding error occurs, interrupted. Line skip mode This mode allows coded amount blank lines decreased half minimum transmission bits. line skip (blank line judgement bit) added code, fill added blank line that coded amount half minimum transmission bits. lines that completely blank, normal codes transmitted after line skip bit. interface This interface 8-bit data bus, various operation modes accessing interface register. interface terminals external controller built-in, transfer between LC8213 memory possible. Image memory interface image memory address space bytes. data size selected from 8-bit 16-bit. transfer function transfer performed between image memory device with internal controller. maximum lines transferring. Data transfer function Data transfer performed without coding/decoding between image memory bus. processing processing selected. processing function that outputs after line coded data that 8-bit unit. Parameter settings following parameters listed values. processing bits line (byte unit) bytes Document width (byte unit) bytes processing lines Minimum transmission bits line parameters during coding processing lines transfer that structure code document width processing bits line separately, part document coded decoded.
No.4605-6/10
LC8213
Read Timing
Write Timing
Controller Read Timing
Controller Write Timing
No.4605-7/10
LC8213
Image Memory Access
No.4605-8/10
LC8213
Transfer
Clock Reset Timing
No.4605-9/10
LC8213
Specifications SANYO products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Electric Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO products(including technical data,services) described contained herein controlled under applicable local export control laws regulations, such products must expor without obtaining expor license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Electric Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO product that intend use. Information (including circuit diagrams circuit parameters) herein example only guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information August, 2001. Specifications information herein subject change without notice.
No.4605-10/10

LC8213 Image Data Compression/Expansion Processor Overview

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